diff --git a/projects/duifei/duifei_online_acq_par/.gitignore b/projects/duifei/duifei_online_acq_par/.gitignore new file mode 100644 index 00000000..d6f41494 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/.gitignore @@ -0,0 +1,131 @@ +################################################################################ +########################### Single Project Specific ############################ +################################################################################ + +# ------------------------------------------------------------------------------ +# ------------------------------ Vivado Specific ------------------------------- +# ------------------------------------------------------------------------------ + +# exclude everything in project directory +project/** + +# include hardware manager projects and sources +# 1. include `.hw` directory +# 2. include everything in `.hw` directory +!project/*.hw/ +!project/*.hw/** + +# include design run results +# 1. include `*.runs` directory +# 2. exclude everything in `.runs` directory +# 3. include `.impl_*` directory +# 4. include `*.bit` file in `.impl_*` directory +# 5. include `*.ltx` file in `.impl_*` directory +!/project/*.runs/ +/project/*.runs/** +!/project/*.runs/impl_*/ +!/project/*.runs/impl_*/*.bit +!/project/*.runs/impl_*/*.ltx + +# ------------------------------------------------------------------------------ +# -------------------------------- SDK Specific -------------------------------- +# ------------------------------------------------------------------------------ + +# include sdk directory and everything in it +!/project/*.sdk/ +!/project/*.sdk/** +/project/*.sdk/**.log + +# exclude some obscure hidden SDK folders +/project/*.sdk/.metadata/ +/project/*.sdk/.sdk/ +/project/*.sdk/RemoteSystemsTempFiles/ +/project/*.sdk/webtalk/ + +# hw_platform: exclude the entire hw_platform folder, as everything can be +# generated from the .hdf file. Make sure to include the bitstream in the .hdf +# file when exporting from Vivado! +/project/*.sdk/*_hw_platform_*/ + +# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and +# Makefile, ps lib files are regenerated automatically +/project/*.sdk/*_bsp/* +!/project/*.sdk/*_bsp/*.cproject +!/project/*.sdk/*_bsp/*.project +!/project/*.sdk/*_bsp/*.sdkproject +!/project/*.sdk/*_bsp/system.mss +!/project/*.sdk/*_bsp/Makefile + +# Application: ignored file patterns, exclude Debug & Release folders +/project/*.sdk/**/*.o +/project/*.sdk/**/*.d +/project/*.sdk/**/*.a +/project/*.sdk/*/Debug/ +/project/*.sdk/*/Release/ + + +################################################################################ +# ############################ Multi Project Specific ############################ +# ################################################################################ + +# # ------------------------------------------------------------------------------ +# # ------------------------------ Vivado Specific ------------------------------- +# # ------------------------------------------------------------------------------ + +# # exclude everything in project directory expect for top level directory +# project/** +# !/project/*/ + +# # include hardware manager projects and sources +# # 1. include `.hw` directory +# # 2. include everything in `.hw` directory +# !project/*/*.hw/ +# !project/*/*.hw/** + +# # include design run results +# # 1. include `*.runs` directory +# # 2. exclude everything in `.runs` directory +# # 3. include `.impl_*` directory +# # 4. include `*.bit` file in `.impl_*` directory +# # 5. include `*.ltx` file in `.impl_*` directory +# !/project/*/*.runs/ +# /project/*/*.runs/** +# !/project/*/*.runs/impl_*/ +# !/project/*/*.runs/impl_*/*.bit +# !/project/*/*.runs/impl_*/*.ltx + +# # ------------------------------------------------------------------------------ +# # -------------------------------- SDK Specific -------------------------------- +# # ------------------------------------------------------------------------------ + +# # include sdk directory and everything in it +# !/project/*/*.sdk/ +# !/project/*/*.sdk/** +# /project/*/*.sdk/**.log + +# # exclude some obscure hidden SDK folders +# /project/*/*.sdk/.metadata/ +# /project/*/*.sdk/.sdk/ +# /project/*/*.sdk/RemoteSystemsTempFiles/ +# /project/*/*.sdk/webtalk/ + +# # hw_platform: exclude the entire hw_platform folder, as everything can be +# # generated from the .hdf file. Make sure to include the bitstream in the .hdf +# # file when exporting from Vivado! +# /project/*/*.sdk/*_hw_platform_*/ + +# # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and +# # Makefile, ps lib files are regenerated automatically +# /project/*/*.sdk/*_bsp/* +# !/project/*/*.sdk/*_bsp/*.cproject +# !/project/*/*.sdk/*_bsp/*.project +# !/project/*/*.sdk/*_bsp/*.sdkproject +# !/project/*/*.sdk/*_bsp/system.mss +# !/project/*/*.sdk/*_bsp/Makefile + +# # Application: ignored file patterns, exclude Debug & Release folders +# /project/*/*.sdk/**/*.o +# /project/*/*.sdk/**/*.d +# /project/*/*.sdk/**/*.a +# /project/*/*.sdk/*/Debug/ +# /project/*/*.sdk/*/Release/ diff --git a/projects/duifei/duifei_online_acq_par/constraints/z7100_hmc7044_2ad9361.xdc b/projects/duifei/duifei_online_acq_par/constraints/z7100_hmc7044_2ad9361.xdc new file mode 100644 index 00000000..8173aa8e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/constraints/z7100_hmc7044_2ad9361.xdc @@ -0,0 +1,194 @@ +# df_z7100_2ad9361 + +## Timing Assertions Section + +## Physical Constraints Section + +# Clocks +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS } [get_ports clk_250m_p ] ;# FPGA_DAC_LOGIC_CLK_C_P +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# AD9361_CLK_OUT +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B_AD9361_CLK_OUT + +# HMC7044-1 Interface +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_clk ] ;# HMC7044_1_SCLK +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_csn ] ;# HMC7044_1_SLEN +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_sdio ] ;# HMC7044_1_DATA + +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports hmc7044_reset ] ;# HMC7044_1_RESET +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} [get_ports hmc7044_sync ] ;# HMC7044_1_SYNC + +set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[0] ] ;# HMC7044_1_GPIO1 +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[1] ] ;# HMC7044_1_GPIO2 +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[2] ] ;# HMC7044_1_GPIO3 +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[3] ] ;# HMC7044_1_GPIO4 + +# AD9361-1 Interface +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# AD9361_DATA_CLK_P +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# AD9361_RX_FRAME_P +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# AD9361_TX_00_D0_N +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# AD9361_TX_01_D0_P +set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# AD9361_TX_02_D1_N +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# AD9361_TX_03_D1_P +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# AD9361_TX_04_D2_N +set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# AD9361_TX_05_D2_P +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# AD9361_TX_06_D3_N +set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# AD9361_TX_07_D3_P +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# AD9361_TX_08_D4_N +set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# AD9361_TX_09_D4_P +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# AD9361_TX_10_D5_N +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# AD9361_TX_11_D5_P + +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# AD9361_FB_CLK_P +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# AD9361_TX_FRAME_P +set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# AD9361_RX_00_D0_N +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# AD9361_RX_01_D0_P +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# AD9361_RX_02_D1_N +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# AD9361_RX_03_D1_P +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# AD9361_RX_04_D2_N +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# AD9361_RX_05_D2_P +set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# AD9361_RX_06_D3_N +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# AD9361_RX_07_D3_P +set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# AD9361_RX_08_D4_N +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# AD9361_RX_09_D4_P +set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# AD9361_RX_10_D5_N +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# AD9361_RX_11_D5_P + +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# AD9361_SPI_CLK +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# AD9361_SPI_ENB +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# AD9361_SPI_DI +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# AD9361_SPI_DO + +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# AD9361_RESETB +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# AD9361_EN_AGC +set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# AD9361_ENABLE +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# AD9361_TXNRX + +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# AD9361_CTRL_IN0 +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# AD9361_CTRL_IN1 +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# AD9361_CTRL_IN2 +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# AD9361_CTRL_IN3 + +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# AD9361_CTRL_OUT0 +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# AD9361_CTRL_OUT1 +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# AD9361_CTRL_OUT2 +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# AD9361_CTRL_OUT3 +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# AD9361_CTRL_OUT4 +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# AD9361_CTRL_OUT5 +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# AD9361_CTRL_OUT6 +set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# AD9361_CTRL_OUT7 + +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# AD9361_SYNC_IN + +# AD9361-2 Interface +set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B_AD9361_DATA_CLK_P +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B_AD9361_RX_FRAME_P +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B_AD9361_TX_00_D0_N +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B_AD9361_TX_01_D0_P +set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B_AD9361_TX_02_D1_N +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B_AD9361_TX_03_D1_P +set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B_AD9361_TX_04_D2_N +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B_AD9361_TX_05_D2_P +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B_AD9361_TX_06_D3_N +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B_AD9361_TX_07_D3_P +set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B_AD9361_TX_08_D4_N +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B_AD9361_TX_09_D4_P +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B_AD9361_TX_10_D5_N +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B_AD9361_TX_11_D5_P + +set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B_AD9361_FB_CLK_P +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B_AD9361_TX_FRAME_P +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B_AD9361_RX_00_D0_N +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B_AD9361_RX_01_D0_P +set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B_AD9361_RX_02_D1_N +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B_AD9361_RX_03_D1_P +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B_AD9361_RX_04_D2_N +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B_AD9361_RX_05_D2_P +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B_AD9361_RX_06_D3_N +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B_AD9361_RX_07_D3_P +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B_AD9361_RX_08_D4_N +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B_AD9361_RX_09_D4_P +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B_AD9361_RX_10_D5_N +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B_AD9361_RX_11_D5_P + +set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B_AD9361_SPI_CLK +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B_AD9361_SPI_ENB +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B_AD9361_SPI_DI +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B_AD9361_SPI_DO + +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B_AD9361_RESETB +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B_AD9361_EN_AGC +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B_AD9361_ENABLE +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B_AD9361_TXNRX + +set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B_AD9361_CTRL_IN0 +set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B_AD9361_CTRL_IN1 +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B_AD9361_CTRL_IN2 +set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B_AD9361_CTRL_IN3 + +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B_AD9361_CTRL_OUT0 +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B_AD9361_CTRL_OUT1 +set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B_AD9361_CTRL_OUT2 +set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B_AD9361_CTRL_OUT3 +set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B_AD9361_CTRL_OUT4 +set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B_AD9361_CTRL_OUT5 +set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B_AD9361_CTRL_OUT6 +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B_AD9361_CTRL_OUT7 + +# Phased-Array Control +set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVTTL } [get_ports ant_clk ] ;# ANT_CLK +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVTTL } [get_ports ant_en ] ;# ANT_EN +set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports ant_data ] ;# ANT_DATA +set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR +set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY +set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports ant_dout ] ;# ANT_DOUT + +# RF Synthesizer Control +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports rf_standby ] ;# ANT_standby_R +set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports rf_sw_pll ] ;# ANT_SW_PLL_R +set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports rf_t ] ;# ANT_T_R +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports rf_r ] ;# ANT_R_R +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports rf_sw_bpf ] ;# ANT_SW_BPF_R +set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports rf_sclk1 ] ;# ANT_SCLK1_R +set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports rf_sdio1 ] ;# ANT_SDIO1_R +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports rf_cs1 ] ;# ANT_CS1_R +set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports rf_ld1 ] ;# ANT_LD1_R +set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports rf_sclk2 ] ;# ANT_SCLK2_R +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS33} [get_ports rf_sdio2 ] ;# ANT_SDIO2_R +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS33} [get_ports rf_cs2 ] ;# ANT_CS2_R +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS33} [get_ports rf_ld2 ] ;# ANT_LD2_R +set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS33} [get_ports rf_sclk3 ] ;# ANT_SCLK3_R +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS33} [get_ports rf_sdio3 ] ;# ANT_SDIO3_R +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS33} [get_ports rf_cs3 ] ;# ANT_CS3_R +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS33} [get_ports rf_ld3 ] ;# ANT_LD3_R +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_16 ] ;# ANT_TMGC_16_R +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_8 ] ;# ANT_TMGC_8_R +set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_4 ] ;# ANT_TMGC_4_R +set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_2 ] ;# ANT_TMGC_2_R +set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_1 ] ;# ANT_TMGC_1_R +set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_16 ] ;# ANT_RMGC_16_R +set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_8 ] ;# ANT_RMGC_8_R +set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_4 ] ;# ANT_RMGC_4_R +set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_2 ] ;# ANT_RMGC_2_R +set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_1 ] ;# ANT_RMGC_1_R +set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS33} [get_ports rf_enable ] ;# ANT_ENABLE_R +set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS33} [get_ports rf_sc ] ;# ANT_SC_R +set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS33} [get_ports rf_sd ] ;# ANT_SD_R +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports rf_endsyn ] ;# ANT_END/SYN_R +set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports rf_sdout ] ;# ANT_SDOUT_R +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS33} [get_ports rf_dq_wd ] ;# ANT_DQ-WD_R 15 +set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33} [get_ports rf_sw_rx ] ;# ANT_SW_RX_R + +# Debug IO +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART1_TXD +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART1_RXD +set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART2_TXD +set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART2_RXD +set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART3_TXD +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART3_RXD +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports debug_io_1 ] ;# DEBUG_IO_1 +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports debug_io_2 ] ;# DEBUG_IO_2 +set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3 +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4 +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5 +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6 +set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7 diff --git a/projects/duifei/duifei_online_acq_par/constraints/z7100_hmc7044_2ad9361_timing.xdc b/projects/duifei/duifei_online_acq_par/constraints/z7100_hmc7044_2ad9361_timing.xdc new file mode 100644 index 00000000..45c759fa --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/constraints/z7100_hmc7044_2ad9361_timing.xdc @@ -0,0 +1 @@ +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_clk_dist/u_ad9361_2_clk_gen/inst/clk_in1_ad9361_clk_gen_cmos_2t2r] diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48Msps_bw15m_ext_lo_bypass.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48Msps_bw15m_ext_lo_bypass.csv new file mode 100644 index 00000000..4acfea1f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48Msps_bw15m_ext_lo_bypass.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:da2a5e413ed5888360149258ef98042e72a3f49c6b126285c407d221206343b0 +size 5696542 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48Msps_bw15m_ext_lo_rxfir.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48Msps_bw15m_ext_lo_rxfir.csv new file mode 100644 index 00000000..9f4aa339 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48Msps_bw15m_ext_lo_rxfir.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:311cc1b3564a4da4ae7ab36b636ceca61d2e8d65e52567825399be34c10a205d +size 5487793 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-1.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-1.csv new file mode 100644 index 00000000..c9f9b6f1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-1.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:657cb426ba63d035ab3770f34507ce4cd5af029740ff483bff4afac61c7fe405 +size 4953881 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-2.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-2.csv new file mode 100644 index 00000000..23d2801e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-2.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fb6a9679fcbde08a28d17d03e42f8dfdc221c1806758e3d74bd28ef146771817 +size 4945576 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-3.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-3.csv new file mode 100644 index 00000000..64e87b35 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-3.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0145e254692b5dd671b20917aaea4e2fbf4729be82979714fb09278cb1798a8a +size 4939528 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-1.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-1.csv new file mode 100644 index 00000000..b517aa3c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-1.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dd4797a467476ed843b806dae7d7635a47160ae1c19990c253e884f4059152fa +size 4950262 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-2.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-2.csv new file mode 100644 index 00000000..c6c00f33 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-2.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:581d94321adb4bb67c689698392e108e45049ca9ec24aa30461b7a2cd3d5ecb2 +size 4955546 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-3.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-3.csv new file mode 100644 index 00000000..6416b667 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-3.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5a327fa69eca5691f0e5d7405de8f0b73e357da4b5738c814fa937d96c1ccf2e +size 4955228 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-1.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-1.csv new file mode 100644 index 00000000..53a9471a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-1.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:bdde224a0bedcdf95e2d8eb249539cecd05005a2514c4d47f1e9fc598c323ce7 +size 4949022 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-2.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-2.csv new file mode 100644 index 00000000..281d385d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-2.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f16321cdcaee69fcc544a29ebe1f87fba10899b2357980539a3d4ba84b5e45ce +size 4948924 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-3.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-3.csv new file mode 100644 index 00000000..3dd6f271 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-3.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:da3cb42b282f8f2455f0a59b1311b7e96c6c5780b773a19027f6ef4996d121a9 +size 4959851 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/noise_analysis.m b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/noise_analysis.m new file mode 100644 index 00000000..4f3e46a5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞接收底噪/noise_analysis.m @@ -0,0 +1,44 @@ +close all; + +% 4 ch +fileNameList = [... +"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-1.csv",... +"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-2.csv",... +"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-3.csv",... +"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-1.csv",... +"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-2.csv",... +"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-3.csv",... +"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-1.csv",... +"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-2.csv",... +"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-3.csv" +]; + +[~,fileNum] = size(fileNameList); + +maxList = strings(fileNum+1,5); +stdList = strings(fileNum+1,5); + +maxList(1,:) = ["Max Value", "ch1", "ch2", "ch3", "ch4"]; +maxList(2:end,1) = fileNameList; +stdList(1,:) = ["Std Value", "ch1", "ch2", "ch3", "ch4"]; +stdList(2:end,1) = fileNameList; + +for i = 1:fileNum + rxRaw = readmatrix(fileNameList(:,i)); + [rowNum,colNum] = size(rxRaw); + + if (colNum == 11) + rx = [rxRaw(:, 4)+1i*rxRaw(:, 5),rxRaw(:, 6)+1i*rxRaw(:, 7),... + rxRaw(:, 8)+1i*rxRaw(:, 9),rxRaw(:,10)+1i*rxRaw(:,11)]; + elseif (colNum == 7) + rx = [rxRaw(:, 4)+1i*rxRaw(:, 5),rxRaw(:, 6)+1i*rxRaw(:, 7),... + zeros(rowNum,1),zeros(rowNum,1)]; + else + disp('Invalid Data Format.') + return + end + + maxList(i+1,2:end) = string(max(rx)); + stdList(i+1,2:end) = string(std(rx)); + +end diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_1-1.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_1-1.csv new file mode 100644 index 00000000..3791549b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_1-1.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e458fbc41fd1a5b2034001a7687343b2883b86a0a618255d3b8c4846d0809895 +size 5650597 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_1-2.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_1-2.csv new file mode 100644 index 00000000..a1d15753 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_1-2.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:81d642f0d1e13578ea2268d69f489ca59f5ea2d2c2d8454ffda37e2ce18bce0f +size 5661088 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_1-3.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_1-3.csv new file mode 100644 index 00000000..22c9b980 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_1-3.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:82e30ec27dc9906506d5aee652c3274825dd79cf951aa6074642a480df76022d +size 5654010 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_10.csv b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_10.csv new file mode 100644 index 00000000..0d6d7bd0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_10.csv @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7e61ed371762bd005038ab6fbd151854ed11da8739f631984c883aa402b7443d +size 5790693 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_11.csv 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sha256:1e815a440a4d2afef741a49254c75239179886f1f4d323f8eb201e8ab7bb653d +size 5685222 diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/multiBitCorrInterSampleDiff.m b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/multiBitCorrInterSampleDiff.m new file mode 100644 index 00000000..7663eb0b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/multiBitCorrInterSampleDiff.m @@ -0,0 +1,86 @@ +%% File Header/文件说明 +% +% Beamforming with phased array derives signal characteristics from phase +% differences between sensors. Therefore the amplitude-phase consistence is +% vital to phased systems. +% +% The script analyzes the amp-phase relations of ILA captured data, the format +% of which is square-shaped pseudorandorm bit sequence. Each channel is +% processed seperately with different frequency shifts and different optimum +% sampling points. The estimation of amplitude and phase are based on +% acculumated correlation peaks. +% +clc; clear; +%% initial parameters/初始参数 +interp = 8; % interpolation factor +channelNum = 4; +dataLen = 131072; +fs = 48e6; +dataFile = "iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_2-1.csv"; + +% standard pn sequence +pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ... + 'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1); +PRBS7 = pnSequence(); +PRBS7_polar = 1-2*[PRBS7;0]; + +chipLen = length(PRBS7_polar); % pn chip length +symNum = dataLen/chipLen/interp; % total symbol number +symNumPerAccum = 1; % symbol nbumber of each accumulation +accNum = symNum/symNumPerAccum; % total accumulation numbers, i.e. peak numbers + +%% data analysis + +% read data, and swap ch1 and ch2, because loop data locate at ch2 and ch4 +rxdata = readmatrix(dataFile); +seqRx(:,1) = (rxdata(:, 6) + 1i*rxdata(:, 7)).'; +seqRx(:,2) = (rxdata(:, 4) + 1i*rxdata(:, 5)).'; +seqRx(:,3) = (rxdata(:, 8) + 1i*rxdata(:, 9)).'; +seqRx(:,4) = (rxdata(:,10) + 1i*rxdata(:,11)).'; + +% compensate frequecny deviation and downsample at optimum sample position based +% on the varience of constellation +[seqRxDown,fd,samplePos] = suqareShapeFreqEst(seqRx,interp,fs,-50,50,5); + +% split [seqRxDown] into multiple groups, each group contains several symbols to +% be correlated with PRBS7 and accumulated +seqRxDownSplit = reshape(seqRxDown(1:dataLen/interp,:),chipLen*symNumPerAccum, ... + accNum,channelNum); + +seqRxAcc = zeros(chipLen,accNum,channelNum); +desiredPnt = zeros(accNum,channelNum); +ampEstSym = zeros(accNum,channelNum); +angleEstSym = zeros(accNum,channelNum); + +for i = 1:accNum + for j = 1:channelNum + % correlation & multi-symbol accumulation + groupCorrAcc = sum(reshape(conv(flip(seqRxDownSplit(:,i,j)), ... + PRBS7_polar,'same'),chipLen,symNumPerAccum),2)'; + seqRxAcc(:,i,j) = groupCorrAcc; + % peak position + desiredPnt(i,j) = groupCorrAcc(abs(groupCorrAcc)==max(abs(groupCorrAcc))); + end +end + +for i = 1:channelNum + ampEstSym(:,i) = abs(desiredPnt(:,i))./abs(desiredPnt(:,1)); + angleEstSym(:,i) = mod((angle(desiredPnt(:,i))-angle(desiredPnt(:,1)))/pi*180,360); +end + +%% figures +figure(1); + +subplot(121); +plot(ampEstSym(:,[1,4])); +legend({"ch1","ch4"}); +title("Amplitude Estimation"); +ylim([min(ampEstSym(:,[1,4]),[],'all')-0.1,max(ampEstSym(:,[1,4]),[],'all')+0.1]); +grid on; grid minor; + +subplot(122); +plot(angleEstSym(:,[1,4])); +legend({"ch1","ch4"}); +title("Angle Estimation"); +ylim([min(angleEstSym(:,[1,4]),[],'all')-1,max(angleEstSym(:,[1,4]),[],'all')+1]); +grid on; grid minor; diff --git a/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/suqareShapeFreqEst.m b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/suqareShapeFreqEst.m new file mode 100644 index 00000000..bb33a13f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/data/20230410-对飞校准通道相差/suqareShapeFreqEst.m @@ -0,0 +1,50 @@ +function [dataOut, fdTarget, samplePosTarget] = suqareShapeFreqEst(dataIn, interp, fs, fmin, fmax, fd) +%suqareShapeFreqEst - 利用星座图的集中程度在一定频率范围内使用频率步进估计方波成形信号的频偏 +% +% data - input complex data, row vector +% dataLen - data length +% interp - interpolation rate +% fs - sampling rate, in Herts +% fmin - minimum estimation frequency, in Herts +% fmax - maximum estimation frequency, in Herts +% fd - estimation frequency step, in Herts + +% dimension +[dataLen,channelNum] = size(dataIn); + +freqList = fmin:fd:fmax; +freqNum = length(freqList); +varRecord = zeros(freqNum,interp); + +dataOut = zeros(dataLen/interp,channelNum); +fdTarget = zeros(channelNum,1); +samplePosTarget = zeros(channelNum,1); + +for channel = 1:channelNum + + for freq = 1:freqNum + + % carrier + cxr = exp(-1i*2*pi*freqList(freq)/fs*(0:dataLen-1)'); + + % apply frequency shift onto input data + seqRx = dataIn(:,channel).*cxr; + + for samplePos = 0:interp-1 + seqRxDown = downsample(seqRx,interp,samplePos); % 下采样 + seqRxDownQuaterOne = abs(real(seqRxDown)) + 1i*abs(imag(seqRxDown)); % 集中到第一象限 + varRecord(freq,samplePos+1) = var(seqRxDownQuaterOne); + end + + end + + [fdIndex, samplePosIndex] = find(varRecord==min(min(varRecord))); + fdTarget(channel) = freqList(fdIndex); + samplePosTarget(channel) = samplePosIndex-1; + + cxrTarget = exp(-1i*2*pi*fdTarget(channel)/fs*(0:dataLen-1)'); + seqRxTarget = dataIn(:,channel).*cxrTarget; + dataOut(:,channel) = downsample(seqRxTarget,interp,samplePosTarget(channel)); +end + +end \ No newline at end of file diff --git a/projects/duifei/duifei_online_acq_par/ip/cmpy_12x8.xcix b/projects/duifei/duifei_online_acq_par/ip/cmpy_12x8.xcix new file mode 100644 index 00000000..fef4a7c8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/cmpy_12x8.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ffe0a51091c3bb733fea96ca6605570e0c171f21f56a2e6fff415024c22eee4b +size 4101451 diff --git a/projects/duifei/duifei_online_acq_par/ip/coe/freq_word.coe b/projects/duifei/duifei_online_acq_par/ip/coe/freq_word.coe new file mode 100755 index 00000000..20ed79a7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/coe/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep2.coe new file mode 100644 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep4.coe b/projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep4.coe new file mode 100644 index 00000000..4ade3f8b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep4.coe @@ -0,0 +1,514 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2.xcix b/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2.xcix new file mode 100644 index 00000000..bf04bd4d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d3489db55b49758e586385420457a7c7af12d8771ec73e1e9bfffb367046283e +size 11923889 diff --git a/projects/duifei/duifei_online_acq_par/ip/ila_cal.xcix b/projects/duifei/duifei_online_acq_par/ip/ila_cal.xcix new file mode 100644 index 00000000..cea832c0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ila_cal.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:bc1c4234d6ff245a66c55fe64feb23613f82299b78c83df2085e7edcec92745f +size 27776835 diff --git a/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp.xcix b/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp.xcix new file mode 100644 index 00000000..0667c5b0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6b96b082a23618df5d8600b746b16bd8b36d65dc898ce7d3ff6091f18df66214 +size 34744662 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/README.txt new file mode 100644 index 00000000..023052ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8.veo new file mode 100644 index 00000000..74ba0701 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8.veo @@ -0,0 +1,71 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:cmpy:6.0 +// IP Revision: 17 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +cmpy_12x8 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid + .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid + .s_axis_b_tdata(s_axis_b_tdata), // input wire [15 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(m_axis_dout_tdata) // output wire [47 : 0] m_axis_dout_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file cmpy_12x8.v when simulating +// the core, cmpy_12x8. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8.vho new file mode 100644 index 00000000..2ee5a299 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8.vho @@ -0,0 +1,87 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:cmpy:6.0 +-- IP Revision: 17 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT cmpy_12x8 + PORT ( + aclk : IN STD_LOGIC; + s_axis_a_tvalid : IN STD_LOGIC; + s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_b_tvalid : IN STD_LOGIC; + s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + m_axis_dout_tvalid : OUT STD_LOGIC; + m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : cmpy_12x8 + PORT MAP ( + aclk => aclk, + s_axis_a_tvalid => s_axis_a_tvalid, + s_axis_a_tdata => s_axis_a_tdata, + s_axis_b_tvalid => s_axis_b_tvalid, + s_axis_b_tdata => s_axis_b_tdata, + m_axis_dout_tvalid => m_axis_dout_tvalid, + m_axis_dout_tdata => m_axis_dout_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file cmpy_12x8.vhd when simulating +-- the core, cmpy_12x8. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_sim_netlist.v new file mode 100644 index 00000000..cdad7ae7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3e99971165427fa7fe69165ac62c7e4dabc22e68d854eb6be28b79d2f8921f49 +size 524462 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_sim_netlist.vhdl new file mode 100644 index 00000000..931952b0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e9e76ad8b28621a962c7bb697d9c71f906708a563996a06df63bf35d98a4dfaf +size 741220 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_stub.v new file mode 100644 index 00000000..548c7ed6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:27 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.v +// Design : cmpy_12x8 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *) +module cmpy_12x8(aclk, s_axis_a_tvalid, s_axis_a_tdata, + s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata) +/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[47:0]" */; + input aclk; + input s_axis_a_tvalid; + input [31:0]s_axis_a_tdata; + input s_axis_b_tvalid; + input [15:0]s_axis_b_tdata; + output m_axis_dout_tvalid; + output [47:0]m_axis_dout_tdata; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_stub.vhdl new file mode 100644 index 00000000..39482542 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/cmpy_12x8_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:27 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.vhdl +-- Design : cmpy_12x8 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity cmpy_12x8 is + Port ( + aclk : in STD_LOGIC; + s_axis_a_tvalid : in STD_LOGIC; + s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axis_b_tvalid : in STD_LOGIC; + s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_dout_tvalid : out STD_LOGIC; + m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 47 downto 0 ) + ); + +end cmpy_12x8; + +architecture stub of cmpy_12x8 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[47:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/demo_tb/tb_cmpy_12x8.vhd b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/demo_tb/tb_cmpy_12x8.vhd new file mode 100644 index 00000000..427663e5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/demo_tb/tb_cmpy_12x8.vhd @@ -0,0 +1,387 @@ +-------------------------------------------------------------------------------- +-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- Description: +-- This is an example testbench for the Complex Multiplier IP core. +-- The testbench has been generated by Vivado to accompany the IP core +-- instance you have generated. +-- +-- This testbench is for demonstration purposes only. See note below for +-- instructions on how to use it with your core. +-- +-- See the Complex Multiplier product guide for further information +-- about this core. +-- +-------------------------------------------------------------------------------- +-- Using this testbench +-- +-- This testbench instantiates your generated Complex Multiplier core +-- instance named "cmpy_12x8". +-- +-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado +-- documentation for details. +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity tb_cmpy_12x8 is +end tb_cmpy_12x8; + +architecture tb of tb_cmpy_12x8 is + + ----------------------------------------------------------------------- + -- Timing constants + ----------------------------------------------------------------------- + constant CLOCK_PERIOD : time := 100 ns; + constant T_HOLD : time := 10 ns; + constant T_STROBE : time := CLOCK_PERIOD - (1 ns); + constant TEST_CYCLES : integer := 3000; + constant PHASE_CYCLES : integer := 1000; + + ----------------------------------------------------------------------- + -- DUT input signals + ----------------------------------------------------------------------- + + -- General inputs + signal aclk : std_logic := '0'; -- the master clock + + -- Slave channel A inputs + signal s_axis_a_tvalid : std_logic := '0'; -- TVALID for channel A + signal s_axis_a_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- TDATA for channel A + + -- Slave channel B inputs + signal s_axis_b_tvalid : std_logic := '0'; -- TVALID for channel B + signal s_axis_b_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- TDATA for channel B + + ----------------------------------------------------------------------- + -- DUT output signals + ----------------------------------------------------------------------- + + -- Master channel DOUT outputs + signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel DOUT + signal m_axis_dout_tdata : std_logic_vector(47 downto 0) := (others => '0'); -- TDATA for channel DOUT + + ----------------------------------------------------------------------- + -- Aliases for AXI channel TDATA fields + -- These are a convenience for viewing data in a simulator waveform viewer. + -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command + -- to prevent the simulator optimizing away these signals. + ----------------------------------------------------------------------- + signal s_axis_a_tdata_real : std_logic_vector(11 downto 0) := (others => '0'); + signal s_axis_a_tdata_imag : std_logic_vector(11 downto 0) := (others => '0'); + signal s_axis_b_tdata_real : std_logic_vector(7 downto 0) := (others => '0'); + signal s_axis_b_tdata_imag : std_logic_vector(7 downto 0) := (others => '0'); + signal m_axis_dout_tdata_real : std_logic_vector(20 downto 0) := (others => '0'); + signal m_axis_dout_tdata_imag : std_logic_vector(20 downto 0) := (others => '0'); + + ----------------------------------------------------------------------- + -- Testbench signals + ----------------------------------------------------------------------- + + signal cycles : integer := 0; -- Clock cycle counter + + ----------------------------------------------------------------------- + -- Constants, types and functions to create input data + -- Treat the complex multiplier as a mixer that is combining two + -- sinusoids exp(+/-jwt) of different frequencies and amplitudes: + -- channel A: exp(+jwt), frequency = clock / 30, amplitude = fullscale >> 3 + -- channel B: exp(-jwt), frequency = clock / 32, amplitude = fullscale + -- The output of the complex multiplier is a sinusoid with a frequency + -- equal to the difference between the input frequencies. + ----------------------------------------------------------------------- + + constant IP_A_DEPTH : integer := 30; + constant IP_A_WIDTH : integer := 12; + constant IP_A_SHIFT : integer := 3; -- bit shift for amplitude + constant IP_B_DEPTH : integer := 32; + constant IP_B_WIDTH : integer := 8; + constant IP_B_SHIFT : integer := 0; -- no bit shift, max amplitude + type T_IP_INT_ENTRY is record + re : integer; + im : integer; + end record; + type T_IP_A_ENTRY is record + re : std_logic_vector(IP_A_WIDTH-1 downto 0); + im : std_logic_vector(IP_A_WIDTH-1 downto 0); + end record; + type T_IP_B_ENTRY is record + re : std_logic_vector(IP_B_WIDTH-1 downto 0); + im : std_logic_vector(IP_B_WIDTH-1 downto 0); + end record; + type T_IP_A_TABLE is array (0 to IP_A_DEPTH-1) of T_IP_A_ENTRY; + type T_IP_B_TABLE is array (0 to IP_B_DEPTH-1) of T_IP_B_ENTRY; + + -- Common function to calculate sine and cosine values + function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is + variable result : T_IP_INT_ENTRY; + variable theta : real; + variable limited_width : integer := width - 2; + begin + if limited_width > 30 then + limited_width := 30; + end if; + theta := real(index) / real(depth) * 2.0 * MATH_PI; + result.re := integer(round(cos(theta) * real(2**limited_width-1))); + result.im := integer(round(sin(theta) * real(2**limited_width-1))); + return result; + end function create_ip_entry; + + -- Use separate functions to calculate channel A and B sinusoids as they return different types + function create_ip_a_table return T_IP_A_TABLE is + variable result : T_IP_A_TABLE; + variable entry_int : T_IP_INT_ENTRY; + begin + for i in 0 to IP_A_DEPTH-1 loop + entry_int := create_ip_entry(i, IP_A_DEPTH, IP_A_WIDTH - IP_A_SHIFT); + result(i).re := std_logic_vector(to_signed(entry_int.re, IP_A_WIDTH)); + result(i).im := std_logic_vector(to_signed(entry_int.im, IP_A_WIDTH)); + end loop; + return result; + end function create_ip_a_table; + + function create_ip_b_table return T_IP_B_TABLE is + variable result : T_IP_B_TABLE; + variable entry_int : T_IP_INT_ENTRY; + begin + for i in 0 to IP_B_DEPTH-1 loop + entry_int := create_ip_entry(IP_B_DEPTH-1-i, IP_B_DEPTH, IP_B_WIDTH - IP_B_SHIFT); -- note rotation direction + result(i).re := std_logic_vector(to_signed(entry_int.re, IP_B_WIDTH)); + result(i).im := std_logic_vector(to_signed(entry_int.im, IP_B_WIDTH)); + end loop; + return result; + end function create_ip_b_table; + + -- Call the functions to create the data + constant IP_A_DATA : T_IP_A_TABLE := create_ip_a_table; + constant IP_B_DATA : T_IP_B_TABLE := create_ip_b_table; + + +begin + + ----------------------------------------------------------------------- + -- Instantiate the DUT + ----------------------------------------------------------------------- + + dut : entity work.cmpy_12x8 + port map ( + aclk => aclk, + s_axis_a_tvalid => s_axis_a_tvalid, + s_axis_a_tdata => s_axis_a_tdata, + s_axis_b_tvalid => s_axis_b_tvalid, + s_axis_b_tdata => s_axis_b_tdata, + m_axis_dout_tvalid => m_axis_dout_tvalid, + m_axis_dout_tdata => m_axis_dout_tdata + ); + + ----------------------------------------------------------------------- + -- Generate clock + ----------------------------------------------------------------------- + + clock_gen : process + begin + aclk <= '0'; + wait for CLOCK_PERIOD; + loop + cycles <= cycles + 1; + aclk <= '0'; + wait for CLOCK_PERIOD/2; + aclk <= '1'; + wait for CLOCK_PERIOD/2; + if cycles >= TEST_CYCLES then + report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; + wait; + end if; + end loop; + end process clock_gen; + + ----------------------------------------------------------------------- + -- Generate inputs + ----------------------------------------------------------------------- + + stimuli : process + variable ip_a_index : integer := 0; + variable ip_b_index : integer := 0; + variable a_tvalid_nxt : std_logic := '0'; + variable b_tvalid_nxt : std_logic := '0'; + variable phase2_cycles : integer := 1; + variable phase2_count : integer := 0; + constant PHASE2_LIMIT : integer := 30; + begin + + -- Test is stopped in clock_gen process, use endless loop here + loop + + -- Drive inputs T_HOLD time after rising edge of clock + wait until rising_edge(aclk); + wait for T_HOLD; + + -- Drive AXI TVALID signals to demonstrate different types of operation + case cycles is -- do different types of operation at different phases of the test + when 0 to PHASE_CYCLES * 1 - 1 => + -- Phase 1: inputs always valid, no missing input data + a_tvalid_nxt := '1'; + b_tvalid_nxt := '1'; + when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 => + -- Phase 2: deprive channel A of valid transactions at an increasing rate + b_tvalid_nxt := '1'; + if phase2_count < phase2_cycles then + a_tvalid_nxt := '0'; + else + a_tvalid_nxt := '1'; + end if; + phase2_count := phase2_count + 1; + if phase2_count >= PHASE2_LIMIT then + phase2_count := 0; + phase2_cycles := phase2_cycles + 1; + end if; + when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 => + -- Phase 3: deprive channel A of 1 out of 2 transactions, and channel B of 1 out of 3 transactions + if cycles mod 2 = 0 then + a_tvalid_nxt := '0'; + else + a_tvalid_nxt := '1'; + end if; + if cycles mod 3 = 0 then + b_tvalid_nxt := '0'; + else + b_tvalid_nxt := '1'; + end if; + when others => + -- Test will stop imminently - do nothing + null; + end case; + + -- Drive handshake signals with local variable values + s_axis_a_tvalid <= a_tvalid_nxt; + s_axis_b_tvalid <= b_tvalid_nxt; + + -- Drive AXI slave channel A payload + -- Drive '0's on payload signals when not valid + if a_tvalid_nxt /= '1' then + s_axis_a_tdata <= (others => '0'); + else + -- TDATA: Real and imaginary components are each 12 bits wide and byte-aligned at their LSBs + s_axis_a_tdata(11 downto 0) <= IP_A_DATA(ip_a_index).re; + s_axis_a_tdata(15 downto 12) <= (others => IP_A_DATA(ip_a_index).re(11)); -- sign-extend; + s_axis_a_tdata(27 downto 16) <= IP_A_DATA(ip_a_index).im; + s_axis_a_tdata(31 downto 28) <= (others => IP_A_DATA(ip_a_index).im(11)); -- sign-extend; + end if; + + -- Drive AXI slave channel B payload + -- Drive '0's on payload signals when not valid + if b_tvalid_nxt /= '1' then + s_axis_b_tdata <= (others => '0'); + else + -- TDATA: Real and imaginary components are each 8 bits wide and byte-aligned at their LSBs + s_axis_b_tdata(7 downto 0) <= IP_B_DATA(ip_b_index).re; + s_axis_b_tdata(15 downto 8) <= IP_B_DATA(ip_b_index).im; + end if; + + -- Increment input data indices + if a_tvalid_nxt = '1' then + ip_a_index := ip_a_index + 1; + if ip_a_index = IP_A_DEPTH then + ip_a_index := 0; + end if; + end if; + if b_tvalid_nxt = '1' then + ip_b_index := ip_b_index + 1; + if ip_b_index = IP_B_DEPTH then + ip_b_index := 0; + end if; + end if; + + end loop; + + end process stimuli; + + ----------------------------------------------------------------------- + -- Check outputs + ----------------------------------------------------------------------- + + check_outputs : process + variable check_ok : boolean := true; + begin + + -- Check outputs T_STROBE time after rising edge of clock + wait until rising_edge(aclk); + wait for T_STROBE; + + -- Do not check the output payload values, as this requires the behavioral model + -- which would make this demonstration testbench unwieldy. + -- Instead, check the protocol of the DOUT channel: + -- check that the payload is valid (not X) when TVALID is high + + if m_axis_dout_tvalid = '1' then + if is_x(m_axis_dout_tdata) then + report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error; + check_ok := false; + end if; + + end if; + + assert check_ok + report "ERROR: terminating test with failures." severity failure; + + end process check_outputs; + + ----------------------------------------------------------------------- + -- Assign TDATA fields to aliases, for easy simulator waveform viewing + ----------------------------------------------------------------------- + + s_axis_a_tdata_real <= s_axis_a_tdata(11 downto 0); + s_axis_a_tdata_imag <= s_axis_a_tdata(27 downto 16); + s_axis_b_tdata_real <= s_axis_b_tdata(7 downto 0); + s_axis_b_tdata_imag <= s_axis_b_tdata(15 downto 8); + m_axis_dout_tdata_real <= m_axis_dout_tdata(20 downto 0); + m_axis_dout_tdata_imag <= m_axis_dout_tdata(44 downto 24); + +end tb; + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/sim/cmpy_12x8.vhd b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/sim/cmpy_12x8.vhd new file mode 100644 index 00000000..c7cfa5de --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12x8/sim/cmpy_12x8.vhd @@ -0,0 +1,202 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:cmpy:6.0 +-- IP Revision: 17 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY cmpy_v6_0_17; +USE cmpy_v6_0_17.cmpy_v6_0_17; + +ENTITY cmpy_12x8 IS + PORT ( + aclk : IN STD_LOGIC; + s_axis_a_tvalid : IN STD_LOGIC; + s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_b_tvalid : IN STD_LOGIC; + s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + m_axis_dout_tvalid : OUT STD_LOGIC; + m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + ); +END cmpy_12x8; + +ARCHITECTURE cmpy_12x8_arch OF cmpy_12x8 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF cmpy_12x8_arch: ARCHITECTURE IS "yes"; + COMPONENT cmpy_v6_0_17 IS + GENERIC ( + C_VERBOSITY : INTEGER; + C_XDEVICEFAMILY : STRING; + C_XDEVICE : STRING; + C_A_WIDTH : INTEGER; + C_B_WIDTH : INTEGER; + C_OUT_WIDTH : INTEGER; + C_LATENCY : INTEGER; + C_MULT_TYPE : INTEGER; + C_OPTIMIZE_GOAL : INTEGER; + HAS_NEGATE : INTEGER; + SINGLE_OUTPUT : INTEGER; + ROUND : INTEGER; + USE_DSP_CASCADES : INTEGER; + C_THROTTLE_SCHEME : INTEGER; + C_HAS_ACLKEN : INTEGER; + C_HAS_ARESETN : INTEGER; + C_HAS_S_AXIS_A_TUSER : INTEGER; + C_HAS_S_AXIS_A_TLAST : INTEGER; + C_HAS_S_AXIS_B_TUSER : INTEGER; + C_HAS_S_AXIS_B_TLAST : INTEGER; + C_HAS_S_AXIS_CTRL_TUSER : INTEGER; + C_HAS_S_AXIS_CTRL_TLAST : INTEGER; + C_TLAST_RESOLUTION : INTEGER; + C_S_AXIS_A_TDATA_WIDTH : INTEGER; + C_S_AXIS_A_TUSER_WIDTH : INTEGER; + C_S_AXIS_B_TDATA_WIDTH : INTEGER; + C_S_AXIS_B_TUSER_WIDTH : INTEGER; + C_S_AXIS_CTRL_TDATA_WIDTH : INTEGER; + C_S_AXIS_CTRL_TUSER_WIDTH : INTEGER; + C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER; + C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER + ); + PORT ( + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_a_tvalid : IN STD_LOGIC; + s_axis_a_tready : OUT STD_LOGIC; + s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_a_tlast : IN STD_LOGIC; + s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_b_tvalid : IN STD_LOGIC; + s_axis_b_tready : OUT STD_LOGIC; + s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_b_tlast : IN STD_LOGIC; + s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + s_axis_ctrl_tvalid : IN STD_LOGIC; + s_axis_ctrl_tready : OUT STD_LOGIC; + s_axis_ctrl_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_ctrl_tlast : IN STD_LOGIC; + s_axis_ctrl_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + m_axis_dout_tvalid : OUT STD_LOGIC; + m_axis_dout_tready : IN STD_LOGIC; + m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_dout_tlast : OUT STD_LOGIC; + m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + ); + END COMPONENT cmpy_v6_0_17; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 6, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; +BEGIN + U0 : cmpy_v6_0_17 + GENERIC MAP ( + C_VERBOSITY => 0, + C_XDEVICEFAMILY => "zynq", + C_XDEVICE => "xc7z100", + C_A_WIDTH => 12, + C_B_WIDTH => 8, + C_OUT_WIDTH => 21, + C_LATENCY => 4, + C_MULT_TYPE => 0, + C_OPTIMIZE_GOAL => 0, + HAS_NEGATE => 0, + SINGLE_OUTPUT => 0, + ROUND => 0, + USE_DSP_CASCADES => 1, + C_THROTTLE_SCHEME => 3, + C_HAS_ACLKEN => 0, + C_HAS_ARESETN => 0, + C_HAS_S_AXIS_A_TUSER => 0, + C_HAS_S_AXIS_A_TLAST => 0, + C_HAS_S_AXIS_B_TUSER => 0, + C_HAS_S_AXIS_B_TLAST => 0, + C_HAS_S_AXIS_CTRL_TUSER => 0, + C_HAS_S_AXIS_CTRL_TLAST => 0, + C_TLAST_RESOLUTION => 0, + C_S_AXIS_A_TDATA_WIDTH => 32, + C_S_AXIS_A_TUSER_WIDTH => 1, + C_S_AXIS_B_TDATA_WIDTH => 16, + C_S_AXIS_B_TUSER_WIDTH => 1, + C_S_AXIS_CTRL_TDATA_WIDTH => 8, + C_S_AXIS_CTRL_TUSER_WIDTH => 1, + C_M_AXIS_DOUT_TDATA_WIDTH => 48, + C_M_AXIS_DOUT_TUSER_WIDTH => 1 + ) + PORT MAP ( + aclk => aclk, + aclken => '1', + aresetn => '1', + s_axis_a_tvalid => s_axis_a_tvalid, + s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_a_tlast => '0', + s_axis_a_tdata => s_axis_a_tdata, + s_axis_b_tvalid => s_axis_b_tvalid, + s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_b_tlast => '0', + s_axis_b_tdata => s_axis_b_tdata, + s_axis_ctrl_tvalid => '0', + s_axis_ctrl_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_ctrl_tlast => '0', + s_axis_ctrl_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), + m_axis_dout_tvalid => m_axis_dout_tvalid, + m_axis_dout_tready => '0', + m_axis_dout_tdata => m_axis_dout_tdata + ); +END cmpy_12x8_arch; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/demo_tb/tb_fir_prbs7_invert_rep2.vhd b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/demo_tb/tb_fir_prbs7_invert_rep2.vhd new file mode 100644 index 00000000..92c86cbf --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/demo_tb/tb_fir_prbs7_invert_rep2.vhd @@ -0,0 +1,272 @@ +-------------------------------------------------------------------------------- +-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- Description: +-- This is an example testbench for the FIR Compiler IP core. +-- The testbench has been generated by Vivado to accompany the IP core +-- instance you have generated. +-- +-- This testbench is for demonstration purposes only. See note below for +-- instructions on how to use it with your core. +-- +-- See the FIR Compiler product guide for further information +-- about this core. +-- +-------------------------------------------------------------------------------- +-- Using this testbench +-- +-- This testbench instantiates your generated FIR Compiler core +-- instance named "fir_prbs7_invert_rep2". +-- +-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado +-- documentation for details. +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_fir_prbs7_invert_rep2 is +end tb_fir_prbs7_invert_rep2; + +architecture tb of tb_fir_prbs7_invert_rep2 is + + ----------------------------------------------------------------------- + -- Timing constants + ----------------------------------------------------------------------- + constant CLOCK_PERIOD : time := 100 ns; + constant T_HOLD : time := 10 ns; + constant T_STROBE : time := CLOCK_PERIOD - (1 ns); + + ----------------------------------------------------------------------- + -- DUT signals + ----------------------------------------------------------------------- + + -- General signals + signal aclk : std_logic := '0'; -- the master clock + signal aresetn : std_logic := '1'; -- synchronous active low reset + + -- Data slave channel signals + signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid + signal s_axis_data_tready : std_logic := '1'; -- slave is ready + signal s_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload + + -- Data master channel signals + signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid + signal m_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload + + ----------------------------------------------------------------------- + -- Aliases for AXI channel TDATA and TUSER fields + -- These are a convenience for viewing data in a simulator waveform viewer. + -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command + -- to prevent the simulator optimizing away these signals. + ----------------------------------------------------------------------- + + -- Data slave channel alias signals + signal s_axis_data_tdata_data : std_logic_vector(11 downto 0) := (others => '0'); + + -- Data master channel alias signals + signal m_axis_data_tdata_data : std_logic_vector(19 downto 0) := (others => '0'); + + +begin + + ----------------------------------------------------------------------- + -- Instantiate the DUT + ----------------------------------------------------------------------- + + dut : entity work.fir_prbs7_invert_rep2 + port map ( + aclk => aclk, + aresetn => aresetn, + s_axis_data_tvalid => s_axis_data_tvalid, + s_axis_data_tready => s_axis_data_tready, + s_axis_data_tdata => s_axis_data_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); + + ----------------------------------------------------------------------- + -- Generate clock + ----------------------------------------------------------------------- + + clock_gen : process + begin + aclk <= '0'; + wait for CLOCK_PERIOD; + loop + aclk <= '0'; + wait for CLOCK_PERIOD/2; + aclk <= '1'; + wait for CLOCK_PERIOD/2; + end loop; + end process clock_gen; + + ----------------------------------------------------------------------- + -- Generate inputs + ----------------------------------------------------------------------- + + stimuli : process + + -- Procedure to drive a number of input samples with specific data + -- data is the data value to drive on the tdata signal + -- samples is the number of zero-data input samples to drive + procedure drive_data ( data : std_logic_vector(15 downto 0); + samples : natural := 1 ) is + variable ip_count : integer := 0; + begin + ip_count := 0; + loop + s_axis_data_tvalid <= '1'; + s_axis_data_tdata <= data; + loop + wait until rising_edge(aclk); + exit when s_axis_data_tready = '1'; + end loop; + ip_count := ip_count + 1; + wait for T_HOLD; + -- Input rate is 1 input each 4 clock cycles: drive valid inputs at this rate + s_axis_data_tvalid <= '0'; + wait for CLOCK_PERIOD * 3; + exit when ip_count >= samples; + end loop; + end procedure drive_data; + + -- Procedure to drive a number of zero-data input samples + -- samples is the number of zero-data input samples to drive + procedure drive_zeros ( samples : natural := 1 ) is + begin + drive_data((others => '0'), samples); + end procedure drive_zeros; + + -- Procedure to drive an impulse and let the impulse response emerge on the data master channel + -- samples is the number of input samples to drive; default is enough for impulse response output to emerge + procedure drive_impulse ( samples : natural := 279 ) is + variable impulse : std_logic_vector(15 downto 0); + begin + impulse := (others => '0'); -- initialize unused bits to zero + impulse(11 downto 0) := "010000000000"; + drive_data(impulse); + if samples > 1 then + drive_zeros(samples-1); + end if; + end procedure drive_impulse; + + begin + + -- Drive inputs T_HOLD time after rising edge of clock + wait until rising_edge(aclk) and aresetn = '1'; + wait for T_HOLD; + + -- Drive a single impulse and let the impulse response emerge + drive_impulse; + + -- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals + drive_impulse(2); -- start of impulse; data is now zero + s_axis_data_tvalid <= '0'; + wait for CLOCK_PERIOD * 20; -- provide no data for 5 input samples worth + drive_zeros(2); -- 2 normal input samples + s_axis_data_tvalid <= '1'; + wait for CLOCK_PERIOD * 20; -- provide data as fast as the core can accept it for 5 input samples worth + drive_zeros(270); -- back to normal operation + + -- Drive another impulse, during which demonstrate: + -- reset (aresetn) + drive_impulse(82); -- to partway through impulse response + s_axis_data_tvalid <= '0'; + aresetn <= '0'; -- assert reset (active low) + wait for CLOCK_PERIOD * 2; -- hold reset active for 2 clock cycles, as recommended in FIR Compiler Datasheet + aresetn <= '1'; -- deassert reset + drive_impulse; -- send new impulse, following reset + + -- End of test + report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; + wait; + + end process stimuli; + + ----------------------------------------------------------------------- + -- Check outputs + ----------------------------------------------------------------------- + + check_outputs : process + variable check_ok : boolean := true; + begin + + -- Check outputs T_STROBE time after rising edge of clock + wait until rising_edge(aclk); + wait for T_STROBE; + + -- Do not check the output payload values, as this requires the behavioral model + -- which would make this demonstration testbench unwieldy. + -- Instead, check the protocol of the master DATA channel: + -- check that the payload is valid (not X) when TVALID is high + + if m_axis_data_tvalid = '1' and aresetn = '1' then + if is_x(m_axis_data_tdata) then + report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error; + check_ok := false; + end if; + + end if; + + assert check_ok + report "ERROR: terminating test with failures." severity failure; + + end process check_outputs; + + ----------------------------------------------------------------------- + -- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing + ----------------------------------------------------------------------- + + -- Data slave channel alias signals + s_axis_data_tdata_data <= s_axis_data_tdata(11 downto 0); + + -- Data master channel alias signals: update these only when they are valid + m_axis_data_tdata_data <= m_axis_data_tdata(19 downto 0) when m_axis_data_tvalid = '1'; + +end tb; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.veo new file mode 100644 index 00000000..b2df9eca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.veo @@ -0,0 +1,71 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 12 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_prbs7_invert_rep2 your_instance_name ( + .aresetn(aresetn), // input wire aresetn + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tdata(s_axis_data_tdata), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [23 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_prbs7_invert_rep2.v when simulating +// the core, fir_prbs7_invert_rep2. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.vho new file mode 100644 index 00000000..16f7afa7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.vho @@ -0,0 +1,87 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fir_compiler:7.2 +-- IP Revision: 12 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT fir_prbs7_invert_rep2 + PORT ( + aresetn : IN STD_LOGIC; + aclk : IN STD_LOGIC; + s_axis_data_tvalid : IN STD_LOGIC; + s_axis_data_tready : OUT STD_LOGIC; + s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fir_prbs7_invert_rep2 + PORT MAP ( + aresetn => aresetn, + aclk => aclk, + s_axis_data_tvalid => s_axis_data_tvalid, + s_axis_data_tready => s_axis_data_tready, + s_axis_data_tdata => s_axis_data_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file fir_prbs7_invert_rep2.vhd when simulating +-- the core, fir_prbs7_invert_rep2. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.v new file mode 100644 index 00000000..d3f1af42 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1443d4bafada7dc1e0c863ea91378c74e51dc722fffc7f31975ed98b8b2156e2 +size 3097268 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.vhdl new file mode 100644 index 00000000..4c1fdd72 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:95dd57d9721f3b42d8a90e06529d75215410975e1f142885dbff239c1e3814b9 +size 4406730 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.v new file mode 100644 index 00000000..68b03a4e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 19:43:16 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v +// Design : fir_prbs7_invert_rep2 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) +module fir_prbs7_invert_rep2(aresetn, aclk, s_axis_data_tvalid, + s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) +/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */; + input aresetn; + input aclk; + input s_axis_data_tvalid; + output s_axis_data_tready; + input [15:0]s_axis_data_tdata; + output m_axis_data_tvalid; + output [23:0]m_axis_data_tdata; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.vhdl new file mode 100644 index 00000000..558f6ff5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 19:43:16 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl +-- Design : fir_prbs7_invert_rep2 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity fir_prbs7_invert_rep2 is + Port ( + aresetn : in STD_LOGIC; + aclk : in STD_LOGIC; + s_axis_data_tvalid : in STD_LOGIC; + s_axis_data_tready : out STD_LOGIC; + s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_data_tvalid : out STD_LOGIC; + m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ) + ); + +end fir_prbs7_invert_rep2; + +architecture stub of fir_prbs7_invert_rep2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd new file mode 100644 index 00000000..b652e4f5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd @@ -0,0 +1,284 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fir_compiler:7.2 +-- IP Revision: 12 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY fir_compiler_v7_2_12; +USE fir_compiler_v7_2_12.fir_compiler_v7_2_12; + +ENTITY fir_prbs7_invert_rep2 IS + PORT ( + aresetn : IN STD_LOGIC; + aclk : IN STD_LOGIC; + s_axis_data_tvalid : IN STD_LOGIC; + s_axis_data_tready : OUT STD_LOGIC; + s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END fir_prbs7_invert_rep2; + +ARCHITECTURE fir_prbs7_invert_rep2_arch OF fir_prbs7_invert_rep2 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_prbs7_invert_rep2_arch: ARCHITECTURE IS "yes"; + COMPONENT fir_compiler_v7_2_12 IS + GENERIC ( + C_XDEVICEFAMILY : STRING; + C_ELABORATION_DIR : STRING; + C_COMPONENT_NAME : STRING; + C_COEF_FILE : STRING; + C_COEF_FILE_LINES : INTEGER; + C_FILTER_TYPE : INTEGER; + C_INTERP_RATE : INTEGER; + C_DECIM_RATE : INTEGER; + C_ZERO_PACKING_FACTOR : INTEGER; + C_SYMMETRY : INTEGER; + C_NUM_FILTS : INTEGER; + C_NUM_TAPS : INTEGER; + C_NUM_CHANNELS : INTEGER; + C_CHANNEL_PATTERN : STRING; + C_ROUND_MODE : INTEGER; + C_COEF_RELOAD : INTEGER; + C_NUM_RELOAD_SLOTS : INTEGER; + C_COL_MODE : INTEGER; + C_COL_PIPE_LEN : INTEGER; + C_COL_CONFIG : STRING; + C_OPTIMIZATION : INTEGER; + C_DATA_PATH_WIDTHS : STRING; + C_DATA_IP_PATH_WIDTHS : STRING; + C_DATA_PX_PATH_WIDTHS : STRING; + C_DATA_WIDTH : INTEGER; + C_COEF_PATH_WIDTHS : STRING; + C_COEF_WIDTH : INTEGER; + C_DATA_PATH_SRC : STRING; + C_COEF_PATH_SRC : STRING; + C_PX_PATH_SRC : STRING; + C_DATA_PATH_SIGN : STRING; + C_COEF_PATH_SIGN : STRING; + C_ACCUM_PATH_WIDTHS : STRING; + C_OUTPUT_WIDTH : INTEGER; + C_OUTPUT_PATH_WIDTHS : STRING; + C_ACCUM_OP_PATH_WIDTHS : STRING; + C_EXT_MULT_CNFG : STRING; + C_DATA_PATH_PSAMP_SRC : STRING; + C_OP_PATH_PSAMP_SRC : STRING; + C_NUM_MADDS : INTEGER; + C_OPT_MADDS : STRING; + C_OVERSAMPLING_RATE : INTEGER; + C_INPUT_RATE : INTEGER; + C_OUTPUT_RATE : INTEGER; + C_DATA_MEMTYPE : INTEGER; + C_COEF_MEMTYPE : INTEGER; + C_IPBUFF_MEMTYPE : INTEGER; + C_OPBUFF_MEMTYPE : INTEGER; + C_DATAPATH_MEMTYPE : INTEGER; + C_MEM_ARRANGEMENT : INTEGER; + C_DATA_MEM_PACKING : INTEGER; + C_COEF_MEM_PACKING : INTEGER; + C_FILTS_PACKED : INTEGER; + C_LATENCY : INTEGER; + C_HAS_ARESETn : INTEGER; + C_HAS_ACLKEN : INTEGER; + C_DATA_HAS_TLAST : INTEGER; + C_S_DATA_HAS_FIFO : INTEGER; + C_S_DATA_HAS_TUSER : INTEGER; + C_S_DATA_TDATA_WIDTH : INTEGER; + C_S_DATA_TUSER_WIDTH : INTEGER; + C_M_DATA_HAS_TREADY : INTEGER; + C_M_DATA_HAS_TUSER : INTEGER; + C_M_DATA_TDATA_WIDTH : INTEGER; + C_M_DATA_TUSER_WIDTH : INTEGER; + C_HAS_CONFIG_CHANNEL : INTEGER; + C_CONFIG_SYNC_MODE : INTEGER; + C_CONFIG_PACKET_SIZE : INTEGER; + C_CONFIG_TDATA_WIDTH : INTEGER; + C_RELOAD_TDATA_WIDTH : INTEGER + ); + PORT ( + aresetn : IN STD_LOGIC; + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + s_axis_data_tvalid : IN STD_LOGIC; + s_axis_data_tready : OUT STD_LOGIC; + s_axis_data_tlast : IN STD_LOGIC; + s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + s_axis_config_tvalid : IN STD_LOGIC; + s_axis_config_tready : OUT STD_LOGIC; + s_axis_config_tlast : IN STD_LOGIC; + s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_reload_tvalid : IN STD_LOGIC; + s_axis_reload_tready : OUT STD_LOGIC; + s_axis_reload_tlast : IN STD_LOGIC; + s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tready : IN STD_LOGIC; + m_axis_data_tlast : OUT STD_LOGIC; + m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + event_s_data_tlast_missing : OUT STD_LOGIC; + event_s_data_tlast_unexpected : OUT STD_LOGIC; + event_s_data_chanid_incorrect : OUT STD_LOGIC; + event_s_config_tlast_missing : OUT STD_LOGIC; + event_s_config_tlast_unexpected : OUT STD_LOGIC; + event_s_reload_tlast_missing : OUT STD_LOGIC; + event_s_reload_tlast_unexpected : OUT STD_LOGIC + ); + END COMPONENT fir_compiler_v7_2_12; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME aresetn_intf, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST"; +BEGIN + U0 : fir_compiler_v7_2_12 + GENERIC MAP ( + C_XDEVICEFAMILY => "zynq", + C_ELABORATION_DIR => "./", + C_COMPONENT_NAME => "fir_prbs7_invert_rep2", + C_COEF_FILE => "fir_prbs7_invert_rep2.mif", + C_COEF_FILE_LINES => 256, + C_FILTER_TYPE => 0, + C_INTERP_RATE => 1, + C_DECIM_RATE => 1, + C_ZERO_PACKING_FACTOR => 1, + C_SYMMETRY => 0, + C_NUM_FILTS => 1, + C_NUM_TAPS => 256, + C_NUM_CHANNELS => 1, + C_CHANNEL_PATTERN => "fixed", + C_ROUND_MODE => 0, + C_COEF_RELOAD => 0, + C_NUM_RELOAD_SLOTS => 1, + C_COL_MODE => 1, + C_COL_PIPE_LEN => 4, + C_COL_CONFIG => "64", + C_OPTIMIZATION => 0, + C_DATA_PATH_WIDTHS => "12", + C_DATA_IP_PATH_WIDTHS => "12", + C_DATA_PX_PATH_WIDTHS => "12", + C_DATA_WIDTH => 12, + C_COEF_PATH_WIDTHS => "8", + C_COEF_WIDTH => 8, + C_DATA_PATH_SRC => "0", + C_COEF_PATH_SRC => "0", + C_PX_PATH_SRC => "0", + C_DATA_PATH_SIGN => "0", + C_COEF_PATH_SIGN => "0", + C_ACCUM_PATH_WIDTHS => "20", + C_OUTPUT_WIDTH => 20, + C_OUTPUT_PATH_WIDTHS => "20", + C_ACCUM_OP_PATH_WIDTHS => "20", + C_EXT_MULT_CNFG => "none", + C_DATA_PATH_PSAMP_SRC => "0", + C_OP_PATH_PSAMP_SRC => "0", + C_NUM_MADDS => 64, + C_OPT_MADDS => "none", + C_OVERSAMPLING_RATE => 4, + C_INPUT_RATE => 4, + C_OUTPUT_RATE => 4, + C_DATA_MEMTYPE => 0, + C_COEF_MEMTYPE => 2, + C_IPBUFF_MEMTYPE => 0, + C_OPBUFF_MEMTYPE => 0, + C_DATAPATH_MEMTYPE => 0, + C_MEM_ARRANGEMENT => 0, + C_DATA_MEM_PACKING => 0, + C_COEF_MEM_PACKING => 0, + C_FILTS_PACKED => 0, + C_LATENCY => 75, + C_HAS_ARESETn => 1, + C_HAS_ACLKEN => 0, + C_DATA_HAS_TLAST => 0, + C_S_DATA_HAS_FIFO => 0, + C_S_DATA_HAS_TUSER => 0, + C_S_DATA_TDATA_WIDTH => 16, + C_S_DATA_TUSER_WIDTH => 1, + C_M_DATA_HAS_TREADY => 0, + C_M_DATA_HAS_TUSER => 0, + C_M_DATA_TDATA_WIDTH => 24, + C_M_DATA_TUSER_WIDTH => 1, + C_HAS_CONFIG_CHANNEL => 0, + C_CONFIG_SYNC_MODE => 0, + C_CONFIG_PACKET_SIZE => 0, + C_CONFIG_TDATA_WIDTH => 1, + C_RELOAD_TDATA_WIDTH => 1 + ) + PORT MAP ( + aresetn => aresetn, + aclk => aclk, + aclken => '1', + s_axis_data_tvalid => s_axis_data_tvalid, + s_axis_data_tready => s_axis_data_tready, + s_axis_data_tlast => '0', + s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_data_tdata => s_axis_data_tdata, + s_axis_config_tvalid => '0', + s_axis_config_tlast => '0', + s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_reload_tvalid => '0', + s_axis_reload_tlast => '0', + s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tready => '1', + m_axis_data_tdata => m_axis_data_tdata + ); +END fir_prbs7_invert_rep2_arch; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal.veo new file mode 100644 index 00000000..50bf2d8a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal.veo @@ -0,0 +1,83 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + +ila_cal your_instance_name ( + .clk(clk), // input wire clk + + + .probe0(probe0), // input wire [0:0] probe0 + .probe1(probe1), // input wire [0:0] probe1 + .probe2(probe2), // input wire [0:0] probe2 + .probe3(probe3), // input wire [0:0] probe3 + .probe4(probe4), // input wire [0:0] probe4 + .probe5(probe5), // input wire [0:0] probe5 + .probe6(probe6), // input wire [1:0] probe6 + .probe7(probe7), // input wire [11:0] probe7 + .probe8(probe8), // input wire [11:0] probe8 + .probe9(probe9), // input wire [11:0] probe9 + .probe10(probe10), // input wire [11:0] probe10 + .probe11(probe11), // input wire [11:0] probe11 + .probe12(probe12), // input wire [11:0] probe12 + .probe13(probe13), // input wire [11:0] probe13 + .probe14(probe14) // input wire [11:0] probe14 +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file ila_cal when simulating +// the core, ila_cal. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_sim_netlist.v new file mode 100644 index 00000000..c76671ba --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:659f5cf8dc8efa6863d03478e7ec76b0dc971388dad12b416ab4ed2cc4b90f50 +size 2068367 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_sim_netlist.vhdl new file mode 100644 index 00000000..2de68408 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7c6e55b2fc749bde17ec7479eb4844eb5622c1f293562fe4667d305fa2bceb02 +size 3699456 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_stub.v new file mode 100644 index 00000000..74ca158d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_stub.v @@ -0,0 +1,36 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon Apr 3 12:05:41 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/ila_cal_stub.v +// Design : ila_cal +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_cal(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[1:0],probe7[11:0],probe8[11:0],probe9[11:0],probe10[11:0],probe11[11:0],probe12[11:0],probe13[11:0],probe14[11:0]" */; + input clk; + input [0:0]probe0; + input [0:0]probe1; + input [0:0]probe2; + input [0:0]probe3; + input [0:0]probe4; + input [0:0]probe5; + input [1:0]probe6; + input [11:0]probe7; + input [11:0]probe8; + input [11:0]probe9; + input [11:0]probe10; + input [11:0]probe11; + input [11:0]probe12; + input [11:0]probe13; + input [11:0]probe14; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_stub.vhdl new file mode 100644 index 00000000..7e3775d3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/ila_cal_stub.vhdl @@ -0,0 +1,45 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon Apr 3 12:05:41 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/ila_cal_stub.vhdl +-- Design : ila_cal +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_cal is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe3 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe4 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe5 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe12 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe13 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe14 : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + +end ila_cal; + +architecture stub of ila_cal is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[1:0],probe7[11:0],probe8[11:0],probe9[11:0],probe10[11:0],probe11[11:0],probe12[11:0],probe13[11:0],probe14[11:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/sim/ila_cal.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/sim/ila_cal.v new file mode 100644 index 00000000..c5b8b1d7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_cal/sim/ila_cal.v @@ -0,0 +1,90 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module ila_cal ( +clk, + + +probe0, +probe1, +probe2, +probe3, +probe4, +probe5, +probe6, +probe7, +probe8, +probe9, +probe10, +probe11, +probe12, +probe13, +probe14 +); + +input clk; + + +input [0 : 0] probe0; +input [0 : 0] probe1; +input [0 : 0] probe2; +input [0 : 0] probe3; +input [0 : 0] probe4; +input [0 : 0] probe5; +input [1 : 0] probe6; +input [11 : 0] probe7; +input [11 : 0] probe8; +input [11 : 0] probe9; +input [11 : 0] probe10; +input [11 : 0] probe11; +input [11 : 0] probe12; +input [11 : 0] probe13; +input [11 : 0] probe14; + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp.veo new file mode 100644 index 00000000..85d4f6e3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp.veo @@ -0,0 +1,92 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + +ila_freq_comp your_instance_name ( + .clk(clk), // input wire clk + + + .probe0(probe0), // input wire [0:0] probe0 + .probe1(probe1), // input wire [17:0] probe1 + .probe2(probe2), // input wire [17:0] probe2 + .probe3(probe3), // input wire [17:0] probe3 + .probe4(probe4), // input wire [17:0] probe4 + .probe5(probe5), // input wire [17:0] probe5 + .probe6(probe6), // input wire [17:0] probe6 + .probe7(probe7), // input wire [17:0] probe7 + .probe8(probe8), // input wire [17:0] probe8 + .probe9(probe9), // input wire [7:0] probe9 + .probe10(probe10), // input wire [7:0] probe10 + .probe11(probe11), // input wire [7:0] probe11 + .probe12(probe12), // input wire [7:0] probe12 + .probe13(probe13), // input wire [0:0] probe13 + .probe14(probe14), // input wire [2:0] probe14 + .probe15(probe15), // input wire [11:0] probe15 + .probe16(probe16), // input wire [11:0] probe16 + .probe17(probe17), // input wire [17:0] probe17 + .probe18(probe18), // input wire [17:0] probe18 + .probe19(probe19), // input wire [17:0] probe19 + .probe20(probe20), // input wire [17:0] probe20 + .probe21(probe21), // input wire [17:0] probe21 + .probe22(probe22), // input wire [31:0] probe22 + .probe23(probe23) // input wire [11:0] probe23 +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file ila_freq_comp when simulating +// the core, ila_freq_comp. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.v new file mode 100644 index 00000000..e946482d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:28bbd13808888eeec92677d70a4630bd5f305d65d412febedaf1a0fbf5ff8655 +size 19954841 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.vhdl new file mode 100644 index 00000000..81bb1801 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dc4cd60578e588c984c2a69ce396150094fc3f9d1d7fc6ee0c37d7812b086045 +size 23892851 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.v new file mode 100644 index 00000000..f31ad22b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.v @@ -0,0 +1,46 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Tue May 9 13:39:41 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v +// Design : ila_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, + probe18, probe19, probe20, probe21, probe22, probe23) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[31:0],probe23[11:0]" */; + input clk; + input [0:0]probe0; + input [17:0]probe1; + input [17:0]probe2; + input [17:0]probe3; + input [17:0]probe4; + input [17:0]probe5; + input [17:0]probe6; + input [17:0]probe7; + input [17:0]probe8; + input [7:0]probe9; + input [7:0]probe10; + input [7:0]probe11; + input [7:0]probe12; + input [0:0]probe13; + input [2:0]probe14; + input [11:0]probe15; + input [11:0]probe16; + input [17:0]probe17; + input [17:0]probe18; + input [17:0]probe19; + input [17:0]probe20; + input [17:0]probe21; + input [31:0]probe22; + input [11:0]probe23; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.vhdl new file mode 100644 index 00000000..c8f4b61c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.vhdl @@ -0,0 +1,54 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Tue May 9 13:39:41 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl +-- Design : ila_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_freq_comp is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe13 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe14 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + probe15 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe16 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe17 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe18 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe19 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe20 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe21 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe22 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe23 : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + +end ila_freq_comp; + +architecture stub of ila_freq_comp is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[31:0],probe23[11:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/sim/ila_freq_comp.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/sim/ila_freq_comp.v new file mode 100644 index 00000000..61ecdc43 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/sim/ila_freq_comp.v @@ -0,0 +1,108 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module ila_freq_comp ( +clk, + + +probe0, +probe1, +probe2, +probe3, +probe4, +probe5, +probe6, +probe7, +probe8, +probe9, +probe10, +probe11, +probe12, +probe13, +probe14, +probe15, +probe16, +probe17, +probe18, +probe19, +probe20, +probe21, +probe22, +probe23 +); + +input clk; + + +input [0 : 0] probe0; +input [17 : 0] probe1; +input [17 : 0] probe2; +input [17 : 0] probe3; +input [17 : 0] probe4; +input [17 : 0] probe5; +input [17 : 0] probe6; +input [17 : 0] probe7; +input [17 : 0] probe8; +input [7 : 0] probe9; +input [7 : 0] probe10; +input [7 : 0] probe11; +input [7 : 0] probe12; +input [0 : 0] probe13; +input [2 : 0] probe14; +input [11 : 0] probe15; +input [11 : 0] probe16; +input [17 : 0] probe17; +input [17 : 0] probe18; +input [17 : 0] probe19; +input [17 : 0] probe20; +input [17 : 0] probe21; +input [31 : 0] probe22; +input [11 : 0] probe23; + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18.veo new file mode 100644 index 00000000..147c02f3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18.veo @@ -0,0 +1,68 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:mult_gen:12.0 +// IP Revision: 15 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +mult_18x18 your_instance_name ( + .CLK(CLK), // input wire CLK + .A(A), // input wire [17 : 0] A + .B(B), // input wire [17 : 0] B + .P(P) // output wire [35 : 0] P +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file mult_18x18.v when simulating +// the core, mult_18x18. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18.vho new file mode 100644 index 00000000..b9157e2a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18.vho @@ -0,0 +1,81 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:mult_gen:12.0 +-- IP Revision: 15 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT mult_18x18 + PORT ( + CLK : IN STD_LOGIC; + A : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + B : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + P : OUT STD_LOGIC_VECTOR(35 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : mult_18x18 + PORT MAP ( + CLK => CLK, + A => A, + B => B, + P => P + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file mult_18x18.vhd when simulating +-- the core, mult_18x18. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_sim_netlist.v new file mode 100644 index 00000000..0133b6dc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6f1851b0ea6dbdb3391593fb3405cd201581c9f4fbd0c99cca1b9a9b0ffc891f +size 602664 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_sim_netlist.vhdl new file mode 100644 index 00000000..a9532eca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8c549a092d1c9191779fc8f0fdedea59f8322da1932e55224cf9426c95f883bb +size 798082 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_stub.v new file mode 100644 index 00000000..e64951e6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:26 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.v +// Design : mult_18x18 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "mult_gen_v12_0_15,Vivado 2019.1.3" *) +module mult_18x18(CLK, A, B, P) +/* synthesis syn_black_box black_box_pad_pin="CLK,A[17:0],B[17:0],P[35:0]" */; + input CLK; + input [17:0]A; + input [17:0]B; + output [35:0]P; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_stub.vhdl new file mode 100644 index 00000000..ff7c77f8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/mult_18x18_stub.vhdl @@ -0,0 +1,33 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:26 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.vhdl +-- Design : mult_18x18 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity mult_18x18 is + Port ( + CLK : in STD_LOGIC; + A : in STD_LOGIC_VECTOR ( 17 downto 0 ); + B : in STD_LOGIC_VECTOR ( 17 downto 0 ); + P : out STD_LOGIC_VECTOR ( 35 downto 0 ) + ); + +end mult_18x18; + +architecture stub of mult_18x18 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "CLK,A[17:0],B[17:0],P[35:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "mult_gen_v12_0_15,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/sim/mult_18x18.vhd b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/sim/mult_18x18.vhd new file mode 100644 index 00000000..5361ec36 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/mult_18x18/sim/mult_18x18.vhd @@ -0,0 +1,145 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:mult_gen:12.0 +-- IP Revision: 15 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY mult_gen_v12_0_15; +USE mult_gen_v12_0_15.mult_gen_v12_0_15; + +ENTITY mult_18x18 IS + PORT ( + CLK : IN STD_LOGIC; + A : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + B : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + P : OUT STD_LOGIC_VECTOR(35 DOWNTO 0) + ); +END mult_18x18; + +ARCHITECTURE mult_18x18_arch OF mult_18x18 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_18x18_arch: ARCHITECTURE IS "yes"; + COMPONENT mult_gen_v12_0_15 IS + GENERIC ( + C_VERBOSITY : INTEGER; + C_MODEL_TYPE : INTEGER; + C_OPTIMIZE_GOAL : INTEGER; + C_XDEVICEFAMILY : STRING; + C_HAS_CE : INTEGER; + C_HAS_SCLR : INTEGER; + C_LATENCY : INTEGER; + C_A_WIDTH : INTEGER; + C_A_TYPE : INTEGER; + C_B_WIDTH : INTEGER; + C_B_TYPE : INTEGER; + C_OUT_HIGH : INTEGER; + C_OUT_LOW : INTEGER; + C_MULT_TYPE : INTEGER; + C_CE_OVERRIDES_SCLR : INTEGER; + C_CCM_IMP : INTEGER; + C_B_VALUE : STRING; + C_HAS_ZERO_DETECT : INTEGER; + C_ROUND_OUTPUT : INTEGER; + C_ROUND_PT : INTEGER + ); + PORT ( + CLK : IN STD_LOGIC; + A : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + B : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + CE : IN STD_LOGIC; + SCLR : IN STD_LOGIC; + P : OUT STD_LOGIC_VECTOR(35 DOWNTO 0) + ); + END COMPONENT mult_gen_v12_0_15; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF P: SIGNAL IS "XIL_INTERFACENAME p_intf, LAYERED_METADATA undef"; + ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF B: SIGNAL IS "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef"; + ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF A: SIGNAL IS "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef"; + ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF p_intf:b_intf:a_intf, ASSOCIATED_RESET sclr, ASSOCIATED_CLKEN ce, FREQ_HZ 10000000, PHASE 0.000, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK"; +BEGIN + U0 : mult_gen_v12_0_15 + GENERIC MAP ( + C_VERBOSITY => 0, + C_MODEL_TYPE => 0, + C_OPTIMIZE_GOAL => 1, + C_XDEVICEFAMILY => "zynq", + C_HAS_CE => 0, + C_HAS_SCLR => 0, + C_LATENCY => 5, + C_A_WIDTH => 18, + C_A_TYPE => 0, + C_B_WIDTH => 18, + C_B_TYPE => 0, + C_OUT_HIGH => 35, + C_OUT_LOW => 0, + C_MULT_TYPE => 0, + C_CE_OVERRIDES_SCLR => 0, + C_CCM_IMP => 0, + C_B_VALUE => "10000001", + C_HAS_ZERO_DETECT => 0, + C_ROUND_OUTPUT => 0, + C_ROUND_PT => 0 + ) + PORT MAP ( + CLK => CLK, + A => A, + B => B, + CE => '1', + SCLR => '0', + P => P + ); +END mult_18x18_arch; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo new file mode 100644 index 00000000..47c2391f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo @@ -0,0 +1,67 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 3 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +rom_freq_word your_instance_name ( + .clka(clka), // input wire clka + .addra(addra), // input wire [6 : 0] addra + .douta(douta) // output wire [15 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file rom_freq_word.v when simulating +// the core, rom_freq_word. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho new file mode 100644 index 00000000..30af5116 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho @@ -0,0 +1,79 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 3 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT rom_freq_word + PORT ( + clka : IN STD_LOGIC; + addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : rom_freq_word + PORT MAP ( + clka => clka, + addra => addra, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file rom_freq_word.vhd when simulating +-- the core, rom_freq_word. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v new file mode 100644 index 00000000..4efbdb17 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d8970a9429c1d09aa63a439ff99735db17ada2a4562d08614a0cc8de0d18b647 +size 28696 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl new file mode 100644 index 00000000..fb2748a9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:08a5871f0563ea46fef07f09505d439930977a1dd68fd0168dddb2826b39a3a0 +size 42195 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v new file mode 100644 index 00000000..b0ec3d6e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 17:28:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module rom_freq_word(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[15:0]" */; + input clka; + input [6:0]addra; + output [15:0]douta; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl new file mode 100644 index 00000000..b7be094b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 17:28:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity rom_freq_word is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end rom_freq_word; + +architecture stub of rom_freq_word is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v new file mode 100644 index 00000000..6fba0ddd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v @@ -0,0 +1,211 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 3 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module rom_freq_word ( + clka, + addra, + douta +); + +(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) +input wire clka; +(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) +input wire [6 : 0] addra; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) +output wire [15 : 0] douta; + + blk_mem_gen_v8_4_3 #( + .C_FAMILY("zynq"), + .C_XDEVICEFAMILY("zynq"), + .C_ELABORATION_DIR("./"), + .C_INTERFACE_TYPE(0), + .C_AXI_TYPE(1), + .C_AXI_SLAVE_TYPE(0), + .C_USE_BRAM_BLOCK(0), + .C_ENABLE_32BIT_ADDRESS(0), + .C_CTRL_ECC_ALGO("NONE"), + .C_HAS_AXI_ID(0), + .C_AXI_ID_WIDTH(4), + .C_MEM_TYPE(3), + .C_BYTE_SIZE(9), + .C_ALGORITHM(1), + .C_PRIM_TYPE(1), + .C_LOAD_INIT_FILE(1), + .C_INIT_FILE_NAME("rom_freq_word.mif"), + .C_INIT_FILE("rom_freq_word.mem"), + .C_USE_DEFAULT_DATA(0), + .C_DEFAULT_DATA("0"), + .C_HAS_RSTA(0), + .C_RST_PRIORITY_A("CE"), + .C_RSTRAM_A(0), + .C_INITA_VAL("0"), + .C_HAS_ENA(0), + .C_HAS_REGCEA(0), + .C_USE_BYTE_WEA(0), + .C_WEA_WIDTH(1), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_WIDTH_A(16), + .C_READ_WIDTH_A(16), + .C_WRITE_DEPTH_A(81), + .C_READ_DEPTH_A(81), + .C_ADDRA_WIDTH(7), + .C_HAS_RSTB(0), + .C_RST_PRIORITY_B("CE"), + .C_RSTRAM_B(0), + .C_INITB_VAL("0"), + .C_HAS_ENB(0), + .C_HAS_REGCEB(0), + .C_USE_BYTE_WEB(0), + .C_WEB_WIDTH(1), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_B(16), + .C_READ_WIDTH_B(16), + .C_WRITE_DEPTH_B(81), + .C_READ_DEPTH_B(81), + .C_ADDRB_WIDTH(7), + .C_HAS_MEM_OUTPUT_REGS_A(1), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_MUX_PIPELINE_STAGES(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_USE_SOFTECC(0), + .C_USE_ECC(0), + .C_EN_ECC_PIPE(0), + .C_READ_LATENCY_A(1), + .C_READ_LATENCY_B(1), + .C_HAS_INJECTERR(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_COMMON_CLK(0), + .C_DISABLE_WARN_BHV_COLL(0), + .C_EN_SLEEP_PIN(0), + .C_USE_URAM(0), + .C_EN_RDADDRA_CHG(0), + .C_EN_RDADDRB_CHG(0), + .C_EN_DEEPSLEEP_PIN(0), + .C_EN_SHUTDOWN_PIN(0), + .C_EN_SAFETY_CKT(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_COUNT_36K_BRAM("0"), + .C_COUNT_18K_BRAM("1"), + .C_EST_POWER_SUMMARY("Estimated Power for IP : 2.7096 mW") + ) inst ( + .clka(clka), + .rsta(1'D0), + .ena(1'D0), + .regcea(1'D0), + .wea(1'B0), + .addra(addra), + .dina(16'B0), + .douta(douta), + .clkb(1'D0), + .rstb(1'D0), + .enb(1'D0), + .regceb(1'D0), + .web(1'B0), + .addrb(7'B0), + .dinb(16'B0), + .doutb(), + .injectsbiterr(1'D0), + .injectdbiterr(1'D0), + .eccpipece(1'D0), + .sbiterr(), + .dbiterr(), + .rdaddrecc(), + .sleep(1'D0), + .deepsleep(1'D0), + .shutdown(1'D0), + .rsta_busy(), + .rstb_busy(), + .s_aclk(1'H0), + .s_aresetn(1'D0), + .s_axi_awid(4'B0), + .s_axi_awaddr(32'B0), + .s_axi_awlen(8'B0), + .s_axi_awsize(3'B0), + .s_axi_awburst(2'B0), + .s_axi_awvalid(1'D0), + .s_axi_awready(), + .s_axi_wdata(16'B0), + .s_axi_wstrb(1'B0), + .s_axi_wlast(1'D0), + .s_axi_wvalid(1'D0), + .s_axi_wready(), + .s_axi_bid(), + .s_axi_bresp(), + .s_axi_bvalid(), + .s_axi_bready(1'D0), + .s_axi_arid(4'B0), + .s_axi_araddr(32'B0), + .s_axi_arlen(8'B0), + .s_axi_arsize(3'B0), + .s_axi_arburst(2'B0), + .s_axi_arvalid(1'D0), + .s_axi_arready(), + .s_axi_rid(), + .s_axi_rdata(), + .s_axi_rresp(), + .s_axi_rlast(), + .s_axi_rvalid(), + .s_axi_rready(1'D0), + .s_axi_injectsbiterr(1'D0), + .s_axi_injectdbiterr(1'D0), + .s_axi_sbiterr(), + .s_axi_dbiterr(), + .s_axi_rdaddrecc() + ); +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v new file mode 100644 index 00000000..0872dbf0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v @@ -0,0 +1,61 @@ +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module vio_clk_ld_rd ( +clk, +probe_in0,probe_in1 + +); + +input clk; +input [0 : 0] probe_in0; +input [0 : 0] probe_in1; + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd.veo new file mode 100644 index 00000000..4ac2b7b3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd.veo @@ -0,0 +1,67 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:vio:3.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +vio_clk_ld_rd your_instance_name ( + .clk(clk), // input wire clk + .probe_in0(probe_in0), // input wire [0 : 0] probe_in0 + .probe_in1(probe_in1) // input wire [0 : 0] probe_in1 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file vio_clk_ld_rd.v when simulating +// the core, vio_clk_ld_rd. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd.vho new file mode 100644 index 00000000..53ada7ac --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd.vho @@ -0,0 +1,79 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:vio:3.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT vio_clk_ld_rd + PORT ( + clk : IN STD_LOGIC; + probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : vio_clk_ld_rd + PORT MAP ( + clk => clk, + probe_in0 => probe_in0, + probe_in1 => probe_in1 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file vio_clk_ld_rd.vhd when simulating +-- the core, vio_clk_ld_rd. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_sim_netlist.v new file mode 100644 index 00000000..e5bb7b91 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2e2845802fb43805eb0abca43b0b80d0e9da80fe287ac736bdc3a136bc2078ee +size 299252 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_sim_netlist.vhdl new file mode 100644 index 00000000..20c4e6bd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:23e10aff13ad3a41068b9f53257a46891e4d59ec35e64c937f95d93a94d83b59 +size 562586 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_stub.v new file mode 100644 index 00000000..7f910084 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu Mar 30 16:42:41 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/vio_clk_ld_rd_stub.v +// Design : vio_clk_ld_rd +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_clk_ld_rd(clk, probe_in0, probe_in1) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[0:0]" */; + input clk; + input [0:0]probe_in0; + input [0:0]probe_in1; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_stub.vhdl new file mode 100644 index 00000000..3cd2c0ba --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_clk_ld_rd/vio_clk_ld_rd_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu Mar 30 16:42:42 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/vio_clk_ld_rd_stub.vhdl +-- Design : vio_clk_ld_rd +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_clk_ld_rd is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end vio_clk_ld_rd; + +architecture stub of vio_clk_ld_rd is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/hdl/vio_v3_0_20_vio_include.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/hdl/vio_v3_0_20_vio_include.v new file mode 100644 index 00000000..0673f57f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/hdl/vio_v3_0_20_vio_include.v @@ -0,0 +1,283 @@ +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "XILINX" +`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`pragma protect key_block +GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx +XWe4lBDDrw== + +`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH +9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c +eVhT3XSIJDvufMyiJUc= + +`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit +pNc3Ov7QvW8kjTq3JHFuCf7SmCYRrmElQv0XobTk6mnMb4khaXw9wTP8YMS0XAqk3Bksal+aKfvX +LL/afyM4UwBfiIb04ZgvhdOlp/dkCqWqZyDL2qVScyGrZcDCW3CCZTVQO29hqMLZP5S82keXpBv3 +5J7nHHbQ3n4dxsRykYtJtwg7JDyqGHiwhj1HDtjhG+LX9ry1wy5YgvxrzSfKoouAeHCKXcG7TY0a +sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ== + +`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +ItrqCM44kZl0WwWeSAjetSYD0fPwYZdVjFp5cRl5XZyoYOMWKCVEXncinM06x/MDVlkYiXgz2Xqn +6ui7jR7RwOKALvqoqdehIoXZUA/5yPMntFpxPcFIY1DonBI4CuMjhqCuB2RkxKNIco5Z7/QxCk49 +MCUlvIFRd2MXM+zvhCRdja7e9blnwJEUETukq+EKuAwuR3+VN3uzCXsNtgBqMZa2CyM6Z60fStuc +v1eiDP/hxOimuSfsS7evakl5WMjgZuj4Jld1+y5hTOuPvw4+s3KIb2ejIH2r/I7ui7sWUZTah36a +4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A== + +`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v +ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX +cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC +xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa +draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg== + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv +j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO +R19uHYIhWP+7IpmjTiQ= + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM +kLLATubglrp6DudyaIY943skTmlH+as6fKaHODrTcy4CDIP4kKrok/7y1rBI6+YAfN3ZIW+45MiV +cHuhXHXxxXblzCT6obAZK5QUCP2qZKgO0jjI1RD7ZEJuS/mX5wkIAvOe8L1HBkyUsRq6Cu30W6u9 +7VI3LOy7TZqb6Nix6Ok85ylO82KP12tdXY2IRivakKu4fdWQ6vc3ARiefSR0+RDmE/eZzhzQbt26 +mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q== + +`pragma protect data_method = "AES128-CBC" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464) +`pragma protect data_block +vLDJJUgjrlRfGtI6e1+Byt5lDBB9Oezy8FH9Uy/Lem9icZpnVjts8rEqPHcw31BJ5u3y4ePWkCUm +QQfQ8vh3WaO2dCX+QhbDMTmPaIe/t8nHJKefrbW5OY3eRKkptlVSIFCFITpJlzyfpSe0CsF+dWLc +F4J0aJzlQEKkTcCFk2ey1erWcvHgIf6eCwkGouO/COjRPomcaMzJt3ty3PwhKodmumGUICNXKjG/ +lH5VI4pSkr0hpeNp/WZhHstrrYJB7GSwMCqfL0IH36wCF3R29Yjp7ouoogJ4+imS5vnMJpU2Czmi +PFyY3LiBeZ4VP5b8Iv0AK4XoJtM3XG9iTBAC/oslCJUtBhINFPia8EueAVn178qtq+htmZXlEAbM +O43w6xZ55fggub8NiHe8M4qAhDC0nwv3LBVndn8xEKF+13iwSiqhLjU1Cya8z+0j0TUExIeVQyri +OXh0d9oxCJ2lfPtNjHZ3LkjbMLvzdJG8pBuDtx5952IJrwkJIaT76aOEs7XK8O+cfrtfhh1fPpY1 +XTzoMx95+Qp7Ay2J8NObIZHBuUKX2ORE3b7zSBW5FPRjaxTibHQ2blQzoAbo5y5f30hxOHsi0+Xe +D4bwHKzoBpsdKAyvlKom17BBx5Q5KccIElz3z9ulgthM6zwAWmMVPzQnJAhmz3Hl3t0m7+YNA4Ia +cg/H8tiXcV6CEnRuaFRr8dvkZAlT16o4u+tEwi85XgpkoApFQ7EytG673+LigwZbb2C7khwEoIiw +1LN4Eh9i2WsLPaEipn3q58x1rH4/MEzwsGw7loWE4BkCf+n5QAWYc/nk4xfSwFTBvxs6sPejsrRX +qbtO8ZOnKuVTT2ZLwEtvGrf+Ii1Xymt1JsQt7Z0QBWTykLt0ZhWTrPnMg/zcRxyRCDNYWVJx8JKC +Fjg1XzSDYIYff4HaLPjmiu5sPEXaKTQJvaZa52Dq87oKwWI0A3g0ymKK7UVXrmX/odtLOlHIxuhy +JnruUntWueD34KJMT2lBO7AP0g/OmHDI6v72Q/2Tk66QaWfnnDJl6qRN2WDuGyNuwSflbEGQiK02 +vyM4a6K9KN70ev9aLX4d2m7Uo9n4GFbdvjakrlHDS/K+TRs6XmOa+y8ErWxn9Pfy9UyRrFg1TdQb +Zk69XUdoQZ6CNWoKazZHaJ5p5+6nk/G0nm8LR039U2sqH+B1hJMuvFvsx4NzEoYpE1jNsiy4B9Ta +ArVNSpGuZCA4Juifia1UC8m+mMYsLBACf9YX/Uua3EeOfU2CEi5koPuBzR/QKb/1oRa3x2oux2Cf ++p+HcJdQfSOpF6AkpWZLChsoTMd2F24Ztmjz3/vNIapPf4rcObfDEJwayu7hSrsslcCIcoXdojo4 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b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/sim/vio_freq_comp.v @@ -0,0 +1,67 @@ +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module vio_freq_comp ( +clk, +probe_in0, +probe_out0, +probe_out1, +probe_out2, +probe_out3 +); + +input clk; +input [0 : 0] probe_in0; + +output reg [0 : 0] probe_out0 = 'h0 ; +output reg [7 : 0] probe_out1 = 'h0A ; +output reg [0 : 0] probe_out2 = 'h0 ; +output reg [31 : 0] probe_out3 = 'h00000000 ; + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo new file mode 100644 index 00000000..ae201a7c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:vio:3.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +vio_freq_comp your_instance_name ( + .clk(clk), // input wire clk + .probe_in0(probe_in0), // input wire [0 : 0] probe_in0 + .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [7 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 + .probe_out3(probe_out3) // output wire [31 : 0] probe_out3 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file vio_freq_comp.v when simulating +// the core, vio_freq_comp. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho new file mode 100644 index 00000000..72f0bda5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:vio:3.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT vio_freq_comp + PORT ( + clk : IN STD_LOGIC; + probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : vio_freq_comp + PORT MAP ( + clk => clk, + probe_in0 => probe_in0, + probe_out0 => probe_out0, + probe_out1 => probe_out1, + probe_out2 => probe_out2, + probe_out3 => probe_out3 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file vio_freq_comp.vhd when simulating +-- the core, vio_freq_comp. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v new file mode 100644 index 00000000..daabb4af --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c34539843f7fa4c5906209eef95783110cbf58f52a239344578ff4d3cfabfab3 +size 347789 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl new file mode 100644 index 00000000..ced3f879 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ab1d7e314e1d93fce13386e493892ccc6fd24d37980345a48e6d890ba0520334 +size 625987 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v new file mode 100644 index 00000000..85124391 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:24 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v +// Design : vio_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]" */; + input clk; + input [0:0]probe_in0; + output [0:0]probe_out0; + output [7:0]probe_out1; + output [0:0]probe_out2; + output [31:0]probe_out3; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl new file mode 100644 index 00000000..015c276d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:24 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl +-- Design : vio_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_freq_comp is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end vio_freq_comp; + +architecture stub of vio_freq_comp is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/hdl/vio_v3_0_20_vio_include.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/hdl/vio_v3_0_20_vio_include.v new file mode 100644 index 00000000..0673f57f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/hdl/vio_v3_0_20_vio_include.v @@ -0,0 +1,283 @@ +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "XILINX" +`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`pragma protect key_block +GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx +XWe4lBDDrw== + +`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH +9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c +eVhT3XSIJDvufMyiJUc= + +`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit +pNc3Ov7QvW8kjTq3JHFuCf7SmCYRrmElQv0XobTk6mnMb4khaXw9wTP8YMS0XAqk3Bksal+aKfvX +LL/afyM4UwBfiIb04ZgvhdOlp/dkCqWqZyDL2qVScyGrZcDCW3CCZTVQO29hqMLZP5S82keXpBv3 +5J7nHHbQ3n4dxsRykYtJtwg7JDyqGHiwhj1HDtjhG+LX9ry1wy5YgvxrzSfKoouAeHCKXcG7TY0a +sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ== + +`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +ItrqCM44kZl0WwWeSAjetSYD0fPwYZdVjFp5cRl5XZyoYOMWKCVEXncinM06x/MDVlkYiXgz2Xqn +6ui7jR7RwOKALvqoqdehIoXZUA/5yPMntFpxPcFIY1DonBI4CuMjhqCuB2RkxKNIco5Z7/QxCk49 +MCUlvIFRd2MXM+zvhCRdja7e9blnwJEUETukq+EKuAwuR3+VN3uzCXsNtgBqMZa2CyM6Z60fStuc +v1eiDP/hxOimuSfsS7evakl5WMjgZuj4Jld1+y5hTOuPvw4+s3KIb2ejIH2r/I7ui7sWUZTah36a +4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A== + +`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v +ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX +cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC +xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa +draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg== + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv +j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO +R19uHYIhWP+7IpmjTiQ= + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM +kLLATubglrp6DudyaIY943skTmlH+as6fKaHODrTcy4CDIP4kKrok/7y1rBI6+YAfN3ZIW+45MiV +cHuhXHXxxXblzCT6obAZK5QUCP2qZKgO0jjI1RD7ZEJuS/mX5wkIAvOe8L1HBkyUsRq6Cu30W6u9 +7VI3LOy7TZqb6Nix6Ok85ylO82KP12tdXY2IRivakKu4fdWQ6vc3ARiefSR0+RDmE/eZzhzQbt26 +mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q== + +`pragma protect data_method = "AES128-CBC" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464) +`pragma protect data_block +vLDJJUgjrlRfGtI6e1+Byt5lDBB9Oezy8FH9Uy/Lem9icZpnVjts8rEqPHcw31BJ5u3y4ePWkCUm +QQfQ8vh3WaO2dCX+QhbDMTmPaIe/t8nHJKefrbW5OY3eRKkptlVSIFCFITpJlzyfpSe0CsF+dWLc +F4J0aJzlQEKkTcCFk2ey1erWcvHgIf6eCwkGouO/COjRPomcaMzJt3ty3PwhKodmumGUICNXKjG/ +lH5VI4pSkr0hpeNp/WZhHstrrYJB7GSwMCqfL0IH36wCF3R29Yjp7ouoogJ4+imS5vnMJpU2Czmi +PFyY3LiBeZ4VP5b8Iv0AK4XoJtM3XG9iTBAC/oslCJUtBhINFPia8EueAVn178qtq+htmZXlEAbM +O43w6xZ55fggub8NiHe8M4qAhDC0nwv3LBVndn8xEKF+13iwSiqhLjU1Cya8z+0j0TUExIeVQyri +OXh0d9oxCJ2lfPtNjHZ3LkjbMLvzdJG8pBuDtx5952IJrwkJIaT76aOEs7XK8O+cfrtfhh1fPpY1 +XTzoMx95+Qp7Ay2J8NObIZHBuUKX2ORE3b7zSBW5FPRjaxTibHQ2blQzoAbo5y5f30hxOHsi0+Xe +D4bwHKzoBpsdKAyvlKom17BBx5Q5KccIElz3z9ulgthM6zwAWmMVPzQnJAhmz3Hl3t0m7+YNA4Ia +cg/H8tiXcV6CEnRuaFRr8dvkZAlT16o4u+tEwi85XgpkoApFQ7EytG673+LigwZbb2C7khwEoIiw +1LN4Eh9i2WsLPaEipn3q58x1rH4/MEzwsGw7loWE4BkCf+n5QAWYc/nk4xfSwFTBvxs6sPejsrRX +qbtO8ZOnKuVTT2ZLwEtvGrf+Ii1Xymt1JsQt7Z0QBWTykLt0ZhWTrPnMg/zcRxyRCDNYWVJx8JKC +Fjg1XzSDYIYff4HaLPjmiu5sPEXaKTQJvaZa52Dq87oKwWI0A3g0ymKK7UVXrmX/odtLOlHIxuhy +JnruUntWueD34KJMT2lBO7AP0g/OmHDI6v72Q/2Tk66QaWfnnDJl6qRN2WDuGyNuwSflbEGQiK02 +vyM4a6K9KN70ev9aLX4d2m7Uo9n4GFbdvjakrlHDS/K+TRs6XmOa+y8ErWxn9Pfy9UyRrFg1TdQb +Zk69XUdoQZ6CNWoKazZHaJ5p5+6nk/G0nm8LR039U2sqH+B1hJMuvFvsx4NzEoYpE1jNsiy4B9Ta +ArVNSpGuZCA4Juifia1UC8m+mMYsLBACf9YX/Uua3EeOfU2CEi5koPuBzR/QKb/1oRa3x2oux2Cf ++p+HcJdQfSOpF6AkpWZLChsoTMd2F24Ztmjz3/vNIapPf4rcObfDEJwayu7hSrsslcCIcoXdojo4 +VXLn2QFVUYMgSq3pYGFywvmQTA5x/JAfOcWO8IBKdixvS3F6xSTwH8JaKocC0735inh65PwNjS9F +2KIwvgHQvLpCxNny+0NvSQ7ETTouC6xXj+EUv4bGpml7J3HNjixHtTPfYXf7cl0mqQmUDJu0wLkp +WuvXFDvCxpwSZ5qw+1H5MPeue3MeB1Z6Ibu51Fs1EwnAe/g9C0Mo1XDCD6LfVjvpZYE62HzlzF/K +IJoLfeJT0O0VhjqhC3+M3TGXHNYm6chuUtfNR31cC7WgG/QiHYOVySvp3zljDZWrxsgHO+JwhbQC +n8ALL+g50X6+uS5w/HkFBsxwCIocmViJb0ojg1j2ncsUjwwEqkDBprVPYFh6Zimk5SJ9f3RO6pQj +saDd3hitIgpMf1ha8rpCYBkwqBTogxXfwijLMplBdGWVGSSSnnp6jTnWb0sV2VPA1l2X6Iq+pomM +jilYYfQ2dBuXFEMpQpwDC3/8N4YxpDZWX3gtyK2XV+2BcRONvrl/naflTsXxuXAhSxOBqggJw7pL +HvsOGKk0ng6uKC5yQPc6Q0SbWwwT54D9vLM4U1OiRKPpL9S1YXak+W8ZCXqdHkQNlUlm21ssL4dl +Et7q9IF5Vil/wnUjm0nJxVZ4QJU/uN7icrtnrvAf1gVLwK3fpC0ed6ku9s7Lq1KvNb7NEPDrOu3Q +hg+xhyl9MJTquidnbUsYlHdTvVzxIkI4q/1kx5mkbEjiIWG0R+haIwSqhTCdxpxxTgm+LGAtWJ4W +lEuCQ2VEu3cyamx3PWNKPt+CE1VayIkgGqEBXIaGpwkymL0y6hkgrA+q+2msQq245iR7XC83U26E +yb3da4UnYxL7g5WjJCSfCdNVOkKS1Yl9VZ6XSW5RFwWIdURQyewZxfPKaJWsDAGfpRftpZ2mOfIl +DP1TwLOJrgsh3QI82hOYlUbHmcPIFMH3Pqp4OpbOBRcPcZhabwMA3pidOtbloqo5pRGblsO79JSJ +OdbTH0XVln2LAlQ0bOmaMt9/rOwfexnMgActW5gvaaxAXuYDKRM1UMECbAxeXCwqzS0dc0V8ypcG +fteDGHXMo0F/XAmGvVeyXJ9wCk8OaNq3QfJv7J98GeFlsisK3g+DzyHnma8+DPiQz5fXZYlWQATB +TYmRqvJl1KzKtTAluhm7MMLb3F8xL2NDeGuxLbfrf6E9zY45m5mPjZ9RgD7Lp/aRq3yRGIHZT/Hj +UOW9tPIFXsnd71c0SWPBukdkw6Iu4mmRap139EPPn1NbxII0Kx4bXAFSaRSVv/XzPy5uqO62NQBW +NGvw4f1JGumSY/O23vkXjZaGvN+S0bz8EKrqST2JR7xwKXiyc1EiBTO4wNbd6azULsK4LQc7wEe9 +fLtkLqeh1/tDw12z4e/cGuujh09rf8Olns7hcq6KvzDyM4MT1hSizKeViDqgTaWsim2icOPXIWGf +sFNi0Bc38qKoDMEnsp36riwZe+y4DdFzqzq0Yrr9+0B5ByNMyLSvi4M65KZswrHoq1MwgubuGmRu +bnAcGsxnoNMIlXHHBxS1+kIY2Dh9+Op3PVTHiBM/kexi6XMyY9pwe8I7Fd+L4PTexmvNKi2x2UOL +UB7l3OgfCdwQ1+9QgliX4xN46NNnISm8EFE0zpn4SAV7B38UDLL5XBcO4aOW2/+q4crLHtw/9GsO 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b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v new file mode 100644 index 00000000..95883a7f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v @@ -0,0 +1,68 @@ +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module vio_manual_ctrl ( +clk, + +probe_out0, +probe_out1, +probe_out2, +probe_out3, +probe_out4 +); + +input clk; + +output reg [1 : 0] probe_out0 = 'h1 ; +output reg [0 : 0] probe_out1 = 'h0 ; +output reg [31 : 0] probe_out2 = 'h00000000 ; +output reg [1 : 0] probe_out3 = 'h3 ; +output reg [3 : 0] probe_out4 = 'h0 ; + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo new file mode 100644 index 00000000..39fbf855 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:vio:3.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +vio_manual_ctrl your_instance_name ( + .clk(clk), // input wire clk + .probe_out0(probe_out0), // output wire [1 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [0 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [31 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [1 : 0] probe_out3 + .probe_out4(probe_out4) // output wire [3 : 0] probe_out4 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file vio_manual_ctrl.v when simulating +// the core, vio_manual_ctrl. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho new file mode 100644 index 00000000..877bb0cb --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:vio:3.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT vio_manual_ctrl + PORT ( + clk : IN STD_LOGIC; + probe_out0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : vio_manual_ctrl + PORT MAP ( + clk => clk, + probe_out0 => probe_out0, + probe_out1 => probe_out1, + probe_out2 => probe_out2, + probe_out3 => probe_out3, + probe_out4 => probe_out4 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file vio_manual_ctrl.vhd when simulating +-- the core, vio_manual_ctrl. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v new file mode 100644 index 00000000..33d3db0a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:928c622093f565ec8678890a646dc15f08b5fbf566985284ea9ce263ba1c7b1f +size 352451 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl new file mode 100644 index 00000000..ab7fec7f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c725a47591eb1e8eacb779c8e17640ca12d923f1c26e0b41367134f96655e23c +size 633932 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v new file mode 100644 index 00000000..424b152f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:26 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +// Design : vio_manual_ctrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; + input clk; + output [1:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl new file mode 100644 index 00000000..7976ded4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:26 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +-- Design : vio_manual_ctrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_manual_ctrl is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end vio_manual_ctrl; + +architecture stub of vio_manual_ctrl is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/hdl/vio_v3_0_20_vio_include.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/hdl/vio_v3_0_20_vio_include.v new file mode 100644 index 00000000..0673f57f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/hdl/vio_v3_0_20_vio_include.v @@ -0,0 +1,283 @@ +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "XILINX" +`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`pragma protect key_block +GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx +XWe4lBDDrw== + +`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH +9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c +eVhT3XSIJDvufMyiJUc= + +`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit +pNc3Ov7QvW8kjTq3JHFuCf7SmCYRrmElQv0XobTk6mnMb4khaXw9wTP8YMS0XAqk3Bksal+aKfvX +LL/afyM4UwBfiIb04ZgvhdOlp/dkCqWqZyDL2qVScyGrZcDCW3CCZTVQO29hqMLZP5S82keXpBv3 +5J7nHHbQ3n4dxsRykYtJtwg7JDyqGHiwhj1HDtjhG+LX9ry1wy5YgvxrzSfKoouAeHCKXcG7TY0a +sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ== + +`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +ItrqCM44kZl0WwWeSAjetSYD0fPwYZdVjFp5cRl5XZyoYOMWKCVEXncinM06x/MDVlkYiXgz2Xqn +6ui7jR7RwOKALvqoqdehIoXZUA/5yPMntFpxPcFIY1DonBI4CuMjhqCuB2RkxKNIco5Z7/QxCk49 +MCUlvIFRd2MXM+zvhCRdja7e9blnwJEUETukq+EKuAwuR3+VN3uzCXsNtgBqMZa2CyM6Z60fStuc +v1eiDP/hxOimuSfsS7evakl5WMjgZuj4Jld1+y5hTOuPvw4+s3KIb2ejIH2r/I7ui7sWUZTah36a +4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A== + +`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v +ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX +cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC +xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa +draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg== + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv +j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO +R19uHYIhWP+7IpmjTiQ= + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM +kLLATubglrp6DudyaIY943skTmlH+as6fKaHODrTcy4CDIP4kKrok/7y1rBI6+YAfN3ZIW+45MiV +cHuhXHXxxXblzCT6obAZK5QUCP2qZKgO0jjI1RD7ZEJuS/mX5wkIAvOe8L1HBkyUsRq6Cu30W6u9 +7VI3LOy7TZqb6Nix6Ok85ylO82KP12tdXY2IRivakKu4fdWQ6vc3ARiefSR0+RDmE/eZzhzQbt26 +mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q== + +`pragma protect data_method = "AES128-CBC" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464) +`pragma protect data_block +vLDJJUgjrlRfGtI6e1+Byt5lDBB9Oezy8FH9Uy/Lem9icZpnVjts8rEqPHcw31BJ5u3y4ePWkCUm +QQfQ8vh3WaO2dCX+QhbDMTmPaIe/t8nHJKefrbW5OY3eRKkptlVSIFCFITpJlzyfpSe0CsF+dWLc +F4J0aJzlQEKkTcCFk2ey1erWcvHgIf6eCwkGouO/COjRPomcaMzJt3ty3PwhKodmumGUICNXKjG/ +lH5VI4pSkr0hpeNp/WZhHstrrYJB7GSwMCqfL0IH36wCF3R29Yjp7ouoogJ4+imS5vnMJpU2Czmi +PFyY3LiBeZ4VP5b8Iv0AK4XoJtM3XG9iTBAC/oslCJUtBhINFPia8EueAVn178qtq+htmZXlEAbM +O43w6xZ55fggub8NiHe8M4qAhDC0nwv3LBVndn8xEKF+13iwSiqhLjU1Cya8z+0j0TUExIeVQyri +OXh0d9oxCJ2lfPtNjHZ3LkjbMLvzdJG8pBuDtx5952IJrwkJIaT76aOEs7XK8O+cfrtfhh1fPpY1 +XTzoMx95+Qp7Ay2J8NObIZHBuUKX2ORE3b7zSBW5FPRjaxTibHQ2blQzoAbo5y5f30hxOHsi0+Xe +D4bwHKzoBpsdKAyvlKom17BBx5Q5KccIElz3z9ulgthM6zwAWmMVPzQnJAhmz3Hl3t0m7+YNA4Ia +cg/H8tiXcV6CEnRuaFRr8dvkZAlT16o4u+tEwi85XgpkoApFQ7EytG673+LigwZbb2C7khwEoIiw +1LN4Eh9i2WsLPaEipn3q58x1rH4/MEzwsGw7loWE4BkCf+n5QAWYc/nk4xfSwFTBvxs6sPejsrRX +qbtO8ZOnKuVTT2ZLwEtvGrf+Ii1Xymt1JsQt7Z0QBWTykLt0ZhWTrPnMg/zcRxyRCDNYWVJx8JKC +Fjg1XzSDYIYff4HaLPjmiu5sPEXaKTQJvaZa52Dq87oKwWI0A3g0ymKK7UVXrmX/odtLOlHIxuhy +JnruUntWueD34KJMT2lBO7AP0g/OmHDI6v72Q/2Tk66QaWfnnDJl6qRN2WDuGyNuwSflbEGQiK02 +vyM4a6K9KN70ev9aLX4d2m7Uo9n4GFbdvjakrlHDS/K+TRs6XmOa+y8ErWxn9Pfy9UyRrFg1TdQb +Zk69XUdoQZ6CNWoKazZHaJ5p5+6nk/G0nm8LR039U2sqH+B1hJMuvFvsx4NzEoYpE1jNsiy4B9Ta +ArVNSpGuZCA4Juifia1UC8m+mMYsLBACf9YX/Uua3EeOfU2CEi5koPuBzR/QKb/1oRa3x2oux2Cf ++p+HcJdQfSOpF6AkpWZLChsoTMd2F24Ztmjz3/vNIapPf4rcObfDEJwayu7hSrsslcCIcoXdojo4 +VXLn2QFVUYMgSq3pYGFywvmQTA5x/JAfOcWO8IBKdixvS3F6xSTwH8JaKocC0735inh65PwNjS9F +2KIwvgHQvLpCxNny+0NvSQ7ETTouC6xXj+EUv4bGpml7J3HNjixHtTPfYXf7cl0mqQmUDJu0wLkp +WuvXFDvCxpwSZ5qw+1H5MPeue3MeB1Z6Ibu51Fs1EwnAe/g9C0Mo1XDCD6LfVjvpZYE62HzlzF/K +IJoLfeJT0O0VhjqhC3+M3TGXHNYm6chuUtfNR31cC7WgG/QiHYOVySvp3zljDZWrxsgHO+JwhbQC +n8ALL+g50X6+uS5w/HkFBsxwCIocmViJb0ojg1j2ncsUjwwEqkDBprVPYFh6Zimk5SJ9f3RO6pQj +saDd3hitIgpMf1ha8rpCYBkwqBTogxXfwijLMplBdGWVGSSSnnp6jTnWb0sV2VPA1l2X6Iq+pomM +jilYYfQ2dBuXFEMpQpwDC3/8N4YxpDZWX3gtyK2XV+2BcRONvrl/naflTsXxuXAhSxOBqggJw7pL +HvsOGKk0ng6uKC5yQPc6Q0SbWwwT54D9vLM4U1OiRKPpL9S1YXak+W8ZCXqdHkQNlUlm21ssL4dl +Et7q9IF5Vil/wnUjm0nJxVZ4QJU/uN7icrtnrvAf1gVLwK3fpC0ed6ku9s7Lq1KvNb7NEPDrOu3Q +hg+xhyl9MJTquidnbUsYlHdTvVzxIkI4q/1kx5mkbEjiIWG0R+haIwSqhTCdxpxxTgm+LGAtWJ4W +lEuCQ2VEu3cyamx3PWNKPt+CE1VayIkgGqEBXIaGpwkymL0y6hkgrA+q+2msQq245iR7XC83U26E +yb3da4UnYxL7g5WjJCSfCdNVOkKS1Yl9VZ6XSW5RFwWIdURQyewZxfPKaJWsDAGfpRftpZ2mOfIl +DP1TwLOJrgsh3QI82hOYlUbHmcPIFMH3Pqp4OpbOBRcPcZhabwMA3pidOtbloqo5pRGblsO79JSJ +OdbTH0XVln2LAlQ0bOmaMt9/rOwfexnMgActW5gvaaxAXuYDKRM1UMECbAxeXCwqzS0dc0V8ypcG +fteDGHXMo0F/XAmGvVeyXJ9wCk8OaNq3QfJv7J98GeFlsisK3g+DzyHnma8+DPiQz5fXZYlWQATB +TYmRqvJl1KzKtTAluhm7MMLb3F8xL2NDeGuxLbfrf6E9zY45m5mPjZ9RgD7Lp/aRq3yRGIHZT/Hj +UOW9tPIFXsnd71c0SWPBukdkw6Iu4mmRap139EPPn1NbxII0Kx4bXAFSaRSVv/XzPy5uqO62NQBW +NGvw4f1JGumSY/O23vkXjZaGvN+S0bz8EKrqST2JR7xwKXiyc1EiBTO4wNbd6azULsK4LQc7wEe9 +fLtkLqeh1/tDw12z4e/cGuujh09rf8Olns7hcq6KvzDyM4MT1hSizKeViDqgTaWsim2icOPXIWGf +sFNi0Bc38qKoDMEnsp36riwZe+y4DdFzqzq0Yrr9+0B5ByNMyLSvi4M65KZswrHoq1MwgubuGmRu +bnAcGsxnoNMIlXHHBxS1+kIY2Dh9+Op3PVTHiBM/kexi6XMyY9pwe8I7Fd+L4PTexmvNKi2x2UOL +UB7l3OgfCdwQ1+9QgliX4xN46NNnISm8EFE0zpn4SAV7B38UDLL5XBcO4aOW2/+q4crLHtw/9GsO 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b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/sim/vio_rfcontrl.v new file mode 100644 index 00000000..d8bfddec --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/sim/vio_rfcontrl.v @@ -0,0 +1,95 @@ +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module vio_rfcontrl ( +clk, +probe_in0, +probe_out0, +probe_out1, +probe_out2, +probe_out3, +probe_out4, +probe_out5, +probe_out6, +probe_out7, +probe_out8, +probe_out9, +probe_out10, +probe_out11, +probe_out12, +probe_out13, +probe_out14, +probe_out15, +probe_out16, +probe_out17 +); + +input clk; +input [15 : 0] probe_in0; + +output reg [0 : 0] probe_out0 = 'h0 ; +output reg [0 : 0] probe_out1 = 'h0 ; +output reg [15 : 0] probe_out2 = 'h05DC ; +output reg [7 : 0] probe_out3 = 'h00 ; +output reg [3 : 0] probe_out4 = 'h0 ; +output reg [3 : 0] probe_out5 = 'h0 ; +output reg [3 : 0] probe_out6 = 'h0 ; +output reg [3 : 0] probe_out7 = 'h0 ; +output reg [7 : 0] probe_out8 = 'h00 ; +output reg [7 : 0] probe_out9 = 'h04 ; +output reg [15 : 0] probe_out10 = 'h0000 ; +output reg [15 : 0] probe_out11 = 'h0000 ; +output reg [15 : 0] probe_out12 = 'h1680 ; +output reg [0 : 0] probe_out13 = 'h0 ; +output reg [0 : 0] probe_out14 = 'h0 ; +output reg [0 : 0] probe_out15 = 'h0 ; +output reg [0 : 0] probe_out16 = 'h0 ; +output reg [15 : 0] probe_out17 = 'h0000 ; + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo new file mode 100644 index 00000000..59ec6ab1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo @@ -0,0 +1,84 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:vio:3.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +vio_rfcontrl your_instance_name ( + .clk(clk), // input wire clk + .probe_in0(probe_in0), // input wire [15 : 0] probe_in0 + .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [0 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [15 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [7 : 0] probe_out3 + .probe_out4(probe_out4), // output wire [3 : 0] probe_out4 + .probe_out5(probe_out5), // output wire [3 : 0] probe_out5 + .probe_out6(probe_out6), // output wire [3 : 0] probe_out6 + .probe_out7(probe_out7), // output wire [3 : 0] probe_out7 + .probe_out8(probe_out8), // output wire [7 : 0] probe_out8 + .probe_out9(probe_out9), // output wire [7 : 0] probe_out9 + .probe_out10(probe_out10), // output wire [15 : 0] probe_out10 + .probe_out11(probe_out11), // output wire [15 : 0] probe_out11 + .probe_out12(probe_out12), // output wire [15 : 0] probe_out12 + .probe_out13(probe_out13), // output wire [0 : 0] probe_out13 + .probe_out14(probe_out14), // output wire [0 : 0] probe_out14 + .probe_out15(probe_out15), // output wire [0 : 0] probe_out15 + .probe_out16(probe_out16), // output wire [0 : 0] probe_out16 + .probe_out17(probe_out17) // output wire [15 : 0] probe_out17 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file vio_rfcontrl.v when simulating +// the core, vio_rfcontrl. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho new file mode 100644 index 00000000..8e3710c3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho @@ -0,0 +1,113 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:vio:3.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT vio_rfcontrl + PORT ( + clk : IN STD_LOGIC; + probe_in0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + probe_out5 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + probe_out6 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + probe_out7 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + probe_out8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + probe_out9 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + probe_out10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out13 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out15 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out16 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : vio_rfcontrl + PORT MAP ( + clk => clk, + probe_in0 => probe_in0, + probe_out0 => probe_out0, + probe_out1 => probe_out1, + probe_out2 => probe_out2, + probe_out3 => probe_out3, + probe_out4 => probe_out4, + probe_out5 => probe_out5, + probe_out6 => probe_out6, + probe_out7 => probe_out7, + probe_out8 => probe_out8, + probe_out9 => probe_out9, + probe_out10 => probe_out10, + probe_out11 => probe_out11, + probe_out12 => probe_out12, + probe_out13 => probe_out13, + probe_out14 => probe_out14, + probe_out15 => probe_out15, + probe_out16 => probe_out16, + probe_out17 => probe_out17 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file vio_rfcontrl.vhd when simulating +-- the core, vio_rfcontrl. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v new file mode 100644 index 00000000..045f923b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:795e37fa5092bed76bd5666e05cb723247face647baf3ad8fae43fc62a1b160e +size 429585 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl new file mode 100644 index 00000000..947c8fdd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9f9b2adcaf809ac070ceed79970f8ed6d58a91149d1358bbad5cf3844870fef4 +size 743518 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v new file mode 100644 index 00000000..1d32ada2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v @@ -0,0 +1,42 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:25 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v +// Design : vio_rfcontrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, probe_out16, + probe_out17) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]" */; + input clk; + input [15:0]probe_in0; + output [0:0]probe_out0; + output [0:0]probe_out1; + output [15:0]probe_out2; + output [7:0]probe_out3; + output [3:0]probe_out4; + output [3:0]probe_out5; + output [3:0]probe_out6; + output [3:0]probe_out7; + output [7:0]probe_out8; + output [7:0]probe_out9; + output [15:0]probe_out10; + output [15:0]probe_out11; + output [15:0]probe_out12; + output [0:0]probe_out13; + output [0:0]probe_out14; + output [0:0]probe_out15; + output [0:0]probe_out16; + output [15:0]probe_out17; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl new file mode 100644 index 00000000..ba0a2f31 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl @@ -0,0 +1,49 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:25 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl +-- Design : vio_rfcontrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_rfcontrl is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end vio_rfcontrl; + +architecture stub of vio_rfcontrl is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd new file mode 100644 index 00000000..e8b18e50 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd @@ -0,0 +1,3821 @@ +`protect begin_protected +`protect version = 1 +`protect encrypt_agent = "XILINX" +`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" 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key_keyname = "cds_rsa_key", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`protect key_block +GHxro9vtiZP+GS2qEMmylgPHt8LLwogr2ZgTUG7cc7qKCQXiq4Blx6gWqJn4baehQ9aa7vTh0mr1 +cEBEDOkYeA== + +`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +H7TYpSdgylfD7Q5rt1NTmSUssY7Mry2O06Lz02qfx+XKsT3E0CS3ScN/AV9qRiCkesZvSFm8B1rV +9AIBo4aW21Bql1wB4Y8mL1oWv9XRgJgW2r8Jm+3dO/2GUSLzZn/xQQrNR4G9iEyFcvmaPE8AOdtu +epNoEG34A3OtbDgY/qw= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +iALQK0rRhfOqPD7UzEnGgJUHVjupk0xDZa/AnaO022AtH5JNAD7udp8tncqBITuQjJpbU/nPz7ax +l9yRcQY2fN6Xmi2ASrJlCEanVirsRyoeRCGSoArIWql31Mr/OQecNXLSIzFil8eR8Ry73uZut3RY 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+`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`protect key_block +I5jBxSA30qMppesbkWzApATD001KfSyiO/EXeiSfqG/mDp7bWT98b6O2aLKwO2KBiQHns7D4kNzR +1vJ+KztHDg== + +`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +WMu7kFTLnidedbfVrZuh/7ca7CUttjqfOqFAqALtw+gkp4fPh7ZCC2c3FriF2MGJNdt0inCBZQ1w +ERGO+2E2lzKAF62aWczdna33VjhJbQEhVD66TE3XkcNa3kH5qqUhb+EgT0e6ErzcmqjyjnkFxoKK +XKvbLV/yC8Myvjbgd1A= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +xD5n0VbWIE6P1VxF0RmDDu2TYD4jh2LNu0PcTQhqBRKitH0v3xG4GrD/vuHfz6qhNoYV25YBOEWi +7kVjcZSXNFtC5ITuwneS2ZMRryiXpM8fFiU2j9L4eELr2/mHrJrVvacPISdaWzzVZMaXZGjjLF31 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= "SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +MnmM+Vq43VfUtOIhY9KEmYMnTOpr5zGRbR3yK+0dJHKXwwZLH8B0qYakf7wLIspjX3+ovqpgjWJs +eexIlQRGL1OO+SY8TKMpSpPoC27AE5XzJfVNJuTctUe4JhGeFQiByX+5cA58rG1UIyVu4V9mVip8 +ZoHCg+AzWCi4RfYkPls= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +eUhGO4Zv/WnFxc3Ba+3s+f/DLJpOX9sq8Be4gTyMUz382PTb/f4BzSbBQRui6DY3i5eftyc5tZ/r +9jkyaJJvfnT8O4dD86LmVGY8oX+idQzuT6rIw4oeMAjWU5UjY5v/yaTsmQhBcHwnQgC8DRkf42i0 +XEqPpWe8H0ufxTjsCna4pW0lhD9kJOaO1+xySDotb2/KYHQnYNgk39dnpd8h1YlG59y1ow7rFcMy +UWmIcilGbYic3ZbL45pqq3Qc+KgOsRMiUkaRnpDoftYq6Hztbz42lF8rrwZUxldZ6UU735PTIlv7 +l6EfQivncRW7xiJFPLrOQ8ajBNaclxJkf5APAg== + +`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +TNh0egv4UJH4qDDvfs7rXQ/oEKQ1bFPgcWj3XkmFI7ALViHSkmG5TFA/n4HynV9CZVIa6lLn7sVz +2VsjFg4wMgfj/qaRkJPKAmoO8Zq84qzu762YbuzOfvXSTxIp4C5s/tA205oxU6Bij7tlu4cynXfZ +lFBFIXMYrDdJJSGr1PVtShFqGfeO/gOaN8Al/Y+raWaS/oDGb/ciu6GlxhyZoLR1gRfhmyCmS8GM +P68kAzVoPMQn4USscnGiG24w7VaFPNwxt5dQyTyiqFXrzy8YCO/QtdWk+3H4JxyUkdc0AwGH3qCS +tHz+2HVWZ9bzU6mSDu5okJQ6uKpzarA83QoPoA== + +`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +FItfQ2y6HUxZgqq1+z0f6GElOMCJtzq6hAcJow3VuOey3t/fInfKfPHNfOH41ZYZwQ6bTMfh9UMm +TXbo3fDmT24V9QM5TX4F2RsHpHTe6NXTFElDX4CFzFTQ4nfp9vXo6X1FOz1QsSeQfNUheFN7XO8E +2UuJBJpMAKO3NlSK2A9X7FVt71yCUYCH5AItGCmtXYE8uLTQ8HfJqrPnTjU1th6jBb9Dh2jwhsnB +cM+Sq5N4MHCkgFOy7p437lRlySPo2Z5NRIBrOG/H6oD4T/8NBdsbQayFqVottK0Dh3VfTb1jwtAN +ZyTiNjnG4FJkzHGCyhcqEappQGlGNKwPGrmPOw== + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +s82pH+ra+n/uhrGCxzeh8pyCj7n05kyecs8hkcYvPeb2OjaTPUGyWjw6P4VgViM0Cp36AVrVKmZx +e2XRK8zinyrzSNWlmzmsfbhUdTgcreMAg1sD4GLrIibiVMk5z+2lk3OaXcx+3+h0+lEyIScEAUGm +JgpYhahET98Duw22gQU= + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +f/e0qWgpwoVoit5qAqHiNIT3ektReghM3GOKqZv5m0PybAN0oNXP7+6xTCTySe5DzU06uDk/ZZ9z +SUxaA3ulymUsx/QeMKs53Et46+1ZEM+Mt5JN7uwe6ztqbgJCorX5ko1wXdg8eQ44KJx1WQqYtROE +Q2juHs2Oiu3TOo6Jnj+eAsirCCc95dhuajyl+16nZfO3YcBO3gOOOMP4AKok95MuILn71qEWpNwj +eukGjfxurCMjbVmULTQxLOJyMUyNxSIL56J5miPGfdxf3TdfDsU7oGDM07mla9EmyExnYwBAAPlT +26Ak2A4bYHWiEWl6jtGtmWCwshl7qyszHdXrsA== + +`protect data_method = "AES128-CBC" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 967904) +`protect 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+`protect end_protected diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd new file mode 100644 index 00000000..c01849d8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd @@ -0,0 +1,1367 @@ +`protect begin_protected +`protect version = 1 +`protect encrypt_agent = "XILINX" +`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`protect key_block +KXJ+KQFrskV+mMOtKobUOdwBU1Q96L1VjuICu4OyHPs6SXeHG6wnV80Fbxov/EzzO8x0Z3emKj2l +1HeobMZFAQ== + +`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +X4MwXfUrUSWPkQbt5itoHIH8a6wAv/G8Rj+yp8qV7SeDqQStFUllazNjiSTqZslwsd31+6cYFL96 +6zDC/D+OYJSVLVhGm8PIy5CAObI6vrQTlPLpCyfSAtnhsAtbpB+/xlglwIui9BMVFAHugGmjRC+C +iEY17T6TvdLguPq7/2w= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +AY6GI+RVO46tZSokl+Im9Qjzoj9Y0Yy5iXxh6iX/9ufj7UK+y/Fu/+jqZGCXnL/D3x5Vw9DvYinN +OZISR+sb1tSrIdKCMSqiOBiGlkfXJX4yx+M3XhT1daec0H95htsSln8Yy5K1heMbTBqwINepRZ7U +JrYhJ3Q2JY1ank6jhbTfC/3R00Z4shzx6DiyAkPWDlGj2jAP7UB2UON4rM5Epg2pIBwbbWQAAHTT +liAIssHV0g/Th4AG8Bf4fCEvKsyZbGuanw6XpNnQFIByrnhyynf/4UpMhc/cwEDSo/e/VIetTjiO +8GPRl0paJ2NqqL3iKfepGqCngXHn6d7TC8EvTg== + +`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +eQCEBXw9ntq2jHoQJtOMWv98AZN5oshrWog2KHmvb0lnK4113pxvwRuEJXr3iDkegHdv+cJXTbmV +8KSCmD8ChKWkFXee/YjyBeJMc10QmohX4Df+J9wImo1z5bbKXBwKiQUjlqkYleMDscVyreupEO0R +OTEbw2wpFMA98KnrxKGJw/X3jY2Nad/7JCJB0vTE/g97Kv5eJ7mB6QLrkoTW8eE1mxiIT95uwU9/ +Y+V0S+/QTWiV/Wy+tbO/lKYDetTh+81EC5aPb1AS8kQr5jmAhi++8HBlocjmTsLpnBT3l8E5jdrY +fTh3V2oMq60AdOU1465MpStQpJeOcnyhacy5fQ== + +`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +iq8QZZRvFbiL1D4/Ut/JYE+zjq0864+0wF2SilIWU8VHt5TtRRWIagETipUl8rN2FoyGyUg5scS6 +d8nSqHAHLTg38L4QzRQEvkmHZ402zq1AywpH+KMXRCEpOzPVOSxNEW1EfktEXBy7EkC7JSpUZ+Db +s6JHsLkDPJ23VSMVSBo1gc4uOdYpop1ncZh6UN3ojGOenKLJibChBpSW9wy0ARqgedKvd5kHn9qK +QXAuDWmqT6HAXiRLvFbXFOQ+xZuyNr+SpToYRvXR1xGUXnXGMCWcv3DlIhK+tL3TnGKh9xBMt+SQ +XbY8H5PqD6F036BBQ+C3yL16yhDmA2o9cdOYLw== + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +OEkw400+LKMrls4nTgbVTZ3P1EKeX5UpOnw+zEzf/LSzF3fV/voU/boIwWGplHAsHALpt4XBOVfd +t+PwzEfEgmsMqapviTLAi1nHqL0rSZoU/TtoxUvPAdVscAAzxs+QHMxHRAQXklxyhzBIyB6exb7q +otSeZ8tJ3vVmgyJfRFg= + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +hjbrFSOsnBewHCQJmsQwWPLXEBgWWlMnbjbcjBor8jiUxGJ5aN5yhGN+Z91PBg3J9NjiPcN/OqZv +1nBcMWRDZRUaV7niwSRKBFH5EU4hSshIo8qhSEXZ8Enh2wk8ZwP7nkVBjpQqshjBMRp47ZvVeqSS +/Qpv+YGPB90Y45prWsH2cdu0en3QY1q75Hfy3/hSS1ueBggYNIzz5qVQ9qc/N503Sl0qpujT+f30 +nPcb9BV9jXIJ1ly6R4vCvu8D0cRs+hv3UTN+gGWv8t+bTGV0ztqMojNvBqHUTIm3rXfaBrqTfVAf +A+9yth4NgrpbJBjDH9nw6zqU9a35TRnhmJTLKQ== + +`protect data_method = "AES128-CBC" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74240) +`protect data_block +GFbD2L95HGQ/miPqPKi/w3xExMCyKu6uL5xS6wg1NRo/IGUuWXLHR0v73dgdbyc+YLZQCGgfMuA6 +HD26BT0dv11ZWyaC3w5jQVrtb+QOhI7Y0/UdApzRGbXtr+AN7RvUT5budRztoaYY6jgfXeYgTta3 +S9CwhCQ7/TKcZrtWjL/7hWiWZwu3inmo/46Gwlv+H8Jsf7tcCKuFY6G2yTT+RFVFIE60Qhmy3kQN +CtNvTmvs3kyIB3q769dxu4Sr3yqwgjFLIHs2CjP7ymmUo0pXtN96A5n8z5+LMRl+Z5EdX7tgGJ8z +dWszYVgZZsE4kLQiFBQ1JZrKe7oEevFoOMUvaQgw8a6tnXcMcv8C5CuAnjhxBaaC0pJNgeOhcLX+ +IrFV9ZxsAA2HS5Ry+80WfegChy2YDydqPzvvbAZI/U70DOagFqULdlNzV3hqvvOgC7D1WwenRD22 +St5lstBEXzvWIQBbIn7ZbpVFF8AvtHQQqMms0C/01/X9DtbvKthUTi7KtNDHX7q9jPQlLQMEw2pI +n+ffo4MGPj9fc3uUc1ZshNy8vcTTPu4SU0HpFKjN/aHv4h67lc041AxeKCjOV2ws8ai8PrjHb4Gl +TlMXY/4wH6fh1xX/vEgZnTYCe/goa8m1fPq2JSxvw4vJtdeErJemtL1GCMerxJt7EchSqO2ECvyk +Xw4gzdPMZ7nj2LOFltK5/WtKtxxIi3V5m5tMivwvGEWGUna5KGTOjNfLAJIaNbN+VrO8MDeZpTQy +6Lvnh3LaoXPoEMPnBkP+X2zdq8pRXzvkwpzPzy+yaM8APheQuaHhR063badRGz1nu8Yt/Bx4KD68 +wsQWJxF407sXHgYt3HPWwG9OS0OCBU0a284ptiYE0VcsL1Qn/3eR+tkotbntmEzGjjmqcWJgXnaR +wu9dQc91LPML/fdYXV/LQM9mPDtHAaGrk5VB1fX+p7vq6H23fIn9ogyw8fOD7MwOlCsQG8CT2jb9 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key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`protect key_block +IijDYFYeRdzkel5iYnZFe2NzgYX9UDO+g6PdWiHeOm5P1+m9Kt//ktx0y9l3PqUsSWKKIi5tWbDg +OqtBZeM3zQ== + +`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +TXFD8G5gE6CUfZ/9/aBQvAaQuQ9Q6vcW5KJtFkYqsiROk19a5PsS1gCxUXtSJ+Xt20njQCTMz6jx +UaSmsNRyiV6PuCAgdQYvfeJWiNmQq7kXQnkYSjycSJyNe/xoXEYIK0mHX7J2x9ouXxNx6jQFR5Lm +jxY8fR7N9m3PTkCqNTI= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +0bdD7I2gr0nFDramUUXzPCEqtk/eE+vK1bghpNlKE+S5t5/NbqJI7gNd3XLwYh6qEIInU1StLpm1 +ZEERnCmEf4+rQBAW7x7u7nIsJjSOmPWtDc9DLn5S3e1Tg+IzLUqT0rFFh5TiwuYq9A6oIvI4ufWQ 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b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd new file mode 100644 index 00000000..8e30555c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd @@ -0,0 +1,2392 @@ +`protect begin_protected +`protect version = 1 +`protect encrypt_agent = "XILINX" +`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`protect key_block +AxZSYlrqWjjbM/ghGgP335GwqxDgV3HmMQL/p5ebckAQyJ+kqJFTPj58BKjOX4mpdCMv1bT58Fu1 +qGdZGqaeUw== + +`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +EIaioRFBcSeMA6Aux6hZm/WyyYgPDWVHaRtKbzIwL1QTiiAUZlNppzkL3bbmZ6KUvAn+f3bbBLZv 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b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ipstatic/simulation/blk_mem_gen_v8_4.v new file mode 100644 index 00000000..2dbe576b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ipstatic/simulation/blk_mem_gen_v8_4.v @@ -0,0 +1,4522 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: blk_mem_gen_v8_4_3.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: Jan 11, 2006 Initial revision + * Jun 11, 2007 Added independent register stages for + * Port A and Port B (IP1_Jm/v2.5) + * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) + * Mar 13, 2008 Behavioral model optimizations + * April 07, 2009 : Added support for Spartan-6 and Virtex-6 + * features, including the following: + * (i) error injection, detection and/or correction + * (ii) reset priority + * (iii) special reset behavior + * + *****************************************************************************/ +`timescale 1ps/1ps + +module STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5); + + parameter INIT = 64'h0000000000000000; + + input I0, I1, I2, I3, I4, I5; + + output O; + + reg O; + reg tmp; + + always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I5, I4, I3, I2, I1, I0}]; + + end +endmodule + +module beh_vlog_muxf7_v8_4 (O, I0, I1, S); + + output O; + reg O; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + O = I1; + else + O = I0; +endmodule + +module beh_vlog_ff_clr_v8_4 (Q, C, CLR, D); + parameter INIT = 0; +localparam FLOP_DELAY = 100; + output Q; + + input C, CLR, D; + + reg Q; + + initial Q= 1'b0; + + always @(posedge C ) + if (CLR) + Q<= 1'b0; + else + Q<= #FLOP_DELAY D; + + +endmodule + +module beh_vlog_ff_pre_v8_4 (Q, C, D, PRE); + + parameter INIT = 0; +localparam FLOP_DELAY = 100; + output Q; + input C, D, PRE; + + reg Q; + + initial Q= 1'b0; + + always @(posedge C ) + if (PRE) + Q <= 1'b1; + else + Q <= #FLOP_DELAY D; + +endmodule + +module beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D); + + parameter INIT = 0; +localparam FLOP_DELAY = 100; + output Q; + input C, CE, CLR, D; + + reg Q; + + initial Q= 1'b0; + always @(posedge C ) + if (CLR) + Q <= 1'b0; + else if (CE) + Q <= #FLOP_DELAY D; + +endmodule + +module write_netlist_v8_4 +#( + parameter C_AXI_TYPE = 0 + ) + ( + S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY, + w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID, + S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c + ); + + input S_ACLK; + input S_ARESETN; + input S_AXI_AWVALID; + input S_AXI_WVALID; + input S_AXI_BREADY; + input w_last_c; + input bready_timeout_c; + output aw_ready_r; + output S_AXI_WREADY; + output S_AXI_BVALID; + output S_AXI_WR_EN; + output addr_en_c; + output incr_addr_c; + output bvalid_c; + //------------------------------------------------------------------------- + //AXI LITE + //------------------------------------------------------------------------- +generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm + wire w_ready_r_7; + wire w_ready_c; + wire aw_ready_c; + wire NlwRenamedSignal_bvalid_c; + wire NlwRenamedSignal_incr_addr_c; + wire present_state_FSM_FFd3_13; + wire present_state_FSM_FFd2_14; + wire present_state_FSM_FFd1_15; + wire present_state_FSM_FFd4_16; + wire present_state_FSM_FFd4_In; + wire present_state_FSM_FFd3_In; + wire present_state_FSM_FFd2_In; + wire present_state_FSM_FFd1_In; + wire present_state_FSM_FFd4_In1_21; + wire [0:0] Mmux_aw_ready_c ; +begin + assign + S_AXI_WREADY = w_ready_r_7, + S_AXI_BVALID = NlwRenamedSignal_incr_addr_c, + S_AXI_WR_EN = NlwRenamedSignal_bvalid_c, + incr_addr_c = NlwRenamedSignal_incr_addr_c, + bvalid_c = NlwRenamedSignal_bvalid_c; + + assign NlwRenamedSignal_incr_addr_c = 1'b0; + + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + aw_ready_r_2 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( aw_ready_c), + .Q ( aw_ready_r) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + w_ready_r ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( w_ready_c), + .Q ( w_ready_r_7) + ); + beh_vlog_ff_pre_v8_4 #( + .INIT (1'b1)) + present_state_FSM_FFd4 ( + .C ( S_ACLK), + .D ( present_state_FSM_FFd4_In), + .PRE ( S_ARESETN), + .Q ( present_state_FSM_FFd4_16) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd3 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd3_In), + .Q ( present_state_FSM_FFd3_13) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd2 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd2_In), + .Q ( present_state_FSM_FFd2_14) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd1 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd1_In), + .Q ( present_state_FSM_FFd1_15) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h0000000055554440)) + present_state_FSM_FFd3_In1 ( + .I0 ( S_AXI_WVALID), + .I1 ( S_AXI_AWVALID), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( present_state_FSM_FFd4_16), + .I4 ( present_state_FSM_FFd3_13), + .I5 (1'b0), + .O ( present_state_FSM_FFd3_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h0000000088880800)) + present_state_FSM_FFd2_In1 ( + .I0 ( S_AXI_AWVALID), + .I1 ( S_AXI_WVALID), + .I2 ( bready_timeout_c), + .I3 ( present_state_FSM_FFd2_14), + .I4 ( present_state_FSM_FFd4_16), + .I5 (1'b0), + .O ( present_state_FSM_FFd2_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h00000000AAAA2000)) + Mmux_addr_en_c_0_1 ( + .I0 ( S_AXI_AWVALID), + .I1 ( bready_timeout_c), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( S_AXI_WVALID), + .I4 ( present_state_FSM_FFd4_16), + .I5 (1'b0), + .O ( addr_en_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hF5F07570F5F05500)) + Mmux_w_ready_c_0_1 ( + .I0 ( S_AXI_WVALID), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd3_13), + .I4 ( present_state_FSM_FFd4_16), + .I5 ( present_state_FSM_FFd2_14), + .O ( w_ready_c) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h88808880FFFF8880)) + present_state_FSM_FFd1_In1 ( + .I0 ( S_AXI_WVALID), + .I1 ( bready_timeout_c), + .I2 ( present_state_FSM_FFd3_13), + .I3 ( present_state_FSM_FFd2_14), + .I4 ( present_state_FSM_FFd1_15), + .I5 ( S_AXI_BREADY), + .O ( present_state_FSM_FFd1_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000A8)) + Mmux_S_AXI_WR_EN_0_1 ( + .I0 ( S_AXI_WVALID), + .I1 ( present_state_FSM_FFd2_14), + .I2 ( present_state_FSM_FFd3_13), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( NlwRenamedSignal_bvalid_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h2F0F27072F0F2200)) + present_state_FSM_FFd4_In1 ( + .I0 ( S_AXI_WVALID), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd3_13), + .I4 ( present_state_FSM_FFd4_16), + .I5 ( present_state_FSM_FFd2_14), + .O ( present_state_FSM_FFd4_In1_21) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000F8)) + present_state_FSM_FFd4_In2 ( + .I0 ( present_state_FSM_FFd1_15), + .I1 ( S_AXI_BREADY), + .I2 ( present_state_FSM_FFd4_In1_21), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( present_state_FSM_FFd4_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h7535753575305500)) + Mmux_aw_ready_c_0_1 ( + .I0 ( S_AXI_AWVALID), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_WVALID), + .I3 ( present_state_FSM_FFd4_16), + .I4 ( present_state_FSM_FFd3_13), + .I5 ( present_state_FSM_FFd2_14), + .O ( Mmux_aw_ready_c[0]) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000F8)) + Mmux_aw_ready_c_0_2 ( + .I0 ( present_state_FSM_FFd1_15), + .I1 ( S_AXI_BREADY), + .I2 ( Mmux_aw_ready_c[0]), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( aw_ready_c) + ); +end +end +endgenerate + + //--------------------------------------------------------------------- + // AXI FULL + //--------------------------------------------------------------------- +generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm + wire w_ready_r_8; + wire w_ready_c; + wire aw_ready_c; + wire NlwRenamedSig_OI_bvalid_c; + wire present_state_FSM_FFd1_16; + wire present_state_FSM_FFd4_17; + wire present_state_FSM_FFd3_18; + wire present_state_FSM_FFd2_19; + wire present_state_FSM_FFd4_In; + wire present_state_FSM_FFd3_In; + wire present_state_FSM_FFd2_In; + wire present_state_FSM_FFd1_In; + wire present_state_FSM_FFd2_In1_24; + wire present_state_FSM_FFd4_In1_25; + wire N2; + wire N4; +begin +assign + S_AXI_WREADY = w_ready_r_8, + bvalid_c = NlwRenamedSig_OI_bvalid_c, + S_AXI_BVALID = 1'b0; + +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + aw_ready_r_2 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( aw_ready_c), + .Q ( aw_ready_r) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + w_ready_r + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( w_ready_c), + .Q ( w_ready_r_8) + ); + beh_vlog_ff_pre_v8_4 #( + .INIT (1'b1)) + present_state_FSM_FFd4 + ( + .C ( S_ACLK), + .D ( present_state_FSM_FFd4_In), + .PRE ( S_ARESETN), + .Q ( present_state_FSM_FFd4_17) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd3 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd3_In), + .Q ( present_state_FSM_FFd3_18) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd2 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd2_In), + .Q ( present_state_FSM_FFd2_19) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd1 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd1_In), + .Q ( present_state_FSM_FFd1_16) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000005540)) + present_state_FSM_FFd3_In1 + ( + .I0 ( S_AXI_WVALID), + .I1 ( present_state_FSM_FFd4_17), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( present_state_FSM_FFd3_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'hBF3FBB33AF0FAA00)) + Mmux_aw_ready_c_0_2 + ( + .I0 ( S_AXI_BREADY), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd1_16), + .I4 ( present_state_FSM_FFd4_17), + .I5 ( NlwRenamedSig_OI_bvalid_c), + .O ( aw_ready_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hAAAAAAAA20000000)) + Mmux_addr_en_c_0_1 + ( + .I0 ( S_AXI_AWVALID), + .I1 ( bready_timeout_c), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( S_AXI_WVALID), + .I4 ( w_last_c), + .I5 ( present_state_FSM_FFd4_17), + .O ( addr_en_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000A8)) + Mmux_S_AXI_WR_EN_0_1 + ( + .I0 ( S_AXI_WVALID), + .I1 ( present_state_FSM_FFd2_19), + .I2 ( present_state_FSM_FFd3_18), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( S_AXI_WR_EN) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000002220)) + Mmux_incr_addr_c_0_1 + ( + .I0 ( S_AXI_WVALID), + .I1 ( w_last_c), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( incr_addr_c) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000008880)) + Mmux_aw_ready_c_0_11 + ( + .I0 ( S_AXI_WVALID), + .I1 ( w_last_c), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( NlwRenamedSig_OI_bvalid_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h000000000000D5C0)) + present_state_FSM_FFd2_In1 + ( + .I0 ( w_last_c), + .I1 ( S_AXI_AWVALID), + .I2 ( present_state_FSM_FFd4_17), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( present_state_FSM_FFd2_In1_24) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'hFFFFAAAA08AAAAAA)) + present_state_FSM_FFd2_In2 + ( + .I0 ( present_state_FSM_FFd2_19), + .I1 ( S_AXI_AWVALID), + .I2 ( bready_timeout_c), + .I3 ( w_last_c), + .I4 ( S_AXI_WVALID), + .I5 ( present_state_FSM_FFd2_In1_24), + .O ( present_state_FSM_FFd2_In) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00C0004000C00000)) + present_state_FSM_FFd4_In1 + ( + .I0 ( S_AXI_AWVALID), + .I1 ( w_last_c), + .I2 ( S_AXI_WVALID), + .I3 ( bready_timeout_c), + .I4 ( present_state_FSM_FFd3_18), + .I5 ( present_state_FSM_FFd2_19), + .O ( present_state_FSM_FFd4_In1_25) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000FFFF88F8)) + present_state_FSM_FFd4_In2 + ( + .I0 ( present_state_FSM_FFd1_16), + .I1 ( S_AXI_BREADY), + .I2 ( present_state_FSM_FFd4_17), + .I3 ( S_AXI_AWVALID), + .I4 ( present_state_FSM_FFd4_In1_25), + .I5 (1'b0), + .O ( present_state_FSM_FFd4_In) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000007)) + Mmux_w_ready_c_0_SW0 + ( + .I0 ( w_last_c), + .I1 ( S_AXI_WVALID), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( N2) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hFABAFABAFAAAF000)) + Mmux_w_ready_c_0_Q + ( + .I0 ( N2), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd4_17), + .I4 ( present_state_FSM_FFd3_18), + .I5 ( present_state_FSM_FFd2_19), + .O ( w_ready_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000008)) + Mmux_aw_ready_c_0_11_SW0 + ( + .I0 ( bready_timeout_c), + .I1 ( S_AXI_WVALID), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( N4) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h88808880FFFF8880)) + present_state_FSM_FFd1_In1 + ( + .I0 ( w_last_c), + .I1 ( N4), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( present_state_FSM_FFd3_18), + .I4 ( present_state_FSM_FFd1_16), + .I5 ( S_AXI_BREADY), + .O ( present_state_FSM_FFd1_In) + ); +end +end +endgenerate +endmodule + + +module read_netlist_v8_4 #( + parameter C_AXI_TYPE = 1, + parameter C_ADDRB_WIDTH = 12 + ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID, + S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN, + S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY, + S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN); + + input S_AXI_R_LAST_INT; + input S_ACLK; + input S_ARESETN; + input S_AXI_ARVALID; + input S_AXI_RREADY; + output S_AXI_INCR_ADDR; + output S_AXI_ADDR_EN; + output S_AXI_SINGLE_TRANS; + output S_AXI_MUX_SEL; + output S_AXI_R_LAST; + output S_AXI_ARREADY; + output S_AXI_RLAST; + output S_AXI_RVALID; + output S_AXI_RD_EN; + input [7:0] S_AXI_ARLEN; + + wire present_state_FSM_FFd1_13 ; + wire present_state_FSM_FFd2_14 ; + wire gaxi_full_sm_outstanding_read_r_15 ; + wire gaxi_full_sm_ar_ready_r_16 ; + wire gaxi_full_sm_r_last_r_17 ; + wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; + wire gaxi_full_sm_r_valid_c ; + wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; + wire gaxi_full_sm_ar_ready_c ; + wire gaxi_full_sm_outstanding_read_c ; + wire NlwRenamedSig_OI_S_AXI_R_LAST ; + wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; + wire present_state_FSM_FFd2_In ; + wire present_state_FSM_FFd1_In ; + wire Mmux_S_AXI_R_LAST13 ; + wire N01 ; + wire N2 ; + wire Mmux_gaxi_full_sm_ar_ready_c11 ; + wire N4 ; + wire N8 ; + wire N9 ; + wire N10 ; + wire N11 ; + wire N12 ; + wire N13 ; + assign + S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST, + S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16, + S_AXI_RLAST = gaxi_full_sm_r_last_r_17, + S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r; + + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + gaxi_full_sm_outstanding_read_r ( + .C (S_ACLK), + .CLR(S_ARESETN), + .D(gaxi_full_sm_outstanding_read_c), + .Q(gaxi_full_sm_outstanding_read_r_15) + ); + beh_vlog_ff_ce_clr_v8_4 #( + .INIT (1'b0)) + gaxi_full_sm_r_valid_r ( + .C (S_ACLK), + .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .CLR (S_ARESETN), + .D (gaxi_full_sm_r_valid_c), + .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + gaxi_full_sm_ar_ready_r ( + .C (S_ACLK), + .CLR (S_ARESETN), + .D (gaxi_full_sm_ar_ready_c), + .Q (gaxi_full_sm_ar_ready_r_16) + ); + beh_vlog_ff_ce_clr_v8_4 #( + .INIT(1'b0)) + gaxi_full_sm_r_last_r ( + .C (S_ACLK), + .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .CLR (S_ARESETN), + .D (NlwRenamedSig_OI_S_AXI_R_LAST), + .Q (gaxi_full_sm_r_last_r_17) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd2 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd2_In), + .Q ( present_state_FSM_FFd2_14) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd1 ( + .C (S_ACLK), + .CLR (S_ARESETN), + .D (present_state_FSM_FFd1_In), + .Q (present_state_FSM_FFd1_13) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h000000000000000B)) + S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 ( + .I0 ( S_AXI_RREADY), + .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000008)) + Mmux_S_AXI_SINGLE_TRANS11 ( + .I0 (S_AXI_ARVALID), + .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O (S_AXI_SINGLE_TRANS) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000004)) + Mmux_S_AXI_ADDR_EN11 ( + .I0 (present_state_FSM_FFd1_13), + .I1 (S_AXI_ARVALID), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O (S_AXI_ADDR_EN) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hECEE2022EEEE2022)) + present_state_FSM_FFd2_In1 ( + .I0 ( S_AXI_ARVALID), + .I1 ( present_state_FSM_FFd1_13), + .I2 ( S_AXI_RREADY), + .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I4 ( present_state_FSM_FFd2_14), + .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .O ( present_state_FSM_FFd2_In) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000044440444)) + Mmux_S_AXI_R_LAST131 ( + .I0 ( present_state_FSM_FFd1_13), + .I1 ( S_AXI_ARVALID), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( S_AXI_RREADY), + .I5 (1'b0), + .O ( Mmux_S_AXI_R_LAST13) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h4000FFFF40004000)) + Mmux_S_AXI_INCR_ADDR11 ( + .I0 ( S_AXI_R_LAST_INT), + .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( present_state_FSM_FFd1_13), + .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I5 ( Mmux_S_AXI_R_LAST13), + .O ( S_AXI_INCR_ADDR) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000FE)) + S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 ( + .I0 ( S_AXI_ARLEN[2]), + .I1 ( S_AXI_ARLEN[1]), + .I2 ( S_AXI_ARLEN[0]), + .I3 ( 1'b0), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( N01) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000001)) + S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q ( + .I0 ( S_AXI_ARLEN[7]), + .I1 ( S_AXI_ARLEN[6]), + .I2 ( S_AXI_ARLEN[5]), + .I3 ( S_AXI_ARLEN[4]), + .I4 ( S_AXI_ARLEN[3]), + .I5 ( N01), + .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000007)) + Mmux_gaxi_full_sm_outstanding_read_c1_SW0 ( + .I0 ( S_AXI_ARVALID), + .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I2 ( 1'b0), + .I3 ( 1'b0), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( N2) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0020000002200200)) + Mmux_gaxi_full_sm_outstanding_read_c1 ( + .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I1 ( S_AXI_RREADY), + .I2 ( present_state_FSM_FFd1_13), + .I3 ( present_state_FSM_FFd2_14), + .I4 ( gaxi_full_sm_outstanding_read_r_15), + .I5 ( N2), + .O ( gaxi_full_sm_outstanding_read_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000004555)) + Mmux_gaxi_full_sm_ar_ready_c12 ( + .I0 ( S_AXI_ARVALID), + .I1 ( S_AXI_RREADY), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( Mmux_gaxi_full_sm_ar_ready_c11) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000EF)) + Mmux_S_AXI_R_LAST11_SW0 ( + .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I1 ( S_AXI_RREADY), + .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I3 ( 1'b0), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( N4) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hFCAAFC0A00AA000A)) + Mmux_S_AXI_R_LAST11 ( + .I0 ( S_AXI_ARVALID), + .I1 ( gaxi_full_sm_outstanding_read_r_15), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( present_state_FSM_FFd1_13), + .I4 ( N4), + .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .O ( gaxi_full_sm_r_valid_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000AAAAAA08)) + S_AXI_MUX_SEL1 ( + .I0 (present_state_FSM_FFd1_13), + .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I2 (S_AXI_RREADY), + .I3 (present_state_FSM_FFd2_14), + .I4 (gaxi_full_sm_outstanding_read_r_15), + .I5 (1'b0), + .O (S_AXI_MUX_SEL) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hF3F3F755A2A2A200)) + Mmux_S_AXI_RD_EN11 ( + .I0 ( present_state_FSM_FFd1_13), + .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I2 ( S_AXI_RREADY), + .I3 ( gaxi_full_sm_outstanding_read_r_15), + .I4 ( present_state_FSM_FFd2_14), + .I5 ( S_AXI_ARVALID), + .O ( S_AXI_RD_EN) + ); + beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 ( + .I0 ( N8), + .I1 ( N9), + .S ( present_state_FSM_FFd1_13), + .O ( present_state_FSM_FFd1_In) + ); + + STATE_LOGIC_v8_4 #( + .INIT (64'h000000005410F4F0)) + present_state_FSM_FFd1_In3_F ( + .I0 ( S_AXI_RREADY), + .I1 ( present_state_FSM_FFd2_14), + .I2 ( S_AXI_ARVALID), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I5 ( 1'b0), + .O ( N8) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000072FF7272)) + present_state_FSM_FFd1_In3_G ( + .I0 ( present_state_FSM_FFd2_14), + .I1 ( S_AXI_R_LAST_INT), + .I2 ( gaxi_full_sm_outstanding_read_r_15), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N9) + ); + beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 ( + .I0 ( N10), + .I1 ( N11), + .S ( present_state_FSM_FFd1_13), + .O ( gaxi_full_sm_ar_ready_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000FFFF88A8)) + Mmux_gaxi_full_sm_ar_ready_c14_F ( + .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I1 ( S_AXI_RREADY), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( Mmux_gaxi_full_sm_ar_ready_c11), + .I5 ( 1'b0), + .O ( N10) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h000000008D008D8D)) + Mmux_gaxi_full_sm_ar_ready_c14_G ( + .I0 ( present_state_FSM_FFd2_14), + .I1 ( S_AXI_R_LAST_INT), + .I2 ( gaxi_full_sm_outstanding_read_r_15), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N11) + ); + beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 ( + .I0 ( N12), + .I1 ( N13), + .S ( present_state_FSM_FFd1_13), + .O ( NlwRenamedSig_OI_S_AXI_R_LAST) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000088088888)) + Mmux_S_AXI_R_LAST1_F ( + .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I1 ( S_AXI_ARVALID), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N12) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000E400E4E4)) + Mmux_S_AXI_R_LAST1_G ( + .I0 ( present_state_FSM_FFd2_14), + .I1 ( gaxi_full_sm_outstanding_read_r_15), + .I2 ( S_AXI_R_LAST_INT), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N13) + ); + +endmodule + + +module blk_mem_axi_write_wrapper_beh_v8_4 + # ( + // AXI Interface related parameters start here + parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface + parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full; + parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; + parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; + parameter C_WRITE_DEPTH_A = 0, + parameter C_AXI_AWADDR_WIDTH = 32, + parameter C_ADDRA_WIDTH = 12, + parameter C_AXI_WDATA_WIDTH = 32, + parameter C_HAS_AXI_ID = 0, + parameter C_AXI_ID_WIDTH = 4, + // AXI OUTSTANDING WRITES + parameter C_AXI_OS_WR = 2 + ) + ( + // AXI Global Signals + input S_ACLK, + input S_ARESETN, + // AXI Full/Lite Slave Write Channel (write side) + input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, + input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR, + input [8-1:0] S_AXI_AWLEN, + input [2:0] S_AXI_AWSIZE, + input [1:0] S_AXI_AWBURST, + input S_AXI_AWVALID, + output S_AXI_AWREADY, + input S_AXI_WVALID, + output S_AXI_WREADY, + output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0, + output S_AXI_BVALID, + input S_AXI_BREADY, + // Signals for BMG interface + output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT, + output S_AXI_WR_EN + ); + + localparam FLOP_DELAY = 100; // 100 ps + + localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0: + ((C_AXI_WDATA_WIDTH==16)?1: + ((C_AXI_WDATA_WIDTH==32)?2: + ((C_AXI_WDATA_WIDTH==64)?3: + ((C_AXI_WDATA_WIDTH==128)?4: + ((C_AXI_WDATA_WIDTH==256)?5:0)))))); + + + + + wire bvalid_c ; + reg bready_timeout_c = 0; + wire [1:0] bvalid_rd_cnt_c; + reg bvalid_r = 0; + reg [2:0] bvalid_count_r = 0; + reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? + C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0; + reg [1:0] bvalid_wr_cnt_r = 0; + reg [1:0] bvalid_rd_cnt_r = 0; + wire w_last_c ; + wire addr_en_c ; + wire incr_addr_c ; + wire aw_ready_r ; + wire dec_alen_c ; + reg bvalid_d1_c = 0; + reg [7:0] awlen_cntr_r = 0; + reg [7:0] awlen_int = 0; + reg [1:0] awburst_int = 0; + + integer total_bytes = 0; + integer wrap_boundary = 0; + integer wrap_base_addr = 0; + integer num_of_bytes_c = 0; + integer num_of_bytes_r = 0; + // Array to store BIDs + reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ; + wire S_AXI_BVALID_axi_wr_fsm; + + //------------------------------------- + //AXI WRITE FSM COMPONENT INSTANTIATION + //------------------------------------- + write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm + ( + .S_ACLK(S_ACLK), + .S_ARESETN(S_ARESETN), + .S_AXI_AWVALID(S_AXI_AWVALID), + .aw_ready_r(aw_ready_r), + .S_AXI_WVALID(S_AXI_WVALID), + .S_AXI_WREADY(S_AXI_WREADY), + .S_AXI_BREADY(S_AXI_BREADY), + .S_AXI_WR_EN(S_AXI_WR_EN), + .w_last_c(w_last_c), + .bready_timeout_c(bready_timeout_c), + .addr_en_c(addr_en_c), + .incr_addr_c(incr_addr_c), + .bvalid_c(bvalid_c), + .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) + ); + + + //Wrap Address boundary calculation + always@(*) begin + num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0); + total_bytes = (num_of_bytes_r)*(awlen_int+1); + wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes); + wrap_boundary = wrap_base_addr+total_bytes; + end + + //------------------------------------------------------------------------- + // BMG address generation + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + awaddr_reg <= 0; + num_of_bytes_r <= 0; + awburst_int <= 0; + end else begin + if (addr_en_c == 1'b1) begin + awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ; + num_of_bytes_r <= num_of_bytes_c; + awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01); + end else if (incr_addr_c == 1'b1) begin + if (awburst_int == 2'b10) begin + if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin + awaddr_reg <= wrap_base_addr; + end else begin + awaddr_reg <= awaddr_reg + num_of_bytes_r; + end + end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin + awaddr_reg <= awaddr_reg + num_of_bytes_r; + end + end + end + end + + + assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? + awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg); + + //------------------------------------------------------------------------- + // AXI wlast generation + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + awlen_cntr_r <= 0; + awlen_int <= 0; + end else begin + if (addr_en_c == 1'b1) begin + awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; + awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; + end else if (dec_alen_c == 1'b1) begin + awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ; + end + end + end + + assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0; + + assign dec_alen_c = (incr_addr_c | w_last_c); + + //------------------------------------------------------------------------- + // Generation of bvalid counter for outstanding transactions + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_count_r <= 0; + end else begin + // bvalid_count_r generation + if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin + bvalid_count_r <= #FLOP_DELAY bvalid_count_r ; + end else if (bvalid_c == 1'b1) begin + bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ; + end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin + bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ; + end + end + end + + //------------------------------------------------------------------------- + // Generation of bvalid when BID is used + //------------------------------------------------------------------------- + generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_r <= 0; + bvalid_d1_c <= 0; + end else begin + // Delay the generation o bvalid_r for generation for BID + bvalid_d1_c <= bvalid_c; + + //external bvalid signal generation + if (bvalid_d1_c == 1'b1) begin + bvalid_r <= #FLOP_DELAY 1'b1 ; + end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin + bvalid_r <= #FLOP_DELAY 0 ; + end + end + end + end + endgenerate + + //------------------------------------------------------------------------- + // Generation of bvalid when BID is not used + //------------------------------------------------------------------------- + generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_r <= 0; + end else begin + //external bvalid signal generation + if (bvalid_c == 1'b1) begin + bvalid_r <= #FLOP_DELAY 1'b1 ; + end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin + bvalid_r <= #FLOP_DELAY 0 ; + end + end + end + end + endgenerate + + //------------------------------------------------------------------------- + // Generation of Bready timeout + //------------------------------------------------------------------------- + always @(bvalid_count_r) begin + // bready_timeout_c generation + if(bvalid_count_r == C_AXI_OS_WR-1) begin + bready_timeout_c <= 1'b1; + end else begin + bready_timeout_c <= 1'b0; + end + end + + //------------------------------------------------------------------------- + // Generation of BID + //------------------------------------------------------------------------- + generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen + + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_wr_cnt_r <= 0; + bvalid_rd_cnt_r <= 0; + end else begin + // STORE AWID IN AN ARRAY + if(bvalid_c == 1'b1) begin + bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1; + end + // generate BID FROM AWID ARRAY + bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ; + S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c]; + end + end + + assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r; + + //------------------------------------------------------------------------- + // Storing AWID for generation of BID + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if(S_ARESETN == 1'b1) begin + axi_bid_array[0] = 0; + axi_bid_array[1] = 0; + axi_bid_array[2] = 0; + axi_bid_array[3] = 0; + end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin + axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID; + end + end + + end + endgenerate + + assign S_AXI_BVALID = bvalid_r; + assign S_AXI_AWREADY = aw_ready_r; + + endmodule + +module blk_mem_axi_read_wrapper_beh_v8_4 +# ( + //// AXI Interface related parameters start here + parameter C_INTERFACE_TYPE = 0, + parameter C_AXI_TYPE = 0, + parameter C_AXI_SLAVE_TYPE = 0, + parameter C_MEMORY_TYPE = 0, + parameter C_WRITE_WIDTH_A = 4, + parameter C_WRITE_DEPTH_A = 32, + parameter C_ADDRA_WIDTH = 12, + parameter C_AXI_PIPELINE_STAGES = 0, + parameter C_AXI_ARADDR_WIDTH = 12, + parameter C_HAS_AXI_ID = 0, + parameter C_AXI_ID_WIDTH = 4, + parameter C_ADDRB_WIDTH = 12 + ) + ( + + //// AXI Global Signals + input S_ACLK, + input S_ARESETN, + //// AXI Full/Lite Slave Read (Read side) + input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR, + input [7:0] S_AXI_ARLEN, + input [2:0] S_AXI_ARSIZE, + input [1:0] S_AXI_ARBURST, + input S_AXI_ARVALID, + output S_AXI_ARREADY, + output S_AXI_RLAST, + output S_AXI_RVALID, + input S_AXI_RREADY, + input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, + output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0, + //// AXI Full/Lite Read Address Signals to BRAM + output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT, + output S_AXI_RD_EN + ); + + localparam FLOP_DELAY = 100; // 100 ps + localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0: + ((C_WRITE_WIDTH_A==16)?1: + ((C_WRITE_WIDTH_A==32)?2: + ((C_WRITE_WIDTH_A==64)?3: + ((C_WRITE_WIDTH_A==128)?4: + ((C_WRITE_WIDTH_A==256)?5:0)))))); + + + + reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0; + wire addr_en_c; + wire rd_en_c; + wire incr_addr_c; + wire single_trans_c; + wire dec_alen_c; + wire mux_sel_c; + wire r_last_c; + wire r_last_int_c; + wire [C_ADDRB_WIDTH-1 : 0] araddr_out; + + reg [7:0] arlen_int_r=0; + reg [7:0] arlen_cntr=8'h01; + reg [1:0] arburst_int_c=0; + reg [1:0] arburst_int_r=0; + reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? + C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0; + integer num_of_bytes_c = 0; + integer total_bytes = 0; + integer num_of_bytes_r = 0; + integer wrap_base_addr_r = 0; + integer wrap_boundary_r = 0; + + reg [7:0] arlen_int_c=0; + integer total_bytes_c = 0; + integer wrap_base_addr_c = 0; + integer wrap_boundary_c = 0; + + assign dec_alen_c = incr_addr_c | r_last_int_c; + + + read_netlist_v8_4 + #(.C_AXI_TYPE (1), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) + axi_read_fsm ( + .S_AXI_INCR_ADDR(incr_addr_c), + .S_AXI_ADDR_EN(addr_en_c), + .S_AXI_SINGLE_TRANS(single_trans_c), + .S_AXI_MUX_SEL(mux_sel_c), + .S_AXI_R_LAST(r_last_c), + .S_AXI_R_LAST_INT(r_last_int_c), + + //// AXI Global Signals + .S_ACLK(S_ACLK), + .S_ARESETN(S_ARESETN), + //// AXI Full/Lite Slave Read (Read side) + .S_AXI_ARLEN(S_AXI_ARLEN), + .S_AXI_ARVALID(S_AXI_ARVALID), + .S_AXI_ARREADY(S_AXI_ARREADY), + .S_AXI_RLAST(S_AXI_RLAST), + .S_AXI_RVALID(S_AXI_RVALID), + .S_AXI_RREADY(S_AXI_RREADY), + //// AXI Full/Lite Read Address Signals to BRAM + .S_AXI_RD_EN(rd_en_c) + ); + + always@(*) begin + num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0); + total_bytes = (num_of_bytes_r)*(arlen_int_r+1); + wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes); + wrap_boundary_r = wrap_base_addr_r+total_bytes; + + //////// combinatorial from interface + arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN); + total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1); + wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c); + wrap_boundary_c = wrap_base_addr_c+total_bytes_c; + + arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1); + end + + ////------------------------------------------------------------------------- + //// BMG address generation + ////------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + araddr_reg <= 0; + arburst_int_r <= 0; + num_of_bytes_r <= 0; + end else begin + if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin + arburst_int_r <= arburst_int_c; + num_of_bytes_r <= num_of_bytes_c; + if (arburst_int_c == 2'b10) begin + if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin + araddr_reg <= wrap_base_addr_c; + end else begin + araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; + end + end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin + araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; + end + + end else if (addr_en_c == 1'b1) begin + araddr_reg <= S_AXI_ARADDR; + num_of_bytes_r <= num_of_bytes_c; + arburst_int_r <= arburst_int_c; + end else if (incr_addr_c == 1'b1) begin + if (arburst_int_r == 2'b10) begin + if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin + araddr_reg <= wrap_base_addr_r; + end else begin + araddr_reg <= araddr_reg + num_of_bytes_r; + end + end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin + araddr_reg <= araddr_reg + num_of_bytes_r; + end + end + end + end + +assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg); + + + ////----------------------------------------------------------------------- + //// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM + ////----------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + arlen_cntr <= 8'h01; + arlen_int_r <= 0; + end else begin + if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin + arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; + arlen_cntr <= S_AXI_ARLEN - 1'b1; + end else if (addr_en_c == 1'b1) begin + arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; + arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; + end else if (dec_alen_c == 1'b1) begin + arlen_cntr <= arlen_cntr - 1'b1 ; + end + else begin + arlen_cntr <= arlen_cntr; + end + end + end + + assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0; + + + ////------------------------------------------------------------------------ + //// AXI FULL FSM + //// Mux Selection of ARADDR + //// ARADDR is driven out from the read fsm based on the mux_sel_c + //// Based on mux_sel either ARADDR is given out or the latched ARADDR is + //// given out to BRAM + ////------------------------------------------------------------------------ + assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out; + + ////------------------------------------------------------------------------ + //// Assign output signals - AXI FULL FSM + ////------------------------------------------------------------------------ + assign S_AXI_RD_EN = rd_en_c; + + generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + S_AXI_RID <= 0; + ar_id_r <= 0; + end else begin + if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin + S_AXI_RID <= S_AXI_ARID; + ar_id_r <= S_AXI_ARID; + end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin + ar_id_r <= S_AXI_ARID; + end else if (rd_en_c == 1'b1) begin + S_AXI_RID <= ar_id_r; + end + end + end + end + endgenerate + +endmodule + +module blk_mem_axi_regs_fwd_v8_4 + #(parameter C_DATA_WIDTH = 8 + )( + input ACLK, + input ARESET, + input S_VALID, + output S_READY, + input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, + output M_VALID, + input M_READY, + output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA + ); + + reg [C_DATA_WIDTH-1:0] STORAGE_DATA; + wire S_READY_I; + reg M_VALID_I; + reg [1:0] ARESET_D; + + //assign local signal to its output signal + assign S_READY = S_READY_I; + assign M_VALID = M_VALID_I; + + always @(posedge ACLK) begin + ARESET_D <= {ARESET_D[0], ARESET}; + end + + //Save payload data whenever we have a transaction on the slave side + always @(posedge ACLK or ARESET) begin + if (ARESET == 1'b1) begin + STORAGE_DATA <= 0; + end else begin + if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin + STORAGE_DATA <= S_PAYLOAD_DATA; + end + end + end + + always @(posedge ACLK) begin + M_PAYLOAD_DATA = STORAGE_DATA; + end + + //M_Valid set to high when we have a completed transfer on slave side + //Is removed on a M_READY except if we have a new transfer on the slave side + + always @(posedge ACLK or ARESET_D) begin + if (ARESET_D != 2'b00) begin + M_VALID_I <= 1'b0; + end else begin + if (S_VALID == 1'b1) begin + //Always set M_VALID_I when slave side is valid + M_VALID_I <= 1'b1; + end else if (M_READY == 1'b1 ) begin + //Clear (or keep) when no slave side is valid but master side is ready + M_VALID_I <= 1'b0; + end + end + end + + //Slave Ready is either when Master side drives M_READY or we have space in our storage data + assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D)); + + endmodule + +//***************************************************************************** +// Output Register Stage module +// +// This module builds the output register stages of the memory. This module is +// instantiated in the main memory module (blk_mem_gen_v8_4_3) which is +// declared/implemented further down in this file. +//***************************************************************************** +module blk_mem_gen_v8_4_3_output_stage + #(parameter C_FAMILY = "virtex7", + parameter C_XDEVICEFAMILY = "virtex7", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RST = 0, + parameter C_RSTRAM = 0, + parameter C_RST_PRIORITY = "CE", + parameter C_INIT_VAL = "0", + parameter C_HAS_EN = 0, + parameter C_HAS_REGCE = 0, + parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter NUM_STAGES = 1, + parameter C_EN_ECC_PIPE = 0, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input RST, + input EN, + input REGCE, + input [C_DATA_WIDTH-1:0] DIN_I, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN_I, + input DBITERR_IN_I, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I, + input ECCPIPECE, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RST : Determines the presence of the RST port + // C_RSTRAM : Determines if special reset behavior is used + // C_RST_PRIORITY : Determines the priority between CE and SR + // C_INIT_VAL : Initialization value + // C_HAS_EN : Determines the presence of the EN port + // C_HAS_REGCE : Determines the presence of the REGCE port + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output + // of the RAM primitive + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // NUM_STAGES : Determines the number of output stages + // FLOP_DELAY : Constant delay for register assignments + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLK : Clock to synchronize all read and write operations + // RST : Reset input to reset memory outputs to a user-defined + // reset state + // EN : Enable all read and write operations + // REGCE : Register Clock Enable to control each pipeline output + // register stages + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + ////////////////////////////////////////////////////////////////////////// + +// Fix for CR-509792 + + localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; + + // Declare the pipeline registers + // (includes mem output reg, mux pipeline stages, and mux output reg) + reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; + reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; + reg [REG_STAGES-1:0] sbiterr_regs; + reg [REG_STAGES-1:0] dbiterr_regs; + + reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; + reg [C_DATA_WIDTH-1:0] init_val ; + + //********************************************* + // Wire off optional inputs based on parameters + //********************************************* + wire en_i; + wire regce_i; + wire rst_i; + + // Internal signals + reg [C_DATA_WIDTH-1:0] DIN; + reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN; + reg SBITERR_IN; + reg DBITERR_IN; + + + // Internal enable for output registers is tied to user EN or '1' depending + // on parameters + assign en_i = (C_HAS_EN==0 || EN); + + // Internal register enable for output registers is tied to user REGCE, EN or + // '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); + + //Internal SRR is tied to user RST or '0' depending on parameters + assign rst_i = (C_HAS_RST==1) && RST; + + //**************************************************** + // Power on: load up the output registers and latches + //**************************************************** + initial begin + if (!($sscanf(init_str, "%h", init_val))) begin + init_val = 0; + end + DOUT = init_val; + RDADDRECC = 0; + SBITERR = 1'b0; + DBITERR = 1'b0; + DIN = {(C_DATA_WIDTH){1'b0}}; + RDADDRECC_IN = 0; + SBITERR_IN = 0; + DBITERR_IN = 0; + // This will be one wider than need, but 0 is an error + out_regs = {(REG_STAGES+1){init_val}}; + rdaddrecc_regs = 0; + sbiterr_regs = {(REG_STAGES+1){1'b0}}; + dbiterr_regs = {(REG_STAGES+1){1'b0}}; + end + + //*********************************************** + // NUM_STAGES = 0 (No output registers. RAM only) + //*********************************************** + generate if (NUM_STAGES == 0) begin : zero_stages + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg + always @* begin + DIN = DIN_I; + SBITERR_IN = SBITERR_IN_I; + DBITERR_IN = DBITERR_IN_I; + RDADDRECC_IN = RDADDRECC_IN_I; + end + end + endgenerate + + generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg + always @(posedge CLK) begin + if(ECCPIPECE == 1) begin + DIN <= #FLOP_DELAY DIN_I; + SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I; + DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I; + RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I; + end + end + end + endgenerate + + + //*********************************************** + // NUM_STAGES = 1 + // (Mem Output Reg only or Mux Output Reg only) + //*********************************************** + + // Possible valid combinations: + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) + // +-----------------------------------------+ + // | C_RSTRAM_* | Reset Behavior | + // +----------------+------------------------+ + // | 0 | Normal Behavior | + // +----------------+------------------------+ + // | 1 | Special Behavior | + // +----------------+------------------------+ + // + // Normal = REGCE gates reset, as in the case of all families except S3ADSP. + // Special = EN gates reset, as in the case of S3ADSP. + + generate if (NUM_STAGES == 1 && + (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) || + C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) + begin : one_stages_norm + + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end //end Priority conditions + end //end RST Type conditions + end //end one_stages_norm generate statement + endgenerate + + // Special Reset Behavior for S3ADSP + generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp")) + begin : one_stage_splbhv + always @(posedge CLK) begin + if (en_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + end else if (regce_i && !rst_i) begin + DOUT <= #FLOP_DELAY DIN; + end //Output signal assignments + end //end CLK + end //end one_stage_splbhv generate statement + endgenerate + + //************************************************************ + // NUM_STAGES > 1 + // Mem Output Reg + Mux Output Reg + // or + // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg + // or + // Mux Pipeline Stages (>0) + Mux Output Reg + //************************************************************* + generate if (NUM_STAGES > 1) begin : multi_stage + //Asynchronous Reset + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end //end Priority conditions + // Shift the data through the output stages + if (en_i) begin + out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; + rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; + sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; + dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; + end + end //end CLK + end //end multi_stage generate statement + endgenerate +endmodule + +module blk_mem_gen_v8_4_3_softecc_output_reg_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_USE_SOFTECC = 0, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN, + input DBITERR_IN, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // FLOP_DELAY : Constant delay for register assignments + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLK : Clock to synchronize all read and write operations + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + ////////////////////////////////////////////////////////////////////////// + + reg [C_DATA_WIDTH-1:0] dout_i = 0; + reg sbiterr_i = 0; + reg dbiterr_i = 0; + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0; + + //*********************************************** + // NO OUTPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + //*********************************************** + // WITH OUTPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage + always @(posedge CLK) begin + dout_i <= #FLOP_DELAY DIN; + rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN; + sbiterr_i <= #FLOP_DELAY SBITERR_IN; + dbiterr_i <= #FLOP_DELAY DBITERR_IN; + end + + always @* begin + DOUT = dout_i; + RDADDRECC = rdaddrecc_i; + SBITERR = sbiterr_i; + DBITERR = dbiterr_i; + end //end always + end //end in_or_out_stage generate statement + endgenerate + +endmodule + + +//***************************************************************************** +// Main Memory module +// +// This module is the top-level behavioral model and this implements the RAM +//***************************************************************************** +module blk_mem_gen_v8_4_3_mem_module + #(parameter C_CORENAME = "blk_mem_gen_v8_4_3", + parameter C_FAMILY = "virtex7", + parameter C_XDEVICEFAMILY = "virtex7", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_USE_BRAM_BLOCK = 0, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_INIT_FILE = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter FLOP_DELAY = 100, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_EN_ECC_PIPE = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 + ) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + input ECCPIPECE, + input SLEEP, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC + ); +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + ////////////////////////////////////////////////////////////////////////// + + +// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_4_3" and it is +// only used by this module to print warning messages. It is neither passed +// down from blk_mem_gen_v8_4_3_xst.v nor present in the instantiation template +// coregen generates + + //*************************************************************************** + // constants for the core behavior + //*************************************************************************** + // file handles for logging + //-------------------------------------------------- + localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range + localparam COLLFILE = 32'h8000_0001; //stdout for coll detection + localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors + + // other constants + //-------------------------------------------------- + localparam COLL_DELAY = 100; // 100 ps + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + + localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); + + localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ? + MIN_WIDTH_A : MIN_WIDTH_B; + + localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ? + MAX_DEPTH_A : MAX_DEPTH_B; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + // Calculate the width ratios of each port with respect to the narrowest + // port + localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH; + localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH; + localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH; + localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A; + localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A; + localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B; + localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B; + + // If byte writes aren't being used, make sure BYTE_SIZE is not + // wider than the memory elements to avoid compilation warnings + localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH; + + // The memory + reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1]; + reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1]; + reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3; + // ECC error arrays + reg sbiterr_arr [0:MAX_DEPTH-1]; + reg dbiterr_arr [0:MAX_DEPTH-1]; + + reg softecc_sbiterr_arr [0:MAX_DEPTH-1]; + reg softecc_dbiterr_arr [0:MAX_DEPTH-1]; + // Memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + + // ECC error inputs and outputs from output_stage module: + reg sbiterr_in; + wire sbiterr_sdp; + reg dbiterr_in; + wire dbiterr_sdp; + + wire [C_READ_WIDTH_B-1:0] dout_i; + wire dbiterr_i; + wire sbiterr_i; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i; + + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; + + // Reset values + reg [C_READ_WIDTH_A-1:0] inita_val; + reg [C_READ_WIDTH_B-1:0] initb_val; + + // Collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // Temporary variables for initialization + //--------------------------------------- + integer status; + integer initfile; + integer meminitfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + reg [C_WRITE_WIDTH_A-1:0] mem_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE; + + + //Constants used to calculate the effective address widths for each of the + //four ports. + integer cnt = 1; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtexuplushbm"?"virtex7":(C_FAMILY=="zynquplusrfsoc"?"virtex7":(C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))))))))); + + // Internal configuration parameters + //--------------------------------------------- + localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam HAS_A_WRITE = (!IS_ROM); + localparam HAS_B_WRITE = (C_MEM_TYPE==2); + localparam HAS_A_READ = (C_MEM_TYPE!=1); + localparam HAS_B_READ = (!SINGLE_PORT); + localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE); + + // Calculate the mux pipeline register stages for Port A and Port B + //------------------------------------------------------------------ + localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ? + C_MUX_PIPELINE_STAGES : 0; + localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ? + C_MUX_PIPELINE_STAGES : 0; + + // Calculate total number of register stages in the core + // ----------------------------------------------------- + localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A); + + localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B); + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + wire rsta_outp_stage; + wire rstb_outp_stage; + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is modeled by the behavioral models only for Virtex-6. + // For Virtex-5, these outputs will be tied to 0. + assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0; + assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0; + assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT; + // To match RTL : In RTL, write enable of the primitive is tied to all 1's and + // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the + // write operation depends on both enable and write enable. So, the below code + // which is actually doing the write operation only on enable ignoring the wea + // is removed to be in consistent with RTL. + // To Fix CR855535 (The fix to this CR is reverted to match RTL) + //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0; + assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0; + assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0; + assign rea_i = (HAS_A_READ) ? ena_i : 'b0; + assign reb_i = (HAS_B_READ) ? enb_i : 'b0; + + // These signals reset the memory latches + + assign reseta_i = + ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) || + (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); + + assign resetb_i = + ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) || + (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); + + // Tasks to access the memory + //--------------------------- + //************** + // write_a + //************** + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data, + input inj_sbiterr, + input inj_dbiterr); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_A_DIV); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_A + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Insert double bit errors: + if (C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin +// Modified for Implementing CR_859399 + current_contents[0] = !(current_contents[30]); + current_contents[1] = !(current_contents[62]); + + /*current_contents[0] = !(current_contents[0]); + current_contents[1] = !(current_contents[1]);*/ + end + end + + // Insert softecc double bit errors: + if (C_USE_SOFTECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0]; + doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1]; + doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2]; + current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0]; + end + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_A] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_A + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + + // Store the address at which error is injected: + if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + sbiterr_arr[addr] = 1; + end else begin + sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + dbiterr_arr[addr] = 1; + end else begin + dbiterr_arr[addr] = 0; + end + end + + // Store the address at which softecc error is injected: + if (C_USE_SOFTECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + softecc_sbiterr_arr[addr] = 1; + end else begin + softecc_sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + softecc_dbiterr_arr[addr] = 1; + end else begin + softecc_dbiterr_arr[addr] = 0; + end + end + + end + end + endtask + + //************** + // write_b + //************** + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_B_DIV); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_B + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_B] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_B + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + end + end + endtask + + //************** + // read_a + //************** + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #FLOP_DELAY inita_val; + end else begin + // Shift the address by the ratio + address = (addr/READ_ADDR_A_DIV); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + memory_out_a <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_A==1) begin + memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin + memory_out_a[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i]; + end + end //end READ_WIDTH_RATIO_A==1 loop + + end //end valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // read_b + //************** + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #FLOP_DELAY initb_val; + sbiterr_in <= #FLOP_DELAY 1'b0; + dbiterr_in <= #FLOP_DELAY 1'b0; + rdaddrecc_in <= #FLOP_DELAY 0; + end else begin + // Shift the address + address = (addr/READ_ADDR_B_DIV); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + memory_out_b <= #FLOP_DELAY 'bX; + sbiterr_in <= #FLOP_DELAY 1'bX; + dbiterr_in <= #FLOP_DELAY 1'bX; + rdaddrecc_in <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_B==1) begin + memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin + memory_out_b[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i]; + end + end + + if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin + rdaddrecc_in <= #FLOP_DELAY addr; + if (sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end + + end else if (C_USE_SOFTECC == 1) begin + rdaddrecc_in <= #FLOP_DELAY addr; + if (softecc_sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (softecc_dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end + end else begin + rdaddrecc_in <= #FLOP_DELAY 0; + dbiterr_in <= #FLOP_DELAY 1'b0; + sbiterr_in <= #FLOP_DELAY 1'b0; + end //end SOFTECC Loop + end //end Valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // reset_a + //************** + task reset_a (input reg reset); + begin + if (reset) memory_out_a <= #FLOP_DELAY inita_val; + end + endtask + + //************** + // reset_b + //************** + task reset_b (input reg reset); + begin + if (reset) memory_out_b <= #FLOP_DELAY initb_val; + end + endtask + + //************** + // init_memory + //************** + task init_memory; + integer i, j, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being + //initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by WRITE_ADDR_A_DIV through the memory via the + // Port A write interface to hit every location once + addr_step = WRITE_ADDR_A_DIV; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + + if (C_USE_BRAM_BLOCK) begin + // Get specialized data from the MIF file + if (C_INIT_FILE != "NONE") begin + if (mem_init_file_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!", + C_CORENAME); + $finish; + end else begin + meminitfile = $fopen(mem_init_file_str, "r"); + if (meminitfile == 0) begin + $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", + "C_INIT_FILE: %0s!"}, + C_CORENAME, mem_init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + $readmemh(mem_init_file_str, memory ); + for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin + end + $fclose(meminitfile); + end //meminitfile + end //mem_init_file_str + end //C_INIT_FILE + end //C_USE_BRAM_BLOCK + + //Display output message indicating that the behavioral model is done + //initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) + $display(" Block Memory Generator data initialization complete."); + end + endtask + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + //******************* + // collision_check + //******************* + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg c_aw_bw, c_aw_br, c_ar_bw; + integer scaled_addra_to_waddrb_width; + integer scaled_addrb_to_waddrb_width; + integer scaled_addra_to_waddra_width; + integer scaled_addrb_to_waddra_width; + integer scaled_addra_to_raddrb_width; + integer scaled_addrb_to_raddrb_width; + integer scaled_addra_to_raddra_width; + integer scaled_addrb_to_raddra_width; + + + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + //If write_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_b_width. Once both are scaled to + //write_addr_b_width, compare. + scaled_addra_to_waddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_b_width)); + scaled_addrb_to_waddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_b_width)); + + //If write_addr_a_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_a_width. Once both are scaled to + //write_addr_a_width, compare. + scaled_addra_to_waddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_a_width)); + scaled_addrb_to_waddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_a_width)); + + //If read_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_b_width. Once both are scaled to + //read_addr_b_width, compare. + scaled_addra_to_raddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_b_width)); + scaled_addrb_to_raddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_b_width)); + + //If read_addr_a_width is smaller, scale both addresses to that width for + //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_a_width. Once both are scaled to + //read_addr_a_width, compare. + scaled_addra_to_raddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_a_width)); + scaled_addrb_to_raddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_a_width)); + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + //a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + //to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + //******************************* + // power on values + //******************************* + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(inita_str, "%h", inita_val)) begin + memory_out_a = inita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(initb_str, "%h", initb_val)) begin + memory_out_b = initb_val; + end else begin + memory_out_b = 0; + end + + sbiterr_in = 1'b0; + dbiterr_in = 1'b0; + rdaddrecc_in = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV); + read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV); + write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV); + read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV); + + $display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //*************************************************************************** + // These are the main blocks which schedule read and write operations + // Note that the reset priority feature at the latch stage is only supported + // for Spartan-6. For other families, the default priority at the latch stage + // is "CE" + //*************************************************************************** + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + generate + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_wf_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + + if (rea_i) read_a(ADDRA, reseta_i); + + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_rf_wf + always @(posedge CLKA) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_wf_rf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_rf_rf + always @(posedge CLKA) begin + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_wf_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_rf_nc + always @(posedge CLKA) begin + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_nc_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_nc_rf + always @(posedge CLKA) begin + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_nc_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + else if(C_COMMON_CLK) begin: com_clk_sched_default + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + endgenerate + + // Asynchronous clocks: port operation is independent + generate + if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf + always @(posedge CLKA) begin + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + end + endgenerate + + generate + if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf + always @(posedge CLKB) begin + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + endgenerate + + + //*************************************************************** + // Instantiate the variable depth output register stage module + //*************************************************************** + // Port A + + assign rsta_outp_stage = RSTA & (~SLEEP); + + blk_mem_gen_v8_4_3_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE ("SYNC"), + .C_HAS_RST (C_HAS_RSTA), + .C_RSTRAM (C_RSTRAM_A), + .C_RST_PRIORITY (C_RST_PRIORITY_A), + .C_INIT_VAL (C_INITA_VAL), + .C_HAS_EN (C_HAS_ENA), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_DATA_WIDTH (C_READ_WIDTH_A), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_A), + .C_EN_ECC_PIPE (0), + .FLOP_DELAY (FLOP_DELAY)) + reg_a + (.CLK (CLKA), + .RST (rsta_outp_stage),//(RSTA), + .EN (ENA), + .REGCE (REGCEA), + .DIN_I (memory_out_a), + .DOUT (DOUTA), + .SBITERR_IN_I (1'b0), + .DBITERR_IN_I (1'b0), + .SBITERR (), + .DBITERR (), + .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}), + .ECCPIPECE (1'b0), + .RDADDRECC () + ); + + assign rstb_outp_stage = RSTB & (~SLEEP); + + // Port B + blk_mem_gen_v8_4_3_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE ("SYNC"), + .C_HAS_RST (C_HAS_RSTB), + .C_RSTRAM (C_RSTRAM_B), + .C_RST_PRIORITY (C_RST_PRIORITY_B), + .C_INIT_VAL (C_INITB_VAL), + .C_HAS_EN (C_HAS_ENB), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_B), + .C_EN_ECC_PIPE (C_EN_ECC_PIPE), + .FLOP_DELAY (FLOP_DELAY)) + reg_b + (.CLK (CLKB), + .RST (rstb_outp_stage),//(RSTB), + .EN (ENB), + .REGCE (REGCEB), + .DIN_I (memory_out_b), + .DOUT (dout_i), + .SBITERR_IN_I (sbiterr_in), + .DBITERR_IN_I (dbiterr_in), + .SBITERR (sbiterr_i), + .DBITERR (dbiterr_i), + .RDADDRECC_IN_I (rdaddrecc_in), + .ECCPIPECE (ECCPIPECE), + .RDADDRECC (rdaddrecc_i) + ); + + //*************************************************************** + // Instantiate the Input and Output register stages + //*************************************************************** +blk_mem_gen_v8_4_3_softecc_output_reg_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_USE_SOFTECC (C_USE_SOFTECC), + .FLOP_DELAY (FLOP_DELAY)) + has_softecc_output_reg_stage + (.CLK (CLKB), + .DIN (dout_i), + .DOUT (DOUTB), + .SBITERR_IN (sbiterr_i), + .DBITERR_IN (dbiterr_i), + .SBITERR (sbiterr_sdp), + .DBITERR (dbiterr_sdp), + .RDADDRECC_IN (rdaddrecc_i), + .RDADDRECC (rdaddrecc_sdp) +); + + //**************************************************** + // Synchronous collision checks + //**************************************************** +// CR 780544 : To make verilog model's collison warnings in consistant with +// vhdl model, the non-blocking assignments are replaced with blocking +// assignments. + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision = 0; + end + end else begin + is_collision = 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision = 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision = 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + //**************************************************** + // Asynchronous collision checks + //**************************************************** + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; + wire [0:0] #COLL_DELAY wea_delay = wea_i; + wire #COLL_DELAY ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; + wire [0:0] #COLL_DELAY web_delay = web_i; + wire #COLL_DELAY enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a = 0; + end + end else begin + is_collision_a = 0; + end + + if (ena_i && enb_delay) begin + if(wea_i || web_delay) begin + is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay, + web_delay); + end else begin + is_collision_delay_a = 0; + end + end else begin + is_collision_delay_a = 0; + end + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b = 0; + end + end else begin + is_collision_b = 0; + end + + if (ena_delay && enb_i) begin + if (wea_delay || web_i) begin + is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB, + web_i); + end else begin + is_collision_delay_b = 0; + end + end else begin + is_collision_delay_b = 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule +//***************************************************************************** +// Top module wraps Input register and Memory module +// +// This module is the top-level behavioral model and this implements the memory +// module and the input registers +//***************************************************************************** +module blk_mem_gen_v8_4_3 + #(parameter C_CORENAME = "blk_mem_gen_v8_4_3", + parameter C_FAMILY = "virtex7", + parameter C_XDEVICEFAMILY = "virtex7", + parameter C_ELABORATION_DIR = "", + parameter C_INTERFACE_TYPE = 0, + parameter C_USE_BRAM_BLOCK = 0, + parameter C_CTRL_ECC_ALGO = "NONE", + parameter C_ENABLE_32BIT_ADDRESS = 0, + parameter C_AXI_TYPE = 0, + parameter C_AXI_SLAVE_TYPE = 0, + parameter C_HAS_AXI_ID = 0, + parameter C_AXI_ID_WIDTH = 4, + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_INIT_FILE = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + //parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_READ_LATENCY_A = 1, + parameter C_READ_LATENCY_B = 1, + parameter C_USE_ECC = 0, + parameter C_EN_ECC_PIPE = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_EN_SLEEP_PIN = 0, + parameter C_USE_URAM = 0, + parameter C_EN_RDADDRA_CHG = 0, + parameter C_EN_RDADDRB_CHG = 0, + parameter C_EN_DEEPSLEEP_PIN = 0, + parameter C_EN_SHUTDOWN_PIN = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_COUNT_36K_BRAM = "", + parameter C_COUNT_18K_BRAM = "", + parameter C_EST_POWER_SUMMARY = "", + parameter C_DISABLE_WARN_BHV_RANGE = 0 + + ) + (input clka, + input rsta, + input ena, + input regcea, + input [C_WEA_WIDTH-1:0] wea, + input [C_ADDRA_WIDTH-1:0] addra, + input [C_WRITE_WIDTH_A-1:0] dina, + output [C_READ_WIDTH_A-1:0] douta, + input clkb, + input rstb, + input enb, + input regceb, + input [C_WEB_WIDTH-1:0] web, + input [C_ADDRB_WIDTH-1:0] addrb, + input [C_WRITE_WIDTH_B-1:0] dinb, + output [C_READ_WIDTH_B-1:0] doutb, + input injectsbiterr, + input injectdbiterr, + output sbiterr, + output dbiterr, + output [C_ADDRB_WIDTH-1:0] rdaddrecc, + input eccpipece, + input sleep, + input deepsleep, + input shutdown, + output rsta_busy, + output rstb_busy, + //AXI BMG Input and Output Port Declarations + + //AXI Global Signals + input s_aclk, + input s_aresetn, + + //AXI Full/lite slave write (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_awid, + input [31:0] s_axi_awaddr, + input [7:0] s_axi_awlen, + input [2:0] s_axi_awsize, + input [1:0] s_axi_awburst, + input s_axi_awvalid, + output s_axi_awready, + input [C_WRITE_WIDTH_A-1:0] s_axi_wdata, + input [C_WEA_WIDTH-1:0] s_axi_wstrb, + input s_axi_wlast, + input s_axi_wvalid, + output s_axi_wready, + output [C_AXI_ID_WIDTH-1:0] s_axi_bid, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + input s_axi_bready, + + //AXI Full/lite slave read (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_arid, + input [31:0] s_axi_araddr, + input [7:0] s_axi_arlen, + input [2:0] s_axi_arsize, + input [1:0] s_axi_arburst, + input s_axi_arvalid, + output s_axi_arready, + output [C_AXI_ID_WIDTH-1:0] s_axi_rid, + output [C_WRITE_WIDTH_B-1:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output s_axi_rlast, + output s_axi_rvalid, + input s_axi_rready, + + //AXI Full/lite sideband signals + input s_axi_injectsbiterr, + input s_axi_injectdbiterr, + output s_axi_sbiterr, + output s_axi_dbiterr, + output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc + + ); +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_HAS_SOFTECC_INPUT_REGS_A : + // C_HAS_SOFTECC_OUTPUT_REGS_B : + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + ////////////////////////////////////////////////////////////////////////// + + wire SBITERR; + wire DBITERR; + wire S_AXI_AWREADY; + wire S_AXI_WREADY; + wire S_AXI_BVALID; + wire S_AXI_ARREADY; + wire S_AXI_RLAST; + wire S_AXI_RVALID; + wire S_AXI_SBITERR; + wire S_AXI_DBITERR; + + wire [C_WEA_WIDTH-1:0] WEA = wea; + wire [C_ADDRA_WIDTH-1:0] ADDRA = addra; + wire [C_WRITE_WIDTH_A-1:0] DINA = dina; + wire [C_READ_WIDTH_A-1:0] DOUTA; + wire [C_WEB_WIDTH-1:0] WEB = web; + wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb; + wire [C_WRITE_WIDTH_B-1:0] DINB = dinb; + wire [C_READ_WIDTH_B-1:0] DOUTB; + wire [C_ADDRB_WIDTH-1:0] RDADDRECC; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid; + wire [31:0] S_AXI_AWADDR = s_axi_awaddr; + wire [7:0] S_AXI_AWLEN = s_axi_awlen; + wire [2:0] S_AXI_AWSIZE = s_axi_awsize; + wire [1:0] S_AXI_AWBURST = s_axi_awburst; + wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata; + wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; + wire [1:0] S_AXI_BRESP; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid; + wire [31:0] S_AXI_ARADDR = s_axi_araddr; + wire [7:0] S_AXI_ARLEN = s_axi_arlen; + wire [2:0] S_AXI_ARSIZE = s_axi_arsize; + wire [1:0] S_AXI_ARBURST = s_axi_arburst; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; + wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA; + wire [1:0] S_AXI_RRESP; + wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC; + // Added to fix the simulation warning #CR731605 + wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0; + wire ECCPIPECE; + wire SLEEP; + reg RSTA_BUSY = 0; + reg RSTB_BUSY = 0; + // Declaration of internal signals to avoid warnings #927399 + wire CLKA; + wire RSTA; + wire ENA; + wire REGCEA; + wire CLKB; + wire RSTB; + wire ENB; + wire REGCEB; + wire INJECTSBITERR; + wire INJECTDBITERR; + wire S_ACLK; + wire S_ARESETN; + wire S_AXI_AWVALID; + wire S_AXI_WLAST; + wire S_AXI_WVALID; + wire S_AXI_BREADY; + wire S_AXI_ARVALID; + wire S_AXI_RREADY; + wire S_AXI_INJECTSBITERR; + wire S_AXI_INJECTDBITERR; + + assign CLKA = clka; + assign RSTA = rsta; + assign ENA = ena; + assign REGCEA = regcea; + assign CLKB = clkb; + assign RSTB = rstb; + assign ENB = enb; + assign REGCEB = regceb; + assign INJECTSBITERR = injectsbiterr; + assign INJECTDBITERR = injectdbiterr; + assign ECCPIPECE = eccpipece; + assign SLEEP = sleep; + assign sbiterr = SBITERR; + assign dbiterr = DBITERR; + assign S_ACLK = s_aclk; + assign S_ARESETN = s_aresetn; + assign S_AXI_AWVALID = s_axi_awvalid; + assign s_axi_awready = S_AXI_AWREADY; + assign S_AXI_WLAST = s_axi_wlast; + assign S_AXI_WVALID = s_axi_wvalid; + assign s_axi_wready = S_AXI_WREADY; + assign s_axi_bvalid = S_AXI_BVALID; + assign S_AXI_BREADY = s_axi_bready; + assign S_AXI_ARVALID = s_axi_arvalid; + assign s_axi_arready = S_AXI_ARREADY; + assign s_axi_rlast = S_AXI_RLAST; + assign s_axi_rvalid = S_AXI_RVALID; + assign S_AXI_RREADY = s_axi_rready; + assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr; + assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr; + assign s_axi_sbiterr = S_AXI_SBITERR; + assign s_axi_dbiterr = S_AXI_DBITERR; + + assign rsta_busy = RSTA_BUSY; + assign rstb_busy = RSTB_BUSY; + + assign doutb = DOUTB; + assign douta = DOUTA; + assign rdaddrecc = RDADDRECC; + assign s_axi_bid = S_AXI_BID; + assign s_axi_bresp = S_AXI_BRESP; + assign s_axi_rid = S_AXI_RID; + assign s_axi_rdata = S_AXI_RDATA; + assign s_axi_rresp = S_AXI_RRESP; + assign s_axi_rdaddrecc = S_AXI_RDADDRECC; + + localparam FLOP_DELAY = 100; // 100 ps + + reg injectsbiterr_in; + reg injectdbiterr_in; + reg rsta_in; + reg ena_in; + reg regcea_in; + reg [C_WEA_WIDTH-1:0] wea_in; + reg [C_ADDRA_WIDTH-1:0] addra_in; + reg [C_WRITE_WIDTH_A-1:0] dina_in; + + wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c; + wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c; + wire s_axi_wr_en_c; + wire s_axi_rd_en_c; + wire s_aresetn_a_c; + wire [7:0] s_axi_arlen_c ; + + + wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c; + wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c; + wire [1:0] s_axi_rresp_c; + wire s_axi_rlast_c; + wire s_axi_rvalid_c; + wire s_axi_rready_c; + wire regceb_c; + + localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3; + wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c; + wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c; + +// Safety logic related signals + + reg [4:0] RSTA_SHFT_REG = 0; + reg POR_A = 0; + reg [4:0] RSTB_SHFT_REG = 0; + reg POR_B = 0; + + reg ENA_dly = 0; + reg ENA_dly_D = 0; + + reg ENB_dly = 0; + reg ENB_dly_D = 0; + + wire RSTA_I_SAFE; + wire RSTB_I_SAFE; + + wire ENA_I_SAFE; + wire ENB_I_SAFE; + + reg ram_rstram_a_busy = 0; + reg ram_rstreg_a_busy = 0; + reg ram_rstram_b_busy = 0; + reg ram_rstreg_b_busy = 0; + + reg ENA_dly_reg = 0; + reg ENB_dly_reg = 0; + + reg ENA_dly_reg_D = 0; + reg ENB_dly_reg_D = 0; + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + //************** + // log2int + //************** + function integer log2int (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + cnt= data_value; + + for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin + width = width + 1; + end //loop + + log2int = width; + + end //log2int + endfunction + + //************************************************************************** + // FUNCTION : divroundup + // Returns the ceiling value of the division + // Data_value - the quantity to be divided, dividend + // Divisor - the value to divide the data_value by + //************************************************************************** + function integer divroundup (input integer data_value,input integer divisor); + integer div; + begin + div = data_value/divisor; + if ((data_value % divisor) != 0) begin + div = div+1; + end //if + divroundup = div; + end //if + endfunction + + localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0); + localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8); + localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB; + + //Data Width Number of LSB address bits to be discarded + //1 to 16 1 + //17 to 32 2 + //33 to 64 3 + //65 to 128 4 + //129 to 256 5 + //257 to 512 6 + //513 to 1024 7 + // The following two constants determine this. + + localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8))); + localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL); + localparam C_AXI_OS_WR = 2; + + //*********************************************** + // INPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage + always @* begin + injectsbiterr_in = INJECTSBITERR; + injectdbiterr_in = INJECTDBITERR; + rsta_in = RSTA; + ena_in = ENA; + regcea_in = REGCEA; + wea_in = WEA; + addra_in = ADDRA; + dina_in = DINA; + end //end always + end //end no_softecc_input_reg_stage + endgenerate + + generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage + always @(posedge CLKA) begin + injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR; + injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR; + rsta_in <= #FLOP_DELAY RSTA; + ena_in <= #FLOP_DELAY ENA; + regcea_in <= #FLOP_DELAY REGCEA; + wea_in <= #FLOP_DELAY WEA; + addra_in <= #FLOP_DELAY ADDRA; + dina_in <= #FLOP_DELAY DINA; + end //end always + end //end input_reg_stages generate statement + endgenerate + + //************************************************************************** + // NO SAFETY LOGIC + //************************************************************************** + + generate + if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN + assign ENA_I_SAFE = ena_in; + assign ENB_I_SAFE = ENB; + assign RSTA_I_SAFE = rsta_in; + assign RSTB_I_SAFE = RSTB; + end + endgenerate + + //*************************************************************************** + // SAFETY LOGIC + // Power-ON Reset Generation + //*************************************************************************** + generate + if (C_EN_SAFETY_CKT == 1) begin + always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ; + always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0]; + always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ; + always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; + + assign RSTA_I_SAFE = rsta_in | POR_A; + assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B); + end + endgenerate + + //----------------------------------------------------------------------------- + // -- RSTA/B_BUSY Generation + //----------------------------------------------------------------------------- + + generate + if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG + always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D; + always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy; + end + endgenerate + + generate + if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG + always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D; + always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy; + end + endgenerate + + generate + if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY + always @(*) RSTB_BUSY = 1'b0; + end + endgenerate + + generate + if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG + always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D; + always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy; + end + endgenerate + + generate + if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG + always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D; + always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy; + end + endgenerate + + //----------------------------------------------------------------------------- + // -- ENA/ENB Generation + //----------------------------------------------------------------------------- + + generate + if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG + always @(posedge clka) begin + ENA_dly <= #FLOP_DELAY RSTA_I_SAFE; + ENA_dly_D <= #FLOP_DELAY ENA_dly; + end + assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in); + end + endgenerate + + generate + if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG + always @(posedge clka) begin + ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE; + ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg; + end + assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in); + end + endgenerate + + generate + if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB + assign ENB_I_SAFE = 1'b0; + end + endgenerate + + generate + if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG + always @(posedge clkb) begin : PROC_ENB_GEN + ENB_dly <= #FLOP_DELAY RSTB_I_SAFE; + ENB_dly_D <= #FLOP_DELAY ENB_dly; + end + assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB); + end + endgenerate + + generate + if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG + always @(posedge clkb) begin : PROC_ENB_GEN + ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE; + ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg; + end + assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB); + end + endgenerate + + generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module +blk_mem_gen_v8_4_3_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_ALGORITHM (C_ALGORITHM), + .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_INIT_FILE (C_INIT_FILE), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE ("SYNC"), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_EN_ECC_PIPE (C_EN_ECC_PIPE), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v8_4_3_inst + (.CLKA (CLKA), + .RSTA (RSTA_I_SAFE),//(rsta_in), + .ENA (ENA_I_SAFE),//(ena_in), + .REGCEA (regcea_in), + .WEA (wea_in), + .ADDRA (addra_in), + .DINA (dina_in), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB_I_SAFE),//(RSTB), + .ENB (ENB_I_SAFE),//(ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .ECCPIPECE (ECCPIPECE), + .SLEEP (SLEEP), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (RDADDRECC) + ); + end + endgenerate + + generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module + + localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A); + localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B); + + localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8); + localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8); + // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8); + // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8); + localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB; + localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB; + + // Data Width Number of LSB address bits to be discarded + // 1 to 16 1 + // 17 to 32 2 + // 33 to 64 3 + // 65 to 128 4 + // 129 to 256 5 + // 257 to 512 6 + // 513 to 1024 7 + // The following two constants determine this. + + localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); + localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8))); + localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A; + localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B; + + wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i; + wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i; + wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i; + + assign msb_zero_i = 0; + assign lsb_zero_i = 0; + assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i}; + +blk_mem_gen_v8_4_3_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_INIT_FILE (C_INIT_FILE), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE ("SYNC"), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_EN_ECC_PIPE (C_EN_ECC_PIPE), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v8_4_3_inst + (.CLKA (CLKA), + .RSTA (RSTA_I_SAFE),//(rsta_in), + .ENA (ENA_I_SAFE),//(ena_in), + .REGCEA (regcea_in), + .WEA (wea_in), + .ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]), + .DINA (dina_in), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB_I_SAFE),//(RSTB), + .ENB (ENB_I_SAFE),//(ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .ECCPIPECE (ECCPIPECE), + .SLEEP (SLEEP), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (rdaddrecc_i) + ); + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs + assign S_AXI_RDATA = s_axi_rdata_c; + assign S_AXI_RLAST = s_axi_rlast_c; + assign S_AXI_RVALID = s_axi_rvalid_c; + assign S_AXI_RID = s_axi_rid_c; + assign S_AXI_RRESP = s_axi_rresp_c; + assign s_axi_rready_c = S_AXI_RREADY; + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb + assign regceb_c = s_axi_rvalid_c && s_axi_rready_c; + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb + assign regceb_c = REGCEB; + end + endgenerate + + generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs + assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c}; + assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; + assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B]; + assign S_AXI_RRESP = m_axi_payload_c[2:1]; + assign S_AXI_RLAST = m_axi_payload_c[0]; + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs + assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c}; + assign S_AXI_RDATA = s_axi_rdata_c; + assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; + assign S_AXI_RRESP = m_axi_payload_c[2:1]; + assign S_AXI_RLAST = m_axi_payload_c[0]; + end + endgenerate + + generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd + + blk_mem_axi_regs_fwd_v8_4 + #(.C_DATA_WIDTH (C_AXI_PAYLOAD)) + axi_regs_inst ( + .ACLK (S_ACLK), + .ARESET (s_aresetn_a_c), + .S_VALID (s_axi_rvalid_c), + .S_READY (s_axi_rready_c), + .S_PAYLOAD_DATA (s_axi_payload_c), + .M_VALID (S_AXI_RVALID), + .M_READY (S_AXI_RREADY), + .M_PAYLOAD_DATA (m_axi_payload_c) + ); + end + endgenerate + + generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module + +assign s_aresetn_a_c = !S_ARESETN; +assign S_AXI_BRESP = 2'b00; +assign s_axi_rresp_c = 2'b00; +assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0; + + blk_mem_axi_write_wrapper_beh_v8_4 + #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_AXI_TYPE (C_AXI_TYPE), + .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), + .C_MEMORY_TYPE (C_MEM_TYPE), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), + .C_HAS_AXI_ID (C_HAS_AXI_ID), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A), + .C_AXI_OS_WR (C_AXI_OS_WR)) + axi_wr_fsm ( + // AXI Global Signals + .S_ACLK (S_ACLK), + .S_ARESETN (s_aresetn_a_c), + // AXI Full/Lite Slave Write interface + .S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), + .S_AXI_AWLEN (S_AXI_AWLEN), + .S_AXI_AWID (S_AXI_AWID), + .S_AXI_AWSIZE (S_AXI_AWSIZE), + .S_AXI_AWBURST (S_AXI_AWBURST), + .S_AXI_AWVALID (S_AXI_AWVALID), + .S_AXI_AWREADY (S_AXI_AWREADY), + .S_AXI_WVALID (S_AXI_WVALID), + .S_AXI_WREADY (S_AXI_WREADY), + .S_AXI_BVALID (S_AXI_BVALID), + .S_AXI_BREADY (S_AXI_BREADY), + .S_AXI_BID (S_AXI_BID), + // Signals for BRAM interfac( + .S_AXI_AWADDR_OUT (s_axi_awaddr_out_c), + .S_AXI_WR_EN (s_axi_wr_en_c) + ); + + blk_mem_axi_read_wrapper_beh_v8_4 + #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_AXI_TYPE (C_AXI_TYPE), + .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), + .C_MEMORY_TYPE (C_MEM_TYPE), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_AXI_PIPELINE_STAGES (1), + .C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), + .C_HAS_AXI_ID (C_HAS_AXI_ID), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) + axi_rd_sm( + //AXI Global Signals + .S_ACLK (S_ACLK), + .S_ARESETN (s_aresetn_a_c), + //AXI Full/Lite Read Side + .S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), + .S_AXI_ARLEN (s_axi_arlen_c), + .S_AXI_ARSIZE (S_AXI_ARSIZE), + .S_AXI_ARBURST (S_AXI_ARBURST), + .S_AXI_ARVALID (S_AXI_ARVALID), + .S_AXI_ARREADY (S_AXI_ARREADY), + .S_AXI_RLAST (s_axi_rlast_c), + .S_AXI_RVALID (s_axi_rvalid_c), + .S_AXI_RREADY (s_axi_rready_c), + .S_AXI_ARID (S_AXI_ARID), + .S_AXI_RID (s_axi_rid_c), + //AXI Full/Lite Read FSM Outputs + .S_AXI_ARADDR_OUT (s_axi_araddr_out_c), + .S_AXI_RD_EN (s_axi_rd_en_c) + ); + +blk_mem_gen_v8_4_3_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_INIT_FILE (C_INIT_FILE), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE ("SYNC"), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (1), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (1), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (1), + .C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_BYTE_WEB (1), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (0), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (0), + .C_HAS_MUX_OUTPUT_REGS_B (0), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_EN_ECC_PIPE (0), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v8_4_3_inst + (.CLKA (S_ACLK), + .RSTA (s_aresetn_a_c), + .ENA (s_axi_wr_en_c), + .REGCEA (regcea_in), + .WEA (S_AXI_WSTRB), + .ADDRA (s_axi_awaddr_out_c), + .DINA (S_AXI_WDATA), + .DOUTA (DOUTA), + .CLKB (S_ACLK), + .RSTB (s_aresetn_a_c), + .ENB (s_axi_rd_en_c), + .REGCEB (regceb_c), + .WEB (WEB_parameterized), + .ADDRB (s_axi_araddr_out_c), + .DINB (DINB), + .DOUTB (s_axi_rdata_c), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .ECCPIPECE (1'b0), + .SLEEP (1'b0), + .RDADDRECC (RDADDRECC) + ); + end + endgenerate +endmodule + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/mem_init_files/fir_prbs7_invert_rep2.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/mem_init_files/fir_prbs7_invert_rep2.mif new file mode 100644 index 00000000..213dc9bc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/mem_init_files/fir_prbs7_invert_rep2.mif @@ -0,0 +1,256 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 1 0 0 4 0 +00000001 0 1 0 0 5 0 +00000001 0 1 0 0 6 0 +00000001 0 1 0 0 7 0 +00000001 0 2 0 0 8 0 +00000001 0 2 0 0 9 0 +00000001 0 2 0 0 10 0 +00000001 0 2 0 0 11 0 +ffffffff 0 3 0 0 12 0 +ffffffff 0 3 0 0 13 0 +ffffffff 0 3 0 0 14 0 +ffffffff 0 3 0 0 15 0 +00000001 0 4 0 0 16 0 +00000001 0 4 0 0 17 0 +00000001 0 4 0 0 18 0 +00000001 0 4 0 0 19 0 +00000001 0 5 0 0 20 0 +00000001 0 5 0 0 21 0 +00000001 0 5 0 0 22 0 +00000001 0 5 0 0 23 0 +ffffffff 0 6 0 0 24 0 +ffffffff 0 6 0 0 25 0 +00000001 0 6 0 0 26 0 +00000001 0 6 0 0 27 0 +ffffffff 0 7 0 0 28 0 +ffffffff 0 7 0 0 29 0 +00000001 0 7 0 0 30 0 +00000001 0 7 0 0 31 0 +00000001 0 8 0 0 32 0 +00000001 0 8 0 0 33 0 +00000001 0 8 0 0 34 0 +00000001 0 8 0 0 35 0 +ffffffff 0 9 0 0 36 0 +ffffffff 0 9 0 0 37 0 +ffffffff 0 9 0 0 38 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b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/mem_init_files/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/mem_init_files/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/mem_init_files/prbs7_invert_rep2.coe new file mode 100755 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/mem_init_files/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, 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--git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/mem_init_files/rom_freq_word.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/mem_init_files/rom_freq_word.mif new file mode 100644 index 00000000..4c2a27b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/mem_init_files/rom_freq_word.mif @@ -0,0 +1,81 @@ +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 +0000011101111100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/README.txt new file mode 100644 index 00000000..3b0ec475 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:04 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12x8.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12x8.sh' script. + +./cmpy_12x8.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12x8.sh -noclean_files + +For more information on the script, please type './cmpy_12x8.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/cmpy_12x8.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/cmpy_12x8.sh new file mode 100755 index 00000000..731fba20 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/cmpy_12x8.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12x8.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:04 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12x8.sh [-help] +# usage: cmpy_12x8.sh [-lib_map_path] +# usage: cmpy_12x8.sh [-noclean_files] +# usage: cmpy_12x8.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12x8.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "cmpy_12x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12x8.sh [-help]\n\ +Usage: cmpy_12x8.sh [-lib_map_path]\n\ +Usage: cmpy_12x8.sh [-reset_run]\n\ +Usage: cmpy_12x8.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/cmpy_12x8.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/cmpy_12x8.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/compile.do new file mode 100644 index 00000000..f00fc5c4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/compile.do @@ -0,0 +1,52 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/xbip_utils_v3_0_10 +vlib activehdl/axi_utils_v2_0_6 +vlib activehdl/xbip_pipe_v3_0_6 +vlib activehdl/xbip_bram18k_v3_0_6 +vlib activehdl/mult_gen_v12_0_15 +vlib activehdl/cmpy_v6_0_17 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6 +vmap xbip_pipe_v3_0_6 activehdl/xbip_pipe_v3_0_6 +vmap xbip_bram18k_v3_0_6 activehdl/xbip_bram18k_v3_0_6 +vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15 +vmap cmpy_v6_0_17 activehdl/cmpy_v6_0_17 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work xbip_pipe_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_bram18k_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + +vcom -work mult_gen_v12_0_15 -93 \ +"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + +vcom -work cmpy_v6_0_17 -93 \ +"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/file_info.txt new file mode 100644 index 00000000..2b429ff1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/simulate.do new file mode 100644 index 00000000..77dc9fad --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+cmpy_12x8 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cmpy_12x8 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {cmpy_12x8.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/README.txt new file mode 100644 index 00000000..17dcdaa4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:04 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12x8.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12x8.sh' script. + +./cmpy_12x8.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12x8.sh -noclean_files + +For more information on the script, please type './cmpy_12x8.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/cmpy_12x8.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/cmpy_12x8.sh new file mode 100755 index 00000000..850f2c8e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/cmpy_12x8.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12x8.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:04 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12x8.sh [-help] +# usage: cmpy_12x8.sh [-lib_map_path] +# usage: cmpy_12x8.sh [-noclean_files] +# usage: cmpy_12x8.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12x8.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "cmpy_12x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.cmpy_12x8 \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12x8.sh [-help]\n\ +Usage: cmpy_12x8.sh [-lib_map_path]\n\ +Usage: cmpy_12x8.sh [-reset_run]\n\ +Usage: cmpy_12x8.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/file_info.txt new file mode 100644 index 00000000..2b429ff1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/run.f new file mode 100644 index 00000000..5e79284b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/ies/run.f @@ -0,0 +1,32 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xbip_utils_v3_0_10 \ + "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/axi_utils_v2_0_6 \ + "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xbip_pipe_v3_0_6 \ + "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xbip_bram18k_v3_0_6 \ + "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/mult_gen_v12_0_15 \ + "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/cmpy_v6_0_17 \ + "../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/README.txt new file mode 100644 index 00000000..3b0ec475 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:04 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12x8.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12x8.sh' script. + +./cmpy_12x8.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12x8.sh -noclean_files + +For more information on the script, please type './cmpy_12x8.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/cmpy_12x8.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/cmpy_12x8.sh new file mode 100755 index 00000000..5e9a84a6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/cmpy_12x8.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12x8.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:04 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12x8.sh [-help] +# usage: cmpy_12x8.sh [-lib_map_path] +# usage: cmpy_12x8.sh [-noclean_files] +# usage: cmpy_12x8.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12x8.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "cmpy_12x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12x8.sh [-help]\n\ +Usage: cmpy_12x8.sh [-lib_map_path]\n\ +Usage: cmpy_12x8.sh [-reset_run]\n\ +Usage: cmpy_12x8.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/cmpy_12x8.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/cmpy_12x8.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/compile.do new file mode 100644 index 00000000..d43e95f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vcom -work xil_defaultlib -64 -93 \ +"../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/file_info.txt new file mode 100644 index 00000000..1c658238 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/file_info.txt @@ -0,0 +1,2 @@ +cmpy_12x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/simulate.do new file mode 100644 index 00000000..3c5bd047 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.cmpy_12x8 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {cmpy_12x8.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/README.txt new file mode 100644 index 00000000..3b0ec475 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:04 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12x8.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12x8.sh' script. + +./cmpy_12x8.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12x8.sh -noclean_files + +For more information on the script, please type './cmpy_12x8.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/cmpy_12x8.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/cmpy_12x8.sh new file mode 100755 index 00000000..d4808039 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/cmpy_12x8.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12x8.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:04 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12x8.sh [-help] +# usage: cmpy_12x8.sh [-lib_map_path] +# usage: cmpy_12x8.sh [-noclean_files] +# usage: cmpy_12x8.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12x8.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "cmpy_12x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12x8.sh [-help]\n\ +Usage: cmpy_12x8.sh [-lib_map_path]\n\ +Usage: cmpy_12x8.sh [-reset_run]\n\ +Usage: cmpy_12x8.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/cmpy_12x8.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/cmpy_12x8.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/compile.do new file mode 100644 index 00000000..fb003626 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/compile.do @@ -0,0 +1,52 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/xbip_utils_v3_0_10 +vlib questa_lib/msim/axi_utils_v2_0_6 +vlib questa_lib/msim/xbip_pipe_v3_0_6 +vlib questa_lib/msim/xbip_bram18k_v3_0_6 +vlib questa_lib/msim/mult_gen_v12_0_15 +vlib questa_lib/msim/cmpy_v6_0_17 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6 +vmap xbip_pipe_v3_0_6 questa_lib/msim/xbip_pipe_v3_0_6 +vmap xbip_bram18k_v3_0_6 questa_lib/msim/xbip_bram18k_v3_0_6 +vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15 +vmap cmpy_v6_0_17 questa_lib/msim/cmpy_v6_0_17 + +vlog -work xil_defaultlib -64 -sv \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -64 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -64 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work xbip_pipe_v3_0_6 -64 -93 \ +"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_bram18k_v3_0_6 -64 -93 \ +"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + +vcom -work mult_gen_v12_0_15 -64 -93 \ +"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + +vcom -work cmpy_v6_0_17 -64 -93 \ +"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/elaborate.do new file mode 100644 index 00000000..824cc3ed --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.cmpy_12x8 xil_defaultlib.glbl -o cmpy_12x8_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/file_info.txt new file mode 100644 index 00000000..2b429ff1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/simulate.do new file mode 100644 index 00000000..2949db3f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib cmpy_12x8_opt + +do {wave.do} + +view wave +view structure +view signals + +do {cmpy_12x8.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/README.txt new file mode 100644 index 00000000..3b0ec475 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:04 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12x8.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12x8.sh' script. + +./cmpy_12x8.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12x8.sh -noclean_files + +For more information on the script, please type './cmpy_12x8.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/cmpy_12x8.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/cmpy_12x8.sh new file mode 100755 index 00000000..7118556b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/cmpy_12x8.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12x8.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:04 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12x8.sh [-help] +# usage: cmpy_12x8.sh [-lib_map_path] +# usage: cmpy_12x8.sh [-noclean_files] +# usage: cmpy_12x8.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12x8.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "cmpy_12x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12x8.sh [-help]\n\ +Usage: cmpy_12x8.sh [-lib_map_path]\n\ +Usage: cmpy_12x8.sh [-reset_run]\n\ +Usage: cmpy_12x8.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/cmpy_12x8.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/cmpy_12x8.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/compile.do new file mode 100644 index 00000000..8797cac4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/compile.do @@ -0,0 +1,52 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/xbip_utils_v3_0_10 +vlib riviera/axi_utils_v2_0_6 +vlib riviera/xbip_pipe_v3_0_6 +vlib riviera/xbip_bram18k_v3_0_6 +vlib riviera/mult_gen_v12_0_15 +vlib riviera/cmpy_v6_0_17 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6 +vmap xbip_pipe_v3_0_6 riviera/xbip_pipe_v3_0_6 +vmap xbip_bram18k_v3_0_6 riviera/xbip_bram18k_v3_0_6 +vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15 +vmap cmpy_v6_0_17 riviera/cmpy_v6_0_17 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work xbip_pipe_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_bram18k_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + +vcom -work mult_gen_v12_0_15 -93 \ +"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + +vcom -work cmpy_v6_0_17 -93 \ +"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/file_info.txt new file mode 100644 index 00000000..2b429ff1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/simulate.do new file mode 100644 index 00000000..77dc9fad --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+cmpy_12x8 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cmpy_12x8 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {cmpy_12x8.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/README.txt new file mode 100644 index 00000000..3b0ec475 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:04 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12x8.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12x8.sh' script. + +./cmpy_12x8.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12x8.sh -noclean_files + +For more information on the script, please type './cmpy_12x8.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/cmpy_12x8.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/cmpy_12x8.sh new file mode 100755 index 00000000..9ff19abf --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/cmpy_12x8.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12x8.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:04 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12x8.sh [-help] +# usage: cmpy_12x8.sh [-lib_map_path] +# usage: cmpy_12x8.sh [-noclean_files] +# usage: cmpy_12x8.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12x8.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "cmpy_12x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd" \ + 2>&1 | tee -a vhdlan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.cmpy_12x8 xil_defaultlib.glbl -o cmpy_12x8_simv +} + +# RUN_STEP: +simulate() +{ + ./cmpy_12x8_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key cmpy_12x8_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc cmpy_12x8_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12x8.sh [-help]\n\ +Usage: cmpy_12x8.sh [-lib_map_path]\n\ +Usage: cmpy_12x8.sh [-reset_run]\n\ +Usage: cmpy_12x8.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/file_info.txt new file mode 100644 index 00000000..1c658238 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/file_info.txt @@ -0,0 +1,2 @@ +cmpy_12x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/README.txt new file mode 100644 index 00000000..17dcdaa4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:04 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12x8.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12x8.sh' script. + +./cmpy_12x8.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12x8.sh -noclean_files + +For more information on the script, please type './cmpy_12x8.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/cmpy_12x8.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/cmpy_12x8.sh new file mode 100755 index 00000000..693f54f9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/cmpy_12x8.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12x8.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:04 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12x8.sh [-help] +# usage: cmpy_12x8.sh [-lib_map_path] +# usage: cmpy_12x8.sh [-noclean_files] +# usage: cmpy_12x8.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12x8.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "cmpy_12x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.cmpy_12x8 \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12x8.sh [-help]\n\ +Usage: cmpy_12x8.sh [-lib_map_path]\n\ +Usage: cmpy_12x8.sh [-reset_run]\n\ +Usage: cmpy_12x8.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/file_info.txt new file mode 100644 index 00000000..2b429ff1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/run.f new file mode 100644 index 00000000..e9286fee --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xcelium/run.f @@ -0,0 +1,32 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xbip_utils_v3_0_10 \ + "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/axi_utils_v2_0_6 \ + "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xbip_pipe_v3_0_6 \ + "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xbip_bram18k_v3_0_6 \ + "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/mult_gen_v12_0_15 \ + "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/cmpy_v6_0_17 \ + "../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/README.txt new file mode 100644 index 00000000..3b0ec475 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:04 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12x8.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12x8.sh' script. + +./cmpy_12x8.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12x8.sh -noclean_files + +For more information on the script, please type './cmpy_12x8.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/cmpy_12x8.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/cmpy_12x8.sh new file mode 100755 index 00000000..ad76930a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/cmpy_12x8.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12x8.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:04 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12x8.sh [-help] +# usage: cmpy_12x8.sh [-lib_map_path] +# usage: cmpy_12x8.sh [-noclean_files] +# usage: cmpy_12x8.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" +xvhdl_opts="--relax" + + +# Script info +echo -e "cmpy_12x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot cmpy_12x8 xil_defaultlib.cmpy_12x8 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim cmpy_12x8 -key {Behavioral:sim_1:Functional:cmpy_12x8} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb cmpy_12x8.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12x8.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12x8.sh [-help]\n\ +Usage: cmpy_12x8.sh [-lib_map_path]\n\ +Usage: cmpy_12x8.sh [-reset_run]\n\ +Usage: cmpy_12x8.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/file_info.txt new file mode 100644 index 00000000..1c658238 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/file_info.txt @@ -0,0 +1,2 @@ +cmpy_12x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/vhdl.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/vhdl.prj new file mode 100644 index 00000000..28de1949 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/vhdl.prj @@ -0,0 +1,4 @@ +vhdl xil_defaultlib \ +"../../../ip/cmpy_12x8/sim/cmpy_12x8.vhd" \ + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/vlog.prj new file mode 100644 index 00000000..35119d5b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12x8/xsim/vlog.prj @@ -0,0 +1,4 @@ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/README.txt new file mode 100644 index 00000000..040622af --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs7_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs7_invert_rep2.sh' script. + +./fir_prbs7_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs7_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs7_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/compile.do new file mode 100644 index 00000000..b3f349a8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/compile.do @@ -0,0 +1,37 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/xbip_utils_v3_0_10 +vlib activehdl/axi_utils_v2_0_6 +vlib activehdl/fir_compiler_v7_2_12 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6 +vmap fir_compiler_v7_2_12 activehdl/fir_compiler_v7_2_12 + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/fir_prbs7_invert_rep2/cmodel" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work fir_compiler_v7_2_12 -93 \ +"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/file_info.txt new file mode 100644 index 00000000..587628e7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +fir_prbs7_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.mif new file mode 100644 index 00000000..213dc9bc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.mif @@ -0,0 +1,256 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 1 0 0 4 0 +00000001 0 1 0 0 5 0 +00000001 0 1 0 0 6 0 +00000001 0 1 0 0 7 0 +00000001 0 2 0 0 8 0 +00000001 0 2 0 0 9 0 +00000001 0 2 0 0 10 0 +00000001 0 2 0 0 11 0 +ffffffff 0 3 0 0 12 0 +ffffffff 0 3 0 0 13 0 +ffffffff 0 3 0 0 14 0 +ffffffff 0 3 0 0 15 0 +00000001 0 4 0 0 16 0 +00000001 0 4 0 0 17 0 +00000001 0 4 0 0 18 0 +00000001 0 4 0 0 19 0 +00000001 0 5 0 0 20 0 +00000001 0 5 0 0 21 0 +00000001 0 5 0 0 22 0 +00000001 0 5 0 0 23 0 +ffffffff 0 6 0 0 24 0 +ffffffff 0 6 0 0 25 0 +00000001 0 6 0 0 26 0 +00000001 0 6 0 0 27 0 +ffffffff 0 7 0 0 28 0 +ffffffff 0 7 0 0 29 0 +00000001 0 7 0 0 30 0 +00000001 0 7 0 0 31 0 +00000001 0 8 0 0 32 0 +00000001 0 8 0 0 33 0 +00000001 0 8 0 0 34 0 +00000001 0 8 0 0 35 0 +ffffffff 0 9 0 0 36 0 +ffffffff 0 9 0 0 37 0 +ffffffff 0 9 0 0 38 0 +ffffffff 0 9 0 0 39 0 +ffffffff 0 10 0 0 40 0 +ffffffff 0 10 0 0 41 0 +ffffffff 0 10 0 0 42 0 +ffffffff 0 10 0 0 43 0 +00000001 0 11 0 0 44 0 +00000001 0 11 0 0 45 0 +00000001 0 11 0 0 46 0 +00000001 0 11 0 0 47 0 +ffffffff 0 12 0 0 48 0 +ffffffff 0 12 0 0 49 0 +00000001 0 12 0 0 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252 0 +00000001 0 63 0 0 253 0 +ffffffff 0 63 0 0 254 0 +ffffffff 0 63 0 0 255 0 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.sh new file mode 100755 index 00000000..4f5b0b38 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fir_prbs7_invert_rep2.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fir_prbs7_invert_rep2.sh [-help] +# usage: fir_prbs7_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs7_invert_rep2.sh [-noclean_files] +# usage: fir_prbs7_invert_rep2.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fir_prbs7_invert_rep2.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fir_prbs7_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fir_prbs7_invert_rep2.sh [-help]\n\ +Usage: fir_prbs7_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs7_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs7_invert_rep2.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/prbs7_invert_rep2.coe new file mode 100755 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/simulate.do new file mode 100644 index 00000000..0f586827 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+fir_prbs7_invert_rep2 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fir_prbs7_invert_rep2 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {fir_prbs7_invert_rep2.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/README.txt new file mode 100644 index 00000000..0435eb8b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs7_invert_rep2.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs7_invert_rep2.sh' script. + +./fir_prbs7_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs7_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs7_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/file_info.txt new file mode 100644 index 00000000..587628e7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +fir_prbs7_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/fir_prbs7_invert_rep2.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/fir_prbs7_invert_rep2.mif new file mode 100644 index 00000000..213dc9bc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/fir_prbs7_invert_rep2.mif @@ -0,0 +1,256 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 1 0 0 4 0 +00000001 0 1 0 0 5 0 +00000001 0 1 0 0 6 0 +00000001 0 1 0 0 7 0 +00000001 0 2 0 0 8 0 +00000001 0 2 0 0 9 0 +00000001 0 2 0 0 10 0 +00000001 0 2 0 0 11 0 +ffffffff 0 3 0 0 12 0 +ffffffff 0 3 0 0 13 0 +ffffffff 0 3 0 0 14 0 +ffffffff 0 3 0 0 15 0 +00000001 0 4 0 0 16 0 +00000001 0 4 0 0 17 0 +00000001 0 4 0 0 18 0 +00000001 0 4 0 0 19 0 +00000001 0 5 0 0 20 0 +00000001 0 5 0 0 21 0 +00000001 0 5 0 0 22 0 +00000001 0 5 0 0 23 0 +ffffffff 0 6 0 0 24 0 +ffffffff 0 6 0 0 25 0 +00000001 0 6 0 0 26 0 +00000001 0 6 0 0 27 0 +ffffffff 0 7 0 0 28 0 +ffffffff 0 7 0 0 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b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/fir_prbs7_invert_rep2.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fir_prbs7_invert_rep2.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fir_prbs7_invert_rep2.sh [-help] +# usage: fir_prbs7_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs7_invert_rep2.sh [-noclean_files] +# usage: fir_prbs7_invert_rep2.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fir_prbs7_invert_rep2.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "fir_prbs7_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.fir_prbs7_invert_rep2 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/fir_prbs7_invert_rep2/cmodel" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fir_prbs7_invert_rep2.sh [-help]\n\ +Usage: fir_prbs7_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs7_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs7_invert_rep2.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/prbs7_invert_rep2.coe new file mode 100755 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/run.f new file mode 100644 index 00000000..96a510b8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/run.f @@ -0,0 +1,23 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xbip_utils_v3_0_10 \ + "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/axi_utils_v2_0_6 \ + "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/fir_compiler_v7_2_12 \ + "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/README.txt new file mode 100644 index 00000000..040622af --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs7_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs7_invert_rep2.sh' script. + +./fir_prbs7_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs7_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs7_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/compile.do new file mode 100644 index 00000000..a9880a43 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vcom -work xil_defaultlib -64 -93 \ +"../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/file_info.txt new file mode 100644 index 00000000..b8557622 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/file_info.txt @@ -0,0 +1,2 @@ +fir_prbs7_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.mif new file mode 100644 index 00000000..213dc9bc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.mif @@ -0,0 +1,256 @@ +00000001 0 0 0 0 0 0 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+00000001 0 61 0 0 247 0 +00000001 0 62 0 0 248 0 +00000001 0 62 0 0 249 0 +00000001 0 62 0 0 250 0 +00000001 0 62 0 0 251 0 +00000001 0 63 0 0 252 0 +00000001 0 63 0 0 253 0 +ffffffff 0 63 0 0 254 0 +ffffffff 0 63 0 0 255 0 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.sh new file mode 100755 index 00000000..0771f27b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fir_prbs7_invert_rep2.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fir_prbs7_invert_rep2.sh [-help] +# usage: fir_prbs7_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs7_invert_rep2.sh [-noclean_files] +# usage: fir_prbs7_invert_rep2.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fir_prbs7_invert_rep2.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fir_prbs7_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fir_prbs7_invert_rep2.sh [-help]\n\ +Usage: fir_prbs7_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs7_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs7_invert_rep2.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/prbs7_invert_rep2.coe new file mode 100755 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/simulate.do new file mode 100644 index 00000000..a92ad59f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.fir_prbs7_invert_rep2 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {fir_prbs7_invert_rep2.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/README.txt new file mode 100644 index 00000000..040622af --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs7_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs7_invert_rep2.sh' script. + +./fir_prbs7_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs7_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs7_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/compile.do new file mode 100644 index 00000000..0af71ccd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/compile.do @@ -0,0 +1,37 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/xbip_utils_v3_0_10 +vlib questa_lib/msim/axi_utils_v2_0_6 +vlib questa_lib/msim/fir_compiler_v7_2_12 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6 +vmap fir_compiler_v7_2_12 questa_lib/msim/fir_compiler_v7_2_12 + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/fir_prbs7_invert_rep2/cmodel" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -64 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -64 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work fir_compiler_v7_2_12 -64 -93 \ +"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/elaborate.do new file mode 100644 index 00000000..b7ca6148 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.fir_prbs7_invert_rep2 xil_defaultlib.glbl -o fir_prbs7_invert_rep2_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/file_info.txt new file mode 100644 index 00000000..587628e7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +fir_prbs7_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.mif new file mode 100644 index 00000000..213dc9bc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.mif @@ -0,0 +1,256 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 1 0 0 4 0 +00000001 0 1 0 0 5 0 +00000001 0 1 0 0 6 0 +00000001 0 1 0 0 7 0 +00000001 0 2 0 0 8 0 +00000001 0 2 0 0 9 0 +00000001 0 2 0 0 10 0 +00000001 0 2 0 0 11 0 +ffffffff 0 3 0 0 12 0 +ffffffff 0 3 0 0 13 0 +ffffffff 0 3 0 0 14 0 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a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.sh new file mode 100755 index 00000000..2fdee444 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fir_prbs7_invert_rep2.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fir_prbs7_invert_rep2.sh [-help] +# usage: fir_prbs7_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs7_invert_rep2.sh [-noclean_files] +# usage: fir_prbs7_invert_rep2.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fir_prbs7_invert_rep2.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fir_prbs7_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fir_prbs7_invert_rep2.sh [-help]\n\ +Usage: fir_prbs7_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs7_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs7_invert_rep2.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/prbs7_invert_rep2.coe new file mode 100755 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/simulate.do new file mode 100644 index 00000000..326c2036 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib fir_prbs7_invert_rep2_opt + +do {wave.do} + +view wave +view structure +view signals + +do {fir_prbs7_invert_rep2.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/README.txt new file mode 100644 index 00000000..040622af --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs7_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs7_invert_rep2.sh' script. + +./fir_prbs7_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs7_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs7_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/compile.do new file mode 100644 index 00000000..c6b4f5a4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/compile.do @@ -0,0 +1,37 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/xbip_utils_v3_0_10 +vlib riviera/axi_utils_v2_0_6 +vlib riviera/fir_compiler_v7_2_12 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6 +vmap fir_compiler_v7_2_12 riviera/fir_compiler_v7_2_12 + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/fir_prbs7_invert_rep2/cmodel" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work fir_compiler_v7_2_12 -93 \ +"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/file_info.txt new file mode 100644 index 00000000..587628e7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +fir_prbs7_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.mif new file mode 100644 index 00000000..213dc9bc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.mif @@ -0,0 +1,256 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 1 0 0 4 0 +00000001 0 1 0 0 5 0 +00000001 0 1 0 0 6 0 +00000001 0 1 0 0 7 0 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+00000001 0 63 0 0 253 0 +ffffffff 0 63 0 0 254 0 +ffffffff 0 63 0 0 255 0 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.sh new file mode 100755 index 00000000..d1b2b808 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fir_prbs7_invert_rep2.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fir_prbs7_invert_rep2.sh [-help] +# usage: fir_prbs7_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs7_invert_rep2.sh [-noclean_files] +# usage: fir_prbs7_invert_rep2.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fir_prbs7_invert_rep2.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fir_prbs7_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fir_prbs7_invert_rep2.sh [-help]\n\ +Usage: fir_prbs7_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs7_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs7_invert_rep2.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/prbs7_invert_rep2.coe new file mode 100755 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/simulate.do new file mode 100644 index 00000000..0f586827 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+fir_prbs7_invert_rep2 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fir_prbs7_invert_rep2 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {fir_prbs7_invert_rep2.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/README.txt new file mode 100644 index 00000000..040622af --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs7_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs7_invert_rep2.sh' script. + +./fir_prbs7_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs7_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs7_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/file_info.txt new file mode 100644 index 00000000..b8557622 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/file_info.txt @@ -0,0 +1,2 @@ +fir_prbs7_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/fir_prbs7_invert_rep2.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/fir_prbs7_invert_rep2.mif new file mode 100644 index 00000000..213dc9bc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/fir_prbs7_invert_rep2.mif @@ -0,0 +1,256 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 1 0 0 4 0 +00000001 0 1 0 0 5 0 +00000001 0 1 0 0 6 0 +00000001 0 1 0 0 7 0 +00000001 0 2 0 0 8 0 +00000001 0 2 0 0 9 0 +00000001 0 2 0 0 10 0 +00000001 0 2 0 0 11 0 +ffffffff 0 3 0 0 12 0 +ffffffff 0 3 0 0 13 0 +ffffffff 0 3 0 0 14 0 +ffffffff 0 3 0 0 15 0 +00000001 0 4 0 0 16 0 +00000001 0 4 0 0 17 0 +00000001 0 4 0 0 18 0 +00000001 0 4 0 0 19 0 +00000001 0 5 0 0 20 0 +00000001 0 5 0 0 21 0 +00000001 0 5 0 0 22 0 +00000001 0 5 0 0 23 0 +ffffffff 0 6 0 0 24 0 +ffffffff 0 6 0 0 25 0 +00000001 0 6 0 0 26 0 +00000001 0 6 0 0 27 0 +ffffffff 0 7 0 0 28 0 +ffffffff 0 7 0 0 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b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/fir_prbs7_invert_rep2.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fir_prbs7_invert_rep2.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fir_prbs7_invert_rep2.sh [-help] +# usage: fir_prbs7_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs7_invert_rep2.sh [-noclean_files] +# usage: fir_prbs7_invert_rep2.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fir_prbs7_invert_rep2.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "fir_prbs7_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd" \ + 2>&1 | tee -a vhdlan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.fir_prbs7_invert_rep2 xil_defaultlib.glbl -o fir_prbs7_invert_rep2_simv +} + +# RUN_STEP: +simulate() +{ + ./fir_prbs7_invert_rep2_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key fir_prbs7_invert_rep2_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc fir_prbs7_invert_rep2_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fir_prbs7_invert_rep2.sh [-help]\n\ +Usage: fir_prbs7_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs7_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs7_invert_rep2.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/prbs7_invert_rep2.coe new file mode 100755 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/README.txt new file mode 100644 index 00000000..0435eb8b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs7_invert_rep2.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs7_invert_rep2.sh' script. + +./fir_prbs7_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs7_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs7_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/file_info.txt new file mode 100644 index 00000000..587628e7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +fir_prbs7_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/fir_prbs7_invert_rep2.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/fir_prbs7_invert_rep2.mif new file mode 100644 index 00000000..213dc9bc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/fir_prbs7_invert_rep2.mif @@ -0,0 +1,256 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 1 0 0 4 0 +00000001 0 1 0 0 5 0 +00000001 0 1 0 0 6 0 +00000001 0 1 0 0 7 0 +00000001 0 2 0 0 8 0 +00000001 0 2 0 0 9 0 +00000001 0 2 0 0 10 0 +00000001 0 2 0 0 11 0 +ffffffff 0 3 0 0 12 0 +ffffffff 0 3 0 0 13 0 +ffffffff 0 3 0 0 14 0 +ffffffff 0 3 0 0 15 0 +00000001 0 4 0 0 16 0 +00000001 0 4 0 0 17 0 +00000001 0 4 0 0 18 0 +00000001 0 4 0 0 19 0 +00000001 0 5 0 0 20 0 +00000001 0 5 0 0 21 0 +00000001 0 5 0 0 22 0 +00000001 0 5 0 0 23 0 +ffffffff 0 6 0 0 24 0 +ffffffff 0 6 0 0 25 0 +00000001 0 6 0 0 26 0 +00000001 0 6 0 0 27 0 +ffffffff 0 7 0 0 28 0 +ffffffff 0 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b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/fir_prbs7_invert_rep2.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fir_prbs7_invert_rep2.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fir_prbs7_invert_rep2.sh [-help] +# usage: fir_prbs7_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs7_invert_rep2.sh [-noclean_files] +# usage: fir_prbs7_invert_rep2.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fir_prbs7_invert_rep2.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "fir_prbs7_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.fir_prbs7_invert_rep2 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/fir_prbs7_invert_rep2/cmodel" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fir_prbs7_invert_rep2.sh [-help]\n\ +Usage: fir_prbs7_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs7_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs7_invert_rep2.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/prbs7_invert_rep2.coe new file mode 100755 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/run.f new file mode 100644 index 00000000..1c000ce6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/run.f @@ -0,0 +1,23 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xbip_utils_v3_0_10 \ + "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/axi_utils_v2_0_6 \ + "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/fir_compiler_v7_2_12 \ + "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/README.txt new file mode 100644 index 00000000..040622af --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs7_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs7_invert_rep2.sh' script. + +./fir_prbs7_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs7_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs7_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/file_info.txt new file mode 100644 index 00000000..b8557622 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/file_info.txt @@ -0,0 +1,2 @@ +fir_prbs7_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd,incdir="../../../ip/fir_prbs7_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/fir_prbs7_invert_rep2.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/fir_prbs7_invert_rep2.mif new file mode 100644 index 00000000..213dc9bc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/fir_prbs7_invert_rep2.mif @@ -0,0 +1,256 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 1 0 0 4 0 +00000001 0 1 0 0 5 0 +00000001 0 1 0 0 6 0 +00000001 0 1 0 0 7 0 +00000001 0 2 0 0 8 0 +00000001 0 2 0 0 9 0 +00000001 0 2 0 0 10 0 +00000001 0 2 0 0 11 0 +ffffffff 0 3 0 0 12 0 +ffffffff 0 3 0 0 13 0 +ffffffff 0 3 0 0 14 0 +ffffffff 0 3 0 0 15 0 +00000001 0 4 0 0 16 0 +00000001 0 4 0 0 17 0 +00000001 0 4 0 0 18 0 +00000001 0 4 0 0 19 0 +00000001 0 5 0 0 20 0 +00000001 0 5 0 0 21 0 +00000001 0 5 0 0 22 0 +00000001 0 5 0 0 23 0 +ffffffff 0 6 0 0 24 0 +ffffffff 0 6 0 0 25 0 +00000001 0 6 0 0 26 0 +00000001 0 6 0 0 27 0 +ffffffff 0 7 0 0 28 0 +ffffffff 0 7 0 0 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+ffffffff 0 58 0 0 233 0 +ffffffff 0 58 0 0 234 0 +ffffffff 0 58 0 0 235 0 +ffffffff 0 59 0 0 236 0 +ffffffff 0 59 0 0 237 0 +ffffffff 0 59 0 0 238 0 +ffffffff 0 59 0 0 239 0 +ffffffff 0 60 0 0 240 0 +ffffffff 0 60 0 0 241 0 +00000001 0 60 0 0 242 0 +00000001 0 60 0 0 243 0 +00000001 0 61 0 0 244 0 +00000001 0 61 0 0 245 0 +00000001 0 61 0 0 246 0 +00000001 0 61 0 0 247 0 +00000001 0 62 0 0 248 0 +00000001 0 62 0 0 249 0 +00000001 0 62 0 0 250 0 +00000001 0 62 0 0 251 0 +00000001 0 63 0 0 252 0 +00000001 0 63 0 0 253 0 +ffffffff 0 63 0 0 254 0 +ffffffff 0 63 0 0 255 0 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/fir_prbs7_invert_rep2.sh new file mode 100755 index 00000000..8285dd81 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/fir_prbs7_invert_rep2.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fir_prbs7_invert_rep2.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fir_prbs7_invert_rep2.sh [-help] +# usage: fir_prbs7_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs7_invert_rep2.sh [-noclean_files] +# usage: fir_prbs7_invert_rep2.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" +xvhdl_opts="--relax" + + +# Script info +echo -e "fir_prbs7_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot fir_prbs7_invert_rep2 xil_defaultlib.fir_prbs7_invert_rep2 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim fir_prbs7_invert_rep2 -key {Behavioral:sim_1:Functional:fir_prbs7_invert_rep2} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb fir_prbs7_invert_rep2.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep2.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fir_prbs7_invert_rep2.sh [-help]\n\ +Usage: fir_prbs7_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs7_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs7_invert_rep2.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/prbs7_invert_rep2.coe new file mode 100755 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/vhdl.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/vhdl.prj new file mode 100644 index 00000000..b90962b9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/vhdl.prj @@ -0,0 +1,4 @@ +vhdl xil_defaultlib \ +"../../../ip/fir_prbs7_invert_rep2/sim/fir_prbs7_invert_rep2.vhd" \ + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/vlog.prj new file mode 100644 index 00000000..35119d5b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/vlog.prj @@ -0,0 +1,4 @@ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/README.txt new file mode 100644 index 00000000..556e3bc6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_cal.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_cal.sh' script. + +./ila_cal.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_cal.sh -noclean_files + +For more information on the script, please type './ila_cal.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/compile.do new file mode 100644 index 00000000..f902045c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_cal/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_cal/hdl/verilog" \ +"../../../ip/ila_cal/sim/ila_cal.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/file_info.txt new file mode 100644 index 00000000..4e50a02a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog" +ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/ila_cal.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/ila_cal.sh new file mode 100755 index 00000000..1a69781b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/ila_cal.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_cal.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_cal.sh [-help] +# usage: ila_cal.sh [-lib_map_path] +# usage: ila_cal.sh [-noclean_files] +# usage: ila_cal.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_cal.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_cal.sh [-help]\n\ +Usage: ila_cal.sh [-lib_map_path]\n\ +Usage: ila_cal.sh [-reset_run]\n\ +Usage: ila_cal.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/ila_cal.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/ila_cal.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/simulate.do new file mode 100644 index 00000000..b343caaa --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_cal -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_cal xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_cal.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/README.txt new file mode 100644 index 00000000..c39d3d5a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_cal.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_cal.sh' script. + +./ila_cal.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_cal.sh -noclean_files + +For more information on the script, please type './ila_cal.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/file_info.txt new file mode 100644 index 00000000..4e50a02a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog" +ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/ila_cal.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/ila_cal.sh new file mode 100755 index 00000000..43573aa6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/ila_cal.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_cal.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_cal.sh [-help] +# usage: ila_cal.sh [-lib_map_path] +# usage: ila_cal.sh [-noclean_files] +# usage: ila_cal.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_cal.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ila_cal \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ila_cal/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_cal.sh [-help]\n\ +Usage: ila_cal.sh [-lib_map_path]\n\ +Usage: ila_cal.sh [-reset_run]\n\ +Usage: ila_cal.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/run.f new file mode 100644 index 00000000..1c7b5e91 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/ila_cal/sim/ila_cal.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/README.txt new file mode 100644 index 00000000..556e3bc6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_cal.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_cal.sh' script. + +./ila_cal.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_cal.sh -noclean_files + +For more information on the script, please type './ila_cal.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/compile.do new file mode 100644 index 00000000..994db411 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/compile.do @@ -0,0 +1,22 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/ila_cal/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_cal/hdl/verilog" \ +"../../../ip/ila_cal/sim/ila_cal.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/file_info.txt new file mode 100644 index 00000000..4e50a02a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog" +ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/ila_cal.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/ila_cal.sh new file mode 100755 index 00000000..03bc9f50 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/ila_cal.sh @@ -0,0 +1,168 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_cal.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_cal.sh [-help] +# usage: ila_cal.sh [-lib_map_path] +# usage: ila_cal.sh [-noclean_files] +# usage: ila_cal.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_cal.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_cal.sh [-help]\n\ +Usage: ila_cal.sh [-lib_map_path]\n\ +Usage: ila_cal.sh [-reset_run]\n\ +Usage: ila_cal.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/ila_cal.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/ila_cal.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/simulate.do new file mode 100644 index 00000000..47e8c932 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.ila_cal xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {ila_cal.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/README.txt new file mode 100644 index 00000000..556e3bc6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_cal.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_cal.sh' script. + +./ila_cal.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_cal.sh -noclean_files + +For more information on the script, please type './ila_cal.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/compile.do new file mode 100644 index 00000000..6aae1b65 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_cal/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_cal/hdl/verilog" \ +"../../../ip/ila_cal/sim/ila_cal.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/elaborate.do new file mode 100644 index 00000000..0d585bc5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_cal xil_defaultlib.glbl -o ila_cal_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/file_info.txt new file mode 100644 index 00000000..4e50a02a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog" +ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/ila_cal.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/ila_cal.sh new file mode 100755 index 00000000..74fb5f5a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/ila_cal.sh @@ -0,0 +1,173 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_cal.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_cal.sh [-help] +# usage: ila_cal.sh [-lib_map_path] +# usage: ila_cal.sh [-noclean_files] +# usage: ila_cal.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_cal.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_cal.sh [-help]\n\ +Usage: ila_cal.sh [-lib_map_path]\n\ +Usage: ila_cal.sh [-reset_run]\n\ +Usage: ila_cal.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/ila_cal.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/ila_cal.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/simulate.do new file mode 100644 index 00000000..6d12f843 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib ila_cal_opt + +do {wave.do} + +view wave +view structure +view signals + +do {ila_cal.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/README.txt new file mode 100644 index 00000000..556e3bc6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_cal.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_cal.sh' script. + +./ila_cal.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_cal.sh -noclean_files + +For more information on the script, please type './ila_cal.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/compile.do new file mode 100644 index 00000000..6597d095 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_cal/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_cal/hdl/verilog" \ +"../../../ip/ila_cal/sim/ila_cal.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/file_info.txt new file mode 100644 index 00000000..4e50a02a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog" +ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/ila_cal.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/ila_cal.sh new file mode 100755 index 00000000..82e13498 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/ila_cal.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_cal.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_cal.sh [-help] +# usage: ila_cal.sh [-lib_map_path] +# usage: ila_cal.sh [-noclean_files] +# usage: ila_cal.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_cal.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_cal.sh [-help]\n\ +Usage: ila_cal.sh [-lib_map_path]\n\ +Usage: ila_cal.sh [-reset_run]\n\ +Usage: ila_cal.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/ila_cal.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/ila_cal.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/simulate.do new file mode 100644 index 00000000..b343caaa --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_cal -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_cal xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_cal.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/README.txt new file mode 100644 index 00000000..556e3bc6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_cal.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_cal.sh' script. + +./ila_cal.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_cal.sh -noclean_files + +For more information on the script, please type './ila_cal.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/file_info.txt new file mode 100644 index 00000000..4e50a02a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog" +ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/ila_cal.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/ila_cal.sh new file mode 100755 index 00000000..c60ca004 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/ila_cal.sh @@ -0,0 +1,229 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_cal.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_cal.sh [-help] +# usage: ila_cal.sh [-lib_map_path] +# usage: ila_cal.sh [-noclean_files] +# usage: ila_cal.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_cal.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/ila_cal/hdl/verilog" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_cal/hdl/verilog" \ + "$ref_dir/../../../ip/ila_cal/sim/ila_cal.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.ila_cal xil_defaultlib.glbl -o ila_cal_simv +} + +# RUN_STEP: +simulate() +{ + ./ila_cal_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key ila_cal_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ila_cal_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_cal.sh [-help]\n\ +Usage: ila_cal.sh [-lib_map_path]\n\ +Usage: ila_cal.sh [-reset_run]\n\ +Usage: ila_cal.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/README.txt new file mode 100644 index 00000000..c39d3d5a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_cal.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_cal.sh' script. + +./ila_cal.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_cal.sh -noclean_files + +For more information on the script, please type './ila_cal.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/file_info.txt new file mode 100644 index 00000000..4e50a02a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog" +ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/ila_cal.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/ila_cal.sh new file mode 100755 index 00000000..d2372ee5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/ila_cal.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_cal.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_cal.sh [-help] +# usage: ila_cal.sh [-lib_map_path] +# usage: ila_cal.sh [-noclean_files] +# usage: ila_cal.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_cal.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ila_cal \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ila_cal/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_cal.sh [-help]\n\ +Usage: ila_cal.sh [-lib_map_path]\n\ +Usage: ila_cal.sh [-reset_run]\n\ +Usage: ila_cal.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/run.f new file mode 100644 index 00000000..ad8f0963 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/ila_cal/sim/ila_cal.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/README.txt new file mode 100644 index 00000000..556e3bc6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_cal.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_cal.sh' script. + +./ila_cal.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_cal.sh -noclean_files + +For more information on the script, please type './ila_cal.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/file_info.txt new file mode 100644 index 00000000..db289374 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/file_info.txt @@ -0,0 +1,2 @@ +ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/ila_cal.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/ila_cal.sh new file mode 100755 index 00000000..eb1ec5da --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/ila_cal.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_cal.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_cal.sh [-help] +# usage: ila_cal.sh [-lib_map_path] +# usage: ila_cal.sh [-noclean_files] +# usage: ila_cal.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ila_cal xil_defaultlib.ila_cal xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim ila_cal -key {Behavioral:sim_1:Functional:ila_cal} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ila_cal.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_cal.sh [-help]\n\ +Usage: ila_cal.sh [-lib_map_path]\n\ +Usage: ila_cal.sh [-reset_run]\n\ +Usage: ila_cal.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/vlog.prj new file mode 100644 index 00000000..01bdc09e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_cal/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/ila_cal/hdl/verilog" \ +"../../../ip/ila_cal/sim/ila_cal.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/README.txt new file mode 100644 index 00000000..9a7ce0b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 09 13:35:14 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_freq_comp.sh' script. + +./ila_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_freq_comp.sh -noclean_files + +For more information on the script, please type './ila_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/compile.do new file mode 100644 index 00000000..00af5fd6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_freq_comp/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_freq_comp/hdl/verilog" \ +"../../../ip/ila_freq_comp/sim/ila_freq_comp.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/file_info.txt new file mode 100644 index 00000000..8b0c4c4c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_freq_comp/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_freq_comp/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_freq_comp/hdl/verilog" +ila_freq_comp.v,verilog,xil_defaultlib,../../../ip/ila_freq_comp/sim/ila_freq_comp.v,incdir="../../../ip/ila_freq_comp/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/ila_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/ila_freq_comp.sh new file mode 100755 index 00000000..5bf27b6f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/ila_freq_comp.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_freq_comp.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 09 13:35:14 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_freq_comp.sh [-help] +# usage: ila_freq_comp.sh [-lib_map_path] +# usage: ila_freq_comp.sh [-noclean_files] +# usage: ila_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_freq_comp.sh [-help]\n\ +Usage: ila_freq_comp.sh [-lib_map_path]\n\ +Usage: ila_freq_comp.sh [-reset_run]\n\ +Usage: ila_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/ila_freq_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/ila_freq_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/simulate.do new file mode 100644 index 00000000..545a87f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_freq_comp -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_freq_comp xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_freq_comp.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/README.txt new file mode 100644 index 00000000..3a1d0d21 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 09 13:35:14 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_freq_comp.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_freq_comp.sh' script. + +./ila_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_freq_comp.sh -noclean_files + +For more information on the script, please type './ila_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/file_info.txt new file mode 100644 index 00000000..8b0c4c4c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_freq_comp/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_freq_comp/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_freq_comp/hdl/verilog" +ila_freq_comp.v,verilog,xil_defaultlib,../../../ip/ila_freq_comp/sim/ila_freq_comp.v,incdir="../../../ip/ila_freq_comp/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/ila_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/ila_freq_comp.sh new file mode 100755 index 00000000..3464245c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/ila_freq_comp.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_freq_comp.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 09 13:35:14 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_freq_comp.sh [-help] +# usage: ila_freq_comp.sh [-lib_map_path] +# usage: ila_freq_comp.sh [-noclean_files] +# usage: ila_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "ila_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ila_freq_comp \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ila_freq_comp/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_freq_comp.sh [-help]\n\ +Usage: ila_freq_comp.sh [-lib_map_path]\n\ +Usage: ila_freq_comp.sh [-reset_run]\n\ +Usage: ila_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/run.f new file mode 100644 index 00000000..042068d2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/ila_freq_comp/sim/ila_freq_comp.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/README.txt new file mode 100644 index 00000000..9a7ce0b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 09 13:35:14 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_freq_comp.sh' script. + +./ila_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_freq_comp.sh -noclean_files + +For more information on the script, please type './ila_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/compile.do new file mode 100644 index 00000000..bccf7713 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_freq_comp/hdl/verilog" \ +"../../../ip/ila_freq_comp/sim/ila_freq_comp.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/file_info.txt new file mode 100644 index 00000000..d7d0480b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/file_info.txt @@ -0,0 +1,2 @@ +ila_freq_comp.v,verilog,xil_defaultlib,../../../ip/ila_freq_comp/sim/ila_freq_comp.v,incdir="../../../ip/ila_freq_comp/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/ila_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/ila_freq_comp.sh new file mode 100755 index 00000000..efbabef2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/ila_freq_comp.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_freq_comp.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 09 13:35:14 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_freq_comp.sh [-help] +# usage: ila_freq_comp.sh [-lib_map_path] +# usage: ila_freq_comp.sh [-noclean_files] +# usage: ila_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_freq_comp.sh [-help]\n\ +Usage: ila_freq_comp.sh [-lib_map_path]\n\ +Usage: ila_freq_comp.sh [-reset_run]\n\ +Usage: ila_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/ila_freq_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/ila_freq_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/simulate.do new file mode 100644 index 00000000..6b9a356b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.ila_freq_comp xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {ila_freq_comp.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/README.txt new file mode 100644 index 00000000..9a7ce0b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 09 13:35:14 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_freq_comp.sh' script. + +./ila_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_freq_comp.sh -noclean_files + +For more information on the script, please type './ila_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/compile.do new file mode 100644 index 00000000..7cbc1acb --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_freq_comp/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_freq_comp/hdl/verilog" \ +"../../../ip/ila_freq_comp/sim/ila_freq_comp.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/elaborate.do new file mode 100644 index 00000000..70c04ee8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_freq_comp xil_defaultlib.glbl -o ila_freq_comp_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/file_info.txt new file mode 100644 index 00000000..8b0c4c4c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_freq_comp/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_freq_comp/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_freq_comp/hdl/verilog" +ila_freq_comp.v,verilog,xil_defaultlib,../../../ip/ila_freq_comp/sim/ila_freq_comp.v,incdir="../../../ip/ila_freq_comp/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/ila_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/ila_freq_comp.sh new file mode 100755 index 00000000..e17b97ad --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/ila_freq_comp.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_freq_comp.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 09 13:35:14 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_freq_comp.sh [-help] +# usage: ila_freq_comp.sh [-lib_map_path] +# usage: ila_freq_comp.sh [-noclean_files] +# usage: ila_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_freq_comp.sh [-help]\n\ +Usage: ila_freq_comp.sh [-lib_map_path]\n\ +Usage: ila_freq_comp.sh [-reset_run]\n\ +Usage: ila_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/ila_freq_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/ila_freq_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/simulate.do new file mode 100644 index 00000000..0a874e40 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib ila_freq_comp_opt + +do {wave.do} + +view wave +view structure +view signals + +do {ila_freq_comp.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/README.txt new file mode 100644 index 00000000..9a7ce0b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 09 13:35:14 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_freq_comp.sh' script. + +./ila_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_freq_comp.sh -noclean_files + +For more information on the script, please type './ila_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/compile.do new file mode 100644 index 00000000..ac4f8b8b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_freq_comp/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_freq_comp/hdl/verilog" \ +"../../../ip/ila_freq_comp/sim/ila_freq_comp.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/file_info.txt new file mode 100644 index 00000000..8b0c4c4c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_freq_comp/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_freq_comp/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_freq_comp/hdl/verilog" +ila_freq_comp.v,verilog,xil_defaultlib,../../../ip/ila_freq_comp/sim/ila_freq_comp.v,incdir="../../../ip/ila_freq_comp/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/ila_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/ila_freq_comp.sh new file mode 100755 index 00000000..f1536439 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/ila_freq_comp.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_freq_comp.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 09 13:35:14 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_freq_comp.sh [-help] +# usage: ila_freq_comp.sh [-lib_map_path] +# usage: ila_freq_comp.sh [-noclean_files] +# usage: ila_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_freq_comp.sh [-help]\n\ +Usage: ila_freq_comp.sh [-lib_map_path]\n\ +Usage: ila_freq_comp.sh [-reset_run]\n\ +Usage: ila_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/ila_freq_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/ila_freq_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/simulate.do new file mode 100644 index 00000000..545a87f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_freq_comp -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_freq_comp xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_freq_comp.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/README.txt new file mode 100644 index 00000000..9a7ce0b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 09 13:35:14 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_freq_comp.sh' script. + +./ila_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_freq_comp.sh -noclean_files + +For more information on the script, please type './ila_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/file_info.txt new file mode 100644 index 00000000..d7d0480b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/file_info.txt @@ -0,0 +1,2 @@ +ila_freq_comp.v,verilog,xil_defaultlib,../../../ip/ila_freq_comp/sim/ila_freq_comp.v,incdir="../../../ip/ila_freq_comp/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/ila_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/ila_freq_comp.sh new file mode 100755 index 00000000..27d00c0e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/ila_freq_comp.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_freq_comp.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 09 13:35:14 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_freq_comp.sh [-help] +# usage: ila_freq_comp.sh [-lib_map_path] +# usage: ila_freq_comp.sh [-noclean_files] +# usage: ila_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "ila_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_freq_comp/hdl/verilog" \ + "$ref_dir/../../../ip/ila_freq_comp/sim/ila_freq_comp.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.ila_freq_comp xil_defaultlib.glbl -o ila_freq_comp_simv +} + +# RUN_STEP: +simulate() +{ + ./ila_freq_comp_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key ila_freq_comp_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ila_freq_comp_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_freq_comp.sh [-help]\n\ +Usage: ila_freq_comp.sh [-lib_map_path]\n\ +Usage: ila_freq_comp.sh [-reset_run]\n\ +Usage: ila_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/README.txt new file mode 100644 index 00000000..3a1d0d21 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 09 13:35:14 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_freq_comp.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_freq_comp.sh' script. + +./ila_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_freq_comp.sh -noclean_files + +For more information on the script, please type './ila_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/file_info.txt new file mode 100644 index 00000000..8b0c4c4c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_freq_comp/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_freq_comp/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_freq_comp/hdl/verilog" +ila_freq_comp.v,verilog,xil_defaultlib,../../../ip/ila_freq_comp/sim/ila_freq_comp.v,incdir="../../../ip/ila_freq_comp/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/ila_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/ila_freq_comp.sh new file mode 100755 index 00000000..a0619507 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/ila_freq_comp.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_freq_comp.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 09 13:35:14 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_freq_comp.sh [-help] +# usage: ila_freq_comp.sh [-lib_map_path] +# usage: ila_freq_comp.sh [-noclean_files] +# usage: ila_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "ila_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ila_freq_comp \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ila_freq_comp/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_freq_comp.sh [-help]\n\ +Usage: ila_freq_comp.sh [-lib_map_path]\n\ +Usage: ila_freq_comp.sh [-reset_run]\n\ +Usage: ila_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/run.f new file mode 100644 index 00000000..90e576b2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/ila_freq_comp/sim/ila_freq_comp.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/README.txt new file mode 100644 index 00000000..9a7ce0b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 09 13:35:14 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_freq_comp.sh' script. + +./ila_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_freq_comp.sh -noclean_files + +For more information on the script, please type './ila_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/file_info.txt new file mode 100644 index 00000000..d7d0480b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/file_info.txt @@ -0,0 +1,2 @@ +ila_freq_comp.v,verilog,xil_defaultlib,../../../ip/ila_freq_comp/sim/ila_freq_comp.v,incdir="../../../ip/ila_freq_comp/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/ila_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/ila_freq_comp.sh new file mode 100755 index 00000000..a57b70fb --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/ila_freq_comp.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_freq_comp.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 09 13:35:14 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_freq_comp.sh [-help] +# usage: ila_freq_comp.sh [-lib_map_path] +# usage: ila_freq_comp.sh [-noclean_files] +# usage: ila_freq_comp.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "ila_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ila_freq_comp xil_defaultlib.ila_freq_comp xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim ila_freq_comp -key {Behavioral:sim_1:Functional:ila_freq_comp} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ila_freq_comp.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_freq_comp.sh [-help]\n\ +Usage: ila_freq_comp.sh [-lib_map_path]\n\ +Usage: ila_freq_comp.sh [-reset_run]\n\ +Usage: ila_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/vlog.prj new file mode 100644 index 00000000..80e61a80 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/ila_freq_comp/hdl/verilog" \ +"../../../ip/ila_freq_comp/sim/ila_freq_comp.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/README.txt new file mode 100644 index 00000000..5ebaed09 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:13 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./mult_18x18.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './mult_18x18.sh' script. + +./mult_18x18.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./mult_18x18.sh -noclean_files + +For more information on the script, please type './mult_18x18.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/compile.do new file mode 100644 index 00000000..d51dbb75 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/compile.do @@ -0,0 +1,42 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/xbip_utils_v3_0_10 +vlib activehdl/xbip_pipe_v3_0_6 +vlib activehdl/xbip_bram18k_v3_0_6 +vlib activehdl/mult_gen_v12_0_15 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10 +vmap xbip_pipe_v3_0_6 activehdl/xbip_pipe_v3_0_6 +vmap xbip_bram18k_v3_0_6 activehdl/xbip_bram18k_v3_0_6 +vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_pipe_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_bram18k_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + +vcom -work mult_gen_v12_0_15 -93 \ +"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../ip/mult_18x18/sim/mult_18x18.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/file_info.txt new file mode 100644 index 00000000..41462ba3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +mult_18x18.vhd,vhdl,xil_defaultlib,../../../ip/mult_18x18/sim/mult_18x18.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/mult_18x18.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/mult_18x18.sh new file mode 100755 index 00000000..208c3ba6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/mult_18x18.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : mult_18x18.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:13 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: mult_18x18.sh [-help] +# usage: mult_18x18.sh [-lib_map_path] +# usage: mult_18x18.sh [-noclean_files] +# usage: mult_18x18.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'mult_18x18.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "mult_18x18.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: mult_18x18.sh [-help]\n\ +Usage: mult_18x18.sh [-lib_map_path]\n\ +Usage: mult_18x18.sh [-reset_run]\n\ +Usage: mult_18x18.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/mult_18x18.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/mult_18x18.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/simulate.do new file mode 100644 index 00000000..f59e7d39 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+mult_18x18 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.mult_18x18 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {mult_18x18.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/README.txt new file mode 100644 index 00000000..ebd84947 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:13 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./mult_18x18.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './mult_18x18.sh' script. + +./mult_18x18.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./mult_18x18.sh -noclean_files + +For more information on the script, please type './mult_18x18.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/file_info.txt new file mode 100644 index 00000000..41462ba3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +mult_18x18.vhd,vhdl,xil_defaultlib,../../../ip/mult_18x18/sim/mult_18x18.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/mult_18x18.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/mult_18x18.sh new file mode 100755 index 00000000..2e3036f2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/mult_18x18.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : mult_18x18.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:13 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: mult_18x18.sh [-help] +# usage: mult_18x18.sh [-lib_map_path] +# usage: mult_18x18.sh [-noclean_files] +# usage: mult_18x18.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'mult_18x18.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "mult_18x18.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.mult_18x18 \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: mult_18x18.sh [-help]\n\ +Usage: mult_18x18.sh [-lib_map_path]\n\ +Usage: mult_18x18.sh [-reset_run]\n\ +Usage: mult_18x18.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/run.f new file mode 100644 index 00000000..5444a10c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/ies/run.f @@ -0,0 +1,26 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xbip_utils_v3_0_10 \ + "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xbip_pipe_v3_0_6 \ + "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xbip_bram18k_v3_0_6 \ + "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/mult_gen_v12_0_15 \ + "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/mult_18x18/sim/mult_18x18.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/README.txt new file mode 100644 index 00000000..5ebaed09 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:13 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./mult_18x18.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './mult_18x18.sh' script. + +./mult_18x18.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./mult_18x18.sh -noclean_files + +For more information on the script, please type './mult_18x18.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/compile.do new file mode 100644 index 00000000..5f779054 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vcom -work xil_defaultlib -64 -93 \ +"../../../ip/mult_18x18/sim/mult_18x18.vhd" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/file_info.txt new file mode 100644 index 00000000..af33f033 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/file_info.txt @@ -0,0 +1,2 @@ +mult_18x18.vhd,vhdl,xil_defaultlib,../../../ip/mult_18x18/sim/mult_18x18.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/mult_18x18.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/mult_18x18.sh new file mode 100755 index 00000000..86a08317 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/mult_18x18.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : mult_18x18.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:13 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: mult_18x18.sh [-help] +# usage: mult_18x18.sh [-lib_map_path] +# usage: mult_18x18.sh [-noclean_files] +# usage: mult_18x18.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'mult_18x18.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "mult_18x18.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: mult_18x18.sh [-help]\n\ +Usage: mult_18x18.sh [-lib_map_path]\n\ +Usage: mult_18x18.sh [-reset_run]\n\ +Usage: mult_18x18.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/mult_18x18.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/mult_18x18.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/simulate.do new file mode 100644 index 00000000..f61d908b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.mult_18x18 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {mult_18x18.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/README.txt new file mode 100644 index 00000000..5ebaed09 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:13 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./mult_18x18.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './mult_18x18.sh' script. + +./mult_18x18.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./mult_18x18.sh -noclean_files + +For more information on the script, please type './mult_18x18.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/compile.do new file mode 100644 index 00000000..3f4899c9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/compile.do @@ -0,0 +1,42 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/xbip_utils_v3_0_10 +vlib questa_lib/msim/xbip_pipe_v3_0_6 +vlib questa_lib/msim/xbip_bram18k_v3_0_6 +vlib questa_lib/msim/mult_gen_v12_0_15 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10 +vmap xbip_pipe_v3_0_6 questa_lib/msim/xbip_pipe_v3_0_6 +vmap xbip_bram18k_v3_0_6 questa_lib/msim/xbip_bram18k_v3_0_6 +vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15 + +vlog -work xil_defaultlib -64 -sv \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -64 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_pipe_v3_0_6 -64 -93 \ +"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_bram18k_v3_0_6 -64 -93 \ +"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + +vcom -work mult_gen_v12_0_15 -64 -93 \ +"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../ip/mult_18x18/sim/mult_18x18.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/elaborate.do new file mode 100644 index 00000000..74a64e75 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.mult_18x18 xil_defaultlib.glbl -o mult_18x18_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/file_info.txt new file mode 100644 index 00000000..41462ba3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +mult_18x18.vhd,vhdl,xil_defaultlib,../../../ip/mult_18x18/sim/mult_18x18.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/mult_18x18.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/mult_18x18.sh new file mode 100755 index 00000000..73255be3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/mult_18x18.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : mult_18x18.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:13 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: mult_18x18.sh [-help] +# usage: mult_18x18.sh [-lib_map_path] +# usage: mult_18x18.sh [-noclean_files] +# usage: mult_18x18.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'mult_18x18.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "mult_18x18.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: mult_18x18.sh [-help]\n\ +Usage: mult_18x18.sh [-lib_map_path]\n\ +Usage: mult_18x18.sh [-reset_run]\n\ +Usage: mult_18x18.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/mult_18x18.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/mult_18x18.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/simulate.do new file mode 100644 index 00000000..0e612d72 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib mult_18x18_opt + +do {wave.do} + +view wave +view structure +view signals + +do {mult_18x18.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/README.txt new file mode 100644 index 00000000..5ebaed09 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:13 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./mult_18x18.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './mult_18x18.sh' script. + +./mult_18x18.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./mult_18x18.sh -noclean_files + +For more information on the script, please type './mult_18x18.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/compile.do new file mode 100644 index 00000000..7e8c2993 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/compile.do @@ -0,0 +1,42 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/xbip_utils_v3_0_10 +vlib riviera/xbip_pipe_v3_0_6 +vlib riviera/xbip_bram18k_v3_0_6 +vlib riviera/mult_gen_v12_0_15 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10 +vmap xbip_pipe_v3_0_6 riviera/xbip_pipe_v3_0_6 +vmap xbip_bram18k_v3_0_6 riviera/xbip_bram18k_v3_0_6 +vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_pipe_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_bram18k_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + +vcom -work mult_gen_v12_0_15 -93 \ +"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../ip/mult_18x18/sim/mult_18x18.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/file_info.txt new file mode 100644 index 00000000..41462ba3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +mult_18x18.vhd,vhdl,xil_defaultlib,../../../ip/mult_18x18/sim/mult_18x18.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/mult_18x18.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/mult_18x18.sh new file mode 100755 index 00000000..454ba275 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/mult_18x18.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : mult_18x18.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:13 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: mult_18x18.sh [-help] +# usage: mult_18x18.sh [-lib_map_path] +# usage: mult_18x18.sh [-noclean_files] +# usage: mult_18x18.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'mult_18x18.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "mult_18x18.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: mult_18x18.sh [-help]\n\ +Usage: mult_18x18.sh [-lib_map_path]\n\ +Usage: mult_18x18.sh [-reset_run]\n\ +Usage: mult_18x18.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/mult_18x18.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/mult_18x18.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/simulate.do new file mode 100644 index 00000000..f59e7d39 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+mult_18x18 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.mult_18x18 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {mult_18x18.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/README.txt new file mode 100644 index 00000000..5ebaed09 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:13 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./mult_18x18.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './mult_18x18.sh' script. + +./mult_18x18.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./mult_18x18.sh -noclean_files + +For more information on the script, please type './mult_18x18.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/file_info.txt new file mode 100644 index 00000000..af33f033 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/file_info.txt @@ -0,0 +1,2 @@ +mult_18x18.vhd,vhdl,xil_defaultlib,../../../ip/mult_18x18/sim/mult_18x18.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/mult_18x18.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/mult_18x18.sh new file mode 100755 index 00000000..875897cb --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/mult_18x18.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : mult_18x18.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:13 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: mult_18x18.sh [-help] +# usage: mult_18x18.sh [-lib_map_path] +# usage: mult_18x18.sh [-noclean_files] +# usage: mult_18x18.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'mult_18x18.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "mult_18x18.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../ip/mult_18x18/sim/mult_18x18.vhd" \ + 2>&1 | tee -a vhdlan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.mult_18x18 xil_defaultlib.glbl -o mult_18x18_simv +} + +# RUN_STEP: +simulate() +{ + ./mult_18x18_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key mult_18x18_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc mult_18x18_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: mult_18x18.sh [-help]\n\ +Usage: mult_18x18.sh [-lib_map_path]\n\ +Usage: mult_18x18.sh [-reset_run]\n\ +Usage: mult_18x18.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/README.txt new file mode 100644 index 00000000..ebd84947 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:13 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./mult_18x18.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './mult_18x18.sh' script. + +./mult_18x18.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./mult_18x18.sh -noclean_files + +For more information on the script, please type './mult_18x18.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/file_info.txt new file mode 100644 index 00000000..41462ba3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +mult_18x18.vhd,vhdl,xil_defaultlib,../../../ip/mult_18x18/sim/mult_18x18.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/mult_18x18.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/mult_18x18.sh new file mode 100755 index 00000000..2f72ff5e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/mult_18x18.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : mult_18x18.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:13 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: mult_18x18.sh [-help] +# usage: mult_18x18.sh [-lib_map_path] +# usage: mult_18x18.sh [-noclean_files] +# usage: mult_18x18.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'mult_18x18.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "mult_18x18.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.mult_18x18 \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: mult_18x18.sh [-help]\n\ +Usage: mult_18x18.sh [-lib_map_path]\n\ +Usage: mult_18x18.sh [-reset_run]\n\ +Usage: mult_18x18.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/run.f new file mode 100644 index 00000000..93820eda --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xcelium/run.f @@ -0,0 +1,26 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xbip_utils_v3_0_10 \ + "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xbip_pipe_v3_0_6 \ + "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xbip_bram18k_v3_0_6 \ + "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/mult_gen_v12_0_15 \ + "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/mult_18x18/sim/mult_18x18.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/README.txt new file mode 100644 index 00000000..5ebaed09 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:13 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./mult_18x18.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './mult_18x18.sh' script. + +./mult_18x18.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./mult_18x18.sh -noclean_files + +For more information on the script, please type './mult_18x18.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/file_info.txt new file mode 100644 index 00000000..af33f033 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/file_info.txt @@ -0,0 +1,2 @@ +mult_18x18.vhd,vhdl,xil_defaultlib,../../../ip/mult_18x18/sim/mult_18x18.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/mult_18x18.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/mult_18x18.sh new file mode 100755 index 00000000..b8203ba1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/mult_18x18.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : mult_18x18.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:13 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: mult_18x18.sh [-help] +# usage: mult_18x18.sh [-lib_map_path] +# usage: mult_18x18.sh [-noclean_files] +# usage: mult_18x18.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" +xvhdl_opts="--relax" + + +# Script info +echo -e "mult_18x18.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot mult_18x18 xil_defaultlib.mult_18x18 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim mult_18x18 -key {Behavioral:sim_1:Functional:mult_18x18} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb mult_18x18.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./mult_18x18.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: mult_18x18.sh [-help]\n\ +Usage: mult_18x18.sh [-lib_map_path]\n\ +Usage: mult_18x18.sh [-reset_run]\n\ +Usage: mult_18x18.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/vhdl.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/vhdl.prj new file mode 100644 index 00000000..6ccbe46e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/vhdl.prj @@ -0,0 +1,4 @@ +vhdl xil_defaultlib \ +"../../../ip/mult_18x18/sim/mult_18x18.vhd" \ + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/vlog.prj new file mode 100644 index 00000000..35119d5b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/mult_18x18/xsim/vlog.prj @@ -0,0 +1,4 @@ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt new file mode 100644 index 00000000..73a4c034 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:27:35 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do new file mode 100644 index 00000000..1e5ae39c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do @@ -0,0 +1,27 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_3 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_3 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe new file mode 100755 index 00000000..20ed79a7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif new file mode 100644 index 00000000..4c2a27b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif @@ -0,0 +1,81 @@ +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 +0000011101111100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh new file mode 100755 index 00000000..e443c8ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:27:35 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/simulate.do new file mode 100644 index 00000000..b880455d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+rom_freq_word -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rom_freq_word xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {rom_freq_word.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt new file mode 100644 index 00000000..7f2099b7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:27:35 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe new file mode 100755 index 00000000..20ed79a7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif new file mode 100644 index 00000000..4c2a27b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif @@ -0,0 +1,81 @@ +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 +0000011101111100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh new file mode 100755 index 00000000..0b86d76e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:27:35 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.rom_freq_word \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f new file mode 100644 index 00000000..09c85501 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f @@ -0,0 +1,17 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_3 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/rom_freq_word/sim/rom_freq_word.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt new file mode 100644 index 00000000..73a4c034 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:27:35 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/compile.do new file mode 100644 index 00000000..8b8458a0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/file_info.txt new file mode 100644 index 00000000..fe59d479 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/file_info.txt @@ -0,0 +1,2 @@ +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe new file mode 100755 index 00000000..20ed79a7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif new file mode 100644 index 00000000..4c2a27b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif @@ -0,0 +1,81 @@ +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 +0000011101111100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh new file mode 100755 index 00000000..e8a6f2f5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:27:35 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/simulate.do new file mode 100644 index 00000000..3bc7aaf4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.rom_freq_word xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {rom_freq_word.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt new file mode 100644 index 00000000..73a4c034 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:27:35 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do new file mode 100644 index 00000000..bd408354 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do @@ -0,0 +1,27 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_3 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3 + +vlog -work xil_defaultlib -64 -sv \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_3 -64 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/elaborate.do new file mode 100644 index 00000000..f81f2bb9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rom_freq_word xil_defaultlib.glbl -o rom_freq_word_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe new file mode 100755 index 00000000..20ed79a7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif new file mode 100644 index 00000000..4c2a27b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif @@ -0,0 +1,81 @@ +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 +0000011101111100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh new file mode 100755 index 00000000..9517915a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:27:35 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/simulate.do new file mode 100644 index 00000000..d8b2f89d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib rom_freq_word_opt + +do {wave.do} + +view wave +view structure +view signals + +do {rom_freq_word.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt new file mode 100644 index 00000000..73a4c034 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:27:35 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do new file mode 100644 index 00000000..1baef140 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do @@ -0,0 +1,27 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_3 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_3 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe new file mode 100755 index 00000000..20ed79a7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif new file mode 100644 index 00000000..4c2a27b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif @@ -0,0 +1,81 @@ +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 +0000011101111100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh new file mode 100755 index 00000000..880fcbd2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:27:35 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/simulate.do new file mode 100644 index 00000000..b880455d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+rom_freq_word -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rom_freq_word xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {rom_freq_word.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt new file mode 100644 index 00000000..73a4c034 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:27:35 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/file_info.txt new file mode 100644 index 00000000..fe59d479 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/file_info.txt @@ -0,0 +1,2 @@ +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe new file mode 100755 index 00000000..20ed79a7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif new file mode 100644 index 00000000..4c2a27b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif @@ -0,0 +1,81 @@ +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 +0000011101111100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh new file mode 100755 index 00000000..7fc9eb3b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:27:35 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.rom_freq_word xil_defaultlib.glbl -o rom_freq_word_simv +} + +# RUN_STEP: +simulate() +{ + ./rom_freq_word_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key rom_freq_word_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc rom_freq_word_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt new file mode 100644 index 00000000..7f2099b7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:27:35 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe new file mode 100755 index 00000000..20ed79a7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif new file mode 100644 index 00000000..4c2a27b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif @@ -0,0 +1,81 @@ +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 +0000011101111100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh new file mode 100755 index 00000000..1c5cf7f4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:27:35 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.rom_freq_word \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f new file mode 100644 index 00000000..7720194b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f @@ -0,0 +1,17 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_3 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/rom_freq_word/sim/rom_freq_word.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt new file mode 100644 index 00000000..73a4c034 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:27:35 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/file_info.txt new file mode 100644 index 00000000..fe59d479 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/file_info.txt @@ -0,0 +1,2 @@ +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe new file mode 100755 index 00000000..20ed79a7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif new file mode 100644 index 00000000..4c2a27b1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif @@ -0,0 +1,81 @@ +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 +0000011101111100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh new file mode 100755 index 00000000..36518236 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:27:35 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rom_freq_word xil_defaultlib.rom_freq_word xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim rom_freq_word -key {Behavioral:sim_1:Functional:rom_freq_word} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb rom_freq_word.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/vlog.prj new file mode 100644 index 00000000..5f7fb546 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/README.txt new file mode 100644 index 00000000..326338be --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_clk_ld_rd.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_clk_ld_rd.sh' script. + +./vio_clk_ld_rd.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_clk_ld_rd.sh -noclean_files + +For more information on the script, please type './vio_clk_ld_rd.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/compile.do new file mode 100644 index 00000000..9ef361f8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_clk_ld_rd/hdl/verilog" "+incdir+../../../ip/vio_clk_ld_rd/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_clk_ld_rd/hdl/verilog" "+incdir+../../../ip/vio_clk_ld_rd/hdl" \ +"../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/file_info.txt new file mode 100644 index 00000000..4e7159e4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +vio_clk_ld_rd.v,verilog,xil_defaultlib,../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/simulate.do new file mode 100644 index 00000000..ca9e41c9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_clk_ld_rd -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_clk_ld_rd xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_clk_ld_rd.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/vio_clk_ld_rd.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/vio_clk_ld_rd.sh new file mode 100755 index 00000000..f8a00035 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/vio_clk_ld_rd.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_clk_ld_rd.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_clk_ld_rd.sh [-help] +# usage: vio_clk_ld_rd.sh [-lib_map_path] +# usage: vio_clk_ld_rd.sh [-noclean_files] +# usage: vio_clk_ld_rd.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_clk_ld_rd.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_clk_ld_rd.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_clk_ld_rd.sh [-help]\n\ +Usage: vio_clk_ld_rd.sh [-lib_map_path]\n\ +Usage: vio_clk_ld_rd.sh [-reset_run]\n\ +Usage: vio_clk_ld_rd.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/vio_clk_ld_rd.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/vio_clk_ld_rd.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/README.txt new file mode 100644 index 00000000..cc03b150 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_clk_ld_rd.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_clk_ld_rd.sh' script. + +./vio_clk_ld_rd.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_clk_ld_rd.sh -noclean_files + +For more information on the script, please type './vio_clk_ld_rd.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/file_info.txt new file mode 100644 index 00000000..4e7159e4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +vio_clk_ld_rd.v,verilog,xil_defaultlib,../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/run.f new file mode 100644 index 00000000..a15c43c4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/vio_clk_ld_rd.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/vio_clk_ld_rd.sh new file mode 100755 index 00000000..8010474d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/ies/vio_clk_ld_rd.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_clk_ld_rd.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_clk_ld_rd.sh [-help] +# usage: vio_clk_ld_rd.sh [-lib_map_path] +# usage: vio_clk_ld_rd.sh [-noclean_files] +# usage: vio_clk_ld_rd.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_clk_ld_rd.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "vio_clk_ld_rd.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_clk_ld_rd \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_clk_ld_rd/hdl/verilog" \ + +incdir+"../../../ip/vio_clk_ld_rd/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_clk_ld_rd.sh [-help]\n\ +Usage: vio_clk_ld_rd.sh [-lib_map_path]\n\ +Usage: vio_clk_ld_rd.sh [-reset_run]\n\ +Usage: vio_clk_ld_rd.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/README.txt new file mode 100644 index 00000000..326338be --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_clk_ld_rd.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_clk_ld_rd.sh' script. + +./vio_clk_ld_rd.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_clk_ld_rd.sh -noclean_files + +For more information on the script, please type './vio_clk_ld_rd.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/compile.do new file mode 100644 index 00000000..d83f5537 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/compile.do @@ -0,0 +1,22 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/vio_clk_ld_rd/hdl/verilog" "+incdir+../../../ip/vio_clk_ld_rd/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_clk_ld_rd/hdl/verilog" "+incdir+../../../ip/vio_clk_ld_rd/hdl" \ +"../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/file_info.txt new file mode 100644 index 00000000..4e7159e4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +vio_clk_ld_rd.v,verilog,xil_defaultlib,../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/simulate.do new file mode 100644 index 00000000..b3a430f9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.vio_clk_ld_rd xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {vio_clk_ld_rd.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/vio_clk_ld_rd.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/vio_clk_ld_rd.sh new file mode 100755 index 00000000..387a203d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/vio_clk_ld_rd.sh @@ -0,0 +1,168 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_clk_ld_rd.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_clk_ld_rd.sh [-help] +# usage: vio_clk_ld_rd.sh [-lib_map_path] +# usage: vio_clk_ld_rd.sh [-noclean_files] +# usage: vio_clk_ld_rd.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_clk_ld_rd.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_clk_ld_rd.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_clk_ld_rd.sh [-help]\n\ +Usage: vio_clk_ld_rd.sh [-lib_map_path]\n\ +Usage: vio_clk_ld_rd.sh [-reset_run]\n\ +Usage: vio_clk_ld_rd.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/vio_clk_ld_rd.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/vio_clk_ld_rd.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/README.txt new file mode 100644 index 00000000..326338be --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_clk_ld_rd.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_clk_ld_rd.sh' script. + +./vio_clk_ld_rd.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_clk_ld_rd.sh -noclean_files + +For more information on the script, please type './vio_clk_ld_rd.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/compile.do new file mode 100644 index 00000000..d925ccb9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_clk_ld_rd/hdl/verilog" "+incdir+../../../ip/vio_clk_ld_rd/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_clk_ld_rd/hdl/verilog" "+incdir+../../../ip/vio_clk_ld_rd/hdl" \ +"../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/elaborate.do new file mode 100644 index 00000000..fc4d374c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_clk_ld_rd xil_defaultlib.glbl -o vio_clk_ld_rd_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/file_info.txt new file mode 100644 index 00000000..4e7159e4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +vio_clk_ld_rd.v,verilog,xil_defaultlib,../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/simulate.do new file mode 100644 index 00000000..2b91b173 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib vio_clk_ld_rd_opt + +do {wave.do} + +view wave +view structure +view signals + +do {vio_clk_ld_rd.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/vio_clk_ld_rd.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/vio_clk_ld_rd.sh new file mode 100755 index 00000000..b503d659 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/vio_clk_ld_rd.sh @@ -0,0 +1,173 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_clk_ld_rd.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_clk_ld_rd.sh [-help] +# usage: vio_clk_ld_rd.sh [-lib_map_path] +# usage: vio_clk_ld_rd.sh [-noclean_files] +# usage: vio_clk_ld_rd.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_clk_ld_rd.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_clk_ld_rd.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_clk_ld_rd.sh [-help]\n\ +Usage: vio_clk_ld_rd.sh [-lib_map_path]\n\ +Usage: vio_clk_ld_rd.sh [-reset_run]\n\ +Usage: vio_clk_ld_rd.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/vio_clk_ld_rd.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/vio_clk_ld_rd.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/README.txt new file mode 100644 index 00000000..326338be --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_clk_ld_rd.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_clk_ld_rd.sh' script. + +./vio_clk_ld_rd.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_clk_ld_rd.sh -noclean_files + +For more information on the script, please type './vio_clk_ld_rd.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/compile.do new file mode 100644 index 00000000..fd3c1613 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_clk_ld_rd/hdl/verilog" "+incdir+../../../ip/vio_clk_ld_rd/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_clk_ld_rd/hdl/verilog" "+incdir+../../../ip/vio_clk_ld_rd/hdl" \ +"../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/file_info.txt new file mode 100644 index 00000000..4e7159e4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +vio_clk_ld_rd.v,verilog,xil_defaultlib,../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/simulate.do new file mode 100644 index 00000000..ca9e41c9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_clk_ld_rd -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_clk_ld_rd xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_clk_ld_rd.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/vio_clk_ld_rd.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/vio_clk_ld_rd.sh new file mode 100755 index 00000000..d2904160 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/vio_clk_ld_rd.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_clk_ld_rd.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_clk_ld_rd.sh [-help] +# usage: vio_clk_ld_rd.sh [-lib_map_path] +# usage: vio_clk_ld_rd.sh [-noclean_files] +# usage: vio_clk_ld_rd.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_clk_ld_rd.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_clk_ld_rd.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_clk_ld_rd.sh [-help]\n\ +Usage: vio_clk_ld_rd.sh [-lib_map_path]\n\ +Usage: vio_clk_ld_rd.sh [-reset_run]\n\ +Usage: vio_clk_ld_rd.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/vio_clk_ld_rd.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/vio_clk_ld_rd.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/README.txt new file mode 100644 index 00000000..326338be --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_clk_ld_rd.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_clk_ld_rd.sh' script. + +./vio_clk_ld_rd.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_clk_ld_rd.sh -noclean_files + +For more information on the script, please type './vio_clk_ld_rd.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/file_info.txt new file mode 100644 index 00000000..4e7159e4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +vio_clk_ld_rd.v,verilog,xil_defaultlib,../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/vio_clk_ld_rd.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/vio_clk_ld_rd.sh new file mode 100755 index 00000000..3fab7a08 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/vcs/vio_clk_ld_rd.sh @@ -0,0 +1,229 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_clk_ld_rd.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_clk_ld_rd.sh [-help] +# usage: vio_clk_ld_rd.sh [-lib_map_path] +# usage: vio_clk_ld_rd.sh [-noclean_files] +# usage: vio_clk_ld_rd.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_clk_ld_rd.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "vio_clk_ld_rd.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/vio_clk_ld_rd/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_clk_ld_rd/hdl" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_clk_ld_rd/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_clk_ld_rd/hdl" \ + "$ref_dir/../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.vio_clk_ld_rd xil_defaultlib.glbl -o vio_clk_ld_rd_simv +} + +# RUN_STEP: +simulate() +{ + ./vio_clk_ld_rd_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key vio_clk_ld_rd_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_clk_ld_rd_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_clk_ld_rd.sh [-help]\n\ +Usage: vio_clk_ld_rd.sh [-lib_map_path]\n\ +Usage: vio_clk_ld_rd.sh [-reset_run]\n\ +Usage: vio_clk_ld_rd.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/README.txt new file mode 100644 index 00000000..cc03b150 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_clk_ld_rd.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_clk_ld_rd.sh' script. + +./vio_clk_ld_rd.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_clk_ld_rd.sh -noclean_files + +For more information on the script, please type './vio_clk_ld_rd.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/file_info.txt new file mode 100644 index 00000000..4e7159e4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +vio_clk_ld_rd.v,verilog,xil_defaultlib,../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/run.f new file mode 100644 index 00000000..5a695f90 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/vio_clk_ld_rd.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/vio_clk_ld_rd.sh new file mode 100755 index 00000000..3c83c788 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xcelium/vio_clk_ld_rd.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_clk_ld_rd.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_clk_ld_rd.sh [-help] +# usage: vio_clk_ld_rd.sh [-lib_map_path] +# usage: vio_clk_ld_rd.sh [-noclean_files] +# usage: vio_clk_ld_rd.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_clk_ld_rd.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "vio_clk_ld_rd.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_clk_ld_rd \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_clk_ld_rd/hdl/verilog" \ + +incdir+"../../../ip/vio_clk_ld_rd/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_clk_ld_rd.sh [-help]\n\ +Usage: vio_clk_ld_rd.sh [-lib_map_path]\n\ +Usage: vio_clk_ld_rd.sh [-reset_run]\n\ +Usage: vio_clk_ld_rd.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/README.txt new file mode 100644 index 00000000..326338be --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 11:50:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_clk_ld_rd.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_clk_ld_rd.sh' script. + +./vio_clk_ld_rd.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_clk_ld_rd.sh -noclean_files + +For more information on the script, please type './vio_clk_ld_rd.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/file_info.txt new file mode 100644 index 00000000..1ea11c37 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_clk_ld_rd.v,verilog,xil_defaultlib,../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/vio_clk_ld_rd.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/vio_clk_ld_rd.sh new file mode 100755 index 00000000..1682670b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/vio_clk_ld_rd.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_clk_ld_rd.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 11:50:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_clk_ld_rd.sh [-help] +# usage: vio_clk_ld_rd.sh [-lib_map_path] +# usage: vio_clk_ld_rd.sh [-noclean_files] +# usage: vio_clk_ld_rd.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "vio_clk_ld_rd.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_clk_ld_rd xil_defaultlib.vio_clk_ld_rd xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim vio_clk_ld_rd -key {Behavioral:sim_1:Functional:vio_clk_ld_rd} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_clk_ld_rd.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_clk_ld_rd.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_clk_ld_rd.sh [-help]\n\ +Usage: vio_clk_ld_rd.sh [-lib_map_path]\n\ +Usage: vio_clk_ld_rd.sh [-reset_run]\n\ +Usage: vio_clk_ld_rd.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/vlog.prj new file mode 100644 index 00000000..af4fc0c4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_clk_ld_rd/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_clk_ld_rd/hdl/verilog" --include "../../../ip/vio_clk_ld_rd/hdl" \ +"../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt new file mode 100644 index 00000000..9a520055 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_freq_comp.sh' script. + +./vio_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_freq_comp.sh -noclean_files + +For more information on the script, please type './vio_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/compile.do new file mode 100644 index 00000000..ec00d4c4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ +"../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/file_info.txt new file mode 100644 index 00000000..3b96929b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/simulate.do new file mode 100644 index 00000000..dcde758a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_freq_comp -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_freq_comp xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_freq_comp.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh new file mode 100755 index 00000000..aa6531a2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_freq_comp.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_freq_comp.sh [-help] +# usage: vio_freq_comp.sh [-lib_map_path] +# usage: vio_freq_comp.sh [-noclean_files] +# usage: vio_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_freq_comp.sh [-help]\n\ +Usage: vio_freq_comp.sh [-lib_map_path]\n\ +Usage: vio_freq_comp.sh [-reset_run]\n\ +Usage: vio_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt new file mode 100644 index 00000000..3ae276e6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_freq_comp.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_freq_comp.sh' script. + +./vio_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_freq_comp.sh -noclean_files + +For more information on the script, please type './vio_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/file_info.txt new file mode 100644 index 00000000..3b96929b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/run.f new file mode 100644 index 00000000..8ac393b6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh new file mode 100755 index 00000000..aa2d4acd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_freq_comp.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_freq_comp.sh [-help] +# usage: vio_freq_comp.sh [-lib_map_path] +# usage: vio_freq_comp.sh [-noclean_files] +# usage: vio_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "vio_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_freq_comp \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_freq_comp/hdl/verilog" \ + +incdir+"../../../ip/vio_freq_comp/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_freq_comp.sh [-help]\n\ +Usage: vio_freq_comp.sh [-lib_map_path]\n\ +Usage: vio_freq_comp.sh [-reset_run]\n\ +Usage: vio_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt new file mode 100644 index 00000000..9a520055 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_freq_comp.sh' script. + +./vio_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_freq_comp.sh -noclean_files + +For more information on the script, please type './vio_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/compile.do new file mode 100644 index 00000000..5cc67c8c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ +"../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/file_info.txt new file mode 100644 index 00000000..5dc177b4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/file_info.txt @@ -0,0 +1,2 @@ +vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/simulate.do new file mode 100644 index 00000000..e3c9751e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_freq_comp xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {vio_freq_comp.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh new file mode 100755 index 00000000..d65d58fe --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_freq_comp.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_freq_comp.sh [-help] +# usage: vio_freq_comp.sh [-lib_map_path] +# usage: vio_freq_comp.sh [-noclean_files] +# usage: vio_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_freq_comp.sh [-help]\n\ +Usage: vio_freq_comp.sh [-lib_map_path]\n\ +Usage: vio_freq_comp.sh [-reset_run]\n\ +Usage: vio_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt new file mode 100644 index 00000000..9a520055 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_freq_comp.sh' script. + +./vio_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_freq_comp.sh -noclean_files + +For more information on the script, please type './vio_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/compile.do new file mode 100644 index 00000000..4abf33e3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ +"../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/elaborate.do new file mode 100644 index 00000000..ff83f085 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_freq_comp xil_defaultlib.glbl -o vio_freq_comp_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/file_info.txt new file mode 100644 index 00000000..3b96929b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/simulate.do new file mode 100644 index 00000000..ccf0579c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib vio_freq_comp_opt + +do {wave.do} + +view wave +view structure +view signals + +do {vio_freq_comp.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh new file mode 100755 index 00000000..f42833f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_freq_comp.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_freq_comp.sh [-help] +# usage: vio_freq_comp.sh [-lib_map_path] +# usage: vio_freq_comp.sh [-noclean_files] +# usage: vio_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_freq_comp.sh [-help]\n\ +Usage: vio_freq_comp.sh [-lib_map_path]\n\ +Usage: vio_freq_comp.sh [-reset_run]\n\ +Usage: vio_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt new file mode 100644 index 00000000..9a520055 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_freq_comp.sh' script. + +./vio_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_freq_comp.sh -noclean_files + +For more information on the script, please type './vio_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/compile.do new file mode 100644 index 00000000..33a3f439 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ +"../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/file_info.txt new file mode 100644 index 00000000..3b96929b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/simulate.do new file mode 100644 index 00000000..dcde758a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_freq_comp -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_freq_comp xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_freq_comp.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh new file mode 100755 index 00000000..e88ba15e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_freq_comp.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_freq_comp.sh [-help] +# usage: vio_freq_comp.sh [-lib_map_path] +# usage: vio_freq_comp.sh [-noclean_files] +# usage: vio_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_freq_comp.sh [-help]\n\ +Usage: vio_freq_comp.sh [-lib_map_path]\n\ +Usage: vio_freq_comp.sh [-reset_run]\n\ +Usage: vio_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt new file mode 100644 index 00000000..9a520055 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_freq_comp.sh' script. + +./vio_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_freq_comp.sh -noclean_files + +For more information on the script, please type './vio_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/file_info.txt new file mode 100644 index 00000000..5dc177b4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/file_info.txt @@ -0,0 +1,2 @@ +vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh new file mode 100755 index 00000000..ed68a199 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_freq_comp.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_freq_comp.sh [-help] +# usage: vio_freq_comp.sh [-lib_map_path] +# usage: vio_freq_comp.sh [-noclean_files] +# usage: vio_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "vio_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_freq_comp/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_freq_comp/hdl" \ + "$ref_dir/../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.vio_freq_comp xil_defaultlib.glbl -o vio_freq_comp_simv +} + +# RUN_STEP: +simulate() +{ + ./vio_freq_comp_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key vio_freq_comp_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_freq_comp_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_freq_comp.sh [-help]\n\ +Usage: vio_freq_comp.sh [-lib_map_path]\n\ +Usage: vio_freq_comp.sh [-reset_run]\n\ +Usage: vio_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt new file mode 100644 index 00000000..3ae276e6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_freq_comp.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_freq_comp.sh' script. + +./vio_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_freq_comp.sh -noclean_files + +For more information on the script, please type './vio_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/file_info.txt new file mode 100644 index 00000000..3b96929b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/run.f new file mode 100644 index 00000000..33886eca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh new file mode 100755 index 00000000..c79679fc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_freq_comp.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_freq_comp.sh [-help] +# usage: vio_freq_comp.sh [-lib_map_path] +# usage: vio_freq_comp.sh [-noclean_files] +# usage: vio_freq_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_freq_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "vio_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_freq_comp \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_freq_comp/hdl/verilog" \ + +incdir+"../../../ip/vio_freq_comp/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_freq_comp.sh [-help]\n\ +Usage: vio_freq_comp.sh [-lib_map_path]\n\ +Usage: vio_freq_comp.sh [-reset_run]\n\ +Usage: vio_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt new file mode 100644 index 00000000..9a520055 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_freq_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_freq_comp.sh' script. + +./vio_freq_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_freq_comp.sh -noclean_files + +For more information on the script, please type './vio_freq_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/file_info.txt new file mode 100644 index 00000000..5dc177b4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh new file mode 100755 index 00000000..4b6f3e20 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_freq_comp.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_freq_comp.sh [-help] +# usage: vio_freq_comp.sh [-lib_map_path] +# usage: vio_freq_comp.sh [-noclean_files] +# usage: vio_freq_comp.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "vio_freq_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_freq_comp xil_defaultlib.vio_freq_comp xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim vio_freq_comp -key {Behavioral:sim_1:Functional:vio_freq_comp} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_freq_comp.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_freq_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_freq_comp.sh [-help]\n\ +Usage: vio_freq_comp.sh [-lib_map_path]\n\ +Usage: vio_freq_comp.sh [-reset_run]\n\ +Usage: vio_freq_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vlog.prj new file mode 100644 index 00000000..6444a099 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_freq_comp/hdl/verilog" --include "../../../ip/vio_freq_comp/hdl" \ +"../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt new file mode 100644 index 00000000..7d15bb3f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do new file mode 100644 index 00000000..1f6495c2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/simulate.do new file mode 100644 index 00000000..dc4a0b81 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_manual_ctrl -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_manual_ctrl.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh new file mode 100755 index 00000000..fe068248 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt new file mode 100644 index 00000000..d41dbfc9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f new file mode 100644 index 00000000..36f5e07d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh new file mode 100755 index 00000000..0fe6e018 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_manual_ctrl \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_manual_ctrl/hdl/verilog" \ + +incdir+"../../../ip/vio_manual_ctrl/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt new file mode 100644 index 00000000..7d15bb3f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/compile.do new file mode 100644 index 00000000..59c2be37 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/file_info.txt new file mode 100644 index 00000000..23d1ee0b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/file_info.txt @@ -0,0 +1,2 @@ +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/simulate.do new file mode 100644 index 00000000..2dedf95d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {vio_manual_ctrl.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh new file mode 100755 index 00000000..d0249452 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt new file mode 100644 index 00000000..7d15bb3f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do new file mode 100644 index 00000000..a2f2d23e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/elaborate.do new file mode 100644 index 00000000..e5aaa3c5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl -o vio_manual_ctrl_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/simulate.do new file mode 100644 index 00000000..f829579e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib vio_manual_ctrl_opt + +do {wave.do} + +view wave +view structure +view signals + +do {vio_manual_ctrl.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh new file mode 100755 index 00000000..8d6d5c86 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt new file mode 100644 index 00000000..7d15bb3f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do new file mode 100644 index 00000000..8710eef1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/simulate.do new file mode 100644 index 00000000..dc4a0b81 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_manual_ctrl -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_manual_ctrl.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh new file mode 100755 index 00000000..b70ec018 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt new file mode 100644 index 00000000..7d15bb3f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/file_info.txt new file mode 100644 index 00000000..23d1ee0b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/file_info.txt @@ -0,0 +1,2 @@ +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh new file mode 100755 index 00000000..f47079c9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_manual_ctrl/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_manual_ctrl/hdl" \ + "$ref_dir/../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl -o vio_manual_ctrl_simv +} + +# RUN_STEP: +simulate() +{ + ./vio_manual_ctrl_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key vio_manual_ctrl_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_manual_ctrl_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt new file mode 100644 index 00000000..d41dbfc9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f new file mode 100644 index 00000000..f65ce74a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh new file mode 100755 index 00000000..79d07559 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_manual_ctrl \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_manual_ctrl/hdl/verilog" \ + +incdir+"../../../ip/vio_manual_ctrl/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt new file mode 100644 index 00000000..7d15bb3f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:20 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/file_info.txt new file mode 100644 index 00000000..23d1ee0b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh new file mode 100755 index 00000000..ed3f0fdb --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:20 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_manual_ctrl xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim vio_manual_ctrl -key {Behavioral:sim_1:Functional:vio_manual_ctrl} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_manual_ctrl.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vlog.prj new file mode 100644 index 00000000..5036d554 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_manual_ctrl/hdl/verilog" --include "../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt new file mode 100644 index 00000000..efc0100d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rfcontrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rfcontrl.sh' script. + +./vio_rfcontrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rfcontrl.sh -noclean_files + +For more information on the script, please type './vio_rfcontrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/compile.do new file mode 100644 index 00000000..82589cab --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \ +"../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/file_info.txt new file mode 100644 index 00000000..3491ec9e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/simulate.do new file mode 100644 index 00000000..b51c2c6b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_rfcontrl -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rfcontrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_rfcontrl.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh new file mode 100755 index 00000000..54569c04 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rfcontrl.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rfcontrl.sh [-help] +# usage: vio_rfcontrl.sh [-lib_map_path] +# usage: vio_rfcontrl.sh [-noclean_files] +# usage: vio_rfcontrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rfcontrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rfcontrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rfcontrl.sh [-help]\n\ +Usage: vio_rfcontrl.sh [-lib_map_path]\n\ +Usage: vio_rfcontrl.sh [-reset_run]\n\ +Usage: vio_rfcontrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt new file mode 100644 index 00000000..74621eb6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rfcontrl.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rfcontrl.sh' script. + +./vio_rfcontrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rfcontrl.sh -noclean_files + +For more information on the script, please type './vio_rfcontrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/file_info.txt new file mode 100644 index 00000000..3491ec9e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/run.f new file mode 100644 index 00000000..ec351740 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh new file mode 100755 index 00000000..bbcc6280 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rfcontrl.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rfcontrl.sh [-help] +# usage: vio_rfcontrl.sh [-lib_map_path] +# usage: vio_rfcontrl.sh [-noclean_files] +# usage: vio_rfcontrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rfcontrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "vio_rfcontrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_rfcontrl \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_rfcontrl/hdl/verilog" \ + +incdir+"../../../ip/vio_rfcontrl/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rfcontrl.sh [-help]\n\ +Usage: vio_rfcontrl.sh [-lib_map_path]\n\ +Usage: vio_rfcontrl.sh [-reset_run]\n\ +Usage: vio_rfcontrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt new file mode 100644 index 00000000..efc0100d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rfcontrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rfcontrl.sh' script. + +./vio_rfcontrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rfcontrl.sh -noclean_files + +For more information on the script, please type './vio_rfcontrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/compile.do new file mode 100644 index 00000000..67f864c9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \ +"../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/file_info.txt new file mode 100644 index 00000000..84bf655e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/file_info.txt @@ -0,0 +1,2 @@ +vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/simulate.do new file mode 100644 index 00000000..18026337 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_rfcontrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {vio_rfcontrl.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh new file mode 100755 index 00000000..02af7064 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rfcontrl.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rfcontrl.sh [-help] +# usage: vio_rfcontrl.sh [-lib_map_path] +# usage: vio_rfcontrl.sh [-noclean_files] +# usage: vio_rfcontrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rfcontrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rfcontrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rfcontrl.sh [-help]\n\ +Usage: vio_rfcontrl.sh [-lib_map_path]\n\ +Usage: vio_rfcontrl.sh [-reset_run]\n\ +Usage: vio_rfcontrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt new file mode 100644 index 00000000..efc0100d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rfcontrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rfcontrl.sh' script. + +./vio_rfcontrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rfcontrl.sh -noclean_files + +For more information on the script, please type './vio_rfcontrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/compile.do new file mode 100644 index 00000000..1bee908c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \ +"../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/elaborate.do new file mode 100644 index 00000000..8236d42b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_rfcontrl xil_defaultlib.glbl -o vio_rfcontrl_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/file_info.txt new file mode 100644 index 00000000..3491ec9e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/simulate.do new file mode 100644 index 00000000..1ef1ade7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib vio_rfcontrl_opt + +do {wave.do} + +view wave +view structure +view signals + +do {vio_rfcontrl.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh new file mode 100755 index 00000000..33725865 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rfcontrl.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rfcontrl.sh [-help] +# usage: vio_rfcontrl.sh [-lib_map_path] +# usage: vio_rfcontrl.sh [-noclean_files] +# usage: vio_rfcontrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rfcontrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rfcontrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rfcontrl.sh [-help]\n\ +Usage: vio_rfcontrl.sh [-lib_map_path]\n\ +Usage: vio_rfcontrl.sh [-reset_run]\n\ +Usage: vio_rfcontrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt new file mode 100644 index 00000000..efc0100d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rfcontrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rfcontrl.sh' script. + +./vio_rfcontrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rfcontrl.sh -noclean_files + +For more information on the script, please type './vio_rfcontrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/compile.do new file mode 100644 index 00000000..a5b38115 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \ +"../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/file_info.txt new file mode 100644 index 00000000..3491ec9e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/simulate.do new file mode 100644 index 00000000..b51c2c6b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_rfcontrl -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rfcontrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_rfcontrl.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh new file mode 100755 index 00000000..96e81713 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rfcontrl.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rfcontrl.sh [-help] +# usage: vio_rfcontrl.sh [-lib_map_path] +# usage: vio_rfcontrl.sh [-noclean_files] +# usage: vio_rfcontrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rfcontrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rfcontrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rfcontrl.sh [-help]\n\ +Usage: vio_rfcontrl.sh [-lib_map_path]\n\ +Usage: vio_rfcontrl.sh [-reset_run]\n\ +Usage: vio_rfcontrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt new file mode 100644 index 00000000..efc0100d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rfcontrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rfcontrl.sh' script. + +./vio_rfcontrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rfcontrl.sh -noclean_files + +For more information on the script, please type './vio_rfcontrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/file_info.txt new file mode 100644 index 00000000..84bf655e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/file_info.txt @@ -0,0 +1,2 @@ +vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh new file mode 100755 index 00000000..83e65030 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rfcontrl.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rfcontrl.sh [-help] +# usage: vio_rfcontrl.sh [-lib_map_path] +# usage: vio_rfcontrl.sh [-noclean_files] +# usage: vio_rfcontrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rfcontrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "vio_rfcontrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_rfcontrl/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_rfcontrl/hdl" \ + "$ref_dir/../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.vio_rfcontrl xil_defaultlib.glbl -o vio_rfcontrl_simv +} + +# RUN_STEP: +simulate() +{ + ./vio_rfcontrl_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key vio_rfcontrl_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_rfcontrl_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rfcontrl.sh [-help]\n\ +Usage: vio_rfcontrl.sh [-lib_map_path]\n\ +Usage: vio_rfcontrl.sh [-reset_run]\n\ +Usage: vio_rfcontrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt new file mode 100644 index 00000000..74621eb6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rfcontrl.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rfcontrl.sh' script. + +./vio_rfcontrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rfcontrl.sh -noclean_files + +For more information on the script, please type './vio_rfcontrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/file_info.txt new file mode 100644 index 00000000..3491ec9e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/run.f new file mode 100644 index 00000000..a5654bff --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh new file mode 100755 index 00000000..9871883f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rfcontrl.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rfcontrl.sh [-help] +# usage: vio_rfcontrl.sh [-lib_map_path] +# usage: vio_rfcontrl.sh [-noclean_files] +# usage: vio_rfcontrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rfcontrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "vio_rfcontrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_rfcontrl \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_rfcontrl/hdl/verilog" \ + +incdir+"../../../ip/vio_rfcontrl/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rfcontrl.sh [-help]\n\ +Usage: vio_rfcontrl.sh [-lib_map_path]\n\ +Usage: vio_rfcontrl.sh [-reset_run]\n\ +Usage: vio_rfcontrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt new file mode 100644 index 00000000..efc0100d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rfcontrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rfcontrl.sh' script. + +./vio_rfcontrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rfcontrl.sh -noclean_files + +For more information on the script, please type './vio_rfcontrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/file_info.txt new file mode 100644 index 00000000..84bf655e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh new file mode 100755 index 00000000..f55e95a1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rfcontrl.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rfcontrl.sh [-help] +# usage: vio_rfcontrl.sh [-lib_map_path] +# usage: vio_rfcontrl.sh [-noclean_files] +# usage: vio_rfcontrl.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "vio_rfcontrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_rfcontrl xil_defaultlib.vio_rfcontrl xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim vio_rfcontrl -key {Behavioral:sim_1:Functional:vio_rfcontrl} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_rfcontrl.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rfcontrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rfcontrl.sh [-help]\n\ +Usage: vio_rfcontrl.sh [-lib_map_path]\n\ +Usage: vio_rfcontrl.sh [-reset_run]\n\ +Usage: vio_rfcontrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vlog.prj new file mode 100644 index 00000000..7585794f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_rfcontrl/hdl/verilog" --include "../../../ip/vio_rfcontrl/hdl" \ +"../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git 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1 + 1 + 32 + 1 + 1 + 1 + 32 + 1 + AXI4 + 1 + 1 + 32 + false + false + DEFAULT + ila_freq_comp + TRUE + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 10fc4a872243c1fc + 48c58d29 + 273 + IP_Unknown + 9 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp.dcp new file mode 100644 index 00000000..f156c803 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:441ab61c592a36016237caec6090b8ef9c5785893e498944d6e7cb1089e5504c +size 7612273 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_sim_netlist.v new file mode 100755 index 00000000..2a19560d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ade8633c23066bfa2aaadc9c7f46be5069bd0c59cd0b387a2b82f4092e06628d +size 20999680 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_sim_netlist.vhdl new file mode 100755 index 00000000..02e0c3c8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:318ea248f6d1d2c61b552250888c72c6f1e043c6b6f06fa30430615f999d6453 +size 25473200 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_stub.v new file mode 100755 index 00000000..4fa6107b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_stub.v @@ -0,0 +1,47 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Tue May 9 09:27:09 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.v +// Design : ila_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, + probe18, probe19, probe20, probe21, probe22, probe23, probe24) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[0:0],probe16[31:0],probe17[11:0],probe18[11:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[17:0],probe23[17:0],probe24[31:0]" */; + input clk; + input [0:0]probe0; + input [17:0]probe1; + input [17:0]probe2; + input [17:0]probe3; + input [17:0]probe4; + input [17:0]probe5; + input [17:0]probe6; + input [17:0]probe7; + input [17:0]probe8; + input [7:0]probe9; + input [7:0]probe10; + input [7:0]probe11; + input [7:0]probe12; + input [0:0]probe13; + input [2:0]probe14; + input [0:0]probe15; + input [31:0]probe16; + input [11:0]probe17; + input [11:0]probe18; + input [17:0]probe19; + input [17:0]probe20; + input [17:0]probe21; + input [17:0]probe22; + input [17:0]probe23; + input [31:0]probe24; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_stub.vhdl new file mode 100755 index 00000000..7abf58f8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/10fc4a872243c1fc/ila_freq_comp_stub.vhdl @@ -0,0 +1,55 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Tue May 9 09:27:09 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.vhdl +-- Design : ila_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe13 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe14 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + probe15 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe16 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe17 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe18 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe19 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe20 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe21 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe22 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe23 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe24 : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[0:0],probe16[31:0],probe17[11:0],probe18[11:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[17:0],probe23[17:0],probe24[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/123136b9c97973fd.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/123136b9c97973fd.xci new file mode 100644 index 00000000..bcd885c3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/123136b9c97973fd.xci @@ -0,0 +1,3147 @@ + + + xilinx.com + ipcache + 123136b9c97973fd + 0 + + + ila_freq_comp + + + 100000000 + TRUE + 2 + true + 10 + 10 + 200 + 5 + 65536 + FALSE + 3 + FALSE + FALSE + 1 + 0 + 2000000 + 0 + Native + 1 + 22 + 2 + 0 + 18 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 2 + 0 + 1 + 1 + 0 + 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VERILOG + + -2 + + + TRUE + TRUE + 123136b9c97973fd + 48c58d29 + 253 + IP_Unknown + 9 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp.dcp new file mode 100644 index 00000000..d6808182 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3ef767f7a1ef475ea5559f5efac408c6d967ab0460c3133a943ce5b42a7b092e +size 6552278 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_sim_netlist.v new file mode 100755 index 00000000..0bbf8d5a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:51e55505b6c2a2825fb0cc1680dfd02e66cb9fca59abbc1c8c08002327451ecf +size 18108637 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_sim_netlist.vhdl new file mode 100755 index 00000000..d0ed4c2f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5118f2b143e64ae9639c531749e51ccabc2a2212ccae8bbe2f6044f486cb3f83 +size 22099223 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_stub.v new file mode 100755 index 00000000..880c822b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_stub.v @@ -0,0 +1,44 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:19:19 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.v +// Design : ila_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, + probe18, probe19, probe20, probe21) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[17:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[2:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[31:0],probe14[0:0],probe15[31:0],probe16[11:0],probe17[11:0],probe18[9:0],probe19[9:0],probe20[9:0],probe21[9:0]" */; + input clk; + input [17:0]probe0; + input [17:0]probe1; + input [17:0]probe2; + input [17:0]probe3; + input [17:0]probe4; + input [17:0]probe5; + input [17:0]probe6; + input [17:0]probe7; + input [17:0]probe8; + input [2:0]probe9; + input [0:0]probe10; + input [0:0]probe11; + input [0:0]probe12; + input [31:0]probe13; + input [0:0]probe14; + input [31:0]probe15; + input [11:0]probe16; + input [11:0]probe17; + input [9:0]probe18; + input [9:0]probe19; + input [9:0]probe20; + input [9:0]probe21; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_stub.vhdl new file mode 100755 index 00000000..08d5a32c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/123136b9c97973fd/ila_freq_comp_stub.vhdl @@ -0,0 +1,52 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:19:19 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.vhdl +-- Design : ila_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe11 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe12 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe13 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe14 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe15 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe16 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe17 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe18 : in STD_LOGIC_VECTOR ( 9 downto 0 ); + probe19 : in STD_LOGIC_VECTOR ( 9 downto 0 ); + probe20 : in STD_LOGIC_VECTOR ( 9 downto 0 ); + probe21 : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[17:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[2:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[31:0],probe14[0:0],probe15[31:0],probe16[11:0],probe17[11:0],probe18[9:0],probe19[9:0],probe20[9:0],probe21[9:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/24988ad35bfeaaca.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/24988ad35bfeaaca.xci new file mode 100644 index 00000000..1c558d93 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/24988ad35bfeaaca.xci @@ -0,0 +1,58 @@ + + + xilinx.com + ipcache + 24988ad35bfeaaca + 0 + + + mult_18x18 + + + 10000000 + Distributed_Memory + false + mult_18x18 + 129 + 0 + Parallel_Multiplier + Use_LUTs + Speed + 35 + 0 + 5 + Signed + 18 + Signed + 18 + 0 + SCLR_Overrides_CE + false + false + false + false + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 24988ad35bfeaaca + 71506489 + 16 + IP_Unknown + 15 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18.dcp new file mode 100644 index 00000000..73037cd3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b3e8e93f0cf14d759afa136c888570b79197572945cb0e1aeabde8d629a93868 +size 156818 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_sim_netlist.v new file mode 100755 index 00000000..507bb039 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b84ef4a6bccaec9deed378d80a77b80429373650954b3df290b27698356cc1e1 +size 602739 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_sim_netlist.vhdl new file mode 100755 index 00000000..27224e05 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b4b7119849345c166a7df95bd47c61e690e6263c9d07df07fad726f8b5cd02e9 +size 799900 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_stub.v new file mode 100755 index 00000000..61ce6f1e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:25 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_18x18_stub.v +// Design : mult_18x18 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "mult_gen_v12_0_15,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, A, B, P) +/* synthesis syn_black_box black_box_pad_pin="CLK,A[17:0],B[17:0],P[35:0]" */; + input CLK; + input [17:0]A; + input [17:0]B; + output [35:0]P; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_stub.vhdl new file mode 100755 index 00000000..9d7e85d8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/24988ad35bfeaaca/mult_18x18_stub.vhdl @@ -0,0 +1,33 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:25 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_18x18_stub.vhdl +-- Design : mult_18x18 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + CLK : in STD_LOGIC; + A : in STD_LOGIC_VECTOR ( 17 downto 0 ); + B : in STD_LOGIC_VECTOR ( 17 downto 0 ); + P : out STD_LOGIC_VECTOR ( 35 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "CLK,A[17:0],B[17:0],P[35:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "mult_gen_v12_0_15,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/33802de7d605f892.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/33802de7d605f892.xci new file mode 100644 index 00000000..5ca8c4d5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/33802de7d605f892.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 33802de7d605f892 + 0 + + + vio_rfcontrl + + + 100000000 + 0 + 1 + 1 + 18 + 16 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 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1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 4 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 4 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 4 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 4 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 8 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x04 + 8 + vio_rfcontrl + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 33802de7d605f892 + 9a10a187 + 17 + IP_Unknown + 20 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl.dcp new file mode 100644 index 00000000..1ad6fc37 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:04b93fb2241847bc8b42654f441d694ac3e271ce262b98b4a435642765ce4268 +size 190042 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_sim_netlist.v new file mode 100755 index 00000000..98c29078 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e8d1b454d48a015ef3de882a414972cb6a5c239501174cafaba3facb272d2b6d +size 430648 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_sim_netlist.vhdl new file mode 100755 index 00000000..05d2e4e3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ca053c6cabe6058c5642b388edfe4a6327287712bdb603804bccac5e05ddbde1 +size 784490 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_stub.v new file mode 100755 index 00000000..94bb821a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_stub.v @@ -0,0 +1,42 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:25 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.v +// Design : vio_rfcontrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, probe_out16, + probe_out17) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]" */; + input clk; + input [15:0]probe_in0; + output [0:0]probe_out0; + output [0:0]probe_out1; + output [15:0]probe_out2; + output [7:0]probe_out3; + output [3:0]probe_out4; + output [3:0]probe_out5; + output [3:0]probe_out6; + output [3:0]probe_out7; + output [7:0]probe_out8; + output [7:0]probe_out9; + output [15:0]probe_out10; + output [15:0]probe_out11; + output [15:0]probe_out12; + output [0:0]probe_out13; + output [0:0]probe_out14; + output [0:0]probe_out15; + output [0:0]probe_out16; + output [15:0]probe_out17; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_stub.vhdl new file mode 100755 index 00000000..5f238454 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/33802de7d605f892/vio_rfcontrl_stub.vhdl @@ -0,0 +1,49 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:25 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.vhdl +-- Design : vio_rfcontrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/36396be4968f0db7.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/36396be4968f0db7.xci new file mode 100644 index 00000000..6625ba06 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/36396be4968f0db7.xci @@ -0,0 +1,107 @@ + + + xilinx.com + ipcache + 36396be4968f0db7 + 0 + + + fir_prbs7_invert_rep4 + + + 100000000 + 100000000 + 100000000 + false + false + Basic + 48 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + ../coe/prbs7_invert_rep4.coe + 0 + false + 1 + Signed + Inferred + 8 + 100,100,56 + fir_prbs7_invert_rep4 + Not_Required + 1 + Automatic + 0 + Signed + 12 + 1 + false + Systolic_Multiply_Accumulate + 1 + Single_Rate + Coregen + false + false + false + 1 + false + true + Automatic + 4 + 1 + false + Not_Required + Automatic + 1 + 1 + 1 + Area + None + None + Automatic + Full_Precision + 21 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + Automatic + Integer_Coefficients + Frequency_Specification + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 1 + 24 + All + 1.0 + 0.5 + 1 + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 36396be4968f0db7 + 71c522b0 + 59 + IP_Unknown + 12 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4.dcp new file mode 100644 index 00000000..6d4c66db --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:20d727eb478eddce19b4901aa56b974ff622653a4ee812c46c5f6ddd266617db +size 5490471 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_sim_netlist.v new file mode 100755 index 00000000..00250d91 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fb4ff3d30cb86a8672330ba382e396c7c99533f3fa850c483b71e22049fd1180 +size 11749350 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_sim_netlist.vhdl new file mode 100755 index 00000000..48df4881 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c77efa11865cb0e05d4e7a3bb0199679787e846a0d6c51bb7561e3bf2ae3389d +size 17177388 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_stub.v new file mode 100755 index 00000000..30a3e226 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:27:44 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep4_stub.v +// Design : fir_prbs7_invert_rep4 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aresetn, aclk, s_axis_data_tvalid, + s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) +/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */; + input aresetn; + input aclk; + input s_axis_data_tvalid; + output s_axis_data_tready; + input [15:0]s_axis_data_tdata; + output m_axis_data_tvalid; + output [23:0]m_axis_data_tdata; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_stub.vhdl new file mode 100755 index 00000000..3a758afd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/36396be4968f0db7/fir_prbs7_invert_rep4_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:27:44 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep4_stub.vhdl +-- Design : fir_prbs7_invert_rep4 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + aresetn : in STD_LOGIC; + aclk : in STD_LOGIC; + s_axis_data_tvalid : in STD_LOGIC; + s_axis_data_tready : out STD_LOGIC; + s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_data_tvalid : out STD_LOGIC; + m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/67605bdfd8643f76.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/67605bdfd8643f76.xci new file mode 100644 index 00000000..20cb4cd8 --- /dev/null +++ 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b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/ila_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1eccf5f317e07d7f89ad1413a3a86efb269958bc2785151fabe125e3ecf931e8 +size 19583943 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/ila_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/ila_freq_comp_sim_netlist.vhdl new file mode 100755 index 00000000..29cdc308 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/ila_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6d897a0853ec51ec638106db2ab18c2a140e35c490f65104585d100a25a2b59e +size 23891325 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/ila_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/ila_freq_comp_stub.v new file mode 100755 index 00000000..688128f9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/ila_freq_comp_stub.v @@ -0,0 +1,46 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Tue May 9 00:36:48 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.v +// Design : ila_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, + probe18, probe19, probe20, probe21, probe22, probe23) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[0:0],probe16[31:0],probe17[11:0],probe18[11:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[17:0],probe23[17:0]" */; + input clk; + input [0:0]probe0; + input [17:0]probe1; + input [17:0]probe2; + input [17:0]probe3; + input [17:0]probe4; + input [17:0]probe5; + input [17:0]probe6; + input [17:0]probe7; + input [17:0]probe8; + input [7:0]probe9; + input [7:0]probe10; + input [7:0]probe11; + input [7:0]probe12; + input [0:0]probe13; + input [2:0]probe14; + input [0:0]probe15; + input [31:0]probe16; + input [11:0]probe17; + input [11:0]probe18; + input [17:0]probe19; + input [17:0]probe20; + input [17:0]probe21; + input [17:0]probe22; + input [17:0]probe23; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/ila_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/ila_freq_comp_stub.vhdl new file mode 100755 index 00000000..30e9cd78 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67605bdfd8643f76/ila_freq_comp_stub.vhdl @@ -0,0 +1,54 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Tue May 9 00:36:48 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.vhdl +-- Design : ila_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe13 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe14 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + probe15 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe16 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe17 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe18 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe19 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe20 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe21 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe22 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe23 : in STD_LOGIC_VECTOR ( 17 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[0:0],probe16[31:0],probe17[11:0],probe18[11:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[17:0],probe23[17:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/803b8df098fcb9e4.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/803b8df098fcb9e4.xci new file mode 100644 index 00000000..538dd43c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/803b8df098fcb9e4.xci @@ -0,0 +1,107 @@ + + + xilinx.com + ipcache + 803b8df098fcb9e4 + 0 + + + fir_prbs7_invert_rep2 + + + 100000000 + 100000000 + 100000000 + false + false + Basic + 48 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + ../coe/prbs7_invert_rep2.coe + 0 + false + 1 + Signed + Inferred + 8 + 64 + fir_prbs7_invert_rep2 + Not_Required + 1 + Automatic + 0 + Signed + 12 + 1 + false + Systolic_Multiply_Accumulate + 1 + Single_Rate + Coregen + false + false + false + 1 + false + true + Automatic + 4 + 1 + false + Not_Required + Automatic + 1 + 1 + 1 + Area + None + None + Automatic + Full_Precision + 20 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + Automatic + Integer_Coefficients + Frequency_Specification + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 1 + 12 + All + 1.0 + 0.5 + 1 + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 803b8df098fcb9e4 + 71c522b0 + 26 + IP_Unknown + 12 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2.dcp new file mode 100644 index 00000000..fbccdf66 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:42c3b5cfdf1f9cdbb19f56f0e27a4d5df8ed3f76107662b3715490fa1497a226 +size 1384325 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_sim_netlist.v new file mode 100755 index 00000000..e5e5f378 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dcf1cac76f7da1408ca5fdc925efda4cb9c2e3a209c9640eb59ca1b82cf9e13a +size 3121707 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_sim_netlist.vhdl new file mode 100755 index 00000000..f785c939 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f32f5fa02979ee4dee815b5d03a97a792d926a5b60153d908e6d47559befd411 +size 4487981 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_stub.v new file mode 100755 index 00000000..ba01ca54 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 19:43:15 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep2_stub.v +// Design : fir_prbs7_invert_rep2 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aresetn, aclk, s_axis_data_tvalid, + s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) +/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */; + input aresetn; + input aclk; + input s_axis_data_tvalid; + output s_axis_data_tready; + input [15:0]s_axis_data_tdata; + output m_axis_data_tvalid; + output [23:0]m_axis_data_tdata; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_stub.vhdl new file mode 100755 index 00000000..f91e1cff --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/fir_prbs7_invert_rep2_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 19:43:15 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep2_stub.vhdl +-- Design : fir_prbs7_invert_rep2 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + aresetn : in STD_LOGIC; + aclk : in STD_LOGIC; + s_axis_data_tvalid : in STD_LOGIC; + s_axis_data_tready : out STD_LOGIC; + s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_data_tvalid : out STD_LOGIC; + m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/8670630cc237b23c.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/8670630cc237b23c.xci new file mode 100644 index 00000000..a01843d8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/8670630cc237b23c.xci @@ -0,0 +1,109 @@ + + + xilinx.com + ipcache + 8670630cc237b23c + 0 + + + rom_freq_word + + + 100000000 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../coe/freq_word.coe + ALL + rom_freq_word + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 16 + 16 + false + true + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 81 + 16 + 16 + No_ECC + false + false + false + Stand_Alone + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 8670630cc237b23c + 0137cb81 + 41 + IP_Unknown + 3 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word.dcp new file mode 100644 index 00000000..e12a472f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0cc806799ac44d08003c5294be44f164ca4b2fd80bb0c989de1b19bf61c7f959 +size 26958 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_sim_netlist.v new file mode 100755 index 00000000..0c73eaa6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:15d347059d571a393ec89b2e6da7976ffe1dc739ea82fc82733779aa0e6659c6 +size 28744 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_sim_netlist.vhdl new file mode 100755 index 00000000..96755855 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:53bd82c6ab43cd0b1dd7c622fb3225175bc895be7c7de5ce56d8b49013ec63d3 +size 44322 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_stub.v new file mode 100755 index 00000000..20838a23 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 17:28:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[15:0]" */; + input clka; + input [6:0]addra; + output [15:0]douta; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_stub.vhdl new file mode 100755 index 00000000..61ad8849 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8670630cc237b23c/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 17:28:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/8b290c62e468fc28.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/8b290c62e468fc28.xci new file mode 100644 index 00000000..5f3d29d0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/8b290c62e468fc28.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 8b290c62e468fc28 + 0 + + + vio_manual_ctrl + + + 100000000 + 0 + 1 + 0 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b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl.dcp new file mode 100644 index 00000000..3b2fc5f9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5ea43da3b05d5ba5df2ab9d68fef018896e39490725a55849e41f30b44019d53 +size 144292 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_sim_netlist.v new file mode 100755 index 00000000..245ce439 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:97f3d003b42e39fdb138e2c6cde931cce00957d305470f8215884ba1ad09f265 +size 352686 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_sim_netlist.vhdl new file mode 100755 index 00000000..0157a98a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:a81e3efccbc9a326eb08833f577e88569d588f48c3844f44404bf10852f2decc +size 668891 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_stub.v new file mode 100755 index 00000000..4acce2f5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:25 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.v +// Design : vio_manual_ctrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; + input clk; + output [1:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_stub.vhdl new file mode 100755 index 00000000..cdaeb750 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8b290c62e468fc28/vio_manual_ctrl_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:25 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.vhdl +-- Design : vio_manual_ctrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/93753bc8666fbd09.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/93753bc8666fbd09.xci new file mode 100644 index 00000000..c16c3248 --- /dev/null +++ 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2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp.dcp new file mode 100644 index 00000000..e7cd3946 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d0eb78f6510b32512acc00c6fb6e1011848bce3828aec6d1b3ba10ca45ceebfd +size 142584 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_sim_netlist.v new file mode 100755 index 00000000..3c22eea4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2ab8363edc311625627149d201037991ce9909d2234cd56db697a57fcd8aff84 +size 348018 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_sim_netlist.vhdl new file mode 100755 index 00000000..d2ff9a5e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6ff82ef629509a4c4cf04a0411ec622ba7dafec68ce8390c7f6e608f5a665346 +size 663544 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_stub.v new file mode 100755 index 00000000..3b00cde9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:24 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_freq_comp_stub.v +// Design : vio_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]" */; + input clk; + input [0:0]probe_in0; + output [0:0]probe_out0; + output [7:0]probe_out1; + output [0:0]probe_out2; + output [31:0]probe_out3; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_stub.vhdl new file mode 100755 index 00000000..2f09f761 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/93753bc8666fbd09/vio_freq_comp_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:24 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_freq_comp_stub.vhdl +-- Design : vio_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/b5da8ddc90a65331.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/b5da8ddc90a65331.xci new file mode 100644 index 00000000..3da0d53a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/b5da8ddc90a65331.xci @@ -0,0 +1,62 @@ + + + xilinx.com + ipcache + b5da8ddc90a65331 + 0 + + + cmpy_12x8 + + + 10000000 + 100000000 + 100000000 + 100000000 + false + 12 + false + 1 + 8 + 1 + 1 + cmpy_12x8 + NonBlocking + false + false + false + false + false + false + Automatic + 4 + Use_LUTs + Performance + Null + 21 + Truncate + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + b5da8ddc90a65331 + c296bec2 + 18 + IP_Unknown + 17 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8.dcp new file mode 100644 index 00000000..68f3d1f6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3171bc0d090e9450de310f5eafd6fd7b1bec930ca32bbfeed93d6e4634bbe830 +size 179962 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_sim_netlist.v new file mode 100755 index 00000000..089b99f3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d166a84be5f60fca5e0b3355a84e269acb28ef202d7e5d8b27306272c1f69ceb +size 525006 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_sim_netlist.vhdl new file mode 100755 index 00000000..ee8546c5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:12c77fb1ac3351598bca509a7cc969f4ad13514d3e659336283b5cd7ccf0c29b +size 747784 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_stub.v new file mode 100755 index 00000000..a1bfbb6f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:26 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_12x8_stub.v +// Design : cmpy_12x8 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_a_tvalid, s_axis_a_tdata, + s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata) +/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[47:0]" */; + input aclk; + input s_axis_a_tvalid; + input [31:0]s_axis_a_tdata; + input s_axis_b_tvalid; + input [15:0]s_axis_b_tdata; + output m_axis_dout_tvalid; + output [47:0]m_axis_dout_tdata; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_stub.vhdl new file mode 100755 index 00000000..dfefbbc4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5da8ddc90a65331/cmpy_12x8_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:26 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_12x8_stub.vhdl +-- Design : cmpy_12x8 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + aclk : in STD_LOGIC; + s_axis_a_tvalid : in STD_LOGIC; + s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axis_b_tvalid : in STD_LOGIC; + s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_dout_tvalid : out STD_LOGIC; + m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 47 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[47:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/c85b6423cc6198b8.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/c85b6423cc6198b8.xci new file mode 100644 index 00000000..32a891c2 --- /dev/null +++ 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a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp.dcp new file mode 100644 index 00000000..f598a389 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d921065fe44feecd8879ed5b0398a7093b2a6151c9ca3c9877a40692983f38bf +size 7241894 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_sim_netlist.v new file mode 100755 index 00000000..f1704cff --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6ba131a4e982b1b6c2b5878314354fb7b4f4ab732bacc41a581ea99f0254e046 +size 20061898 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_sim_netlist.vhdl new file mode 100755 index 00000000..69b5d91d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:46326650c5ab8b031f0deda926d69a4f4eb6ace2f04e07d0886655b484239e50 +size 24419862 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_stub.v new file mode 100755 index 00000000..c889f71a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_stub.v @@ -0,0 +1,46 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Tue May 9 13:39:35 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.v +// Design : ila_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, + probe18, probe19, probe20, probe21, probe22, probe23) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[31:0],probe23[11:0]" */; + input clk; + input [0:0]probe0; + input [17:0]probe1; + input [17:0]probe2; + input [17:0]probe3; + input [17:0]probe4; + input [17:0]probe5; + input [17:0]probe6; + input [17:0]probe7; + input [17:0]probe8; + input [7:0]probe9; + input [7:0]probe10; + input [7:0]probe11; + input [7:0]probe12; + input [0:0]probe13; + input [2:0]probe14; + input [11:0]probe15; + input [11:0]probe16; + input [17:0]probe17; + input [17:0]probe18; + input [17:0]probe19; + input [17:0]probe20; + input [17:0]probe21; + input [31:0]probe22; + input [11:0]probe23; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_stub.vhdl new file mode 100755 index 00000000..c3e90ba1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c85b6423cc6198b8/ila_freq_comp_stub.vhdl @@ -0,0 +1,54 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Tue May 9 13:39:35 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.vhdl +-- Design : ila_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe13 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe14 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + probe15 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe16 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe17 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe18 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe19 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe20 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe21 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe22 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe23 : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[31:0],probe23[11:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/c986e771edb05f56.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/c986e771edb05f56.xci new file mode 100644 index 00000000..89d6fd19 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/c986e771edb05f56.xci @@ -0,0 +1,109 @@ + + + xilinx.com + ipcache + c986e771edb05f56 + 0 + + + rom_freq_word + + + 100000000 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../coe/freq_word.coe + ALL + rom_freq_word + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 16 + 16 + false + true + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 81 + 16 + 16 + No_ECC + false + false + false + Stand_Alone + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + c986e771edb05f56 + 0137cb81 + 45 + IP_Unknown + 3 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word.dcp new file mode 100644 index 00000000..377592ef --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:a9c57f8553a8bc82ecbc8c0ca4fb7824ec6b2190ee2e4a5277e52c07988e2241 +size 26874 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_sim_netlist.v new file mode 100755 index 00000000..c87440e5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ec16568d923e47b1b6a32e286e8e0cf3d41f26310e6e7ab0b1a7591a6d7a0446 +size 28744 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_sim_netlist.vhdl new file mode 100755 index 00000000..e6be01c0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f177bdbff7c7350c6b28d14d33de21dba3c920a2cabd74143f9b912e0b02af9b +size 44322 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_stub.v new file mode 100755 index 00000000..ee240ae2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:55 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[15:0]" */; + input clka; + input [6:0]addra; + output [15:0]douta; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_stub.vhdl new file mode 100755 index 00000000..c1bcfb82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c986e771edb05f56/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:55 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/dd1a5058a7007eb5.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/dd1a5058a7007eb5.xci new file mode 100644 index 00000000..6a278c86 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/dd1a5058a7007eb5.xci @@ -0,0 +1,107 @@ + + + xilinx.com + ipcache + dd1a5058a7007eb5 + 0 + + + fir_prbs7_invert_rep4 + + + 100000000 + 100000000 + 100000000 + false + false + Basic + 48 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + ../coe/prbs7_invert_rep4.coe + 0 + false + 1 + Signed + Inferred + 8 + 100,100,56 + fir_prbs7_invert_rep4 + Not_Required + 1 + Automatic + 0 + Signed + 12 + 1 + false + Systolic_Multiply_Accumulate + 1 + Single_Rate + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + 1 + 1 + 1 + Area + None + None + Automatic + Full_Precision + 21 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + Automatic + Integer_Coefficients + Frequency_Specification + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 1 + 24 + All + 1.0 + 0.5 + 1 + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + dd1a5058a7007eb5 + 71c522b0 + 62 + IP_Unknown + 12 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4.dcp new file mode 100644 index 00000000..24bec09f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6bff978ad487b97fdc73e8e1a7619a34cb1555eb5831e0a31bd0f6081a270183 +size 4585199 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_sim_netlist.v new file mode 100755 index 00000000..88919aa6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:42cb3db0d2aab24db994a3c05e33af9c149855d48724b963a98c767cac468a0a +size 7960367 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_sim_netlist.vhdl new file mode 100755 index 00000000..7a8cc082 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:687920eed62d2b20d6b45e9aa782d0c161f9779771614e7d262b566f21c9efd2 +size 11292226 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_stub.v new file mode 100755 index 00000000..7c7c4e78 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:16:09 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep4_stub.v +// Design : fir_prbs7_invert_rep4 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_data_tvalid, s_axis_data_tready, + s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) +/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */; + input aclk; + input s_axis_data_tvalid; + output s_axis_data_tready; + input [15:0]s_axis_data_tdata; + output m_axis_data_tvalid; + output [23:0]m_axis_data_tdata; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_stub.vhdl new file mode 100755 index 00000000..8d817e9f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dd1a5058a7007eb5/fir_prbs7_invert_rep4_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:16:09 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep4_stub.vhdl +-- Design : fir_prbs7_invert_rep4 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + aclk : in STD_LOGIC; + s_axis_data_tvalid : in STD_LOGIC; + s_axis_data_tready : out STD_LOGIC; + s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_data_tvalid : out STD_LOGIC; + m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf new file mode 100644 index 00000000..f4ff7423 --- /dev/null +++ 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b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -0,0 +1,79 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr new file mode 100644 index 00000000..29d8123e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml new file mode 100644 index 00000000..90235529 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml new file mode 100644 index 00000000..9c69477b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml new file mode 100644 index 00000000..7c72c4dc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml new file mode 100644 index 00000000..16c40488 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_5.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_5.xml new file mode 100644 index 00000000..f8c12230 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_6.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_6.xml new file mode 100644 index 00000000..f8c12230 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_7.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_7.xml new file mode 100644 index 00000000..f8c12230 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..17dbbef0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/ISEWrap.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/ISEWrap.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.dcp new file mode 100644 index 00000000..9c7b64ad --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4045b360a861fa27997464c274ee6f2b8a1ed504923a1faaec9fbceaf8a9cbe4 +size 180024 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.tcl new file mode 100644 index 00000000..0b802de4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.tcl @@ -0,0 +1,156 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1 -new_name cmpy_12x8 -ip [get_ips cmpy_12x8]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top cmpy_12x8 -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix cmpy_12x8_ cmpy_12x8.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_12x8_stub.v + lappend ipCachedFiles cmpy_12x8_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_12x8_stub.vhdl + lappend ipCachedFiles cmpy_12x8_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_12x8_sim_netlist.v + lappend ipCachedFiles cmpy_12x8_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_12x8_sim_netlist.vhdl + lappend ipCachedFiles cmpy_12x8_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp cmpy_12x8.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips cmpy_12x8] +} + +rename_ref -prefix_all cmpy_12x8_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef cmpy_12x8.dcp +create_report "cmpy_12x8_synth_1_synth_report_utilization_0" "report_utilization -file cmpy_12x8_utilization_synth.rpt -pb cmpy_12x8_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/cmpy_12x8]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/cmpy_12x8 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/cmpy_12x8]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/cmpy_12x8 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/cmpy_12x8]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/cmpy_12x8 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/cmpy_12x8]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/cmpy_12x8 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.vds new file mode 100644 index 00000000..a0bc3b2d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.vds @@ -0,0 +1,384 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Mon May 8 13:15:05 2023 +# Process ID: 2006882 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1 +# Command line: vivado -log cmpy_12x8.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_12x8.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/vivado.jou +#----------------------------------------------------------- +source cmpy_12x8.tcl -notrace +Command: synth_design -top cmpy_12x8 -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2007150 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1853.570 ; gain = 148.688 ; free physical = 823 ; free virtual = 39532 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'cmpy_12x8' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/synth/cmpy_12x8.vhd:71] + Parameter C_VERBOSITY bound to: 0 - type: integer + Parameter C_XDEVICEFAMILY bound to: zynq - type: string + Parameter C_XDEVICE bound to: xc7z100 - type: string + Parameter C_A_WIDTH bound to: 12 - type: integer + Parameter C_B_WIDTH bound to: 8 - type: integer + Parameter C_OUT_WIDTH bound to: 21 - type: integer + Parameter C_LATENCY bound to: 4 - type: integer + Parameter C_MULT_TYPE bound to: 0 - type: integer + Parameter C_OPTIMIZE_GOAL bound to: 0 - type: integer + Parameter HAS_NEGATE bound to: 0 - type: integer + Parameter SINGLE_OUTPUT bound to: 0 - type: integer + Parameter ROUND bound to: 0 - type: integer + Parameter USE_DSP_CASCADES bound to: 1 - type: integer + Parameter C_THROTTLE_SCHEME bound to: 3 - type: integer + Parameter C_HAS_ACLKEN bound to: 0 - type: integer + Parameter C_HAS_ARESETN bound to: 0 - type: integer + Parameter C_HAS_S_AXIS_A_TUSER bound to: 0 - type: integer + Parameter C_HAS_S_AXIS_A_TLAST bound to: 0 - type: integer + Parameter C_HAS_S_AXIS_B_TUSER bound to: 0 - type: integer + Parameter C_HAS_S_AXIS_B_TLAST bound to: 0 - type: integer + Parameter C_HAS_S_AXIS_CTRL_TUSER bound to: 0 - type: integer + Parameter C_HAS_S_AXIS_CTRL_TLAST bound to: 0 - type: integer + Parameter C_TLAST_RESOLUTION bound to: 0 - type: integer + Parameter C_S_AXIS_A_TDATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXIS_A_TUSER_WIDTH bound to: 1 - type: integer + Parameter C_S_AXIS_B_TDATA_WIDTH bound to: 16 - type: integer + Parameter C_S_AXIS_B_TUSER_WIDTH bound to: 1 - type: integer + Parameter C_S_AXIS_CTRL_TDATA_WIDTH bound to: 8 - type: integer + Parameter C_S_AXIS_CTRL_TUSER_WIDTH bound to: 1 - type: integer + Parameter C_M_AXIS_DOUT_TDATA_WIDTH bound to: 48 - type: integer + Parameter C_M_AXIS_DOUT_TUSER_WIDTH bound to: 1 - type: integer +INFO: [Synth 8-3491] module 'cmpy_v6_0_17' declared at '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/hdl/cmpy_v6_0_vh_rfs.vhd:13922' bound to instance 'U0' of component 'cmpy_v6_0_17' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/synth/cmpy_12x8.vhd:155] +INFO: [Synth 8-256] done synthesizing module 'cmpy_12x8' (10#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/synth/cmpy_12x8.vhd:71] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port CLK +WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port CE +WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port SCLR +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv__parameterized0 has unconnected port CE +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv__parameterized0 has unconnected port SCLR +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port CE +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port SCLR +WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port CLK +WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port CE +WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port SCLR +WARNING: [Synth 8-3331] design input_negation has unconnected port NEGATE_R +WARNING: [Synth 8-3331] design input_negation has unconnected port NEGATE_I +WARNING: [Synth 8-3331] design input_negation has unconnected port CLK +WARNING: [Synth 8-3331] design input_negation has unconnected port CE +WARNING: [Synth 8-3331] design input_negation has unconnected port SCLR +WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port CE +WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port SCLR +WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port ROUND_CY +WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port SO_START +WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line has unconnected port SCLR +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aclken +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aresetn +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tuser[0] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tlast +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[31] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[30] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[29] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[28] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[15] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[14] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[13] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[12] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tuser[0] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tlast +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tvalid +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tuser[0] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tlast +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[7] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[6] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[5] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[4] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[3] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[2] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[1] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[0] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port m_axis_dout_tready +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1972.289 ; gain = 267.406 ; free physical = 1054 ; free virtual = 39301 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1972.289 ; gain = 267.406 ; free physical = 1095 ; free virtual = 39342 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1972.289 ; gain = 267.406 ; free physical = 1095 ; free virtual = 39342 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 492 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2140.070 ; gain = 0.000 ; free physical = 1024 ; free virtual = 39279 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 160 instances were transformed. + MULT_AND => LUT2: 160 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2140.070 ; gain = 0.000 ; free physical = 1015 ; free virtual = 39278 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 939 ; free virtual = 39016 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 939 ; free virtual = 39016 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 938 ; free virtual = 39015 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 938 ; free virtual = 38987 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv__parameterized0 has unconnected port CE +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv__parameterized0 has unconnected port SCLR +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port CE +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port SCLR +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aclken +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aresetn +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tuser[0] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tlast +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[31] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[30] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[29] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[28] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[15] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[14] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[13] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[12] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tuser[0] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tlast +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tvalid +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tuser[0] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tlast +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[7] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[6] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[5] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[4] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[3] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[2] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[1] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[0] +WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port m_axis_dout_tready +INFO: [Synth 8-3886] merging instance 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][14]' (FDR) to 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][13]' +INFO: [Synth 8-3886] merging instance 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][15]' (FDR) to 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][13]' +INFO: [Synth 8-3886] merging instance 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][16]' (FDR) to 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][13]' +INFO: [Synth 8-3886] merging instance 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[0][15]' (FDR) to 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[0][16]' +INFO: [Synth 8-3886] merging instance 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[1][15]' (FDR) to 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[1][16]' +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 934 ; free virtual = 38913 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 1840 ; free virtual = 39435 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 1865 ; free virtual = 39459 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 1917 ; free virtual = 39511 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 1932 ; free virtual = 39529 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 1931 ; free virtual = 39528 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 1932 ; free virtual = 39529 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 1931 ; free virtual = 39528 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 1929 ; free virtual = 39526 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 1926 ; free virtual = 39523 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |CARRY4 | 69| +|2 |LUT1 | 11| +|3 |LUT2 | 225| +|4 |LUT3 | 50| +|5 |LUT4 | 136| +|6 |MULT_AND | 157| +|7 |MUXCY | 160| +|8 |SRL16E | 1| +|9 |XORCY | 172| +|10 |FDRE | 322| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 1925 ; free virtual = 39522 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 30 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2140.070 ; gain = 267.406 ; free physical = 2012 ; free virtual = 39607 +Synthesis Optimization Complete : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2140.070 ; gain = 435.188 ; free physical = 2018 ; free virtual = 39613 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 558 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2140.070 ; gain = 0.000 ; free physical = 3481 ; free virtual = 41077 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 205 instances were transformed. + (MUXCY,XORCY) => CARRY4: 48 instances + MULT_AND => LUT2: 157 instances + +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 76 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2140.070 ; gain = 748.027 ; free physical = 3598 ; free virtual = 41191 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2140.070 ; gain = 0.000 ; free physical = 3594 ; free virtual = 41188 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP cmpy_12x8, cache-ID = b5da8ddc90a65331 +INFO: [Coretcl 2-1174] Renamed 11 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2140.070 ; gain = 0.000 ; free physical = 4387 ; free virtual = 41982 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file cmpy_12x8_utilization_synth.rpt -pb cmpy_12x8_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon May 8 13:15:27 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.v new file mode 100644 index 00000000..cdad7ae7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3e99971165427fa7fe69165ac62c7e4dabc22e68d854eb6be28b79d2f8921f49 +size 524462 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.vhdl new file mode 100644 index 00000000..931952b0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e9e76ad8b28621a962c7bb697d9c71f906708a563996a06df63bf35d98a4dfaf +size 741220 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.v new file mode 100644 index 00000000..548c7ed6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:27 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.v +// Design : cmpy_12x8 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *) +module cmpy_12x8(aclk, s_axis_a_tvalid, s_axis_a_tdata, + s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata) +/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[47:0]" */; + input aclk; + input s_axis_a_tvalid; + input [31:0]s_axis_a_tdata; + input s_axis_b_tvalid; + input [15:0]s_axis_b_tdata; + output m_axis_dout_tvalid; + output [47:0]m_axis_dout_tdata; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.vhdl new file mode 100644 index 00000000..39482542 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:27 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.vhdl +-- Design : cmpy_12x8 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity cmpy_12x8 is + Port ( + aclk : in STD_LOGIC; + s_axis_a_tvalid : in STD_LOGIC; + s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axis_b_tvalid : in STD_LOGIC; + s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_dout_tvalid : out STD_LOGIC; + m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 47 downto 0 ) + ); + +end cmpy_12x8; + +architecture stub of cmpy_12x8 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[47:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_utilization_synth.pb new file mode 100644 index 00000000..77085df3 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_utilization_synth.rpt new file mode 100644 index 00000000..59aa2772 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_utilization_synth.rpt @@ -0,0 +1,182 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Mon May 8 13:15:27 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file cmpy_12x8_utilization_synth.rpt -pb cmpy_12x8_utilization_synth.pb +| Design : cmpy_12x8 +| Device : 7z100ffg900-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 409 | 0 | 277400 | 0.15 | +| LUT as Logic | 408 | 0 | 277400 | 0.15 | +| LUT as Memory | 1 | 0 | 108200 | <0.01 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 1 | 0 | | | +| Slice Registers | 322 | 0 | 554800 | 0.06 | +| Register as Flip Flop | 322 | 0 | 554800 | 0.06 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 322 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT2 | 382 | LUT | +| FDRE | 322 | Flop & Latch | +| LUT4 | 136 | LUT | +| CARRY4 | 117 | CarryLogic | +| LUT3 | 50 | LUT | +| LUT1 | 11 | LUT | +| SRL16E | 1 | Distributed Memory | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/dont_touch.xdc b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/dont_touch.xdc new file mode 100644 index 00000000..ad4f31cf --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/dont_touch.xdc @@ -0,0 +1,16 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8.xci +# IP: The module: 'cmpy_12x8' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'cmpy_12x8'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8.xci +# IP: The module: 'cmpy_12x8' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/cmpy_12x8/cmpy_12x8_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'cmpy_12x8'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/gen_run.xml new file mode 100644 index 00000000..b9861298 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/htr.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/htr.txt new file mode 100644 index 00000000..5c9cd9de --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log cmpy_12x8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_12x8.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/project.wdf new file mode 100644 index 00000000..c1ef2fc1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/project.wdf @@ -0,0 +1,41 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3130:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 +eof:3099610940 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/rundef.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/rundef.js new file mode 100644 index 00000000..79ebd8f7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log cmpy_12x8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_12x8.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/runme.bat b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/runme.sh new file mode 100755 index 00000000..ca6326b4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log cmpy_12x8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_12x8.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/vivado.pb new file mode 100644 index 00000000..e299c288 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..5ead3798 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/ISEWrap.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/ISEWrap.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc new file mode 100644 index 00000000..e1729df2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc @@ -0,0 +1,24 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci +# IP: The module: 'fir_prbs7_invert_rep2' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/constraints/fir_compiler_v7_2.xdc +# XDC: The top module name and the constraint reference have the same name: 'fir_prbs7_invert_rep2'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'fir_prbs7_invert_rep2'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci +# IP: The module: 'fir_prbs7_invert_rep2' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/constraints/fir_compiler_v7_2.xdc +# XDC: The top module name and the constraint reference have the same name: 'fir_prbs7_invert_rep2'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'fir_prbs7_invert_rep2'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp new file mode 100644 index 00000000..49759195 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9a726f8146fa94c962f939f929f726098df42cf331d3c8797ae07fba83eccc5e +size 1390882 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.tcl new file mode 100644 index 00000000..1d47e291 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.tcl @@ -0,0 +1,157 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/constraints/fir_compiler_v7_2.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1 -new_name fir_prbs7_invert_rep2 -ip [get_ips fir_prbs7_invert_rep2]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top fir_prbs7_invert_rep2 -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix fir_prbs7_invert_rep2_ fir_prbs7_invert_rep2.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep2_stub.v + lappend ipCachedFiles fir_prbs7_invert_rep2_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep2_stub.vhdl + lappend ipCachedFiles fir_prbs7_invert_rep2_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep2_sim_netlist.v + lappend ipCachedFiles fir_prbs7_invert_rep2_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep2_sim_netlist.vhdl + lappend ipCachedFiles fir_prbs7_invert_rep2_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp fir_prbs7_invert_rep2.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips fir_prbs7_invert_rep2] +} + +rename_ref -prefix_all fir_prbs7_invert_rep2_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef fir_prbs7_invert_rep2.dcp +create_report "fir_prbs7_invert_rep2_synth_1_synth_report_utilization_0" "report_utilization -file fir_prbs7_invert_rep2_utilization_synth.rpt -pb fir_prbs7_invert_rep2_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.vds new file mode 100644 index 00000000..993ad85a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.vds @@ -0,0 +1,746 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Mon May 8 19:42:47 2023 +# Process ID: 2699758 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1 +# Command line: vivado -log fir_prbs7_invert_rep2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs7_invert_rep2.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/vivado.jou +#----------------------------------------------------------- +source fir_prbs7_invert_rep2.tcl -notrace +Command: synth_design -top fir_prbs7_invert_rep2 -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2699833 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1855.598 ; gain = 152.719 ; free physical = 780 ; free virtual = 47398 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'fir_prbs7_invert_rep2' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/synth/fir_prbs7_invert_rep2.vhd:71] + Parameter C_XDEVICEFAMILY bound to: zynq - type: string + Parameter C_ELABORATION_DIR bound to: ./ - type: string + Parameter C_COMPONENT_NAME bound to: fir_prbs7_invert_rep2 - type: string + Parameter C_COEF_FILE bound to: fir_prbs7_invert_rep2.mif - type: string + Parameter C_COEF_FILE_LINES bound to: 256 - type: integer + Parameter C_FILTER_TYPE bound to: 0 - type: integer + Parameter C_INTERP_RATE bound to: 1 - type: integer + Parameter C_DECIM_RATE bound to: 1 - type: integer + Parameter C_ZERO_PACKING_FACTOR bound to: 1 - type: integer + Parameter C_SYMMETRY bound to: 0 - type: integer + Parameter C_NUM_FILTS bound to: 1 - type: integer + Parameter C_NUM_TAPS bound to: 256 - type: integer + Parameter C_NUM_CHANNELS bound to: 1 - type: integer + Parameter C_CHANNEL_PATTERN bound to: fixed - type: string + Parameter C_ROUND_MODE bound to: 0 - type: integer + Parameter C_COEF_RELOAD bound to: 0 - type: integer + Parameter C_NUM_RELOAD_SLOTS bound to: 1 - type: integer + Parameter C_COL_MODE bound to: 1 - type: integer + Parameter C_COL_PIPE_LEN bound to: 4 - type: integer + Parameter C_COL_CONFIG bound to: 64 - type: string + Parameter C_OPTIMIZATION bound to: 0 - type: integer + Parameter C_DATA_PATH_WIDTHS bound to: 12 - type: string + Parameter C_DATA_IP_PATH_WIDTHS bound to: 12 - type: string + Parameter C_DATA_PX_PATH_WIDTHS bound to: 12 - type: string + Parameter C_DATA_WIDTH bound to: 12 - type: integer + Parameter C_COEF_PATH_WIDTHS bound to: 8 - type: string + Parameter C_COEF_WIDTH bound to: 8 - type: integer + Parameter C_DATA_PATH_SRC bound to: 0 - type: string + Parameter C_COEF_PATH_SRC bound to: 0 - type: string + Parameter C_PX_PATH_SRC bound to: 0 - type: string + Parameter C_DATA_PATH_SIGN bound to: 0 - type: string + Parameter C_COEF_PATH_SIGN bound to: 0 - type: string + Parameter C_ACCUM_PATH_WIDTHS bound to: 20 - type: string + Parameter C_OUTPUT_WIDTH bound to: 20 - type: integer + Parameter C_OUTPUT_PATH_WIDTHS bound to: 20 - type: string + Parameter C_ACCUM_OP_PATH_WIDTHS bound to: 20 - type: string + Parameter C_EXT_MULT_CNFG bound to: none - type: string + Parameter C_DATA_PATH_PSAMP_SRC bound to: 0 - type: string + Parameter C_OP_PATH_PSAMP_SRC bound to: 0 - type: string + Parameter C_NUM_MADDS bound to: 64 - type: integer + Parameter C_OPT_MADDS bound to: none - type: string + Parameter C_OVERSAMPLING_RATE bound to: 4 - type: integer + Parameter C_INPUT_RATE bound to: 4 - type: integer + Parameter C_OUTPUT_RATE bound to: 4 - type: integer + Parameter C_DATA_MEMTYPE bound to: 0 - type: integer + Parameter C_COEF_MEMTYPE bound to: 2 - type: integer + Parameter C_IPBUFF_MEMTYPE bound to: 0 - type: integer + Parameter C_OPBUFF_MEMTYPE bound to: 0 - type: integer + Parameter C_DATAPATH_MEMTYPE bound to: 0 - type: integer + Parameter C_MEM_ARRANGEMENT bound to: 0 - type: integer + Parameter C_DATA_MEM_PACKING bound to: 0 - type: integer + Parameter C_COEF_MEM_PACKING bound to: 0 - type: integer + Parameter C_FILTS_PACKED bound to: 0 - type: integer + Parameter C_LATENCY bound to: 75 - type: integer + Parameter C_HAS_ARESETn bound to: 1 - type: integer + Parameter C_HAS_ACLKEN bound to: 0 - type: integer + Parameter C_DATA_HAS_TLAST bound to: 0 - type: integer + Parameter C_S_DATA_HAS_FIFO bound to: 0 - type: integer + Parameter C_S_DATA_HAS_TUSER bound to: 0 - type: integer + Parameter C_S_DATA_TDATA_WIDTH bound to: 16 - type: integer + Parameter C_S_DATA_TUSER_WIDTH bound to: 1 - type: integer + Parameter C_M_DATA_HAS_TREADY bound to: 0 - type: integer + Parameter C_M_DATA_HAS_TUSER bound to: 0 - type: integer + Parameter C_M_DATA_TDATA_WIDTH bound to: 24 - type: integer + Parameter C_M_DATA_TUSER_WIDTH bound to: 1 - type: integer + Parameter C_HAS_CONFIG_CHANNEL bound to: 0 - type: integer + Parameter C_CONFIG_SYNC_MODE bound to: 0 - type: integer + Parameter C_CONFIG_PACKET_SIZE bound to: 0 - type: integer + Parameter C_CONFIG_TDATA_WIDTH bound to: 1 - type: integer + Parameter C_RELOAD_TDATA_WIDTH bound to: 1 - type: integer +INFO: [Synth 8-3491] module 'fir_compiler_v7_2_12' declared at '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/hdl/fir_compiler_v7_2_vh_rfs.vhd:61264' bound to instance 'U0' of component 'fir_compiler_v7_2_12' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/synth/fir_prbs7_invert_rep2.vhd:201] +WARNING: [Synth 8-5858] RAM p_path_out_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers +INFO: [Synth 8-256] done synthesizing module 'fir_prbs7_invert_rep2' (12#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/synth/fir_prbs7_invert_rep2.vhd:71] +WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port WE +WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port CE +WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port SCLR +WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port SCLR_ALT +WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port CLK +WARNING: [Synth 8-3331] design cntrl_delay__parameterized0 has unconnected port CE +WARNING: [Synth 8-3331] design cntrl_delay__parameterized0 has unconnected port SCLR +WARNING: [Synth 8-3331] design cntrl_delay__parameterized0 has unconnected port CLK +WARNING: [Synth 8-3331] design delay__parameterized7 has unconnected port SCLR_ALT +WARNING: [Synth 8-3331] design buff has unconnected port RE +WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port WE +WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port CE +WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port SCLR +WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port SCLR_ALT +WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port CLK +WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port WE +WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port CE +WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port SCLR +WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port SCLR_ALT +WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port CLK +WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port PRE_ADDSUB +WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port PRE_ADD_BYPASS +WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port CED +WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port WE +WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port CE +WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port SCLR +WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port SCLR_ALT +WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port CLK +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][57] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][56] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][55] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][54] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][53] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][52] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][51] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][50] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][49] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][48] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][62] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][61] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][60] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][59] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][58] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][57] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][56] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][55] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][54] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][53] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][52] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][51] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][50] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][49] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][48] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][57] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][56] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][55] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][54] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][53] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][52] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][51] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][50] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][49] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][48] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][47] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][46] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][45] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][44] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][43] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][42] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][41] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][40] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][39] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][38] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][37] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][36] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][35] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][34] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][33] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][32] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][31] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][30] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][29] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][28] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][27] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][26] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][25] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][24] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][23] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][22] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][21] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][20] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][19] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][18] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][17] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][16] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][15] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][14] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][13] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][12] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][11] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2009.316 ; gain = 306.438 ; free physical = 902 ; free virtual = 47301 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2009.316 ; gain = 306.438 ; free physical = 930 ; free virtual = 47329 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2009.316 ; gain = 306.438 ; free physical = 930 ; free virtual = 47329 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 65 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/constraints/fir_compiler_v7_2.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/constraints/fir_compiler_v7_2.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2168.098 ; gain = 0.000 ; free physical = 797 ; free virtual = 47202 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2168.098 ; gain = 0.000 ; free physical = 793 ; free virtual = 47199 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 757 ; free virtual = 47106 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 757 ; free virtual = 47106 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 757 ; free virtual = 47106 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 796 ; free virtual = 47144 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic +INFO: [Common 17-14] Message 'Synth 8-5542' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_cntrl_signals[4].i_delay/gen_dly.gen_regs.delay_bus_reg[0][0]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.i_cntrl_cntrl_mem_we/gen_reg.d_reg_reg[0]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.sclr_cntrl_algn_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[0].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[2].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[4].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[5].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[8].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[11].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[13].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[16].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[25].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[26].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[29].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[32].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[42].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[51].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[53].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[61].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[62].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.chan_max_early_reg ) +INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[19]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[23]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[20]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[23]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[21]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[23]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[22]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[23]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tlast_int_reg ) +INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.base_max_cntrl_reg' (FDR) to 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.base_max_reg' +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 782 ; free virtual = 47132 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 688 ; free virtual = 46938 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 687 ; free virtual = 46925 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +INFO: [Common 17-14] Message 'Synth 8-5591' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 705 ; free virtual = 46931 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 704 ; free virtual = 46927 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 704 ; free virtual = 46927 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 711 ; free virtual = 46936 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 711 ; free virtual = 46936 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 710 ; free virtual = 46935 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 710 ; free virtual = 46935 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+----------+------+ +| |Cell |Count | ++------+----------+------+ +|1 |DSP48E1 | 64| +|2 |DSP48E1_1 | 1| +|3 |LUT1 | 21| +|4 |LUT2 | 10| +|5 |LUT3 | 14| +|6 |LUT4 | 4| +|7 |LUT5 | 6| +|8 |LUT6 | 7| +|9 |SRL16E | 782| +|10 |SRLC32E | 9| +|11 |FDRE | 2796| +|12 |FDSE | 6| ++------+----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 710 ; free virtual = 46935 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 2256 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2168.098 ; gain = 306.438 ; free physical = 780 ; free virtual = 47005 +Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 780 ; free virtual = 47005 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 65 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2168.098 ; gain = 0.000 ; free physical = 811 ; free virtual = 47036 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +218 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2168.098 ; gain = 772.121 ; free physical = 916 ; free virtual = 47141 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2168.098 ; gain = 0.000 ; free physical = 916 ; free virtual = 47141 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP fir_prbs7_invert_rep2, cache-ID = 803b8df098fcb9e4 +INFO: [Coretcl 2-1174] Renamed 462 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2192.109 ; gain = 0.000 ; free physical = 913 ; free virtual = 47152 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file fir_prbs7_invert_rep2_utilization_synth.rpt -pb fir_prbs7_invert_rep2_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon May 8 19:43:17 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v new file mode 100644 index 00000000..d3f1af42 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1443d4bafada7dc1e0c863ea91378c74e51dc722fffc7f31975ed98b8b2156e2 +size 3097268 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl new file mode 100644 index 00000000..4c1fdd72 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:95dd57d9721f3b42d8a90e06529d75215410975e1f142885dbff239c1e3814b9 +size 4406730 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v new file mode 100644 index 00000000..68b03a4e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 19:43:16 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v +// Design : fir_prbs7_invert_rep2 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) +module fir_prbs7_invert_rep2(aresetn, aclk, s_axis_data_tvalid, + s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) +/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */; + input aresetn; + input aclk; + input s_axis_data_tvalid; + output s_axis_data_tready; + input [15:0]s_axis_data_tdata; + output m_axis_data_tvalid; + output [23:0]m_axis_data_tdata; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl new file mode 100644 index 00000000..558f6ff5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 19:43:16 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl +-- Design : fir_prbs7_invert_rep2 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity fir_prbs7_invert_rep2 is + Port ( + aresetn : in STD_LOGIC; + aclk : in STD_LOGIC; + s_axis_data_tvalid : in STD_LOGIC; + s_axis_data_tready : out STD_LOGIC; + s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_data_tvalid : out STD_LOGIC; + m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ) + ); + +end fir_prbs7_invert_rep2; + +architecture stub of fir_prbs7_invert_rep2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.pb new file mode 100644 index 00000000..230a6d70 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.rpt new file mode 100644 index 00000000..30fb7b03 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.rpt @@ -0,0 +1,187 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Mon May 8 19:43:16 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file fir_prbs7_invert_rep2_utilization_synth.rpt -pb fir_prbs7_invert_rep2_utilization_synth.pb +| Design : fir_prbs7_invert_rep2 +| Device : 7z100ffg900-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 839 | 0 | 277400 | 0.30 | +| LUT as Logic | 48 | 0 | 277400 | 0.02 | +| LUT as Memory | 791 | 0 | 108200 | 0.73 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 791 | 0 | | | +| Slice Registers | 2802 | 0 | 554800 | 0.51 | +| Register as Flip Flop | 2802 | 0 | 554800 | 0.51 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 6 | Yes | Set | - | +| 2796 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| DSPs | 65 | 0 | 2020 | 3.22 | +| DSP48E1 only | 65 | | | | ++----------------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 2796 | Flop & Latch | +| SRL16E | 782 | Distributed Memory | +| DSP48E1 | 65 | Block Arithmetic | +| LUT1 | 21 | LUT | +| LUT3 | 14 | LUT | +| LUT2 | 10 | LUT | +| SRLC32E | 9 | Distributed Memory | +| LUT6 | 7 | LUT | +| LUT5 | 6 | LUT | +| FDSE | 6 | Flop & Latch | +| LUT4 | 4 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/gen_run.xml new file mode 100644 index 00000000..c7272869 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/gen_run.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/htr.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/htr.txt new file mode 100644 index 00000000..9b4f26c4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log fir_prbs7_invert_rep2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs7_invert_rep2.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/project.wdf new file mode 100644 index 00000000..d724c79c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/project.wdf @@ -0,0 +1,42 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3230:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3230:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 +eof:516242679 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/rundef.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/rundef.js new file mode 100644 index 00000000..058585ea --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log fir_prbs7_invert_rep2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs7_invert_rep2.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.bat b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.sh new file mode 100755 index 00000000..c7d8f5ad --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log fir_prbs7_invert_rep2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs7_invert_rep2.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/vivado.pb new file mode 100644 index 00000000..4f304037 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..85d0bfe7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ISEWrap.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ISEWrap.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/dont_touch.xdc b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/dont_touch.xdc new file mode 100644 index 00000000..80c8900e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci +# IP: The module: 'ila_freq_comp' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_v6_2/constraints/ila_impl.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_freq_comp'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_v6_2/constraints/ila.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_freq_comp'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_freq_comp'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci +# IP: The module: 'ila_freq_comp' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_v6_2/constraints/ila_impl.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_freq_comp'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_v6_2/constraints/ila.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_freq_comp'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_freq_comp'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml new file mode 100644 index 00000000..fb9c6d9c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/htr.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/htr.txt new file mode 100644 index 00000000..bcf978b4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log ila_freq_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_freq_comp.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp new file mode 100644 index 00000000..96e243e0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:59670aabe78e291f12338a6423df3818e522ccb657d94fe5d88281760137815a +size 7266059 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.tcl new file mode 100644 index 00000000..bb0bb682 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.tcl @@ -0,0 +1,159 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci +set_property used_in_synthesis false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_v6_2/constraints/ila_impl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_v6_2/constraints/ila_impl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_v6_2/constraints/ila.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1 -new_name ila_freq_comp -ip [get_ips ila_freq_comp]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top ila_freq_comp -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix ila_freq_comp_ ila_freq_comp.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.v + lappend ipCachedFiles ila_freq_comp_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.vhdl + lappend ipCachedFiles ila_freq_comp_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_sim_netlist.v + lappend ipCachedFiles ila_freq_comp_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_sim_netlist.vhdl + lappend ipCachedFiles ila_freq_comp_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp ila_freq_comp.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips ila_freq_comp] +} + +rename_ref -prefix_all ila_freq_comp_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef ila_freq_comp.dcp +create_report "ila_freq_comp_synth_1_synth_report_utilization_0" "report_utilization -file ila_freq_comp_utilization_synth.rpt -pb ila_freq_comp_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.vds new file mode 100644 index 00000000..46459d7b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.vds @@ -0,0 +1,6956 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Tue May 9 13:35:15 2023 +# Process ID: 3636820 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1 +# Command line: vivado -log ila_freq_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_freq_comp.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/vivado.jou +#----------------------------------------------------------- +source ila_freq_comp.tcl -notrace +Command: synth_design -top ila_freq_comp -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 3636995 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1882.078 ; gain = 161.688 ; free physical = 465 ; free virtual = 45163 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'ila_freq_comp' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/synth/ila_freq_comp.v:84] +INFO: [Synth 8-6157] synthesizing module 'CFGLUT5' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] +INFO: [Synth 8-6155] done synthesizing module 'CFGLUT5' (12#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] +INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] +INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (13#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (23#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] +INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] +INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (25#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] +INFO: [Synth 8-6157] synthesizing module 'SRLC16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] +INFO: [Synth 8-6155] done synthesizing module 'SRLC16E' (27#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] +INFO: [Synth 8-6157] synthesizing module 'FDRE' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +INFO: [Synth 8-6155] done synthesizing module 'FDRE' (32#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +WARNING: [Synth 8-7023] instance 'inst' of module 'ila_v6_2_9_ila' has 1033 connections declared, but only 1027 given [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/synth/ila_freq_comp.v:3255] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity ila_freq_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/synth/ila_freq_comp.v:144] +INFO: [Synth 8-6155] done synthesizing module 'ila_freq_comp' (52#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/synth/ila_freq_comp.v:84] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MUX_RST[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MEM_LAT_RST +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MUX_REGCE[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port WE +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[15] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[14] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[13] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[12] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[11] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[10] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[9] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[8] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[7] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[6] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[5] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[4] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4095] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4094] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4093] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4092] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4091] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4090] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4089] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4088] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4087] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4086] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4085] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4084] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4083] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4082] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4081] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4080] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4079] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4078] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4077] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4076] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4075] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4074] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4073] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4072] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4071] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4070] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4069] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4068] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4067] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4066] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4065] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4064] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4063] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4062] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4061] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4060] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4059] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4058] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4057] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4056] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4055] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4054] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4053] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4052] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4051] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4050] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4049] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4048] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4047] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4046] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4045] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4044] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4043] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4042] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4041] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4040] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4039] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4038] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4037] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4036] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4035] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4034] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4033] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4032] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4031] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4030] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4029] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4028] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4027] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4026] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4025] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4024] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4023] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4022] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4021] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4020] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4019] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4018] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4017] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4016] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:03:01 ; elapsed = 00:03:11 . Memory (MB): peak = 2616.219 ; gain = 895.828 ; free physical = 701 ; free virtual = 44725 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:03:02 ; elapsed = 00:03:13 . Memory (MB): peak = 2616.219 ; gain = 895.828 ; free physical = 780 ; free virtual = 44839 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:03:02 ; elapsed = 00:03:13 . Memory (MB): peak = 2616.219 ; gain = 895.828 ; free physical = 780 ; free virtual = 44839 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 2354 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_v6_2/constraints/ila.xdc] for cell 'inst' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_v6_2/constraints/ila.xdc] for cell 'inst' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2689.156 ; gain = 0.000 ; free physical = 495 ; free virtual = 44551 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1348 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 1264 instances + CFGLUT5 => SRLC32E: 84 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2689.156 ; gain = 0.000 ; free physical = 491 ; free virtual = 44548 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:03:11 ; elapsed = 00:03:22 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 744 ; free virtual = 44804 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:03:11 ; elapsed = 00:03:22 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 744 ; free virtual = 44803 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:03:11 ; elapsed = 00:03:22 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 739 ; free virtual = 44799 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized83' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized84' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized11' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized12' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized13' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized14' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized15' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized16' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized17' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized18' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized19' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized20' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized21' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized22' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized23' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized24' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized25' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized26' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized27' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized28' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized29' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized30' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized31' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized32' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized33' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized34' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized35' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized36' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized37' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized38' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized39' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized40' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized41' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized42' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized43' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized44' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized45' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized46' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized47' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized48' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized49' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized50' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized51' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized52' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized53' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized54' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized55' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized56' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized57' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized58' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized59' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized60' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized61' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized62' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized63' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized64' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized65' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized66' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized67' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized68' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized69' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized70' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized71' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized72' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized73' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized74' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized75' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized76' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized77' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized78' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized79' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized80' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized81' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized82' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized83' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized84' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized11' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized12' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized13' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized14' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized15' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized16' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized17' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized18' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized19' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized20' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized21' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized22' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized23' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized24' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized25' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized26' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized27' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized28' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized29' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized30' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized31' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized32' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized33' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized34' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized35' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized36' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized37' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized38' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized39' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized40' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized41' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized42' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized43' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized44' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized45' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized46' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized47' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized48' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized49' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized50' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized51' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized52' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized53' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized54' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized55' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized56' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized57' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized58' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized59' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized60' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized61' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized62' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized63' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized64' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized65' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized66' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized67' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized68' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized69' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized70' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized71' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized72' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized73' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized74' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized75' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized76' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized77' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized78' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized79' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized80' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized81' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized82' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:03:17 ; elapsed = 00:03:30 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 462 ; free virtual = 43316 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++------+-------------------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++------+-------------------------+------------+----------+ +|1 |ila_v6_2_9_ila_core__GB0 | 1| 31126| +|2 |ila_v6_2_9_ila_core__GB1 | 1| 23478| +|3 |ila_v6_2_9_ila__GC0 | 1| 6| ++------+-------------------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 4 + 2 Input 16 Bit Adders := 1 + 2 Input 9 Bit Adders := 1 + 2 Input 7 Bit Adders := 4 + 2 Input 6 Bit Adders := 1 + 2 Input 5 Bit Adders := 1 + 2 Input 4 Bit Adders := 86 ++---XORs : + 2 Input 13 Bit XORs := 100 + 2 Input 1 Bit XORs := 4 ++---Registers : + 1024 Bit Registers := 2 + 352 Bit Registers := 1 + 339 Bit Registers := 9 + 128 Bit Registers := 1 + 48 Bit Registers := 33 + 33 Bit Registers := 2 + 32 Bit Registers := 13 + 24 Bit Registers := 1 + 18 Bit Registers := 52 + 17 Bit Registers := 2 + 16 Bit Registers := 325 + 12 Bit Registers := 12 + 9 Bit Registers := 1 + 8 Bit Registers := 17 + 7 Bit Registers := 5 + 6 Bit Registers := 2 + 5 Bit Registers := 1 + 4 Bit Registers := 97 + 3 Bit Registers := 4 + 2 Bit Registers := 6 + 1 Bit Registers := 525 ++---Muxes : + 2 Input 339 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 12 + 2 Input 16 Bit Muxes := 100 + 4 Input 16 Bit Muxes := 2 + 3 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 86 + 3 Input 15 Bit Muxes := 1 + 3 Input 7 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 4 + 2 Input 5 Bit Muxes := 2 + 8 Input 5 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 86 + 2 Input 4 Bit Muxes := 260 + 2 Input 3 Bit Muxes := 86 + 2 Input 2 Bit Muxes := 6 + 2 Input 1 Bit Muxes := 554 + 3 Input 1 Bit Muxes := 86 + 9 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 2 + 8 Input 1 Bit Muxes := 5 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module xsdbs_v1_0_2_reg_p2s__parameterized83 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_stat +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_ctl +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stream__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 17 Bit Registers := 1 + 16 Bit Registers := 4 + 1 Bit Registers := 4 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_stat__103 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__102 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__101 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__100 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__99 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__98 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_ctl__11 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized81 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized82 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_stat__97 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__96 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__95 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__94 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__93 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__92 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__91 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__90 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__89 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__88 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__87 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__86 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__85 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_ctl__10 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized96 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__9 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized97 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__8 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized98 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__7 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized99 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__6 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized100 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized101 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized102 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__5 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized103 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized2__1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized104 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__4 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized105 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__3 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized106 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized107 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_stat__84 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__83 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__82 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__81 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__80 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__79 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__78 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized84 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_ctl__1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stream__parameterized1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__77 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__76 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__75 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__74 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__73 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__72 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__71 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__70 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__69 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__68 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__67 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__66 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__65 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__64 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__63 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__62 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__61 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__60 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__59 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__58 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__57 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__56 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__55 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__54 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__53 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__52 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__51 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__50 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__49 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__48 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__47 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__46 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__45 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__44 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__43 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__42 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__41 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__40 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__39 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__38 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__37 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__36 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__35 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__34 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__33 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__32 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__31 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__30 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__29 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__28 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__27 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__26 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__25 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__24 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__23 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__22 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__21 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__20 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__19 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__18 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__17 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__16 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__15 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__14 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__13 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__12 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__11 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__10 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__9 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__8 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__7 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__6 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__5 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__4 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__3 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stat__1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_p2s +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized0 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized1 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized2 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized3 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized4 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized5 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized6 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized7 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized8 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized9 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized10 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized11 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized12 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized13 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized14 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized15 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized16 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized17 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized18 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized19 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized20 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized21 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized22 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized23 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized24 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized25 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized26 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized27 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized28 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized29 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized30 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized31 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized32 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized33 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized34 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized35 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized36 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized37 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized38 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized39 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized40 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized41 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized42 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized43 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized44 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized45 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized46 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized47 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized48 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized49 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized50 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized51 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized52 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized53 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized54 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized55 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized56 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized57 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized58 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized59 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized60 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized61 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized62 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized63 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized64 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized65 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized66 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized67 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized68 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized69 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized70 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized71 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized72 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized73 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized74 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized75 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized76 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized77 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized78 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized79 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized80 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized81 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized82 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_register +Detailed RTL Component Info : ++---Adders : + 2 Input 9 Bit Adders := 1 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 ++---Registers : + 1024 Bit Registers := 2 + 17 Bit Registers := 1 + 16 Bit Registers := 12 + 9 Bit Registers := 1 + 7 Bit Registers := 2 + 6 Bit Registers := 1 + 1 Bit Registers := 31 ++---Muxes : + 2 Input 16 Bit Muxes := 10 + 4 Input 16 Bit Muxes := 2 + 3 Input 16 Bit Muxes := 1 + 3 Input 15 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 4 + 2 Input 5 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 13 + 9 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_fsm_memory_read +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 8 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module ila_v6_2_9_ila_adv_trigger_sequencer +Detailed RTL Component Info : ++---Adders : + 2 Input 7 Bit Adders := 2 ++---Registers : + 24 Bit Registers := 1 + 16 Bit Registers := 1 + 7 Bit Registers := 2 + 4 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 10 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 9 + 4 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__5 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__1 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__71 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized0__1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized0__1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__72 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized0__2 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized0__2 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__43 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__1 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__44 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__2 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__2 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__45 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__3 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__3 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__46 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__4 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__4 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__47 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__5 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__5 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__48 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__6 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__6 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__49 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__7 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__7 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__50 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__8 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__8 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__51 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__9 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__9 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__52 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__10 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__10 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__53 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__11 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__11 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__54 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__12 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__12 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__55 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__13 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__13 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__56 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__14 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__14 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__57 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__15 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__15 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__58 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__16 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__16 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__74 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized2__1 +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized2__1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__75 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized2__2 +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized2__2 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__76 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized2__3 +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized2__3 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__77 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized2__4 +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized2__4 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__78 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized2__5 +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized2__5 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__79 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized2__6 +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized2__6 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__80 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized2__7 +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized2__7 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized2 +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized2 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__73 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized0__3 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized0__3 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__69 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__70 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized3__1 +Detailed RTL Component Info : ++---Registers : + 3 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized3__1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__68 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized3 +Detailed RTL Component Info : ++---Registers : + 3 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized3 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__37 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized4__1 +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized4__1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__38 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized4__2 +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized4__2 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__39 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized4__3 +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized4__3 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__40 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized4__4 +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized4__4 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__59 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__17 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__17 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__60 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__18 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__18 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__61 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__19 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__19 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__62 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__20 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__20 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__63 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__21 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__21 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__64 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__22 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__22 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__65 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__23 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__23 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__66 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__24 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__24 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__67 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1__25 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1__25 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__4 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1 +Detailed RTL Component Info : ++---Registers : + 18 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__42 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized5__1 +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized5__1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__3 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized5 +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized5 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__41 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized4__5 +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized4__5 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__2 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized4 +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized4 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__6 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__2 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__2 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__7 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__3 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__3 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__8 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__4 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__4 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__9 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__5 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__5 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__10 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__6 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__6 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__11 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__7 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__7 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__12 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__8 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__8 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__13 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__9 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__9 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__14 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__10 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__10 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__15 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__11 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__11 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__16 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__12 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__12 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__17 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__13 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__13 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__18 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__14 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__14 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__19 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__15 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__15 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__20 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__16 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__16 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__21 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__17 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__17 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__22 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__18 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__18 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__23 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__19 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__19 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__24 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__20 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__20 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__25 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__21 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__21 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__26 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__22 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__22 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__27 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__23 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__23 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__28 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__24 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__24 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__29 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__25 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__25 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__30 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__26 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__26 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__31 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__27 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__27 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__32 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__28 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__28 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__33 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__29 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__29 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__34 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__30 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__30 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__35 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__31 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__31 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__36 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__32 +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match__32 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0__1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA +Detailed RTL Component Info : ++---Registers : + 48 Bit Registers := 1 +Module ltlib_v1_0_0_match +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ila_v6_2_9_ila_trigger +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 2 +Module ltlib_v1_0_0_async_edge_xfer__1 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 1 Bit Registers := 5 +Module ltlib_v1_0_0_async_edge_xfer__2 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 1 Bit Registers := 5 +Module ltlib_v1_0_0_async_edge_xfer__3 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 1 Bit Registers := 5 +Module ltlib_v1_0_0_async_edge_xfer +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 1 Bit Registers := 5 +Module ltlib_v1_0_0_rising_edge_detection__1 +Detailed RTL Component Info : ++---Registers : + 2 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 2 Bit Muxes := 2 +Module ltlib_v1_0_0_rising_edge_detection +Detailed RTL Component Info : ++---Registers : + 2 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 2 Bit Muxes := 2 +Module ila_v6_2_9_ila_reset_ctrl +Detailed RTL Component Info : ++---Registers : + 6 Bit Registers := 1 + 1 Bit Registers := 2 +Module ltlib_v1_0_0_cfglut7__1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 3 +Module ltlib_v1_0_0_cfglut7 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 3 +Module ltlib_v1_0_0_cfglut6 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_cfglut6__1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_allx_typeA_nodelay +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA_nodelay__1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA_nodelay__2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module ila_v6_2_9_ila_cap_addrgen +Detailed RTL Component Info : ++---Registers : + 33 Bit Registers := 2 + 16 Bit Registers := 4 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 16 +Module ltlib_v1_0_0_cfglut6__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_cap_ctrl_legacy +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 3 ++---Muxes : + 2 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 1 +Module blk_mem_gen_v8_4_3_bindec__3 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 16 +Module blk_mem_gen_v8_4_3_bindec +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 16 +Module blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module blk_mem_gen_v8_4_3_bindec__1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 16 +Module blk_mem_gen_v8_4_3_bindec__2 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 16 +Module blk_mem_gen_v8_4_3_blk_mem_gen_mux +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_generic_memrd +Detailed RTL Component Info : ++---Adders : + 2 Input 16 Bit Adders := 1 + 2 Input 5 Bit Adders := 1 ++---Registers : + 352 Bit Registers := 1 + 16 Bit Registers := 1 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 4 Bit Registers := 2 + 1 Bit Registers := 3 ++---Muxes : + 8 Input 16 Bit Muxes := 1 + 3 Input 7 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 8 Input 5 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1 + 8 Input 1 Bit Muxes := 5 +Module ila_v6_2_9_generic_counter__1 +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 2 +Module ila_v6_2_9_generic_counter__2 +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 2 +Module ila_v6_2_9_generic_counter__3 +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 2 +Module ila_v6_2_9_generic_counter +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 2 +Module ila_v6_2_9_ila_core +Detailed RTL Component Info : ++---Registers : + 339 Bit Registers := 9 + 16 Bit Registers := 2 + 2 Bit Registers := 3 + 1 Bit Registers := 5 ++---Muxes : + 2 Input 339 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 1 +Module ila_v6_2_9_ila +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 6 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1023] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1023] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[0]' (FDRE) to 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[5]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[0] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[44].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[38].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[34].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[32].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[30].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[28].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[26].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[24].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[36].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[1]' (FDRE) to 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[1] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[44].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[38].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[34].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[32].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[30].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[28].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[26].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[24].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[36].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[2]' (FDRE) to 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[2] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[44].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[38].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[34].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[32].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[30].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[28].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[26].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[24].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[46].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[8] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/ila_core_insti_1/u_ila_regs/\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff8_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[15] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:03:29 ; elapsed = 00:03:49 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 516 ; free virtual = 42027 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+--------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+--------------------------------------+----------------+----------------------+---------------+ +|inst | ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | ++------------+--------------------------------------+----------------+----------------------+---------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++------+-------------------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++------+-------------------------+------------+----------+ +|1 |ila_v6_2_9_ila_core__GB0 | 1| 16487| +|2 |ila_v6_2_9_ila_core__GB1 | 1| 13729| +|3 |ila_v6_2_9_ila__GC0 | 1| 6| ++------+-------------------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:36 ; elapsed = 00:03:56 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 452 ; free virtual = 41920 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:03:37 ; elapsed = 00:03:58 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 474 ; free virtual = 41913 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+--------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+--------------------------------------+----------------+----------------------+---------------+ +|inst | ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | ++------------+--------------------------------------+----------------+----------------------+---------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++------+-------------------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++------+-------------------------+------------+----------+ +|1 |ila_v6_2_9_ila_core__GB0 | 1| 16487| +|2 |ila_v6_2_9_ila_core__GB1 | 1| 13729| +|3 |ila_v6_2_9_ila__GC0 | 1| 6| ++------+-------------------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:03:40 ; elapsed = 00:04:01 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 479 ; free virtual = 41918 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [9] is driving 606 big block pins (URAM, BRAM and DSP loads). Created 61 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [10] is driving 606 big block pins (URAM, BRAM and DSP loads). Created 61 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_en is driving 606 big block pins (URAM, BRAM and DSP loads). Created 61 replicas of its driver. +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-3295] tying undriven pin dummy_inferred:in0 to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:trig_in to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:trig_out_ack to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:03:41 ; elapsed = 00:04:02 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 481 ; free virtual = 41920 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:03:41 ; elapsed = 00:04:02 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 481 ; free virtual = 41920 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:43 ; elapsed = 00:04:03 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 482 ; free virtual = 41916 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:03:43 ; elapsed = 00:04:03 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 482 ; free virtual = 41916 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:03:43 ; elapsed = 00:04:03 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 450 ; free virtual = 41916 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:03:43 ; elapsed = 00:04:03 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 450 ; free virtual = 41916 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|ila_v6_2_9_generic_counter | counter_load_i_reg[16] | 16 | 4 | NO | NO | YES | 4 | 0 | +|ila_v6_2_9_ila | ila_core_inst/u_ila_regs/adv_rb_drdy4_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/shifted_data_in_reg[8][338] | 9 | 339 | NO | NO | YES | 339 | 0 | ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |CARRY4 | 428| +|2 |CFGLUT5 | 1348| +|3 |LUT1 | 118| +|4 |LUT2 | 212| +|5 |LUT3 | 765| +|6 |LUT4 | 892| +|7 |LUT5 | 224| +|8 |LUT6 | 3653| +|9 |MUXF7 | 880| +|10 |MUXF8 | 396| +|11 |RAM64M | 32| +|12 |RAMB36E1 | 592| +|13 |RAMB36E1_1 | 7| +|14 |RAMB36E1_2 | 7| +|15 |SRL16E | 347| +|16 |SRLC16E | 2| +|17 |SRLC32E | 17| +|18 |FDRE | 7104| +|19 |FDSE | 12| ++------+-----------+------+ + +Report Instance Areas: ++------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ +| |Instance |Module |Cells | ++------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ +|1 |top | | 17036| +|2 | inst |ila_v6_2_9_ila | 17036| +|3 | ila_core_inst |ila_v6_2_9_ila_core | 17029| +|4 | \ADV_TRIG_MEM_READ.u_fsm_memory_read_inst |ila_v6_2_9_ila_fsm_memory_read | 52| +|5 | ila_trace_memory_inst |ila_v6_2_9_ila_trace_memory | 2984| +|6 | \SUBCORE_RAM.BLK_MEM_GEN[0].trace_block_memory |blk_mem_gen_v8_4_3 | 2220| +|7 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 2220| +|8 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_v8_4_3_blk_mem_gen_top | 2220| +|9 | \valid.cstr |blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr | 2220| +|10 | \has_mux_b.B |blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 | 1764| +|11 | \ramloop[0].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width | 1| +|12 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper | 1| +|13 | \ramloop[100].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized99 | 1| +|14 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized99 | 1| +|15 | \ramloop[101].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized100 | 1| +|16 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized100 | 1| +|17 | \ramloop[102].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized101 | 1| +|18 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized101 | 1| +|19 | \ramloop[103].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized102 | 1| +|20 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized102 | 1| +|21 | \ramloop[104].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized103 | 1| +|22 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized103 | 1| +|23 | \ramloop[105].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized104 | 1| +|24 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized104 | 1| +|25 | \ramloop[106].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized105 | 1| +|26 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized105 | 1| +|27 | \ramloop[107].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized106 | 1| +|28 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized106 | 1| +|29 | \ramloop[108].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized107 | 1| +|30 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized107 | 1| +|31 | \ramloop[109].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized108 | 1| +|32 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized108 | 1| +|33 | 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized554 | 1| +|929 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized554 | 1| +|930 | \ramloop[104].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized555 | 1| +|931 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized555 | 1| +|932 | \ramloop[105].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized556 | 1| +|933 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized556 | 1| +|934 | \ramloop[106].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized557 | 1| +|935 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized557 | 1| +|936 | \ramloop[107].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized558 | 1| +|937 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized558 | 1| +|938 | \ramloop[108].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized559 | 1| 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized582 | 1| +|992 | \ramloop[132].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized583 | 1| +|993 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized583 | 1| +|994 | \ramloop[133].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized584 | 1| +|995 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized584 | 1| +|996 | \ramloop[134].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized585 | 1| +|997 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized585 | 1| +|998 | \ramloop[135].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized586 | 1| +|999 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized586 | 1| +|1000 | \ramloop[136].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized587 | 1| +|1001 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized587 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized592 | 1| +|1013 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized592 | 1| +|1014 | \ramloop[142].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized593 | 1| +|1015 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized593 | 1| +|1016 | \ramloop[143].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized594 | 1| +|1017 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized594 | 1| +|1018 | \ramloop[144].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized595 | 2| +|1019 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized595 | 2| +|1020 | \ramloop[145].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized596 | 2| +|1021 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized596 | 2| +|1022 | \ramloop[146].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized597 | 2| +|1023 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized597 | 2| +|1024 | \ramloop[14].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized465 | 1| +|1025 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized465 | 1| +|1026 | \ramloop[15].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized466 | 1| +|1027 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized466 | 1| +|1028 | \ramloop[16].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized467 | 1| +|1029 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized467 | 1| +|1030 | \ramloop[17].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized468 | 1| +|1031 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized468 | 1| +|1032 | \ramloop[18].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized469 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized519 | 1| +|1144 | \ramloop[69].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized520 | 1| +|1145 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized520 | 1| +|1146 | \ramloop[6].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized457 | 1| +|1147 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized457 | 1| +|1148 | \ramloop[70].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized521 | 1| +|1149 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized521 | 1| +|1150 | \ramloop[71].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized522 | 1| +|1151 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized522 | 1| +|1152 | \ramloop[72].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized523 | 1| +|1153 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized523 | 1| +|1154 | \ramloop[73].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized524 | 1| +|1155 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized524 | 1| +|1156 | \ramloop[74].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized525 | 1| +|1157 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized525 | 1| +|1158 | \ramloop[75].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized526 | 1| +|1159 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized526 | 1| +|1160 | \ramloop[76].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized527 | 1| +|1161 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized527 | 1| +|1162 | \ramloop[77].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized528 | 1| +|1163 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized528 | 1| +|1164 | \ramloop[78].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized529 | 1| +|1165 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized529 | 1| +|1166 | \ramloop[79].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized530 | 1| +|1167 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized530 | 1| +|1168 | \ramloop[7].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized458 | 1| +|1169 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized458 | 1| +|1170 | \ramloop[80].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized531 | 1| +|1171 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized531 | 1| +|1172 | \ramloop[81].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized532 | 1| +|1173 | \prim_noinit.ram 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized537 | 1| +|1184 | \ramloop[87].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized538 | 1| +|1185 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized538 | 1| +|1186 | \ramloop[88].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized539 | 1| +|1187 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized539 | 1| +|1188 | \ramloop[89].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized540 | 1| +|1189 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized540 | 1| +|1190 | \ramloop[8].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized459 | 1| +|1191 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized459 | 1| +|1192 | \ramloop[90].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized541 | 1| +|1193 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized541 | 1| +|1194 | \ramloop[91].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized542 | 1| +|1195 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized542 | 1| +|1196 | \ramloop[92].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized543 | 1| +|1197 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized543 | 1| +|1198 | \ramloop[93].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized544 | 1| +|1199 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized544 | 1| +|1200 | \ramloop[94].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized545 | 1| +|1201 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized545 | 1| +|1202 | \ramloop[95].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized546 | 1| +|1203 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized546 | 1| +|1204 | \ramloop[96].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized547 | 1| +|1205 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized547 | 1| +|1206 | \ramloop[97].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized548 | 1| +|1207 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized548 | 1| +|1208 | \ramloop[98].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized549 | 1| +|1209 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized549 | 1| +|1210 | \ramloop[99].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized550 | 1| +|1211 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized550 | 1| +|1212 | \ramloop[9].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized460 | 1| +|1213 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized460 | 1| +|1214 | \ADV_TRIG.u_adv_trig |ila_v6_2_9_ila_adv_trigger_sequencer | 205| +|1215 | \COUNTER.u_count |ila_v6_2_9_ila_counter | 232| +|1216 | \G_COUNTER[0].U_COUNTER |ila_v6_2_9_generic_counter__1 | 58| +|1217 | \G_COUNTER[1].U_COUNTER |ila_v6_2_9_generic_counter__2 | 58| +|1218 | \G_COUNTER[2].U_COUNTER |ila_v6_2_9_generic_counter__3 | 58| +|1219 | \G_COUNTER[3].U_COUNTER |ila_v6_2_9_generic_counter | 58| +|1220 | u_ila_cap_ctrl |ila_v6_2_9_ila_cap_ctrl_legacy | 349| +|1221 | U_CDONE |ltlib_v1_0_0_cfglut6__parameterized0 | 5| +|1222 | U_NS0 |ltlib_v1_0_0_cfglut7 | 8| +|1223 | U_NS1 |ltlib_v1_0_0_cfglut7_556 | 10| +|1224 | u_cap_addrgen |ila_v6_2_9_ila_cap_addrgen | 321| +|1225 | U_CMPRESET |ltlib_v1_0_0_cfglut6 | 3| +|1226 | u_cap_sample_counter |ila_v6_2_9_ila_cap_sample_counter | 71| +|1227 | U_SCE |ltlib_v1_0_0_cfglut4_563 | 1| +|1228 | U_SCMPCE |ltlib_v1_0_0_cfglut5_564 | 1| +|1229 | U_SCRST |ltlib_v1_0_0_cfglut6_565 | 3| +|1230 | u_scnt_cmp |ltlib_v1_0_0_match_nodelay_566 | 28| +|1231 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_567 | 28| +|1232 | DUT |ltlib_v1_0_0_all_typeA__parameterized4_568 | 12| +|1233 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_569 | 5| +|1234 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_570 | 5| +|1235 | u_cap_window_counter |ila_v6_2_9_ila_cap_window_counter | 66| +|1236 | U_WCE |ltlib_v1_0_0_cfglut4 | 1| +|1237 | U_WHCMPCE |ltlib_v1_0_0_cfglut5 | 1| +|1238 | U_WLCMPCE |ltlib_v1_0_0_cfglut5_557 | 1| +|1239 | u_wcnt_hcmp |ltlib_v1_0_0_match_nodelay | 12| +|1240 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_559 | 12| +|1241 | DUT |ltlib_v1_0_0_all_typeA__parameterized4_560 | 12| +|1242 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_561 | 5| +|1243 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_562 | 5| +|1244 | u_wcnt_lcmp |ltlib_v1_0_0_match_nodelay_558 | 28| +|1245 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay | 28| +|1246 | DUT |ltlib_v1_0_0_all_typeA__parameterized4 | 12| +|1247 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1 | 5| +|1248 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2 | 5| +|1249 | u_ila_regs |ila_v6_2_9_ila_register | 8242| +|1250 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 302| +|1251 | reg_890 |xsdbs_v1_0_2_reg__parameterized114 | 16| +|1252 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_555 | 16| +|1253 | \ADV_TRIG_STREAM.reg_stream_ffc |xsdbs_v1_0_2_reg_stream__parameterized0 | 26| +|1254 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_554 | 22| +|1255 | \ADV_TRIG_STREAM_READBACK.reg_stream_ffb |xsdbs_v1_0_2_reg_stream | 35| +|1256 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_553 | 35| +|1257 | \CNT.CNT_SRL[0].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized79 | 75| +|1258 | \CNT.CNT_SRL[1].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized80 | 75| +|1259 | \CNT.CNT_SRL[2].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized81 | 107| +|1260 | \CNT.CNT_SRL[3].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized82 | 76| +|1261 | \MU_SRL[0].mu_srl_reg |xsdbs_v1_0_2_reg_p2s | 76| +|1262 | \MU_SRL[10].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized9 | 74| +|1263 | \MU_SRL[11].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized10 | 106| +|1264 | \MU_SRL[12].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized11 | 74| +|1265 | \MU_SRL[13].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized12 | 74| +|1266 | \MU_SRL[14].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized13 | 74| +|1267 | \MU_SRL[15].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized14 | 90| +|1268 | \MU_SRL[16].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized15 | 74| +|1269 | \MU_SRL[17].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized16 | 74| +|1270 | \MU_SRL[18].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized17 | 74| +|1271 | \MU_SRL[19].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized18 | 122| +|1272 | \MU_SRL[1].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized0 | 75| +|1273 | \MU_SRL[20].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized19 | 74| +|1274 | \MU_SRL[21].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized20 | 74| +|1275 | \MU_SRL[22].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized21 | 74| +|1276 | \MU_SRL[23].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized22 | 90| +|1277 | \MU_SRL[24].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized23 | 74| +|1278 | \MU_SRL[25].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized24 | 74| +|1279 | \MU_SRL[26].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized25 | 74| +|1280 | \MU_SRL[27].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized26 | 106| +|1281 | \MU_SRL[28].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized27 | 74| +|1282 | \MU_SRL[29].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized28 | 74| +|1283 | \MU_SRL[2].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized1 | 75| +|1284 | \MU_SRL[30].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized29 | 74| +|1285 | \MU_SRL[31].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized30 | 90| +|1286 | \MU_SRL[32].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized31 | 74| +|1287 | \MU_SRL[33].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized32 | 74| +|1288 | \MU_SRL[34].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized33 | 74| +|1289 | \MU_SRL[35].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized34 | 138| +|1290 | \MU_SRL[36].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized35 | 74| +|1291 | \MU_SRL[37].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized36 | 74| +|1292 | \MU_SRL[38].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized37 | 74| +|1293 | \MU_SRL[39].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized38 | 90| +|1294 | \MU_SRL[3].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized2 | 123| +|1295 | \MU_SRL[40].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized39 | 74| +|1296 | \MU_SRL[41].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized40 | 74| +|1297 | \MU_SRL[42].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized41 | 74| +|1298 | \MU_SRL[43].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized42 | 106| +|1299 | \MU_SRL[44].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized43 | 74| +|1300 | \MU_SRL[45].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized44 | 74| +|1301 | \MU_SRL[46].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized45 | 74| +|1302 | \MU_SRL[47].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized46 | 90| +|1303 | \MU_SRL[4].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized3 | 74| +|1304 | \MU_SRL[5].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized4 | 74| +|1305 | \MU_SRL[6].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized5 | 74| +|1306 | \MU_SRL[7].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized6 | 90| +|1307 | \MU_SRL[8].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized7 | 74| +|1308 | \MU_SRL[9].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized8 | 74| +|1309 | \STRG_QUAL.qual_strg_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized83 | 74| +|1310 | \TC_SRL[0].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized47 | 75| +|1311 | \TC_SRL[10].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized57 | 74| +|1312 | \TC_SRL[11].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized58 | 106| +|1313 | \TC_SRL[12].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized59 | 74| +|1314 | \TC_SRL[13].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized60 | 74| +|1315 | \TC_SRL[14].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized61 | 74| +|1316 | \TC_SRL[15].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized62 | 90| +|1317 | \TC_SRL[16].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized63 | 74| +|1318 | \TC_SRL[17].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized64 | 74| +|1319 | \TC_SRL[18].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized65 | 74| +|1320 | \TC_SRL[19].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized66 | 106| +|1321 | \TC_SRL[1].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized48 | 75| +|1322 | \TC_SRL[20].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized67 | 74| +|1323 | \TC_SRL[21].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized68 | 74| +|1324 | \TC_SRL[22].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized69 | 74| +|1325 | \TC_SRL[23].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized70 | 90| +|1326 | \TC_SRL[24].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized71 | 74| +|1327 | \TC_SRL[25].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized72 | 74| +|1328 | \TC_SRL[26].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized73 | 74| +|1329 | \TC_SRL[27].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized74 | 122| +|1330 | \TC_SRL[28].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized75 | 74| +|1331 | \TC_SRL[29].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized76 | 74| +|1332 | \TC_SRL[2].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized49 | 75| +|1333 | \TC_SRL[30].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized77 | 74| +|1334 | \TC_SRL[31].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized78 | 90| +|1335 | \TC_SRL[3].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized50 | 107| +|1336 | \TC_SRL[4].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized51 | 74| +|1337 | \TC_SRL[5].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized52 | 74| +|1338 | \TC_SRL[6].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized53 | 74| +|1339 | \TC_SRL[7].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized54 | 90| +|1340 | \TC_SRL[8].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized55 | 74| +|1341 | \TC_SRL[9].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized56 | 74| +|1342 | reg_15 |xsdbs_v1_0_2_reg__parameterized96 | 31| +|1343 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_552 | 31| +|1344 | reg_16 |xsdbs_v1_0_2_reg__parameterized97 | 23| +|1345 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_551 | 23| +|1346 | reg_17 |xsdbs_v1_0_2_reg__parameterized98 | 27| +|1347 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_550 | 27| +|1348 | reg_18 |xsdbs_v1_0_2_reg__parameterized99 | 29| +|1349 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_549 | 29| +|1350 | reg_19 |xsdbs_v1_0_2_reg__parameterized100 | 18| +|1351 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_548 | 18| +|1352 | reg_1a |xsdbs_v1_0_2_reg__parameterized101 | 26| +|1353 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1 | 26| +|1354 | reg_6 |xsdbs_v1_0_2_reg__parameterized81 | 34| +|1355 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_547 | 34| +|1356 | reg_7 |xsdbs_v1_0_2_reg__parameterized82 | 34| +|1357 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized0 | 34| +|1358 | reg_8 |xsdbs_v1_0_2_reg__parameterized83 | 6| +|1359 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_546 | 6| +|1360 | reg_80 |xsdbs_v1_0_2_reg__parameterized102 | 18| +|1361 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2_545 | 18| +|1362 | reg_81 |xsdbs_v1_0_2_reg__parameterized103 | 17| +|1363 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_544 | 17| +|1364 | reg_82 |xsdbs_v1_0_2_reg__parameterized104 | 17| +|1365 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2 | 17| +|1366 | reg_83 |xsdbs_v1_0_2_reg__parameterized105 | 45| +|1367 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_543 | 45| +|1368 | reg_84 |xsdbs_v1_0_2_reg__parameterized106 | 44| +|1369 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_542 | 44| +|1370 | reg_85 |xsdbs_v1_0_2_reg__parameterized107 | 19| +|1371 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_541 | 19| +|1372 | reg_887 |xsdbs_v1_0_2_reg__parameterized109 | 4| +|1373 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_540 | 4| +|1374 | reg_88d |xsdbs_v1_0_2_reg__parameterized111 | 4| +|1375 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_539 | 4| +|1376 | reg_88f |xsdbs_v1_0_2_reg__parameterized113 | 35| +|1377 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_538 | 35| +|1378 | reg_892 |xsdbs_v1_0_2_reg__parameterized112 | 4| +|1379 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_537 | 4| +|1380 | reg_9 |xsdbs_v1_0_2_reg__parameterized84 | 25| +|1381 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_536 | 25| +|1382 | reg_srl_fff |xsdbs_v1_0_2_reg_p2s__parameterized84 | 94| +|1383 | reg_stream_ffd |xsdbs_v1_0_2_reg_stream__parameterized1 | 18| +|1384 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl | 18| +|1385 | reg_stream_ffe |xsdbs_v1_0_2_reg_stream__parameterized2 | 16| +|1386 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat | 16| +|1387 | u_ila_reset_ctrl |ila_v6_2_9_ila_reset_ctrl | 47| +|1388 | arm_detection_inst |ltlib_v1_0_0_rising_edge_detection | 5| +|1389 | \asyncrounous_transfer.arm_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer | 7| +|1390 | \asyncrounous_transfer.arm_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_532 | 7| +|1391 | \asyncrounous_transfer.halt_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer_533 | 7| +|1392 | \asyncrounous_transfer.halt_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_534 | 6| +|1393 | halt_detection_inst |ltlib_v1_0_0_rising_edge_detection_535 | 6| +|1394 | u_trig |ila_v6_2_9_ila_trigger | 2664| +|1395 | \N_DDR_TC.N_DDR_TC_INST[0].U_TC |ltlib_v1_0_0_match | 34| +|1396 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_524 | 33| +|1397 | DUT |ltlib_v1_0_0_all_typeA_525 | 33| +|1398 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_526 | 5| +|1399 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_527 | 5| +|1400 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_528 | 5| +|1401 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_529 | 5| +|1402 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_530 | 5| +|1403 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_531 | 6| +|1404 | \N_DDR_TC.N_DDR_TC_INST[10].U_TC |ltlib_v1_0_0_match_0 | 34| +|1405 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_516 | 33| +|1406 | DUT |ltlib_v1_0_0_all_typeA_517 | 33| +|1407 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_518 | 5| +|1408 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_519 | 5| +|1409 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_520 | 5| +|1410 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_521 | 5| +|1411 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_522 | 5| +|1412 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_523 | 6| +|1413 | \N_DDR_TC.N_DDR_TC_INST[11].U_TC |ltlib_v1_0_0_match_1 | 34| +|1414 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_508 | 33| +|1415 | DUT |ltlib_v1_0_0_all_typeA_509 | 33| +|1416 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_510 | 5| +|1417 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_511 | 5| +|1418 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_512 | 5| +|1419 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_513 | 5| +|1420 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_514 | 5| +|1421 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_515 | 6| +|1422 | \N_DDR_TC.N_DDR_TC_INST[12].U_TC |ltlib_v1_0_0_match_2 | 34| +|1423 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_500 | 33| +|1424 | DUT |ltlib_v1_0_0_all_typeA_501 | 33| +|1425 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_502 | 5| +|1426 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_503 | 5| +|1427 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_504 | 5| +|1428 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_505 | 5| +|1429 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_506 | 5| +|1430 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_507 | 6| +|1431 | \N_DDR_TC.N_DDR_TC_INST[13].U_TC |ltlib_v1_0_0_match_3 | 34| +|1432 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_492 | 33| +|1433 | DUT |ltlib_v1_0_0_all_typeA_493 | 33| +|1434 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_494 | 5| +|1435 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_495 | 5| +|1436 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_496 | 5| +|1437 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_497 | 5| +|1438 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_498 | 5| +|1439 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_499 | 6| +|1440 | \N_DDR_TC.N_DDR_TC_INST[14].U_TC |ltlib_v1_0_0_match_4 | 34| +|1441 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_484 | 33| +|1442 | DUT |ltlib_v1_0_0_all_typeA_485 | 33| +|1443 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_486 | 5| +|1444 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_487 | 5| +|1445 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_488 | 5| +|1446 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_489 | 5| +|1447 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_490 | 5| +|1448 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_491 | 6| +|1449 | \N_DDR_TC.N_DDR_TC_INST[15].U_TC |ltlib_v1_0_0_match_5 | 34| +|1450 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_476 | 33| +|1451 | DUT |ltlib_v1_0_0_all_typeA_477 | 33| +|1452 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_478 | 5| +|1453 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_479 | 5| +|1454 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_480 | 5| +|1455 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_481 | 5| +|1456 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_482 | 5| +|1457 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_483 | 6| +|1458 | \N_DDR_TC.N_DDR_TC_INST[16].U_TC |ltlib_v1_0_0_match_6 | 34| +|1459 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_468 | 33| +|1460 | DUT |ltlib_v1_0_0_all_typeA_469 | 33| +|1461 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_470 | 5| +|1462 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_471 | 5| +|1463 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_472 | 5| +|1464 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_473 | 5| +|1465 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_474 | 5| +|1466 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_475 | 6| +|1467 | \N_DDR_TC.N_DDR_TC_INST[17].U_TC |ltlib_v1_0_0_match_7 | 34| +|1468 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_460 | 33| +|1469 | DUT |ltlib_v1_0_0_all_typeA_461 | 33| +|1470 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_462 | 5| +|1471 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_463 | 5| +|1472 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_464 | 5| +|1473 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_465 | 5| +|1474 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_466 | 5| +|1475 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_467 | 6| +|1476 | \N_DDR_TC.N_DDR_TC_INST[18].U_TC |ltlib_v1_0_0_match_8 | 34| +|1477 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_452 | 33| +|1478 | DUT |ltlib_v1_0_0_all_typeA_453 | 33| +|1479 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_454 | 5| +|1480 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_455 | 5| +|1481 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_456 | 5| +|1482 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_457 | 5| +|1483 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_458 | 5| +|1484 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_459 | 6| +|1485 | \N_DDR_TC.N_DDR_TC_INST[19].U_TC |ltlib_v1_0_0_match_9 | 34| +|1486 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_444 | 33| +|1487 | DUT |ltlib_v1_0_0_all_typeA_445 | 33| +|1488 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_446 | 5| +|1489 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_447 | 5| +|1490 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_448 | 5| +|1491 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_449 | 5| +|1492 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_450 | 5| +|1493 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_451 | 6| +|1494 | \N_DDR_TC.N_DDR_TC_INST[1].U_TC |ltlib_v1_0_0_match_10 | 34| +|1495 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_436 | 33| +|1496 | DUT |ltlib_v1_0_0_all_typeA_437 | 33| +|1497 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_438 | 5| +|1498 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_439 | 5| +|1499 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_440 | 5| +|1500 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_441 | 5| +|1501 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_442 | 5| +|1502 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_443 | 6| +|1503 | \N_DDR_TC.N_DDR_TC_INST[20].U_TC |ltlib_v1_0_0_match_11 | 34| +|1504 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_428 | 33| +|1505 | DUT |ltlib_v1_0_0_all_typeA_429 | 33| +|1506 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_430 | 5| +|1507 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_431 | 5| +|1508 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_432 | 5| +|1509 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_433 | 5| +|1510 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_434 | 5| +|1511 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_435 | 6| +|1512 | \N_DDR_TC.N_DDR_TC_INST[21].U_TC |ltlib_v1_0_0_match_12 | 34| +|1513 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_420 | 33| +|1514 | DUT |ltlib_v1_0_0_all_typeA_421 | 33| +|1515 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_422 | 5| +|1516 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_423 | 5| +|1517 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_424 | 5| +|1518 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_425 | 5| +|1519 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_426 | 5| +|1520 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_427 | 6| +|1521 | \N_DDR_TC.N_DDR_TC_INST[22].U_TC |ltlib_v1_0_0_match_13 | 34| +|1522 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_412 | 33| +|1523 | DUT |ltlib_v1_0_0_all_typeA_413 | 33| +|1524 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_414 | 5| +|1525 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_415 | 5| +|1526 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_416 | 5| +|1527 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_417 | 5| +|1528 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_418 | 5| +|1529 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_419 | 6| +|1530 | \N_DDR_TC.N_DDR_TC_INST[23].U_TC |ltlib_v1_0_0_match_14 | 34| +|1531 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_404 | 33| +|1532 | DUT |ltlib_v1_0_0_all_typeA_405 | 33| +|1533 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_406 | 5| +|1534 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_407 | 5| +|1535 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_408 | 5| +|1536 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_409 | 5| +|1537 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_410 | 5| +|1538 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_411 | 6| +|1539 | \N_DDR_TC.N_DDR_TC_INST[24].U_TC |ltlib_v1_0_0_match_15 | 34| +|1540 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_396 | 33| +|1541 | DUT |ltlib_v1_0_0_all_typeA_397 | 33| +|1542 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_398 | 5| +|1543 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_399 | 5| +|1544 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_400 | 5| +|1545 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_401 | 5| +|1546 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_402 | 5| +|1547 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_403 | 6| +|1548 | \N_DDR_TC.N_DDR_TC_INST[25].U_TC |ltlib_v1_0_0_match_16 | 34| +|1549 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_388 | 33| +|1550 | DUT |ltlib_v1_0_0_all_typeA_389 | 33| +|1551 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_390 | 5| +|1552 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_391 | 5| +|1553 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_392 | 5| +|1554 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_393 | 5| +|1555 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_394 | 5| +|1556 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_395 | 6| +|1557 | \N_DDR_TC.N_DDR_TC_INST[26].U_TC |ltlib_v1_0_0_match_17 | 34| +|1558 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_380 | 33| +|1559 | DUT |ltlib_v1_0_0_all_typeA_381 | 33| +|1560 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_382 | 5| +|1561 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_383 | 5| +|1562 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_384 | 5| +|1563 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_385 | 5| +|1564 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_386 | 5| +|1565 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_387 | 6| +|1566 | \N_DDR_TC.N_DDR_TC_INST[27].U_TC |ltlib_v1_0_0_match_18 | 34| +|1567 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_372 | 33| +|1568 | DUT |ltlib_v1_0_0_all_typeA_373 | 33| +|1569 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_374 | 5| +|1570 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_375 | 5| +|1571 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_376 | 5| +|1572 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_377 | 5| +|1573 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_378 | 5| +|1574 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_379 | 6| +|1575 | \N_DDR_TC.N_DDR_TC_INST[28].U_TC |ltlib_v1_0_0_match_19 | 34| +|1576 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_364 | 33| +|1577 | DUT |ltlib_v1_0_0_all_typeA_365 | 33| +|1578 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_366 | 5| +|1579 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_367 | 5| +|1580 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_368 | 5| +|1581 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_369 | 5| +|1582 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_370 | 5| +|1583 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_371 | 6| +|1584 | \N_DDR_TC.N_DDR_TC_INST[29].U_TC |ltlib_v1_0_0_match_20 | 34| +|1585 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_356 | 33| +|1586 | DUT |ltlib_v1_0_0_all_typeA_357 | 33| +|1587 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_358 | 5| +|1588 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_359 | 5| +|1589 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_360 | 5| +|1590 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_361 | 5| +|1591 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_362 | 5| +|1592 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_363 | 6| +|1593 | \N_DDR_TC.N_DDR_TC_INST[2].U_TC |ltlib_v1_0_0_match_21 | 34| +|1594 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_348 | 33| +|1595 | DUT |ltlib_v1_0_0_all_typeA_349 | 33| +|1596 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_350 | 5| +|1597 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_351 | 5| +|1598 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_352 | 5| +|1599 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_353 | 5| +|1600 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_354 | 5| +|1601 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_355 | 6| +|1602 | \N_DDR_TC.N_DDR_TC_INST[30].U_TC |ltlib_v1_0_0_match_22 | 34| +|1603 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_340 | 33| +|1604 | DUT |ltlib_v1_0_0_all_typeA_341 | 33| +|1605 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_342 | 5| +|1606 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_343 | 5| +|1607 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_344 | 5| +|1608 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_345 | 5| +|1609 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_346 | 5| +|1610 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_347 | 6| +|1611 | \N_DDR_TC.N_DDR_TC_INST[31].U_TC |ltlib_v1_0_0_match_23 | 34| +|1612 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_332 | 33| +|1613 | DUT |ltlib_v1_0_0_all_typeA_333 | 33| +|1614 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_334 | 5| +|1615 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_335 | 5| +|1616 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_336 | 5| +|1617 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_337 | 5| +|1618 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_338 | 5| +|1619 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_339 | 6| +|1620 | \N_DDR_TC.N_DDR_TC_INST[3].U_TC |ltlib_v1_0_0_match_24 | 34| +|1621 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_324 | 33| +|1622 | DUT |ltlib_v1_0_0_all_typeA_325 | 33| +|1623 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_326 | 5| +|1624 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_327 | 5| +|1625 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_328 | 5| +|1626 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_329 | 5| +|1627 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_330 | 5| +|1628 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_331 | 6| +|1629 | \N_DDR_TC.N_DDR_TC_INST[4].U_TC |ltlib_v1_0_0_match_25 | 34| +|1630 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_316 | 33| +|1631 | DUT |ltlib_v1_0_0_all_typeA_317 | 33| +|1632 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_318 | 5| +|1633 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_319 | 5| +|1634 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_320 | 5| +|1635 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_321 | 5| +|1636 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_322 | 5| +|1637 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_323 | 6| +|1638 | \N_DDR_TC.N_DDR_TC_INST[5].U_TC |ltlib_v1_0_0_match_26 | 34| +|1639 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_308 | 33| +|1640 | DUT |ltlib_v1_0_0_all_typeA_309 | 33| +|1641 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_310 | 5| +|1642 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_311 | 5| +|1643 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_312 | 5| +|1644 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_313 | 5| +|1645 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_314 | 5| +|1646 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_315 | 6| +|1647 | \N_DDR_TC.N_DDR_TC_INST[6].U_TC |ltlib_v1_0_0_match_27 | 34| +|1648 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_300 | 33| +|1649 | DUT |ltlib_v1_0_0_all_typeA_301 | 33| +|1650 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_302 | 5| +|1651 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_303 | 5| +|1652 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_304 | 5| +|1653 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_305 | 5| +|1654 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_306 | 5| +|1655 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_307 | 6| +|1656 | \N_DDR_TC.N_DDR_TC_INST[7].U_TC |ltlib_v1_0_0_match_28 | 34| +|1657 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_292 | 33| +|1658 | DUT |ltlib_v1_0_0_all_typeA_293 | 33| +|1659 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_294 | 5| +|1660 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_295 | 5| +|1661 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_296 | 5| +|1662 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_297 | 5| +|1663 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_298 | 5| +|1664 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_299 | 6| +|1665 | \N_DDR_TC.N_DDR_TC_INST[8].U_TC |ltlib_v1_0_0_match_29 | 34| +|1666 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_284 | 33| +|1667 | DUT |ltlib_v1_0_0_all_typeA_285 | 33| +|1668 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_286 | 5| +|1669 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_287 | 5| +|1670 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_288 | 5| +|1671 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_289 | 5| +|1672 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_290 | 5| +|1673 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_291 | 6| +|1674 | \N_DDR_TC.N_DDR_TC_INST[9].U_TC |ltlib_v1_0_0_match_30 | 34| +|1675 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_276 | 33| +|1676 | DUT |ltlib_v1_0_0_all_typeA_277 | 33| +|1677 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_278 | 5| +|1678 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_279 | 5| +|1679 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_280 | 5| +|1680 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_281 | 5| +|1681 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_282 | 5| +|1682 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_283 | 6| +|1683 | \STRG_QUAL.U_STRG_QUAL |ltlib_v1_0_0_match_31 | 82| +|1684 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA | 81| +|1685 | DUT |ltlib_v1_0_0_all_typeA | 33| +|1686 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_270 | 5| +|1687 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_271 | 5| +|1688 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_272 | 5| +|1689 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_273 | 5| +|1690 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_274 | 5| +|1691 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_275 | 6| +|1692 | U_TM |ila_v6_2_9_ila_trig_match | 1446| +|1693 | \N_DDR_MODE.G_NMU[0].U_M |ltlib_v1_0_0_match__parameterized0 | 12| +|1694 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_267 | 11| +|1695 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_268 | 8| +|1696 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_269 | 6| +|1697 | \N_DDR_MODE.G_NMU[10].U_M |ltlib_v1_0_0_match__parameterized1 | 55| +|1698 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_262 | 54| +|1699 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_263 | 18| +|1700 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_264 | 5| +|1701 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_265 | 5| +|1702 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_266 | 6| +|1703 | \N_DDR_MODE.G_NMU[11].U_M |ltlib_v1_0_0_match__parameterized1_32 | 19| +|1704 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_257 | 18| +|1705 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_258 | 18| +|1706 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_259 | 5| +|1707 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_260 | 5| +|1708 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_261 | 6| +|1709 | \N_DDR_MODE.G_NMU[12].U_M |ltlib_v1_0_0_match__parameterized1_33 | 55| +|1710 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_252 | 54| +|1711 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_253 | 18| +|1712 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_254 | 5| +|1713 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_255 | 5| +|1714 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_256 | 6| +|1715 | \N_DDR_MODE.G_NMU[13].U_M |ltlib_v1_0_0_match__parameterized1_34 | 19| +|1716 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_247 | 18| +|1717 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_248 | 18| +|1718 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_249 | 5| +|1719 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_250 | 5| +|1720 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_251 | 6| +|1721 | \N_DDR_MODE.G_NMU[14].U_M |ltlib_v1_0_0_match__parameterized1_35 | 55| +|1722 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_242 | 54| +|1723 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_243 | 18| +|1724 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_244 | 5| +|1725 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_245 | 5| +|1726 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_246 | 6| +|1727 | \N_DDR_MODE.G_NMU[15].U_M |ltlib_v1_0_0_match__parameterized1_36 | 19| +|1728 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_237 | 18| +|1729 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_238 | 18| +|1730 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_239 | 5| +|1731 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_240 | 5| +|1732 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_241 | 6| +|1733 | \N_DDR_MODE.G_NMU[16].U_M |ltlib_v1_0_0_match__parameterized1_37 | 55| +|1734 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_232 | 54| +|1735 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_233 | 18| +|1736 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_234 | 5| +|1737 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_235 | 5| +|1738 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_236 | 6| +|1739 | \N_DDR_MODE.G_NMU[17].U_M |ltlib_v1_0_0_match__parameterized1_38 | 19| +|1740 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_227 | 18| +|1741 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_228 | 18| +|1742 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_229 | 5| +|1743 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_230 | 5| +|1744 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_231 | 6| +|1745 | \N_DDR_MODE.G_NMU[18].U_M |ltlib_v1_0_0_match__parameterized2 | 25| +|1746 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_224 | 24| +|1747 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_225 | 8| +|1748 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_226 | 6| +|1749 | \N_DDR_MODE.G_NMU[19].U_M |ltlib_v1_0_0_match__parameterized2_39 | 9| +|1750 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_221 | 8| +|1751 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_222 | 8| +|1752 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_223 | 6| +|1753 | \N_DDR_MODE.G_NMU[1].U_M |ltlib_v1_0_0_match__parameterized0_40 | 9| +|1754 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_218 | 8| +|1755 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_219 | 8| +|1756 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_220 | 6| +|1757 | \N_DDR_MODE.G_NMU[20].U_M |ltlib_v1_0_0_match__parameterized2_41 | 25| +|1758 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_215 | 24| +|1759 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_216 | 8| +|1760 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_217 | 6| +|1761 | \N_DDR_MODE.G_NMU[21].U_M |ltlib_v1_0_0_match__parameterized2_42 | 9| +|1762 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_212 | 8| +|1763 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_213 | 8| +|1764 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_214 | 6| +|1765 | \N_DDR_MODE.G_NMU[22].U_M |ltlib_v1_0_0_match__parameterized2_43 | 25| +|1766 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_209 | 24| +|1767 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_210 | 8| +|1768 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_211 | 6| +|1769 | \N_DDR_MODE.G_NMU[23].U_M |ltlib_v1_0_0_match__parameterized2_44 | 9| +|1770 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_206 | 8| +|1771 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_207 | 8| +|1772 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_208 | 6| +|1773 | \N_DDR_MODE.G_NMU[24].U_M |ltlib_v1_0_0_match__parameterized2_45 | 25| +|1774 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_203 | 24| +|1775 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_204 | 8| +|1776 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_205 | 6| +|1777 | \N_DDR_MODE.G_NMU[25].U_M |ltlib_v1_0_0_match__parameterized2_46 | 9| +|1778 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2 | 8| +|1779 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_201 | 8| +|1780 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_202 | 6| +|1781 | \N_DDR_MODE.G_NMU[26].U_M |ltlib_v1_0_0_match__parameterized0_47 | 11| +|1782 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_198 | 10| +|1783 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_199 | 8| +|1784 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_200 | 6| +|1785 | \N_DDR_MODE.G_NMU[27].U_M |ltlib_v1_0_0_match__parameterized0_48 | 9| +|1786 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0 | 8| +|1787 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_196 | 8| +|1788 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_197 | 6| +|1789 | \N_DDR_MODE.G_NMU[28].U_M |ltlib_v1_0_0_match__parameterized3 | 15| +|1790 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized3_193 | 14| +|1791 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_194 | 8| +|1792 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_195 | 6| +|1793 | \N_DDR_MODE.G_NMU[29].U_M |ltlib_v1_0_0_match__parameterized3_49 | 9| +|1794 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized3 | 8| +|1795 | DUT |ltlib_v1_0_0_all_typeA__parameterized0 | 8| +|1796 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_192 | 6| +|1797 | \N_DDR_MODE.G_NMU[2].U_M |ltlib_v1_0_0_match__parameterized1_50 | 70| +|1798 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_187 | 69| +|1799 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_188 | 18| +|1800 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_189 | 5| +|1801 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_190 | 5| +|1802 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_191 | 6| +|1803 | \N_DDR_MODE.G_NMU[30].U_M |ltlib_v1_0_0_match__parameterized4 | 38| +|1804 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_183 | 37| +|1805 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_184 | 13| +|1806 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_185 | 5| +|1807 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_186 | 6| +|1808 | \N_DDR_MODE.G_NMU[31].U_M |ltlib_v1_0_0_match__parameterized4_51 | 14| +|1809 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_179 | 13| +|1810 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_180 | 13| +|1811 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_181 | 5| +|1812 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_182 | 6| +|1813 | \N_DDR_MODE.G_NMU[32].U_M |ltlib_v1_0_0_match__parameterized4_52 | 38| +|1814 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_175 | 37| +|1815 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_176 | 13| +|1816 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_177 | 5| +|1817 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_178 | 6| +|1818 | \N_DDR_MODE.G_NMU[33].U_M |ltlib_v1_0_0_match__parameterized4_53 | 14| +|1819 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_171 | 13| +|1820 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_172 | 13| +|1821 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_173 | 5| +|1822 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_174 | 6| +|1823 | \N_DDR_MODE.G_NMU[34].U_M |ltlib_v1_0_0_match__parameterized1_54 | 55| +|1824 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_166 | 54| +|1825 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_167 | 18| +|1826 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_168 | 5| +|1827 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_169 | 5| +|1828 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_170 | 6| +|1829 | \N_DDR_MODE.G_NMU[35].U_M |ltlib_v1_0_0_match__parameterized1_55 | 19| +|1830 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_161 | 18| +|1831 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_162 | 18| +|1832 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_163 | 5| +|1833 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_164 | 5| +|1834 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_165 | 6| +|1835 | \N_DDR_MODE.G_NMU[36].U_M |ltlib_v1_0_0_match__parameterized1_56 | 55| +|1836 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_156 | 54| +|1837 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_157 | 18| +|1838 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_158 | 5| +|1839 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_159 | 5| +|1840 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_160 | 6| +|1841 | \N_DDR_MODE.G_NMU[37].U_M |ltlib_v1_0_0_match__parameterized1_57 | 19| +|1842 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_151 | 18| +|1843 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_152 | 18| +|1844 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_153 | 5| +|1845 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_154 | 5| +|1846 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_155 | 6| +|1847 | \N_DDR_MODE.G_NMU[38].U_M |ltlib_v1_0_0_match__parameterized1_58 | 55| +|1848 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_146 | 54| +|1849 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_147 | 18| +|1850 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_148 | 5| +|1851 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_149 | 5| +|1852 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_150 | 6| +|1853 | \N_DDR_MODE.G_NMU[39].U_M |ltlib_v1_0_0_match__parameterized1_59 | 19| +|1854 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_141 | 18| +|1855 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_142 | 18| +|1856 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_143 | 5| +|1857 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_144 | 5| +|1858 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_145 | 6| +|1859 | \N_DDR_MODE.G_NMU[3].U_M |ltlib_v1_0_0_match__parameterized1_60 | 19| +|1860 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_136 | 18| +|1861 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_137 | 18| +|1862 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_138 | 5| +|1863 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_139 | 5| +|1864 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_140 | 6| +|1865 | \N_DDR_MODE.G_NMU[40].U_M |ltlib_v1_0_0_match__parameterized1_61 | 55| +|1866 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_131 | 54| +|1867 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_132 | 18| +|1868 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_133 | 5| +|1869 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_134 | 5| +|1870 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_135 | 6| +|1871 | \N_DDR_MODE.G_NMU[41].U_M |ltlib_v1_0_0_match__parameterized1_62 | 19| +|1872 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_126 | 18| +|1873 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_127 | 18| +|1874 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_128 | 5| +|1875 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_129 | 5| +|1876 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_130 | 6| +|1877 | \N_DDR_MODE.G_NMU[42].U_M |ltlib_v1_0_0_match__parameterized1_63 | 55| +|1878 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_121 | 54| +|1879 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_122 | 18| +|1880 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_123 | 5| +|1881 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_124 | 5| +|1882 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_125 | 6| +|1883 | \N_DDR_MODE.G_NMU[43].U_M |ltlib_v1_0_0_match__parameterized1_64 | 19| +|1884 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_116 | 18| +|1885 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_117 | 18| +|1886 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_118 | 5| +|1887 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_119 | 5| +|1888 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_120 | 6| +|1889 | \N_DDR_MODE.G_NMU[44].U_M |ltlib_v1_0_0_match__parameterized5 | 88| +|1890 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5_110 | 87| +|1891 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_111 | 23| +|1892 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_112 | 5| +|1893 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_113 | 5| +|1894 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_114 | 5| +|1895 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_115 | 6| +|1896 | \N_DDR_MODE.G_NMU[45].U_M |ltlib_v1_0_0_match__parameterized5_65 | 24| +|1897 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5 | 23| +|1898 | DUT |ltlib_v1_0_0_all_typeA__parameterized3 | 23| +|1899 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_106 | 5| +|1900 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_107 | 5| +|1901 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_108 | 5| +|1902 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_109 | 6| +|1903 | \N_DDR_MODE.G_NMU[46].U_M |ltlib_v1_0_0_match__parameterized4_66 | 38| +|1904 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_102 | 37| +|1905 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_103 | 13| +|1906 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_104 | 5| +|1907 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_105 | 6| +|1908 | \N_DDR_MODE.G_NMU[47].U_M |ltlib_v1_0_0_match__parameterized4_67 | 14| +|1909 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4 | 13| +|1910 | DUT |ltlib_v1_0_0_all_typeA__parameterized2 | 13| +|1911 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_100 | 5| +|1912 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_101 | 6| +|1913 | \N_DDR_MODE.G_NMU[4].U_M |ltlib_v1_0_0_match__parameterized1_68 | 55| +|1914 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_95 | 54| +|1915 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_96 | 18| +|1916 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_97 | 5| +|1917 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_98 | 5| +|1918 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_99 | 6| +|1919 | \N_DDR_MODE.G_NMU[5].U_M |ltlib_v1_0_0_match__parameterized1_69 | 19| +|1920 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_90 | 18| +|1921 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_91 | 18| +|1922 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_92 | 5| +|1923 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_93 | 5| +|1924 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_94 | 6| +|1925 | \N_DDR_MODE.G_NMU[6].U_M |ltlib_v1_0_0_match__parameterized1_70 | 55| +|1926 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_85 | 54| +|1927 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_86 | 18| +|1928 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_87 | 5| +|1929 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_88 | 5| +|1930 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_89 | 6| +|1931 | \N_DDR_MODE.G_NMU[7].U_M |ltlib_v1_0_0_match__parameterized1_71 | 19| +|1932 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_80 | 18| +|1933 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_81 | 18| +|1934 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_82 | 5| +|1935 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_83 | 5| +|1936 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_84 | 6| +|1937 | \N_DDR_MODE.G_NMU[8].U_M |ltlib_v1_0_0_match__parameterized1_72 | 55| +|1938 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_75 | 54| +|1939 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_76 | 18| +|1940 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_77 | 5| +|1941 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_78 | 5| +|1942 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_79 | 6| +|1943 | \N_DDR_MODE.G_NMU[9].U_M |ltlib_v1_0_0_match__parameterized1_73 | 19| +|1944 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1 | 18| +|1945 | DUT |ltlib_v1_0_0_all_typeA__parameterized1 | 18| +|1946 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice | 5| +|1947 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_74 | 5| +|1948 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0 | 6| +|1949 | xsdb_memory_read_inst |ltlib_v1_0_0_generic_memrd | 1533| ++------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:03:43 ; elapsed = 00:04:03 . Memory (MB): peak = 2689.156 ; gain = 968.766 ; free physical = 449 ; free virtual = 41916 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1001 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:03:36 ; elapsed = 00:04:00 . Memory (MB): peak = 2693.066 ; gain = 899.738 ; free physical = 3293 ; free virtual = 44760 +Synthesis Optimization Complete : Time (s): cpu = 00:03:43 ; elapsed = 00:04:07 . Memory (MB): peak = 2693.066 ; gain = 972.676 ; free physical = 3293 ; free virtual = 44760 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 3690 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2729.176 ; gain = 0.000 ; free physical = 3180 ; free virtual = 44680 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1380 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 1264 instances + CFGLUT5 => SRLC32E: 84 instances + RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 32 instances + +INFO: [Common 17-83] Releasing license: Synthesis +406 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:03:49 ; elapsed = 00:04:13 . Memory (MB): peak = 2729.176 ; gain = 1317.719 ; free physical = 3329 ; free virtual = 44829 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2729.176 ; gain = 0.000 ; free physical = 3329 ; free virtual = 44828 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ila_freq_comp, cache-ID = c85b6423cc6198b8 +INFO: [Coretcl 2-1174] Renamed 1948 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2753.188 ; gain = 0.000 ; free physical = 3218 ; free virtual = 44806 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file ila_freq_comp_utilization_synth.rpt -pb ila_freq_comp_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Tue May 9 13:39:43 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.v new file mode 100644 index 00000000..e946482d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:28bbd13808888eeec92677d70a4630bd5f305d65d412febedaf1a0fbf5ff8655 +size 19954841 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.vhdl new file mode 100644 index 00000000..81bb1801 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dc4cd60578e588c984c2a69ce396150094fc3f9d1d7fc6ee0c37d7812b086045 +size 23892851 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v new file mode 100644 index 00000000..f31ad22b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v @@ -0,0 +1,46 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Tue May 9 13:39:41 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v +// Design : ila_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, + probe18, probe19, probe20, probe21, probe22, probe23) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[31:0],probe23[11:0]" */; + input clk; + input [0:0]probe0; + input [17:0]probe1; + input [17:0]probe2; + input [17:0]probe3; + input [17:0]probe4; + input [17:0]probe5; + input [17:0]probe6; + input [17:0]probe7; + input [17:0]probe8; + input [7:0]probe9; + input [7:0]probe10; + input [7:0]probe11; + input [7:0]probe12; + input [0:0]probe13; + input [2:0]probe14; + input [11:0]probe15; + input [11:0]probe16; + input [17:0]probe17; + input [17:0]probe18; + input [17:0]probe19; + input [17:0]probe20; + input [17:0]probe21; + input [31:0]probe22; + input [11:0]probe23; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl new file mode 100644 index 00000000..c8f4b61c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl @@ -0,0 +1,54 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Tue May 9 13:39:41 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl +-- Design : ila_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_freq_comp is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + probe13 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe14 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + probe15 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe16 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe17 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe18 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe19 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe20 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe21 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe22 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe23 : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + +end ila_freq_comp; + +architecture stub of ila_freq_comp is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[31:0],probe23[11:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.pb new file mode 100644 index 00000000..3dd0ce9d Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.rpt new file mode 100644 index 00000000..84d5da51 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.rpt @@ -0,0 +1,192 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Tue May 9 13:39:41 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file ila_freq_comp_utilization_synth.rpt -pb ila_freq_comp_utilization_synth.pb +| Design : ila_freq_comp +| Device : 7z100ffg900-2 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 7340 | 0 | 277400 | 2.65 | +| LUT as Logic | 5498 | 0 | 277400 | 1.98 | +| LUT as Memory | 1842 | 0 | 108200 | 1.70 | +| LUT as Distributed RAM | 128 | 0 | | | +| LUT as Shift Register | 1714 | 0 | | | +| Slice Registers | 7116 | 0 | 554800 | 1.28 | +| Register as Flip Flop | 7116 | 0 | 554800 | 1.28 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 880 | 0 | 138700 | 0.63 | +| F8 Muxes | 396 | 0 | 69350 | 0.57 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 12 | Yes | Set | - | +| 7104 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------+------+-------+-----------+-------+ +| Block RAM Tile | 606 | 0 | 755 | 80.26 | +| RAMB36/FIFO* | 606 | 0 | 755 | 80.26 | +| RAMB36E1 only | 606 | | | | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++-------------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 7104 | Flop & Latch | +| LUT6 | 3653 | LUT | +| SRL16E | 1611 | Distributed Memory | +| SRLC32E | 1365 | Distributed Memory | +| LUT4 | 892 | LUT | +| MUXF7 | 880 | MuxFx | +| LUT3 | 765 | LUT | +| RAMB36E1 | 606 | Block Memory | +| CARRY4 | 428 | CarryLogic | +| MUXF8 | 396 | MuxFx | +| LUT5 | 224 | LUT | +| LUT2 | 212 | LUT | +| RAMD64E | 128 | Distributed Memory | +| LUT1 | 118 | LUT | +| FDSE | 12 | Flop & Latch | +| SRLC16E | 2 | Distributed Memory | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/project.wdf new file mode 100644 index 00000000..504e4560 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/project.wdf @@ -0,0 +1,41 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3233:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 +eof:730324547 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/rundef.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/rundef.js new file mode 100644 index 00000000..6642aa6b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log ila_freq_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_freq_comp.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/runme.bat b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/runme.sh new file mode 100755 index 00000000..cc6e8027 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log ila_freq_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_freq_comp.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/vivado.pb new file mode 100644 index 00000000..be514388 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..42f4ac1d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/ISEWrap.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/ISEWrap.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/dont_touch.xdc b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/dont_touch.xdc new file mode 100644 index 00000000..05221a0e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/dont_touch.xdc @@ -0,0 +1,16 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18.xci +# IP: The module: 'mult_18x18' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'mult_18x18'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18.xci +# IP: The module: 'mult_18x18' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'mult_18x18'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml new file mode 100644 index 00000000..12202685 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/htr.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/htr.txt new file mode 100644 index 00000000..e53ca721 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log mult_18x18.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source mult_18x18.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.dcp new file mode 100644 index 00000000..a1fdc992 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:da17b9818fb583c3b08bd977b78a9477a0b2a2f1f7c56156d8051e517e241711 +size 156939 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.tcl new file mode 100644 index 00000000..85a64799 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.tcl @@ -0,0 +1,156 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1 -new_name mult_18x18 -ip [get_ips mult_18x18]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top mult_18x18 -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix mult_18x18_ mult_18x18.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_18x18_stub.v + lappend ipCachedFiles mult_18x18_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_18x18_stub.vhdl + lappend ipCachedFiles mult_18x18_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_18x18_sim_netlist.v + lappend ipCachedFiles mult_18x18_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_18x18_sim_netlist.vhdl + lappend ipCachedFiles mult_18x18_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp mult_18x18.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips mult_18x18] +} + +rename_ref -prefix_all mult_18x18_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef mult_18x18.dcp +create_report "mult_18x18_synth_1_synth_report_utilization_0" "report_utilization -file mult_18x18_utilization_synth.rpt -pb mult_18x18_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/mult_18x18]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/mult_18x18 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/mult_18x18]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/mult_18x18 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/mult_18x18]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/mult_18x18 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/mult_18x18]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/mult_18x18 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.vds new file mode 100644 index 00000000..151fb3e7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.vds @@ -0,0 +1,306 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Mon May 8 13:15:05 2023 +# Process ID: 2006877 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1 +# Command line: vivado -log mult_18x18.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source mult_18x18.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/vivado.jou +#----------------------------------------------------------- +source mult_18x18.tcl -notrace +Command: synth_design -top mult_18x18 -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2007151 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1854.387 ; gain = 153.719 ; free physical = 818 ; free virtual = 39698 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'mult_18x18' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/synth/mult_18x18.vhd:68] +WARNING: [Synth 8-5640] Port 'zero_detect' is missing in component declaration [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/synth/mult_18x18.vhd:71] +WARNING: [Synth 8-5640] Port 'pcasc' is missing in component declaration [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/synth/mult_18x18.vhd:71] + Parameter C_VERBOSITY bound to: 0 - type: integer + Parameter C_MODEL_TYPE bound to: 0 - type: integer + Parameter C_OPTIMIZE_GOAL bound to: 1 - type: integer + Parameter C_XDEVICEFAMILY bound to: zynq - type: string + Parameter C_HAS_CE bound to: 0 - type: integer + Parameter C_HAS_SCLR bound to: 0 - type: integer + Parameter C_LATENCY bound to: 5 - type: integer + Parameter C_A_WIDTH bound to: 18 - type: integer + Parameter C_A_TYPE bound to: 0 - type: integer + Parameter C_B_WIDTH bound to: 18 - type: integer + Parameter C_B_TYPE bound to: 0 - type: integer + Parameter C_OUT_HIGH bound to: 35 - type: integer + Parameter C_OUT_LOW bound to: 0 - type: integer + Parameter C_MULT_TYPE bound to: 0 - type: integer + Parameter C_CE_OVERRIDES_SCLR bound to: 0 - type: integer + Parameter C_CCM_IMP bound to: 0 - type: integer + Parameter C_B_VALUE bound to: 10000001 - type: string + Parameter C_HAS_ZERO_DETECT bound to: 0 - type: integer + Parameter C_ROUND_OUTPUT bound to: 0 - type: integer + Parameter C_ROUND_PT bound to: 0 - type: integer +INFO: [Synth 8-3491] module 'mult_gen_v12_0_15' declared at '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/hdl/mult_gen_v12_0_vh_rfs.vhd:21013' bound to instance 'U0' of component 'mult_gen_v12_0_15' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/synth/mult_18x18.vhd:120] +INFO: [Synth 8-256] done synthesizing module 'mult_18x18' (5#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/synth/mult_18x18.vhd:68] +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port CE +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port SCLR +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1929.105 ; gain = 228.438 ; free physical = 998 ; free virtual = 39401 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1932.074 ; gain = 231.406 ; free physical = 914 ; free virtual = 39316 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1932.074 ; gain = 231.406 ; free physical = 914 ; free virtual = 39316 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 522 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/mult_18x18/mult_18x18_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2107.793 ; gain = 0.000 ; free physical = 897 ; free virtual = 39149 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 171 instances were transformed. + MULT_AND => LUT2: 171 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2107.793 ; gain = 0.000 ; free physical = 926 ; free virtual = 39173 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 1000 ; free virtual = 39251 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 1002 ; free virtual = 39253 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 999 ; free virtual = 39250 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 1075 ; free virtual = 39338 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port CE +WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port SCLR +INFO: [Synth 8-3886] merging instance 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[0][21]' (FDR) to 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[0][22]' +INFO: [Synth 8-3886] merging instance 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[1][21]' (FDR) to 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[1][22]' +INFO: [Synth 8-3886] merging instance 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][21]' (FDR) to 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][22]' +INFO: [Synth 8-3886] merging instance 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[3][21]' (FDR) to 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[3][22]' +INFO: [Synth 8-3886] merging instance 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_2_add.stage_2_pipeline.s2_add_out_reg[0][26]' (FDR) to 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_2_add.stage_2_pipeline.s2_add_out_reg[0][27]' +INFO: [Synth 8-3886] merging instance 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_2_add.stage_2_pipeline.s2_add_out_reg[1][26]' (FDR) to 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_2_add.stage_2_pipeline.s2_add_out_reg[1][27]' +INFO: [Synth 8-3886] merging instance 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_3_add.stage_3_pipeline.s3_add_out_reg[0][36]' (FDR) to 'U0/i_mult/gLUT.gLUT_speed.iLUT/NxM_mult.stage_3_add.stage_3_pipeline.s3_add_out_reg[0][35]' +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 938 ; free virtual = 39204 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 914 ; free virtual = 38780 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 908 ; free virtual = 38769 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 926 ; free virtual = 38742 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 990 ; free virtual = 38706 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 990 ; free virtual = 38706 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 973 ; free virtual = 38689 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 975 ; free virtual = 38691 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 961 ; free virtual = 38678 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 959 ; free virtual = 38675 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |CARRY4 | 44| +|2 |LUT1 | 7| +|3 |LUT2 | 181| +|4 |LUT3 | 18| +|5 |LUT4 | 153| +|6 |MULT_AND | 170| +|7 |MUXCY | 171| +|8 |SRL16E | 24| +|9 |XORCY | 180| +|10 |FDRE | 404| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 958 ; free virtual = 38675 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2107.793 ; gain = 231.406 ; free physical = 973 ; free virtual = 38689 +Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2107.793 ; gain = 407.125 ; free physical = 973 ; free virtual = 38689 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 565 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +WARNING: [Netlist 29-101] Netlist 'mult_18x18' is not ideal for floorplanning, since the cellview 'luts' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2107.793 ; gain = 0.000 ; free physical = 1270 ; free virtual = 38864 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 215 instances were transformed. + (MUXCY,XORCY) => CARRY4: 45 instances + MULT_AND => LUT2: 170 instances + +INFO: [Common 17-83] Releasing license: Synthesis +23 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2107.793 ; gain = 692.152 ; free physical = 1867 ; free virtual = 39462 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2107.793 ; gain = 0.000 ; free physical = 1867 ; free virtual = 39462 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP mult_18x18, cache-ID = 24988ad35bfeaaca +INFO: [Coretcl 2-1174] Renamed 3 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2107.793 ; gain = 0.000 ; free physical = 1951 ; free virtual = 39548 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file mult_18x18_utilization_synth.rpt -pb mult_18x18_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon May 8 13:15:26 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.v new file mode 100644 index 00000000..0133b6dc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6f1851b0ea6dbdb3391593fb3405cd201581c9f4fbd0c99cca1b9a9b0ffc891f +size 602664 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.vhdl new file mode 100644 index 00000000..a9532eca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8c549a092d1c9191779fc8f0fdedea59f8322da1932e55224cf9426c95f883bb +size 798082 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.v new file mode 100644 index 00000000..e64951e6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:26 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.v +// Design : mult_18x18 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "mult_gen_v12_0_15,Vivado 2019.1.3" *) +module mult_18x18(CLK, A, B, P) +/* synthesis syn_black_box black_box_pad_pin="CLK,A[17:0],B[17:0],P[35:0]" */; + input CLK; + input [17:0]A; + input [17:0]B; + output [35:0]P; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.vhdl new file mode 100644 index 00000000..ff7c77f8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.vhdl @@ -0,0 +1,33 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:26 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.vhdl +-- Design : mult_18x18 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity mult_18x18 is + Port ( + CLK : in STD_LOGIC; + A : in STD_LOGIC_VECTOR ( 17 downto 0 ); + B : in STD_LOGIC_VECTOR ( 17 downto 0 ); + P : out STD_LOGIC_VECTOR ( 35 downto 0 ) + ); + +end mult_18x18; + +architecture stub of mult_18x18 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "CLK,A[17:0],B[17:0],P[35:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "mult_gen_v12_0_15,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_utilization_synth.pb new file mode 100644 index 00000000..775984de Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_utilization_synth.rpt new file mode 100644 index 00000000..59d00eb5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_utilization_synth.rpt @@ -0,0 +1,182 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Mon May 8 13:15:25 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file mult_18x18_utilization_synth.rpt -pb mult_18x18_utilization_synth.pb +| Design : mult_18x18 +| Device : 7z100ffg900-2 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 375 | 0 | 277400 | 0.14 | +| LUT as Logic | 351 | 0 | 277400 | 0.13 | +| LUT as Memory | 24 | 0 | 108200 | 0.02 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 24 | 0 | | | +| Slice Registers | 404 | 0 | 554800 | 0.07 | +| Register as Flip Flop | 404 | 0 | 554800 | 0.07 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 404 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 404 | Flop & Latch | +| LUT2 | 351 | LUT | +| LUT4 | 153 | LUT | +| CARRY4 | 89 | CarryLogic | +| SRL16E | 24 | Distributed Memory | +| LUT3 | 18 | LUT | +| LUT1 | 7 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/project.wdf new file mode 100644 index 00000000..c1ef2fc1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/project.wdf @@ -0,0 +1,41 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3130:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 +eof:3099610940 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/rundef.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/rundef.js new file mode 100644 index 00000000..7dcb9689 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log mult_18x18.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source mult_18x18.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/runme.bat b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/runme.sh new file mode 100755 index 00000000..987b7b89 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log mult_18x18.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source mult_18x18.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/vivado.pb new file mode 100644 index 00000000..20663095 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..53b48039 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc new file mode 100644 index 00000000..ef0e7173 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc @@ -0,0 +1,16 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word.xci +# IP: The module: 'rom_freq_word' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'rom_freq_word'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word.xci +# IP: The module: 'rom_freq_word' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'rom_freq_word'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml new file mode 100644 index 00000000..b1fba6e9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/htr.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/htr.txt new file mode 100644 index 00000000..144dc12a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log rom_freq_word.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf new file mode 100644 index 00000000..23ee2ccf --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf @@ -0,0 +1,41 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3139:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 +eof:400008829 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp new file mode 100644 index 00000000..b81d6572 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9b82458d37a42e8d123d70b19812d27cad0d81b5184a89e2e60a715d1c5a43d3 +size 27132 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl new file mode 100644 index 00000000..21a990e6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl @@ -0,0 +1,156 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1 -new_name rom_freq_word -ip [get_ips rom_freq_word]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top rom_freq_word -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix rom_freq_word_ rom_freq_word.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v + lappend ipCachedFiles rom_freq_word_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl + lappend ipCachedFiles rom_freq_word_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_sim_netlist.v + lappend ipCachedFiles rom_freq_word_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_sim_netlist.vhdl + lappend ipCachedFiles rom_freq_word_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp rom_freq_word.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips rom_freq_word] +} + +rename_ref -prefix_all rom_freq_word_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef rom_freq_word.dcp +create_report "rom_freq_word_synth_1_synth_report_utilization_0" "report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/rom_freq_word]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/rom_freq_word + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/rom_freq_word]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/rom_freq_word + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/rom_freq_word]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/rom_freq_word + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/rom_freq_word]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/rom_freq_word + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds new file mode 100644 index 00000000..984a4288 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds @@ -0,0 +1,451 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Mon May 8 17:27:36 2023 +# Process ID: 2463293 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1 +# Command line: vivado -log rom_freq_word.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.jou +#----------------------------------------------------------- +source rom_freq_word.tcl -notrace +Command: synth_design -top rom_freq_word -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2463410 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1855.602 ; gain = 153.688 ; free physical = 849 ; free virtual = 46113 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'rom_freq_word' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/synth/rom_freq_word.vhd:67] + Parameter C_FAMILY bound to: zynq - type: string + Parameter C_XDEVICEFAMILY bound to: zynq - type: string + Parameter C_ELABORATION_DIR bound to: ./ - type: string + Parameter C_INTERFACE_TYPE bound to: 0 - type: integer + Parameter C_AXI_TYPE bound to: 1 - type: integer + Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer + Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer + Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer + Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string + Parameter C_HAS_AXI_ID bound to: 0 - type: integer + Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_MEM_TYPE bound to: 3 - type: integer + Parameter C_BYTE_SIZE bound to: 9 - type: integer + Parameter C_ALGORITHM bound to: 1 - type: integer + Parameter C_PRIM_TYPE bound to: 1 - type: integer + Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer + Parameter C_INIT_FILE_NAME bound to: rom_freq_word.mif - type: string + Parameter C_INIT_FILE bound to: rom_freq_word.mem - type: string + Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer + Parameter C_DEFAULT_DATA bound to: 0 - type: string + Parameter C_HAS_RSTA bound to: 0 - type: integer + Parameter C_RST_PRIORITY_A bound to: CE - type: string + Parameter C_RSTRAM_A bound to: 0 - type: integer + Parameter C_INITA_VAL bound to: 0 - type: string + Parameter C_HAS_ENA bound to: 0 - type: integer + Parameter C_HAS_REGCEA bound to: 0 - type: integer + Parameter C_USE_BYTE_WEA bound to: 0 - type: integer + Parameter C_WEA_WIDTH bound to: 1 - type: integer + Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string + Parameter C_WRITE_WIDTH_A bound to: 16 - type: integer + Parameter C_READ_WIDTH_A bound to: 16 - type: integer + Parameter C_WRITE_DEPTH_A bound to: 81 - type: integer + Parameter C_READ_DEPTH_A bound to: 81 - type: integer + Parameter C_ADDRA_WIDTH bound to: 7 - type: integer + Parameter C_HAS_RSTB bound to: 0 - type: integer + Parameter C_RST_PRIORITY_B bound to: CE - type: string + Parameter C_RSTRAM_B bound to: 0 - type: integer + Parameter C_INITB_VAL bound to: 0 - type: string + Parameter C_HAS_ENB bound to: 0 - type: integer + Parameter C_HAS_REGCEB bound to: 0 - type: integer + Parameter C_USE_BYTE_WEB bound to: 0 - type: integer + Parameter C_WEB_WIDTH bound to: 1 - type: integer + Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string + Parameter C_WRITE_WIDTH_B bound to: 16 - type: integer + Parameter C_READ_WIDTH_B bound to: 16 - type: integer + Parameter C_WRITE_DEPTH_B bound to: 81 - type: integer + Parameter C_READ_DEPTH_B bound to: 81 - type: integer + Parameter C_ADDRB_WIDTH bound to: 7 - type: integer + Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 1 - type: integer + Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer + Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer + Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer + Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_USE_SOFTECC bound to: 0 - type: integer + Parameter C_USE_ECC bound to: 0 - type: integer + Parameter C_EN_ECC_PIPE bound to: 0 - type: integer + Parameter C_READ_LATENCY_A bound to: 1 - type: integer + Parameter C_READ_LATENCY_B bound to: 1 - type: integer + Parameter C_HAS_INJECTERR bound to: 0 - type: integer + Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string + Parameter C_COMMON_CLK bound to: 0 - type: integer + Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer + Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer + Parameter C_USE_URAM bound to: 0 - type: integer + Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer + Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer + Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer + Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer + Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer + Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer + Parameter C_COUNT_36K_BRAM bound to: 0 - type: string + Parameter C_COUNT_18K_BRAM bound to: 1 - type: string + Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 2.7096 mW - type: string +INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_3' declared at '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_3' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/synth/rom_freq_word.vhd:230] +INFO: [Synth 8-256] done synthesizing module 'rom_freq_word' (9#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/synth/rom_freq_word.vhd:67] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ENB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port REGCEB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[35] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[34] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[33] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[32] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[31] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[30] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[29] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[28] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[27] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[26] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[25] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[24] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[23] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[22] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[21] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[20] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[19] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[18] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[17] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[16] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[15] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[14] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[13] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[12] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[11] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[10] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[9] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SLEEP +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ECCPIPECE +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstram_b +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstreg_b +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTA[0] +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[1] +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port REGCEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[15] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[14] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[13] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[12] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[11] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[10] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[9] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[8] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[7] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[6] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[5] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[4] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[3] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[2] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[1] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[0] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port SBITERR_I +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DBITERR_I +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[6] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[5] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[4] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[3] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[2] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[1] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[0] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port RSTA +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ENA +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port REGCEA +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port WEA[0] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[15] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[14] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[13] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[12] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[11] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[10] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[9] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2071.281 ; gain = 369.367 ; free physical = 873 ; free virtual = 46135 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2083.156 ; gain = 381.242 ; free physical = 873 ; free virtual = 46135 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2083.156 ; gain = 381.242 ; free physical = 873 ; free virtual = 46135 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2156.094 ; gain = 0.000 ; free physical = 781 ; free virtual = 46043 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2156.094 ; gain = 0.000 ; free physical = 781 ; free virtual = 46043 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 858 ; free virtual = 46121 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 858 ; free virtual = 46121 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 858 ; free virtual = 46121 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 861 ; free virtual = 46124 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 857 ; free virtual = 46126 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 738 ; free virtual = 46007 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 738 ; free virtual = 46007 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 733 ; free virtual = 46002 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 733 ; free virtual = 46003 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 733 ; free virtual = 46003 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 733 ; free virtual = 46003 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 733 ; free virtual = 46003 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 733 ; free virtual = 46003 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 733 ; free virtual = 46003 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |RAMB18E1 | 1| ++------+---------+------+ + +Report Instance Areas: ++------+---------------------------------------------+------------------------------+------+ +| |Instance |Module |Cells | ++------+---------------------------------------------+------------------------------+------+ +|1 |top | | 1| +|2 | U0 |blk_mem_gen_v8_4_3 | 1| +|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 1| +|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 1| +|5 | \valid.cstr |blk_mem_gen_generic_cstr | 1| +|6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1| +|7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| ++------+---------------------------------------------+------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 733 ; free virtual = 46003 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 179 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2156.094 ; gain = 381.242 ; free physical = 787 ; free virtual = 46056 +Synthesis Optimization Complete : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2156.094 ; gain = 454.180 ; free physical = 787 ; free virtual = 46056 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2156.094 ; gain = 0.000 ; free physical = 735 ; free virtual = 46004 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2156.094 ; gain = 761.113 ; free physical = 824 ; free virtual = 46093 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2156.094 ; gain = 0.000 ; free physical = 824 ; free virtual = 46093 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rom_freq_word, cache-ID = 8670630cc237b23c +INFO: [Coretcl 2-1174] Renamed 6 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2156.094 ; gain = 0.000 ; free physical = 833 ; free virtual = 46102 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon May 8 17:28:20 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v new file mode 100644 index 00000000..4efbdb17 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d8970a9429c1d09aa63a439ff99735db17ada2a4562d08614a0cc8de0d18b647 +size 28696 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl new file mode 100644 index 00000000..fb2748a9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:08a5871f0563ea46fef07f09505d439930977a1dd68fd0168dddb2826b39a3a0 +size 42195 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v new file mode 100644 index 00000000..b0ec3d6e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 17:28:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module rom_freq_word(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[15:0]" */; + input clka; + input [6:0]addra; + output [15:0]douta; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl new file mode 100644 index 00000000..b7be094b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 17:28:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity rom_freq_word is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end rom_freq_word; + +architecture stub of rom_freq_word is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.pb new file mode 100644 index 00000000..343f2870 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt new file mode 100644 index 00000000..eb63b56c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt @@ -0,0 +1,175 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Mon May 8 17:28:20 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb +| Design : rom_freq_word +| Device : 7z100ffg900-2 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 0 | 0 | 277400 | 0.00 | +| LUT as Logic | 0 | 0 | 277400 | 0.00 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 0 | 0 | 554800 | 0.00 | +| Register as Flip Flop | 0 | 0 | 554800 | 0.00 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------+------+-------+-----------+-------+ +| Block RAM Tile | 0.5 | 0 | 755 | 0.07 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 1 | 0 | 1510 | 0.07 | +| RAMB18E1 only | 1 | | | | ++-------------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| RAMB18E1 | 1 | Block Memory | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js new file mode 100644 index 00000000..f8e5a2e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log rom_freq_word.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.bat b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh new file mode 100755 index 00000000..05095a10 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log rom_freq_word.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb new file mode 100644 index 00000000..fef52023 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..55aa00b2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/ISEWrap.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/ISEWrap.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml new file mode 100644 index 00000000..da8950f1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/htr.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/htr.txt new file mode 100644 index 00000000..3ab68961 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log vio_freq_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_freq_comp.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf new file mode 100644 index 00000000..c1ef2fc1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf @@ -0,0 +1,41 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3130:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 +eof:3099610940 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/rundef.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/rundef.js new file mode 100644 index 00000000..b52d876f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log vio_freq_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_freq_comp.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/runme.bat b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/runme.sh new file mode 100755 index 00000000..2bff452c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log vio_freq_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_freq_comp.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp new file mode 100644 index 00000000..0ed17db4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c220c5a859a43924996f76569432e04e0649230e0f3869f1979d1665fb4dd5b9 +size 142892 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl new file mode 100644 index 00000000..cb130ecf --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl @@ -0,0 +1,155 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1 -new_name vio_freq_comp -ip [get_ips vio_freq_comp]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top vio_freq_comp -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix vio_freq_comp_ vio_freq_comp.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_freq_comp_stub.v + lappend ipCachedFiles vio_freq_comp_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_freq_comp_stub.vhdl + lappend ipCachedFiles vio_freq_comp_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_freq_comp_sim_netlist.v + lappend ipCachedFiles vio_freq_comp_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_freq_comp_sim_netlist.vhdl + lappend ipCachedFiles vio_freq_comp_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp vio_freq_comp.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_freq_comp] +} + +rename_ref -prefix_all vio_freq_comp_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef vio_freq_comp.dcp +create_report "vio_freq_comp_synth_1_synth_report_utilization_0" "report_utilization -file vio_freq_comp_utilization_synth.rpt -pb vio_freq_comp_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds new file mode 100644 index 00000000..0a2f9e10 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds @@ -0,0 +1,561 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Mon May 8 13:15:05 2023 +# Process ID: 2006878 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1 +# Command line: vivado -log vio_freq_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_freq_comp.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.jou +#----------------------------------------------------------- +source vio_freq_comp.tcl -notrace +Command: synth_design -top vio_freq_comp -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2007149 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1858.629 ; gain = 152.719 ; free physical = 861 ; free virtual = 39827 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'vio_freq_comp' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/synth/vio_freq_comp.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_freq_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/synth/vio_freq_comp.v:78] +INFO: [Synth 8-6155] done synthesizing module 'vio_freq_comp' (8#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/synth/vio_freq_comp.v:59] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_in_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in36[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in37[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in38[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in39[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in40[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in41[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in42[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in43[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in44[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in45[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in46[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in47[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in48[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in49[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in50[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in51[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in52[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in53[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in54[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in55[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in56[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in57[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in58[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in59[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in60[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in61[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in62[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in63[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in64[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in65[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in66[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in67[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in68[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in69[0] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1921.316 ; gain = 215.406 ; free physical = 880 ; free virtual = 39551 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1924.285 ; gain = 218.375 ; free physical = 839 ; free virtual = 39475 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1924.285 ; gain = 218.375 ; free physical = 839 ; free virtual = 39475 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2096.973 ; gain = 0.000 ; free physical = 914 ; free virtual = 39183 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2103.910 ; gain = 6.938 ; free physical = 910 ; free virtual = 39179 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 1087 ; free virtual = 39333 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 1087 ; free virtual = 39333 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 1082 ; free virtual = 39328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 1065 ; free virtual = 39315 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 + 2 Input 1 Bit Adders := 1 ++---Registers : + 128 Bit Registers := 1 + 32 Bit Registers := 1 + 16 Bit Registers := 13 + 8 Bit Registers := 1 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 3 Bit Registers := 2 + 2 Bit Registers := 2 + 1 Bit Registers := 25 ++---Muxes : + 2 Input 16 Bit Muxes := 3 + 4 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module vio_v3_0_20_probe_in_one +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 6 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 8 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized1 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_all +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 6 ++---Muxes : + 4 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 2 +Module vio_v3_0_20_probe_width +Detailed RTL Component Info : ++---Adders : + 2 Input 1 Bit Adders := 1 ++---Registers : + 16 Bit Registers := 1 + 1 Bit Registers := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_decoder +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 3 Bit Registers := 2 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module vio_v3_0_20_vio +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[1]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FDS) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FDS) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[10] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]' (FDS) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[13]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[14]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[15] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 1022 ; free virtual = 39277 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 925 ; free virtual = 38886 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 924 ; free virtual = 38885 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 922 ; free virtual = 38872 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 925 ; free virtual = 38742 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 924 ; free virtual = 38740 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 913 ; free virtual = 38729 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 911 ; free virtual = 38728 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 915 ; free virtual = 38732 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 915 ; free virtual = 38731 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT1 | 1| +|2 |LUT2 | 8| +|3 |LUT3 | 51| +|4 |LUT4 | 11| +|5 |LUT5 | 13| +|6 |LUT6 | 84| +|7 |FDRE | 355| +|8 |FDSE | 4| ++------+-----+------+ + +Report Instance Areas: ++------+---------------------------------------+------------------------------------------+------+ +| |Instance |Module |Cells | ++------+---------------------------------------+------------------------------------------+------+ +|1 |top | | 527| +|2 | inst |vio_v3_0_20_vio | 527| +|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| +|4 | DECODER_INST |vio_v3_0_20_decoder | 80| +|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 18| +|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 163| +|7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| +|8 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 16| +|9 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| +|10 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 105| +|11 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 2| ++------+---------------------------------------+------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 914 ; free virtual = 38731 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 292 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2103.910 ; gain = 218.375 ; free physical = 947 ; free virtual = 38763 +Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 947 ; free virtual = 38763 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2103.910 ; gain = 0.000 ; free physical = 900 ; free virtual = 38616 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +67 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2103.910 ; gain = 706.934 ; free physical = 991 ; free virtual = 38707 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2103.910 ; gain = 0.000 ; free physical = 991 ; free virtual = 38707 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_freq_comp, cache-ID = 93753bc8666fbd09 +INFO: [Coretcl 2-1174] Renamed 10 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2127.922 ; gain = 0.000 ; free physical = 957 ; free virtual = 38646 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file vio_freq_comp_utilization_synth.rpt -pb vio_freq_comp_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon May 8 13:15:25 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v new file mode 100644 index 00000000..daabb4af --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c34539843f7fa4c5906209eef95783110cbf58f52a239344578ff4d3cfabfab3 +size 347789 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl new file mode 100644 index 00000000..ced3f879 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ab1d7e314e1d93fce13386e493892ccc6fd24d37980345a48e6d890ba0520334 +size 625987 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v new file mode 100644 index 00000000..85124391 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:24 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v +// Design : vio_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]" */; + input clk; + input [0:0]probe_in0; + output [0:0]probe_out0; + output [7:0]probe_out1; + output [0:0]probe_out2; + output [31:0]probe_out3; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl new file mode 100644 index 00000000..015c276d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:24 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl +-- Design : vio_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_freq_comp is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end vio_freq_comp; + +architecture stub of vio_freq_comp is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb new file mode 100644 index 00000000..990c3d13 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt new file mode 100644 index 00000000..18e76da6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt @@ -0,0 +1,181 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Mon May 8 13:15:24 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file vio_freq_comp_utilization_synth.rpt -pb vio_freq_comp_utilization_synth.pb +| Design : vio_freq_comp +| Device : 7z100ffg900-2 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 141 | 0 | 277400 | 0.05 | +| LUT as Logic | 141 | 0 | 277400 | 0.05 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 359 | 0 | 554800 | 0.06 | +| Register as Flip Flop | 359 | 0 | 554800 | 0.06 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 4 | Yes | Set | - | +| 355 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 355 | Flop & Latch | +| LUT6 | 84 | LUT | +| LUT3 | 51 | LUT | +| LUT5 | 13 | LUT | +| LUT4 | 11 | LUT | +| LUT2 | 8 | LUT | +| FDSE | 4 | Flop & Latch | +| LUT1 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb new file mode 100644 index 00000000..a8c04925 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..08f9df91 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml new file mode 100644 index 00000000..4769398c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/htr.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/htr.txt new file mode 100644 index 00000000..998ecb35 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log vio_manual_ctrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf new file mode 100644 index 00000000..c1ef2fc1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf @@ -0,0 +1,41 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3130:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 +eof:3099610940 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/rundef.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/rundef.js new file mode 100644 index 00000000..33a47a99 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log vio_manual_ctrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.bat b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh new file mode 100755 index 00000000..d359fed1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log vio_manual_ctrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp new file mode 100644 index 00000000..1bb58ba3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9e754cee11d6ce89b84841de562958e26d4f1ed234f7df289458de4568da337c +size 144617 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl new file mode 100644 index 00000000..7a566647 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl @@ -0,0 +1,155 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1 -new_name vio_manual_ctrl -ip [get_ips vio_manual_ctrl]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top vio_manual_ctrl -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix vio_manual_ctrl_ vio_manual_ctrl.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.v + lappend ipCachedFiles vio_manual_ctrl_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.vhdl + lappend ipCachedFiles vio_manual_ctrl_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_sim_netlist.v + lappend ipCachedFiles vio_manual_ctrl_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_sim_netlist.vhdl + lappend ipCachedFiles vio_manual_ctrl_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp vio_manual_ctrl.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_manual_ctrl] +} + +rename_ref -prefix_all vio_manual_ctrl_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef vio_manual_ctrl.dcp +create_report "vio_manual_ctrl_synth_1_synth_report_utilization_0" "report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_manual_ctrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_manual_ctrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_manual_ctrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_manual_ctrl + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds new file mode 100644 index 00000000..c4ad8a9d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds @@ -0,0 +1,575 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Mon May 8 13:15:05 2023 +# Process ID: 2006883 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1 +# Command line: vivado -log vio_manual_ctrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.jou +#----------------------------------------------------------- +source vio_manual_ctrl.tcl -notrace +Command: synth_design -top vio_manual_ctrl -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2007290 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1859.539 ; gain = 152.719 ; free physical = 908 ; free virtual = 39423 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'vio_manual_ctrl' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_manual_ctrl does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:79] +INFO: [Synth 8-6155] done synthesizing module 'vio_manual_ctrl' (7#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[1] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in0[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1922.227 ; gain = 215.406 ; free physical = 956 ; free virtual = 39225 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1925.195 ; gain = 218.375 ; free physical = 958 ; free virtual = 39227 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1925.195 ; gain = 218.375 ; free physical = 959 ; free virtual = 39227 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2098.852 ; gain = 0.000 ; free physical = 1054 ; free virtual = 39301 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2104.789 ; gain = 5.938 ; free physical = 1052 ; free virtual = 39299 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 952 ; free virtual = 39218 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 959 ; free virtual = 39225 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 959 ; free virtual = 39225 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 952 ; free virtual = 39219 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 2 ++---Registers : + 128 Bit Registers := 1 + 32 Bit Registers := 1 + 16 Bit Registers := 13 + 9 Bit Registers := 1 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 4 Bit Registers := 1 + 3 Bit Registers := 3 + 2 Bit Registers := 4 + 1 Bit Registers := 18 ++---Muxes : + 2 Input 16 Bit Muxes := 3 + 3 Input 9 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module vio_v3_0_20_probe_out_one +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized1 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized3 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_all +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 3 Bit Registers := 1 + 1 Bit Registers := 7 ++---Muxes : + 2 Input 1 Bit Muxes := 2 +Module vio_v3_0_20_probe_width +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 9 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 3 Input 9 Bit Muxes := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_decoder +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 3 Bit Registers := 2 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module vio_v3_0_20_vio +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 942 ; free virtual = 39030 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 940 ; free virtual = 38628 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 941 ; free virtual = 38629 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 916 ; free virtual = 38605 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 911 ; free virtual = 38524 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 908 ; free virtual = 38521 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 907 ; free virtual = 38515 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 906 ; free virtual = 38514 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 908 ; free virtual = 38510 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 906 ; free virtual = 38509 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT2 | 7| +|2 |LUT3 | 58| +|3 |LUT4 | 10| +|4 |LUT5 | 26| +|5 |LUT6 | 81| +|6 |FDRE | 348| +|7 |FDSE | 6| ++------+-----+------+ + +Report Instance Areas: ++------+---------------------------------------+------------------------------------------+------+ +| |Instance |Module |Cells | ++------+---------------------------------------+------------------------------------------+------+ +|1 |top | | 536| +|2 | inst |vio_v3_0_20_vio | 536| +|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| +|4 | DECODER_INST |vio_v3_0_20_decoder | 82| +|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 180| +|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 6| +|7 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 3| +|8 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 104| +|9 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 6| +|10 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 8| +|11 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 10| ++------+---------------------------------------+------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 906 ; free virtual = 38507 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 293 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2104.789 ; gain = 218.375 ; free physical = 1037 ; free virtual = 38631 +Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2104.789 ; gain = 397.969 ; free physical = 1044 ; free virtual = 38638 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2104.789 ; gain = 0.000 ; free physical = 1863 ; free virtual = 39459 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +73 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2104.789 ; gain = 706.840 ; free physical = 1942 ; free virtual = 39538 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2104.789 ; gain = 0.000 ; free physical = 1949 ; free virtual = 39545 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_manual_ctrl, cache-ID = 8b290c62e468fc28 +INFO: [Coretcl 2-1174] Renamed 10 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2128.801 ; gain = 0.000 ; free physical = 2352 ; free virtual = 39949 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon May 8 13:15:26 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v new file mode 100644 index 00000000..33d3db0a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:928c622093f565ec8678890a646dc15f08b5fbf566985284ea9ce263ba1c7b1f +size 352451 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl new file mode 100644 index 00000000..ab7fec7f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c725a47591eb1e8eacb779c8e17640ca12d923f1c26e0b41367134f96655e23c +size 633932 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v new file mode 100644 index 00000000..424b152f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:26 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +// Design : vio_manual_ctrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; + input clk; + output [1:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl new file mode 100644 index 00000000..7976ded4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:26 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +-- Design : vio_manual_ctrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_manual_ctrl is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end vio_manual_ctrl; + +architecture stub of vio_manual_ctrl is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb new file mode 100644 index 00000000..0ada8600 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt new file mode 100644 index 00000000..ba78f251 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt @@ -0,0 +1,180 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Mon May 8 13:15:26 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb +| Design : vio_manual_ctrl +| Device : 7z100ffg900-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 150 | 0 | 277400 | 0.05 | +| LUT as Logic | 150 | 0 | 277400 | 0.05 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 354 | 0 | 554800 | 0.06 | +| Register as Flip Flop | 354 | 0 | 554800 | 0.06 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 6 | Yes | Set | - | +| 348 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 348 | Flop & Latch | +| LUT6 | 81 | LUT | +| LUT3 | 58 | LUT | +| LUT5 | 26 | LUT | +| LUT4 | 10 | LUT | +| LUT2 | 7 | LUT | +| FDSE | 6 | Flop & Latch | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb new file mode 100644 index 00000000..6ac3e769 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..74165460 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/ISEWrap.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/ISEWrap.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml new file mode 100644 index 00000000..34fcadaf --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/htr.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/htr.txt new file mode 100644 index 00000000..a70abd68 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log vio_rfcontrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rfcontrl.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf new file mode 100644 index 00000000..c1ef2fc1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf @@ -0,0 +1,41 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3130:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 +eof:3099610940 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/rundef.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/rundef.js new file mode 100644 index 00000000..a61f52de --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log vio_rfcontrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rfcontrl.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/runme.bat b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/runme.sh new file mode 100755 index 00000000..2b522c2c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log vio_rfcontrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rfcontrl.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp new file mode 100644 index 00000000..7c995c6a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7cf3a067fc1987bfdb0f1cd0e107ad1450aa77b58b99f773f450abd6cf8384c5 +size 190431 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.tcl new file mode 100644 index 00000000..e5b22796 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.tcl @@ -0,0 +1,155 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1 -new_name vio_rfcontrl -ip [get_ips vio_rfcontrl]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top vio_rfcontrl -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix vio_rfcontrl_ vio_rfcontrl.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.v + lappend ipCachedFiles vio_rfcontrl_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.vhdl + lappend ipCachedFiles vio_rfcontrl_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_sim_netlist.v + lappend ipCachedFiles vio_rfcontrl_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_sim_netlist.vhdl + lappend ipCachedFiles vio_rfcontrl_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp vio_rfcontrl.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_rfcontrl] +} + +rename_ref -prefix_all vio_rfcontrl_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef vio_rfcontrl.dcp +create_report "vio_rfcontrl_synth_1_synth_report_utilization_0" "report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds new file mode 100644 index 00000000..7494f5e9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds @@ -0,0 +1,652 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Mon May 8 13:15:05 2023 +# Process ID: 2006880 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1 +# Command line: vivado -log vio_rfcontrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rfcontrl.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.jou +#----------------------------------------------------------- +source vio_rfcontrl.tcl -notrace +Command: synth_design -top vio_rfcontrl -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2007378 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.441 ; gain = 150.688 ; free physical = 824 ; free virtual = 39534 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'vio_rfcontrl' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rfcontrl does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/synth/vio_rfcontrl.v:106] +INFO: [Synth 8-6155] done synthesizing module 'vio_rfcontrl' (8#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_in_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1922.129 ; gain = 212.375 ; free physical = 917 ; free virtual = 39432 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1926.098 ; gain = 216.344 ; free physical = 974 ; free virtual = 39409 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1926.098 ; gain = 216.344 ; free physical = 974 ; free virtual = 39409 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2109.754 ; gain = 0.000 ; free physical = 961 ; free virtual = 39230 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2115.691 ; gain = 5.938 ; free physical = 950 ; free virtual = 39219 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 1074 ; free virtual = 39321 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 1075 ; free virtual = 39323 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 1070 ; free virtual = 39317 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 1007 ; free virtual = 39261 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 33 + 12 Bit Registers := 1 + 8 Bit Registers := 3 + 7 Bit Registers := 1 + 5 Bit Registers := 2 + 4 Bit Registers := 5 + 3 Bit Registers := 2 + 1 Bit Registers := 38 ++---Muxes : + 2 Input 16 Bit Muxes := 2 + 9 Input 12 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 20 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module vio_v3_0_20_probe_in_one +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 4 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 +Module vio_v3_0_20_probe_out_one__parameterized1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 8 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized3 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 8 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized4 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 +Module vio_v3_0_20_probe_out_one__parameterized5 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 +Module vio_v3_0_20_probe_out_all +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 5 Bit Registers := 1 + 1 Bit Registers := 20 ++---Muxes : + 2 Input 1 Bit Muxes := 2 +Module vio_v3_0_20_probe_width +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 12 Bit Registers := 1 + 4 Bit Registers := 1 ++---Muxes : + 9 Input 12 Bit Muxes := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_decoder +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 3 Bit Registers := 2 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module vio_v3_0_20_vio +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[16].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[15].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[13].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 974 ; free virtual = 39241 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 920 ; free virtual = 38697 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 918 ; free virtual = 38695 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 913 ; free virtual = 38651 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 928 ; free virtual = 38616 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 927 ; free virtual = 38616 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 923 ; free virtual = 38612 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 916 ; free virtual = 38605 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 912 ; free virtual = 38600 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 910 ; free virtual = 38598 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT1 | 2| +|2 |LUT2 | 16| +|3 |LUT3 | 35| +|4 |LUT4 | 11| +|5 |LUT5 | 42| +|6 |LUT6 | 122| +|7 |FDRE | 569| +|8 |FDSE | 24| ++------+-----+------+ + +Report Instance Areas: ++------+----------------------------------------+---------------------------------------------+------+ +| |Instance |Module |Cells | ++------+----------------------------------------+---------------------------------------------+------+ +|1 |top | | 821| +|2 | inst |vio_v3_0_20_vio | 821| +|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| +|4 | DECODER_INST |vio_v3_0_20_decoder | 91| +|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 77| +|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 367| +|7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| +|8 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 32| +|9 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_0 | 32| +|10 | \G_PROBE_OUT[12].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized5 | 32| +|11 | \G_PROBE_OUT[13].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3| +|12 | \G_PROBE_OUT[14].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3| +|13 | \G_PROBE_OUT[15].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_3 | 3| +|14 | \G_PROBE_OUT[16].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_4 | 3| +|15 | \G_PROBE_OUT[17].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_5 | 32| +|16 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_6 | 3| +|17 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 32| +|18 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 16| +|19 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 8| +|20 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_7 | 8| +|21 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_8 | 8| +|22 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_9 | 8| +|23 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_10 | 16| +|24 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 16| +|25 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 22| ++------+----------------------------------------+---------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 910 ; free virtual = 38599 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 292 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2115.691 ; gain = 216.344 ; free physical = 959 ; free virtual = 38648 +Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 972 ; free virtual = 38661 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.691 ; gain = 0.000 ; free physical = 954 ; free virtual = 38548 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +127 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2115.691 ; gain = 716.777 ; free physical = 1167 ; free virtual = 38760 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.691 ; gain = 0.000 ; free physical = 1168 ; free virtual = 38762 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rfcontrl, cache-ID = 33802de7d605f892 +INFO: [Coretcl 2-1174] Renamed 24 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2139.703 ; gain = 0.000 ; free physical = 1872 ; free virtual = 39468 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon May 8 13:15:26 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v new file mode 100644 index 00000000..045f923b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:795e37fa5092bed76bd5666e05cb723247face647baf3ad8fae43fc62a1b160e +size 429585 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl new file mode 100644 index 00000000..947c8fdd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9f9b2adcaf809ac070ceed79970f8ed6d58a91149d1358bbad5cf3844870fef4 +size 743518 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v new file mode 100644 index 00000000..1d32ada2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v @@ -0,0 +1,42 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 13:15:25 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v +// Design : vio_rfcontrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, probe_out16, + probe_out17) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]" */; + input clk; + input [15:0]probe_in0; + output [0:0]probe_out0; + output [0:0]probe_out1; + output [15:0]probe_out2; + output [7:0]probe_out3; + output [3:0]probe_out4; + output [3:0]probe_out5; + output [3:0]probe_out6; + output [3:0]probe_out7; + output [7:0]probe_out8; + output [7:0]probe_out9; + output [15:0]probe_out10; + output [15:0]probe_out11; + output [15:0]probe_out12; + output [0:0]probe_out13; + output [0:0]probe_out14; + output [0:0]probe_out15; + output [0:0]probe_out16; + output [15:0]probe_out17; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl new file mode 100644 index 00000000..ba0a2f31 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl @@ -0,0 +1,49 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 13:15:25 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl +-- Design : vio_rfcontrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_rfcontrl is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end vio_rfcontrl; + +architecture stub of vio_rfcontrl is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb new file mode 100644 index 00000000..4a83b4e8 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt new file mode 100644 index 00000000..0edcd8e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt @@ -0,0 +1,181 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Mon May 8 13:15:25 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb +| Design : vio_rfcontrl +| Device : 7z100ffg900-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 203 | 0 | 277400 | 0.07 | +| LUT as Logic | 203 | 0 | 277400 | 0.07 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 593 | 0 | 554800 | 0.11 | +| Register as Flip Flop | 593 | 0 | 554800 | 0.11 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 24 | Yes | Set | - | +| 569 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 569 | Flop & Latch | +| LUT6 | 122 | LUT | +| LUT5 | 42 | LUT | +| LUT3 | 35 | LUT | +| FDSE | 24 | Flop & Latch | +| LUT2 | 16 | LUT | +| LUT4 | 11 | LUT | +| LUT1 | 2 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb new file mode 100644 index 00000000..8b337497 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr new file mode 100644 index 00000000..c4723e03 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr @@ -0,0 +1,606 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/mult_18x18.xcix b/projects/duifei/duifei_online_acq_par/ip/mult_18x18.xcix new file mode 100644 index 00000000..8ff2bd79 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/mult_18x18.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:54ad01ec7a70cbc4923f3ba804f74356ce40580583afc1030c7466b0d11b3739 +size 2516459 diff --git a/projects/duifei/duifei_online_acq_par/ip/rom_freq_word.xcix b/projects/duifei/duifei_online_acq_par/ip/rom_freq_word.xcix new file mode 100644 index 00000000..5039b1b5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/rom_freq_word.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9604ec7d6ab9998cca04cb8e48831f64a1186fdf4d26c7d7d61bc73a3d8ea429 +size 11665816 diff --git a/projects/duifei/duifei_online_acq_par/ip/vio_clk_ld_rd.xcix b/projects/duifei/duifei_online_acq_par/ip/vio_clk_ld_rd.xcix new file mode 100644 index 00000000..13f53f93 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/vio_clk_ld_rd.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:49a664927ef81a8810367c4adf8fdafdf3e1f7766961b07f11b443b619a17893 +size 670816 diff --git a/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp.xcix b/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp.xcix new file mode 100644 index 00000000..dbd8f935 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:71b6e9fe05c8bb3bf625454b16ed66378b2e932a379fbf863749545aa64f9b5d +size 717725 diff --git a/projects/duifei/duifei_online_acq_par/ip/vio_manual_ctrl.xcix b/projects/duifei/duifei_online_acq_par/ip/vio_manual_ctrl.xcix new file mode 100644 index 00000000..92442d46 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/vio_manual_ctrl.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:14901030873720749115a51ddc41dcd635d58a66c03e9b93465095d96c5a0158 +size 720235 diff --git a/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl.xcix b/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl.xcix new file mode 100644 index 00000000..e693102f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3a91bb76bc5257de78d7e025f9d9a6605f052fae6df2fe2a5e0e874d1d873e8c +size 780410 diff --git a/projects/duifei/duifei_online_acq_par/project.tcl b/projects/duifei/duifei_online_acq_par/project.tcl new file mode 100644 index 00000000..41551623 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project.tcl @@ -0,0 +1,899 @@ +#***************************************************************************************** +# Vivado (TM) v2019.1.3 (64-bit) +# +# project.tcl: Tcl script for re-creating project 'project' +# +# Generated by Vivado on Tue May 09 20:50:10 CST 2023 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (project.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# +# +# 3. The following remote source files that were added to the original project:- +# +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/vio_manual_ctrl/vio_manual_ctrl.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_cal/ila_cal.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/ant_rf_interface/vio_ant_test/vio_ant_test.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/mult_18x18/mult_18x18.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/cmpy_12x8/cmpy_12x8.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/rom_freq_word/rom_freq_word.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ipi-bd/basic_driver_bd/system_bd.bd" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/sys_clock_gen/ant_clk_gen_stg2/ant_clk_gen_stg2.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/sys_clock_gen/ant_clk_gen_stg1/ant_clk_gen_stg1.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/sys_clock_gen/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/ADF4351_2.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/FRAC1.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/INT_ROMb.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_1.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_2.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_3.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_4.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/Sisyif.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/T_CAL.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/rx_pre_process/ad9361_phase_cal_coarse.v" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/adf4371_a.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/adf4371_b.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/ant_rf_ctrl.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/band_rom_a.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/band_rom_b.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/clk_dist.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/ds18b20_temp.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/frac2_rom.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/fre_caliatt.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/freq_comp.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mgc_ctrl.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mod2_rom.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/rx_dmf.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_master.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_salve.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_tx.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/tx_pre_process.v" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/system_top.v" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/coe/sweep_freq.coe" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/coe/freq_word.coe" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep2.coe" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/constraints/z7100_hmc7044_2ad9361.xdc" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/constraints/z7100_hmc7044_2ad9361_timing.xdc" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/testbenches/tb_freq_comp.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/testbenches/tb_rx_dmf.v" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "project" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "project.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/project"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z100ffg900-2 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "compxlib.modelsim_compiled_library_dir" -value "/home/josh/Software/Xilinx/CompLib/Model/2019.1" -objects $obj +set_property -name "compxlib.vcs_compiled_library_dir" -value "/home/josh/Software/Xilinx/CompLib/VCS/2019.1" -objects $obj +set_property -name "corecontainer.enable" -value "1" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_core_container" -value "1" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "part" -value "xc7z100ffg900-2" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "target_simulator" -value "VCS" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "50" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "50" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "50" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "50" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "50" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "50" -objects $obj +set_property -name "webtalk.vcs_launch_sim" -value "47" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "50" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../adi_library"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/ip/ila_freq_comp/ila_freq_comp.xci"] \ + [file normalize "${origin_dir}/ip/vio_freq_comp/vio_freq_comp.xci"] \ + [file normalize "${origin_dir}/../common_ip/basic_driver/vio_manual_ctrl/vio_manual_ctrl.xci"] \ + [file normalize "${origin_dir}/ip/ila_cal/ila_cal.xci"] \ + [file normalize "${origin_dir}/../common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci"] \ + [file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"] \ + [file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci"] \ + [file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"] \ + [file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"] \ + [file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"] \ + [file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_ant_test/vio_ant_test.xci"] \ + [file normalize "${origin_dir}/ip/vio_rfcontrl/vio_rfcontrl.xci"] \ + [file normalize "${origin_dir}/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"] \ + [file normalize "${origin_dir}/ip/mult_18x18/mult_18x18.xci"] \ + [file normalize "${origin_dir}/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci"] \ + [file normalize "${origin_dir}/ip/cmpy_12x8/cmpy_12x8.xci"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci"] \ + [file normalize "${origin_dir}/../common_ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci"] \ + [file normalize "${origin_dir}/ip/rom_freq_word/rom_freq_word.xci"] \ + [file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/system_bd.bd"] \ + [file normalize "${origin_dir}/../common_ip/sys_clock_gen/ant_clk_gen_stg2/ant_clk_gen_stg2.xci"] \ + [file normalize "${origin_dir}/../common_ip/sys_clock_gen/ant_clk_gen_stg1/ant_clk_gen_stg1.xci"] \ + [file normalize "${origin_dir}/../common_ip/sys_clock_gen/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/ADF4351_2.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/FRAC1.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/INT_ROMb.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/R_CAL_1.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/R_CAL_2.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/R_CAL_3.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/R_CAL_4.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/Sisyif.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/T_CAL.v"] \ + [file normalize "${origin_dir}/rtl/rx_pre_process/ad9361_phase_cal_coarse.v"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/adf4371_a.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/adf4371_b.v"] \ + [file normalize "${origin_dir}/rtl/ant_rf_ctrl.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/band_rom_a.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/band_rom_b.v"] \ + [file normalize "${origin_dir}/rtl/clk_dist.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/ds18b20_temp.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/frac2_rom.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/fre_caliatt.v"] \ + [file normalize "${origin_dir}/rtl/freq_comp.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/mgc_ctrl.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/mod2_rom.v"] \ + [file normalize "${origin_dir}/rtl/rf_auto_switch_freq.v"] \ + [file normalize "${origin_dir}/rtl/rx_dmf.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/spi_master.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/spi_salve.v"] \ + [file normalize "${origin_dir}/rtl/Sisyif_src/spi_tx.v"] \ + [file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v"] \ + [file normalize "${origin_dir}/rtl/tx_pre_process.v"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \ + [file normalize "${origin_dir}/rtl/system_top.v"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \ + [file normalize "${origin_dir}/ip/coe/freq_word.coe"] \ + [file normalize "${origin_dir}/ip/coe/prbs7_invert_rep2.coe"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/ip/ila_freq_comp/ila_freq_comp.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/vio_freq_comp/vio_freq_comp.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/basic_driver/vio_manual_ctrl/vio_manual_ctrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/ila_cal/ila_cal.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/ant_rf_interface/vio_ant_test/vio_ant_test.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/vio_rfcontrl/vio_rfcontrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/mult_18x18/mult_18x18.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/cmpy_12x8/cmpy_12x8.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../../../modules/xc7z100ffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/rom_freq_word/rom_freq_word.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ipi-bd/basic_driver_bd/system_bd.bd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "registered_with_manager" -value "1" -objects $file_obj + +set file "$origin_dir/../common_ip/sys_clock_gen/ant_clk_gen_stg2/ant_clk_gen_stg2.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/sys_clock_gen/ant_clk_gen_stg1/ant_clk_gen_stg1.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/sys_clock_gen/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "system_top" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/constraints/z7100_hmc7044_2ad9361.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/constraints/z7100_hmc7044_2ad9361.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/constraints/z7100_hmc7044_2ad9361_timing.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/constraints/z7100_hmc7044_2ad9361_timing.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property -name "target_part" -value "xc7z100ffg900-2" -objects $obj + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +set files [list \ + [file normalize "${origin_dir}/testbenches/tb_freq_comp.v"] \ + [file normalize "${origin_dir}/testbenches/tb_rx_dmf.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "tb_freq_comp" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj +set_property -name "vcs.compile.vlogan.more_options" -value "-kdb -v2005" -objects $obj +set_property -name "vcs.elaborate.vcs.more_options" -value "-debug_access+all" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z100ffg900-2 -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2019" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "part" -value "xc7z100ffg900-2" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z100ffg900-2 -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2019" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "part" -value "xc7z100ffg900-2" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/projects/duifei/duifei_online_acq_par/project/project.hw/project.lpr b/projects/duifei/duifei_online_acq_par/project/project.hw/project.lpr new file mode 100644 index 00000000..29d8123e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.hw/project.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/debug_nets.ltx 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"name": "u_ad9361_phase_cal/curr_state[0]", + "state_reg": [ + { + "name": "u_ad9361_phase_cal/curr_state_reg[0]", + "states": [ + { + "name": "STATE_IDLE", + "val": "00" + }, + { + "name": "STATE_CAL_1", + "val": "01" + }, + { + "name": "STATE_CAL_2", + "val": "10" + }, + { + "name": "STATE_DONE", + "val": "11" + } + ] + } + ] + }, + { + "id": 450, + "name": "u_freq_comp/state_curr__0[2]", + "state_reg": [ + { + "name": "u_freq_comp/state_curr_reg[2]", + "states": [ + { + "name": "STATE_IDLE", + "val": "000" + }, + { + "name": "STATE_FREQ_SW", + "val": "001" + }, + { + "name": "STATE_FREQ_DMF", + "val": "010" + }, + { + "name": "STATE_CH_SW", + "val": "011" + }, + { + "name": "STATE_CH_DMF", + "val": "100" + } + ] + } + ] + }, + { + "id": 451, + "name": "u_freq_comp/state_curr__0[1]", + "state_reg": [ + { + "name": "u_freq_comp/state_curr_reg[1]", + "states": [ + { + "name": "STATE_IDLE", + "val": "000" + }, + { + "name": "STATE_FREQ_SW", + "val": "001" + }, + { + "name": "STATE_FREQ_DMF", + "val": "010" + }, + { + "name": "STATE_CH_SW", + "val": "011" + }, + { + "name": "STATE_CH_DMF", + "val": "100" + } + ] + } + ] + }, + { + "id": 452, + "name": "u_freq_comp/state_curr__0[0]", + "state_reg": [ + { + "name": "u_freq_comp/state_curr_reg[0]", + "states": [ + { + "name": "STATE_IDLE", + "val": "000" + }, + { + "name": "STATE_FREQ_SW", + "val": "001" + }, + { + "name": "STATE_FREQ_DMF", + "val": "010" + }, + { + "name": "STATE_CH_SW", + "val": "011" + }, + { + "name": "STATE_CH_DMF", + "val": "100" + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/.cproject b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/.cproject new file mode 100644 index 00000000..9d730db8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/.cproject @@ -0,0 +1,162 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/.project b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/.project new file mode 100644 index 00000000..a546fc24 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/.project @@ -0,0 +1,26 @@ + + + duifei_cmos_48m + Created by SDK v2019.1. duifei_cmos_48m_bsp - ps7_cortexa9_0 + + duifei_cmos_48m_bsp + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/README.txt b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/README.txt new file mode 100644 index 00000000..c4d32efe --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/README.txt @@ -0,0 +1 @@ +Empty application. Add your own sources. diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/Xilinx.spec b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/Xilinx.spec new file mode 100644 index 00000000..8eea3774 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/Xilinx.spec @@ -0,0 +1,2 @@ +*startfile: +crti%O%s crtbegin%O%s diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/adc/ad9694/ad9694.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/adc/ad9694/ad9694.c new file mode 100644 index 00000000..336ea4ba --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/adc/ad9694/ad9694.c @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file ad9694.c + * @brief Implementation of AD9680 Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include "ad9694.h" +#include "../../../include/error.h" + +/***************************************************************************//** + * @brief ad9694_read + *******************************************************************************/ +int32_t ad9694_read(struct ad9694_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data) +{ + uint8_t tx_buf[2]; + uint8_t rx_buf[1]; + int32_t ret; + + tx_buf[0] = 0x80 | (reg_addr >> 8); + tx_buf[1] = reg_addr & 0xFF; + + + ret = spi_write_and_read_3wire(dev->spi_desc, + tx_buf, rx_buf, 2, 1); + + *reg_data = rx_buf[0]; + + return ret; +} + +/***************************************************************************//** + * @brief ad9694_write + *******************************************************************************/ +int32_t ad9694_write(struct ad9694_dev *dev, + uint16_t reg_addr, + uint8_t reg_data) +{ + uint8_t buf[3]; + + int32_t ret; + + buf[0] = reg_addr >> 8; + buf[1] = reg_addr & 0xFF; + buf[2] = reg_data; + + ret = spi_write_and_read_3wire(dev->spi_desc, + buf, NULL, 3, 0); + return ret; +} + +/***************************************************************************//** + * @brief ad9694_init + *******************************************************************************/ +int32_t ad9694_init(struct ad9694_dev **device, + const struct ad9694_init_param *init_param) +{ + int ret = SUCCESS; + struct ad9694_dev *dev; + + dev = (struct ad9694_dev *)malloc(sizeof(*dev)); + if (!dev) + return FAILURE; + + /* SPI */ + ret = spi_init(&dev->spi_desc, init_param->spi_init); + + *device = dev; + + return ret; +} + +/***************************************************************************//** + * @brief Free the resources allocated by ad9694_setup(). + * + * @param dev - The device structure. + * + * @return SUCCESS in case of success, negative error code otherwise. +*******************************************************************************/ +int32_t ad9694_remove(struct ad9694_dev *dev) +{ + int32_t ret; + + ret = spi_remove(dev->spi_desc); + + free(dev); + + return ret; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/adc/ad9694/ad9694.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/adc/ad9694/ad9694.h new file mode 100644 index 00000000..589af2f7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/adc/ad9694/ad9694.h @@ -0,0 +1,231 @@ +/***************************************************************************//** + * @file ad9694.h + * @brief Header file of AD9694 Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ +#ifndef AD9694_H_ +#define AD9694_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "../../../include/delay.h" +#include "../../../include/spi.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#define AD9694_REG_GLOBAL_MAP_SPI_CONF_A 0x0000 +#define AD9694_REG_GLOBAL_MAP_SPI_CONF_B 0x0001 +#define AD9694_REG_CH_MAP_CHIP_CONF 0x0002 +#define AD9694_REG_PAIR_MAP_CHIP_TYPE 0x0003 +#define AD9694_REG_PAIR_MAP_CHIP_ID_LSB 0x0004 +#define AD9694_REG_PAIR_MAP_CHIP_GRADE 0x0006 +#define AD9694_REG_PAIR_MAP_DEV_INDEX 0x0008 +#define AD9694_REG_GLOBAL_MAP_PAIR_INDEX 0x0009 +#define AD9694_REG_PAIR_MAP_SCRATCH_PAD 0x000A +#define AD9694_REG_PAIR_MAP_SPI_REVISION 0x000B +#define AD9694_REG_PAIR_MAP_VENDOR_ID_LSB 0x000C +#define AD9694_REG_PAIR_MAP_VENDOR_ID_MSB 0x000D +#define AD9694_REG_CH_MAP_CHIP_PD_PIN 0x003F +#define AD9694_REG_PAIR_MAP_CHIP_PIN_CTRL_1 0x0040 +#define AD9694_REG_PAIR_MAP_CLK_DIV_CTRL 0x0108 +#define AD9694_REG_CH_MAP_CLK_DIV_PHASE 0x0109 +#define AD9694_REG_PAIR_MAP_CLK_DIV_SYSREF_CTRL 0x010A +#define AD9694_REG_PAIR_MAP_CLK_DELAY_CTRL 0x0110 +#define AD9694_REG_CH_MAP_CLK_SUPER_FINE_DELAY 0x0111 +#define AD9694_REG_CH_MAP_CLK_FINE_DELAY 0x0112 +#define AD9694_REG_CLK_DETN_CTRL 0x011A +#define AD9694_REG_PAIR_MAP_CLK_STAT 0x011B +#define AD9694_REG_CLK_DCS_CTRL_1 0x011C +#define AD9694_REG_CLK_DCS_CTRL_2 0x011E +#define AD9694_REG_CLK_DCS_CTRL_3 0x011F +#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_1 0x0120 +#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_2 0x0121 +#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_4 0x0123 +#define AD9694_REG_PAIR_MAP_SYSREF_STAT_1 0x0128 +#define AD9694_REG_PAIR_MAP_SYSREF_STAT_2 0x0129 +#define AD9694_REG_PAIR_MAP_SYSREF_STAT_3 0x012A +#define AD9694_REG_PAIR_MAP_CHIP_SYNC 0x01FF +#define AD9694_REG_PAIR_MAP_CHIP_MODE 0x0200 +#define AD9694_REG_PAIR_MAP_CHIP_DEC_RATIO 0x0201 +#define AD9694_REG_CH_MAP_CUSTOM_OFFSET 0x0228 +#define AD9694_REG_CH_MAP_FD_CTRL 0x0245 +#define AD9694_REG_CH_MAP_FD_UT_LSB 0x0247 +#define AD9694_REG_CH_MAP_FD_UT_MSB 0x0248 +#define AD9694_REG_CH_MAP_FD_LT_LSB 0x0249 +#define AD9694_REG_CH_MAP_FD_LT_MSB 0x024A +#define AD9694_REG_CH_MAP_FD_DWELL_TIME_LSB 0x024B +#define AD9694_REG_CH_MAP_FD_DWELL_TIME_MSB 0x024C +#define AD9694_REG_PAIR_MAP_SIG_MON_SYNC_CTRL 0x026F +#define AD9694_REG_CH_MAP_SIG_MON_CTRL 0x0270 +#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_0 0x0271 +#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_1 0x0272 +#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_2 0x0273 +#define AD9694_REG_CH_MAP_SIG_MON_STAT_CTRL 0x0274 +#define AD9694_REG_CH_MAP_SIG_MON_STAT_0 0x0275 +#define AD9694_REG_CH_MAP_SIG_MON_STAT_1 0x0276 +#define AD9694_REG_CH_MAP_SIG_MON_STAT_2 0x0277 +#define AD9694_REG_CH_MAP_SIG_MON_STAT_FRAME_CNT 0x0278 +#define AD9694_REG_CH_MAP_SIG_MON_SERIAL_FRAMER_CTRL 0x0279 +#define AD9694_REG_SPORT_OVER_JESD204B_INPUT_SEL 0x027A +#define AD9694_REG_PAIR_MAP_DDC_SYNC_CTRL 0x0300 +#define AD9694_REG_PAIR_MAP_DDC_0_CTRL 0x0310 +#define AD9694_REG_PAIR_MAP_DDC_0_INPUT_SEL 0x0311 +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_0 0x0314 +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_1 0x0315 +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_2 0x0316 +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_3 0x0317 +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_4 0x0318 +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_5 0x031A +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_0 0x031D +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_1 0x031E +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_2 0x031F +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_3 0x0320 +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_4 0x0321 +#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_5 0x0322 +#define AD9694_REG_PAIR_MAP_DDC_0_TEST_ENABLE 0x0327 +#define AD9694_REG_PAIR_MAP_DDC_1_CTRL 0x0330 +#define AD9694_REG_PAIR_MAP_DDC_1_INPUT_SEL 0x0331 +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_0 0x0334 +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_1 0x0335 +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_2 0x0336 +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_3 0x0337 +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_4 0x0338 +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_5 0x033A +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_0 0x033D +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_1 0x033E +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_2 0x033F +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_3 0x0340 +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_4 0x0341 +#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_5 0x0342 +#define AD9694_REG_PAIR_MAP_DDC_1_TEST_ENABLE 0x0347 +#define AD9694_REG_CH_MAP_TEST_MODE_CTRL 0x0550 +#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_LSB 0x0551 +#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_MSB 0x0552 +#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_LSB 0x0553 +#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_MSB 0x0554 +#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_LSB 0x0555 +#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_MSB 0x0556 +#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_LSB 0x0557 +#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_MSB 0x0558 +#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_0 0x0559 +#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_1 0x055A +#define AD9694_REG_PAIR_MAP_OUTPUT_SAMPLE_MODE 0x0561 +#define AD9694_REG_PAIR_MAP_OUTPUT_CH_SEL 0x0564 +#define AD9694_REG_JESD204B_MAP_PLL_CTRL 0x056E +#define AD9694_REG_JESD204B_MAP_PLL_STAT 0x056F +#define AD9694_REG_JESD204B_MAP_JTX_QUICK_CONF 0x0570 +#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_1 0x0571 +#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_2 0x0572 +#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_3 0x0573 +#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_4 0x0574 +#define AD9694_REG_JESD204B_MAP_JTX_LMFC_OFFSET 0x0578 +#define AD9694_REG_JESD204B_MAP_JTX_DID_CONF 0x0580 +#define AD9694_REG_JESD204B_MAP_JTX_BID_CONF 0x0581 +#define AD9694_REG_JESD204B_MAP_JTX_LID_0_CONF 0x0583 +#define AD9694_REG_JESD204B_MAP_JTX_LID_1_CONF 0x0585 +#define AD9694_REG_JESD204B_MAP_JTX_SCR_L_CONF 0x058B +#define AD9694_REG_JESD204B_MAP_JTX_F_CONF 0x058C +#define AD9694_REG_JESD204B_MAP_JTX_K_CONF 0x058D +#define AD9694_REG_JESD204B_MAP_JTX_M_CONF 0x058E +#define AD9694_REG_JESD204B_MAP_JTX_CS_N_CONF 0x058F +#define AD9694_REG_JESD204B_MAP_JTX_SUBCLASS_CONF 0x0590 +#define AD9694_REG_JESD204B_MAP_JTX_S_CONF 0x0591 +#define AD9694_REG_JESD204B_MAP_JTX_HD_CF_CONF 0x0592 +#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_0_CONF 0x05A0 +#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_1_CONF 0x05A1 +#define AD9694_REG_SERDOUTX0_SERDOUTX1_LANE_PD 0x05B0 +#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_1 0x05B2 +#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_2 0x05B3 +#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_0 0x05C0 +#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_1 0x05C1 +#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_0 0x05C4 +#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_1 0x05C6 +#define AD9694_REG_LARGE_DITHER_CTRL 0x0922 +#define AD9694_REG_PLL_CAL 0x1222 +#define AD9694_REG_JESD204B_STARTUP_CIRCUIT_RST 0x1228 +#define AD9694_REG_PLL_LOSS_OF_LOCK_CTRL 0x1262 +#define AD9694_REG_DC_OFFSET_CAL_CTRL 0x0701 +#define AD9694_REG_DC_OFFSET_CAL_CTRL_2 0x073B +#define AD9694_REG_PAIR_MAP_VREF_CTRL 0x18A6 +#define AD9694_REG_EXT_VCM_BUF_CTRL_1 0x18E0 +#define AD9694_REG_EXT_VCM_BUF_CTRL_2 0x18E1 +#define AD9694_REG_EXT_VCM_BUF_CTRL_3 0x18E2 +#define AD9694_REG_EXT_VCM_BUF_CTRL 0x18E3 +#define AD9694_REG_TEMP_DIODE_EXPORT 0x18E6 +#define AD9694_REG_CH_MAP_ANALOG_INPUT_CTRL 0x1908 +#define AD9694_REG_CH_MAP_INPUT_FULLSCALE_RANGE 0x1910 +#define AD9694_REG_CH_MAP_BUF_CTRL_1 0x1A4C +#define AD9694_REG_CH_MAP_BUF_CTRL_2 0x1A4D + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +struct ad9694_dev { + /* SPI */ + spi_desc *spi_desc; +}; + +struct ad9694_init_param { + /* SPI */ + spi_init_param *spi_init; +}; + +struct ad9694_config { + uint16_t addr; + uint8_t value; +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +int32_t ad9694_read(struct ad9694_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data); + +int32_t ad9694_write(struct ad9694_dev *dev, + uint16_t reg_addr, + uint8_t reg_data); + +int32_t ad9694_init(struct ad9694_dev **device, + const struct ad9694_init_param *init_param); + +int32_t ad9694_remove(struct ad9694_dev *dev); + +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/api/gpio.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/api/gpio.c new file mode 100644 index 00000000..9742613d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/api/gpio.c @@ -0,0 +1,184 @@ +/***************************************************************************//** + * @file gpio.c + * @brief Implementation of the GPIO Interface + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2020(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include +#include +#include "../../include/gpio.h" +#include "../../include/error.h" + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Obtain the GPIO decriptor. + * @param desc - The GPIO descriptor. + * @param param - GPIO Initialization parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + if (!param) + return FAILURE; + + if ((param->platform_ops->gpio_ops_get(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} + +/** + * @brief Get the value of an optional GPIO. + * @param desc - The GPIO descriptor. + * @param param - GPIO Initialization parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_optional(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + if (!param || (param->number == -1)) { + *desc = NULL; + return SUCCESS; + } + + if ((param->platform_ops->gpio_ops_get_optional(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} +/** + * @brief Free the resources allocated by gpio_get(). + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_remove(struct gpio_desc *desc) +{ + if (desc) + return desc->platform_ops->gpio_ops_remove(desc); + else + return SUCCESS; +} + +/** + * @brief Enable the input direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_direction_input(struct gpio_desc *desc) +{ + if (desc) + return desc->platform_ops->gpio_ops_direction_input(desc); + else + return SUCCESS; +} + +/** + * @brief Enable the output direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_direction_output(struct gpio_desc *desc, + uint8_t value) +{ + if (desc) + return desc->platform_ops-> + gpio_ops_direction_output(desc, value); + else + return SUCCESS; +} + +/** + * @brief Get the direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param direction - The direction. + * Example: GPIO_OUT + * GPIO_IN + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction) +{ + if (desc) + return desc->platform_ops-> + gpio_ops_get_direction(desc, direction); + else + return SUCCESS; +} + +/** + * @brief Set the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_set_value(struct gpio_desc *desc, + uint8_t value) +{ + if (desc) + return desc->platform_ops->gpio_ops_set_value(desc, value); + else + return SUCCESS; +} + +/** + * @brief Get the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_value(struct gpio_desc *desc, + uint8_t *value) +{ + if (desc) + return desc->platform_ops->gpio_ops_get_value(desc, value); + else + return SUCCESS; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/api/irq.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/api/irq.c new file mode 100644 index 00000000..937c57f8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/api/irq.c @@ -0,0 +1,153 @@ +/***************************************************************************//** + * @file irq.c + * @brief Implementation of the IRQ Interface + * @author Andrei Porumb (andrei.porumb@analog.com) +******************************************************************************** + * Copyright 2021(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include +#include +#include "../../include/irq.h" +#include "../../include/error.h" + +/** + * @brief Initialize the IRQ interrupts. + * @param desc - The IRQ descriptor. + * @param param - The structure that contains the IRQ parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_ctrl_init(struct irq_ctrl_desc **desc, + const struct irq_init_param *param) +{ + if (!param) + return FAILURE; + + if ((param->platform_ops->init(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by irq_ctrl_init(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc) +{ + return desc->platform_ops->remove(desc); +} + +/** + * @brief Register a callback to handle the irq events. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param callback_desc - Callback descriptor + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc) +{ + return desc->platform_ops->register_callback(desc, irq_id, callback_desc); +} + +/** + * @brief Unregisters a generic IRQ handling function. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + return desc->platform_ops->unregister(desc, irq_id); +} + +/** + * @brief Enable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_global_enable(struct irq_ctrl_desc *desc) +{ + return desc->platform_ops->global_enable(desc); +} + +/** + * @brief Disable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_global_disable(struct irq_ctrl_desc *desc) +{ + return desc->platform_ops->global_disable(desc); +} + +/** + * @brief Set interrupt trigger level. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param trig - New trigger level for the interrupt. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig) +{ + if(desc->platform_ops->trigger_level_set) + return desc->platform_ops->trigger_level_set(desc, irq_id, trig); + else + return ENOSYS; +} + +/** + * @brief Enable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + return desc->platform_ops->enable(desc, irq_id); +} + +/** + * @brief Disable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + return desc->platform_ops->disable(desc, irq_id); +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/api/spi.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/api/spi.c new file mode 100644 index 00000000..c114eda7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/api/spi.c @@ -0,0 +1,144 @@ +/***************************************************************************//** + * @file spi.c + * @brief Implementation of the SPI Interface + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2020(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include +#include +#include +#include "../../include/spi.h" +#include "../../include/error.h" + +/** + * @brief Initialize the SPI communication peripheral. + * @param desc - The SPI descriptor. + * @param param - The structure that contains the SPI parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_init(struct spi_desc **desc, + const struct spi_init_param *param) +{ + if (!param) + return FAILURE; + + if ((param->platform_ops->init(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by spi_init(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_remove(struct spi_desc *desc) +{ + return desc->platform_ops->remove(desc); +} + +/** + * @brief Write and read data to/from SPI. + * @param desc - The SPI descriptor. + * @param data - The buffer with the transmitted/received data. + * @param bytes_number - Number of bytes to write/read. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number) +{ + return desc->platform_ops->write_and_read(desc, data, bytes_number); +} + +/** + * @brief Write and read data to/from SPI in 3 wire mode. + * @param desc - The SPI descriptor. + * @param write_data - The buffer with the transmitted data. + * @param read_data - The buffer with the received data. + * @param write_bytes_number - Number of bytes to write. + * @param read_bytes_number - Number of bytes to read. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number) +{ + int ret; + if(desc->platform_ops->write_and_read_3wire != NULL){ + return desc->platform_ops->write_and_read_3wire(desc, write_data, read_data, + write_bytes_number, read_bytes_number); + } + else{ + return FAILURE; + } +} + + +/** + * @brief Iterate over head list and send all spi messages + * @param desc - The SPI descriptor. + * @param msgs - Array of messages. + * @param len - Number of messages in the array. + * @return SUCCESS in case of success, negativ error code otherwise. + */ +int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len) +{ + int32_t ret; + uint32_t i; + + if (!desc || !desc->platform_ops) + return -EINVAL; + + if (desc->platform_ops->transfer) + return desc->platform_ops->transfer(desc, msgs, len); + + for (i = 0; i < len; i++) { + if (msgs[i].rx_buff != msgs[i].tx_buff || !msgs[i].tx_buff) + return -EINVAL; + ret = spi_write_and_read(desc, msgs[i].rx_buff, + msgs[i].bytes_number); + if (IS_ERR_VALUE(ret)) + return ret; + } + + return SUCCESS; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c new file mode 100644 index 00000000..7964fbf3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c @@ -0,0 +1,328 @@ +/***************************************************************************//** + * @file axi_dmac.c + * @brief Driver for the Analog Devices AXI-DMAC core. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include +#include +#include "../../../include/axi_io.h" +#include "../../../include/error.h" +#include "../axi_dmac/axi_dmac.h" + +/***************************************************************************//** + * @brief dma_isr +*******************************************************************************/ +void axi_dmac_default_isr(void *instance) +{ + struct axi_dmac *dmac = (struct axi_dmac *)instance; + uint32_t remaining_size, burst_size; + uint32_t reg_val; + + /* Get interrupt sources and clear interrupts. */ + axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val); + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val); + + if ((reg_val & AXI_DMAC_IRQ_SOT) && (dmac->big_transfer.size != 0)) { + remaining_size = dmac->big_transfer.size - + dmac->big_transfer.size_done; + burst_size = (remaining_size <= dmac->transfer_max_size) ? + remaining_size : dmac->transfer_max_size; + + dmac->big_transfer.size_done += burst_size; + dmac->big_transfer.address += burst_size; + switch (dmac->direction) { + case DMA_DEV_TO_MEM: + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, + dmac->big_transfer.address); + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0); + break; + case DMA_MEM_TO_DEV: + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, + dmac->big_transfer.address); + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0); + break; + default: + return; // Other directions are not supported yet + } + /* The current transfer was started and a new one is queued. */ + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + burst_size); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + } + if (reg_val & AXI_DMAC_IRQ_EOT) { + dmac->big_transfer.transfer_done = true; + dmac->big_transfer.address = 0; + dmac->big_transfer.size = 0; + dmac->big_transfer.size_done = 0; + } +} + +/***************************************************************************//** + * @brief axi_dmac_read + *******************************************************************************/ +int32_t axi_dmac_read(struct axi_dmac *dmac, + uint32_t reg_addr, + uint32_t *reg_data) +{ + axi_io_read(dmac->base, reg_addr, reg_data); + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_write + *******************************************************************************/ +int32_t axi_dmac_write(struct axi_dmac *dmac, + uint32_t reg_addr, + uint32_t reg_data) +{ + axi_io_write(dmac->base, reg_addr, reg_data); + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_transfer_nonblock + *******************************************************************************/ +int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac, + uint32_t address, uint32_t size) +{ + uint32_t reg_val; + + if (size == 0) + return SUCCESS; /* nothing to do */ + + axi_dmac_read(dmac, AXI_DMAC_REG_CTRL, ®_val); + if (!(reg_val & AXI_DMAC_CTRL_ENABLE)) { + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0); + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE); + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0); + } + + axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, ®_val); + if (!(reg_val & 1)) { + switch (dmac->direction) { + case DMA_DEV_TO_MEM: + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0); + break; + case DMA_MEM_TO_DEV: + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0); + break; + default: + return FAILURE; // Other directions are not supported yet + } + if ((size - 1) > dmac->transfer_max_size) { + dmac->big_transfer.address = address; + dmac->big_transfer.size = size - 1; + dmac->big_transfer.size_done = dmac->transfer_max_size; + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + dmac->transfer_max_size); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + } else { + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + size - 1); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + } + } else { + return FAILURE; + } + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_is_transfer_ready + *******************************************************************************/ +int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy) +{ + *rdy = dmac->big_transfer.transfer_done; + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_transfer + *******************************************************************************/ +int32_t axi_dmac_transfer(struct axi_dmac *dmac, + uint32_t address, uint32_t size) +{ + uint32_t transfer_id; + uint32_t reg_val; + uint32_t timeout = 0; + + if (size == 0) + return SUCCESS; /* nothing to do */ + + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0); + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE); + + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0); + + axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID, &transfer_id); + axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val); + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val); + + switch (dmac->direction) { + case DMA_DEV_TO_MEM: + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0); + break; + case DMA_MEM_TO_DEV: + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0); + break; + default: + return FAILURE; // Other directions are not supported yet + } + + if ((size - 1) > dmac->transfer_max_size) { + dmac->big_transfer.address = address; + dmac->big_transfer.size = size - 1; + dmac->big_transfer.size_done = dmac->transfer_max_size; + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + dmac->transfer_max_size); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + + while(!dmac->big_transfer.transfer_done) { + timeout++; + if (timeout == UINT32_MAX) + return FAILURE; + } + + dmac->big_transfer.address = 0; + dmac->big_transfer.size = 0; + dmac->big_transfer.size_done = 0; + + return SUCCESS; + } + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, size - 1); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + + if (dmac->flags & DMA_CYCLIC) + return SUCCESS; + + /* Wait until the new transfer is queued. */ + do { + axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, ®_val); + } while(reg_val == 1); + + /* Wait until the current transfer is completed. */ + do { + axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val); + if (reg_val == (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT)) + break; + } while(!dmac->big_transfer.transfer_done); + if (reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT)) + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val); + + /* Wait until the transfer with the ID transfer_id is completed. */ + do { + axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE, ®_val); + } while((reg_val & (1u << transfer_id)) != (1u << transfer_id)); + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_init + *******************************************************************************/ +int32_t axi_dmac_init(struct axi_dmac **dmac_core, + const struct axi_dmac_init *init) +{ + struct axi_dmac *dmac; + + dmac = (struct axi_dmac *)malloc(sizeof(*dmac)); + if (!dmac) + return FAILURE; + + dmac->name = init->name; + dmac->base = init->base; + dmac->direction = init->direction; + dmac->flags = init->flags; + dmac->transfer_max_size = -1; + dmac->big_transfer.address = 0; + dmac->big_transfer.size = 0; + dmac->big_transfer.size_done = 0; + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, dmac->transfer_max_size); + axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH, &dmac->transfer_max_size); + + *dmac_core = dmac; + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_remove + *******************************************************************************/ +int32_t axi_dmac_remove(struct axi_dmac *dmac) +{ + if(!dmac) + return FAILURE; + + free(dmac); + + return SUCCESS; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h new file mode 100644 index 00000000..d7a10858 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h @@ -0,0 +1,124 @@ +/***************************************************************************//** + * @file axi_dmac.h + * @brief Driver for the Analog Devices AXI-DMAC core. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef AXI_DMAC_H_ +#define AXI_DMAC_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "../../../include/util.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#define AXI_DMAC_REG_IRQ_MASK 0x80 +#define AXI_DMAC_REG_IRQ_PENDING 0x84 +#define AXI_DMAC_IRQ_SOT BIT(0) +#define AXI_DMAC_IRQ_EOT BIT(1) + +#define AXI_DMAC_REG_CTRL 0x400 +#define AXI_DMAC_CTRL_ENABLE BIT(0) +#define AXI_DMAC_CTRL_PAUSE BIT(1) + +#define AXI_DMAC_REG_TRANSFER_ID 0x404 +#define AXI_DMAC_REG_START_TRANSFER 0x408 +#define AXI_DMAC_REG_FLAGS 0x40c +#define AXI_DMAC_REG_DEST_ADDRESS 0x410 +#define AXI_DMAC_REG_SRC_ADDRESS 0x414 +#define AXI_DMAC_REG_X_LENGTH 0x418 +#define AXI_DMAC_REG_Y_LENGTH 0x41c +#define AXI_DMAC_REG_DEST_STRIDE 0x420 +#define AXI_DMAC_REG_SRC_STRIDE 0x424 +#define AXI_DMAC_REG_TRANSFER_DONE 0x428 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +enum dma_direction { + DMA_DEV_TO_MEM, + DMA_MEM_TO_DEV +}; + +enum dma_flags { + DMA_CYCLIC = 1, + DMA_LAST = 2 +}; + +struct axi_dma_transfer { + uint32_t size; + uint32_t address; + uint32_t size_done; + volatile bool transfer_done; +}; + +struct axi_dmac { + const char *name; + uint32_t base; + enum dma_direction direction; + uint32_t flags; + uint32_t transfer_max_size; + volatile struct axi_dma_transfer big_transfer; +}; + +struct axi_dmac_init { + const char *name; + uint32_t base; + enum dma_direction direction; + uint32_t flags; +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ +void axi_dmac_default_isr(void *instance); +int32_t axi_dmac_read(struct axi_dmac *dmac, uint32_t reg_addr, + uint32_t *reg_data); +int32_t axi_dmac_write(struct axi_dmac *dmac, uint32_t reg_addr, + uint32_t reg_data); +int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac, + uint32_t address, uint32_t size); +int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy); +int32_t axi_dmac_transfer(struct axi_dmac *dmac, + uint32_t address, uint32_t size); +int32_t axi_dmac_init(struct axi_dmac **adc_core, + const struct axi_dmac_init *init); +int32_t axi_dmac_remove(struct axi_dmac *dmac); + +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.c new file mode 100644 index 00000000..702d97df --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.c @@ -0,0 +1,978 @@ +/******************************************************************************* + * @file spi_engine.c + * @brief Core implementation of the SPI Engine Driver. + * @author Sergiu Cuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +/* In debug mode the printf function used in displaying the messages is causing +significant delays */ +//#define DEBUG_LEVEL 2 + +#include +#include +#include +#include +#include +#include + +#include "spi_engine.h" +#include "../axi_dmac/axi_dmac.h" +#include "../../../include/axi_io.h" +#include "../../../include/error.h" + +/** + * @brief Spi engine platform specific SPI platform ops structure + */ +const struct spi_platform_ops spi_eng_platform_ops = { + .init = &spi_engine_init, + .write_and_read = &spi_engine_spi_write_and_read, + .write_and_read_3wire = &spi_engine_spi_write_and_read_3wire, + .remove = &spi_engine_remove +}; + +/******************************************************************************/ +/***************************** Static variables *******************************/ +/******************************************************************************/ + +/** + * @brief Static variable used to sync transfers + * + */ +static uint8_t _sync_id = 0x01; + +/******************************************************************************/ +/************************** Functions Implementation **************************/ +/******************************************************************************/ + +/** + * @brief Write SPI Engine's axi registers + * + * @param desc Decriptor containing SPI Engine's parameters + * @param reg_addr The address of the SPI Engine's axi register where the data + * will be written + * @param reg_data Data that will be written + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_write(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t reg_data) +{ + axi_io_write(desc->spi_engine_baseaddr, reg_addr, reg_data); + + return SUCCESS; +} + +/** + * @brief Read SPI Engine's axi registers + * + * @param desc Decriptor containing SPI Engine's parameters + * @param reg_addr The address of the SPI Engine's axi register from where the + * data where the data will be read + * @param reg_data Pointer where the read that will be stored + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_read(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t *reg_data) +{ + axi_io_read(desc->spi_engine_baseaddr, reg_addr, reg_data); + return SUCCESS; +} + +/** + * @brief Set width of the transferred word over SPI + * + * @param desc Decriptor containing SPI interface parameters + * @param data_width The desired data width + * The supported values are: + * - 8 + * - 16 + * - 24 + * - 32 + */ +int32_t spi_engine_set_transfer_width(struct spi_desc *desc, + uint8_t data_width) +{ + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + if (data_width > desc_extra->max_data_width) + desc_extra->data_width = desc_extra->max_data_width; + else + desc_extra->data_width = data_width; + + return SUCCESS; +} + +/** + * @brief Set SPI engine clock frequency + * + * @param desc Decriptor containing SPI Engine's parameters + * @param speed_hz SPI engine transfer speed + */ +void spi_engine_set_speed(struct spi_desc *desc, + uint32_t speed_hz) +{ + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + desc_extra->clk_div = desc_extra->ref_clk_hz / + (2 * speed_hz) - 1; +} + +/** + * @brief Set the number of words transferred in a single transaction + * + * @param desc Decriptor containing SPI Engine's parameters + * @param bytes_number The number of bytes to be converted + * @return uint8_t A number of words in which bytes_number can be grouped + */ +static uint8_t spi_get_words_number(struct spi_engine_desc *desc, + uint8_t bytes_number) +{ + uint8_t xfer_word_len; + uint8_t words_number; + + xfer_word_len = desc->data_width / 8; + words_number = bytes_number / xfer_word_len; + + if ((bytes_number % xfer_word_len) != 0) + words_number++; + + return words_number; +} + +/** + * @brief Get the word length in bytes + * + * @param desc Decriptor containing SPI Engine's parameters + * @return uint8_t Number of bytes that fit in one word + */ +static uint8_t spi_get_word_length(struct spi_engine_desc *desc) +{ + uint8_t word_length; + + word_length = desc->data_width / 8; + + return word_length; +} + +/** + * @brief Compute the prescaler used to set the sleep period. + * + * @param desc Decriptor containing SPI interface parameters + * @param sleep_time_ns The amount of time where the transfer hangs + * @param sleep_div Clock prescaler + * @return int32_t This function allways returns SUCCESS + */ +static int32_t spi_get_sleep_div(struct spi_desc *desc, + uint32_t sleep_time_ns, + uint32_t *sleep_div) +{ + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + /* + * Engine Wiki: + * + * The frequency of the SCLK signal is derived from the + * module clock frequency using the following formula: + * f_sclk = f_clk / ((div + 1) * 2) + */ + + *sleep_div = (desc->max_speed_hz / 1000000 * sleep_time_ns / 1000) / + ((eng_desc->clk_div + 1) * 2) - 1; + + return SUCCESS; +} + +/** + * @brief Create a new commands queue used in a spi transfer + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Command with witch the buffer will be initiated + * @return int32_t Failure if the memory allocation failed + */ +static int32_t spi_engine_queue_new_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t cmd) +{ + struct spi_engine_cmd_queue *local_fifo; + + local_fifo = (spi_engine_cmd_queue*)malloc(sizeof(*local_fifo)); + + if(!local_fifo) + return FAILURE; + + local_fifo->cmd = cmd; + local_fifo->next = NULL; + *fifo = local_fifo; + + return SUCCESS; +} + +/** + * @brief Add a command at the end of an existing queue + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Command to be added + */ +static void spi_engine_queue_add_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t cmd) +{ + struct spi_engine_cmd_queue *to_add = NULL; + struct spi_engine_cmd_queue *local_fifo; + + local_fifo = *fifo; + while (local_fifo->next != NULL) { + // Get the last element + local_fifo = local_fifo->next; + } + + // Create a new element + spi_engine_queue_new_cmd(&to_add, cmd); + // Add as the next element + local_fifo->next = to_add; +} + +/** + * @brief Add a command at the beginning of an existing queue + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Command to be added + */ +static void spi_engine_queue_append_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t cmd) +{ + struct spi_engine_cmd_queue *to_add = NULL; + + // Create a new element + spi_engine_queue_new_cmd(&to_add, cmd); + // Interchange the addresses + to_add->next = *fifo; + *fifo = to_add; +} + + +/** + * @brief Get the command from the beginning of the queue + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Value of the command that was extracted + * @return int32_t Return FAILURE if the queue is empty + */ +static int32_t spi_engine_queue_get_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t *cmd) +{ + struct spi_engine_cmd_queue *local_fifo; + + if (!*fifo) + return FAILURE; + + local_fifo = *fifo; + *cmd = local_fifo->cmd; + if ((*fifo)->next) { + *fifo = local_fifo->next; + free(local_fifo); + } else { + free(*fifo); + *fifo = NULL; + } + + return SUCCESS; +} + +/** + * @brief Free the memory allocated by a queue + * + * @param fifo The queue that needs it's memory freed + * @return int32_t This function allways return SUCCESS + */ +static int32_t spi_engine_queue_free(struct spi_engine_cmd_queue **fifo) +{ + if(*fifo && (*fifo)->next) + spi_engine_queue_free(&(*fifo)->next); + if((*fifo) != NULL) { + free(*fifo); + *fifo = NULL; + } + + return SUCCESS; +} + +/** + * @brief Write the SPI engine's command fifo + * + * @param desc Decriptor containing SPI Engine's parameters + * @param cmd The command that will be written + * @return int32_t Returns FAILURE if the the axi transfer failed + */ +static int32_t spi_engine_write_cmd_reg(struct spi_engine_desc *desc, + uint32_t cmd) +{ + int32_t ret; + + /* Check if offload is enabled */ + if(desc->offload_config & (OFFLOAD_TX_EN | OFFLOAD_RX_EN)) { + ret = spi_engine_write(desc, + SPI_ENGINE_REG_OFFLOAD_CMD_MEM(0), + cmd); + + } else { + ret = spi_engine_write(desc, + SPI_ENGINE_REG_CMD_FIFO, + cmd); + } + + return ret; +} + +/** + * @brief Write a transfer command to the SPI engine's command fifo + * + * @param desc Decriptor containing SPI Engine's parameters + * @param read_write Read/Write operation flag + * @param bytes_number Number of bytes to transfer + * @return int32_t This function allways returns SUCCESS + */ +static int32_t spi_engine_transfer(struct spi_engine_desc *desc, + uint8_t read_write, + uint8_t bytes_number) +{ + uint8_t words_number; + + words_number = spi_get_words_number(desc, bytes_number); + + desc->offload_tx_len += words_number; + + /* + * Engine Wiki: + * + * https://wiki.analog.com/resources/fpga/peripherals/spi_engine + * + * The words number is zero based + */ + + spi_engine_write_cmd_reg(desc, + SPI_ENGINE_CMD_TRANSFER(read_write, + words_number - 1)); + + return SUCCESS; +} + +/** + * @brief Change the state of the chip select port + * + * @param desc Decriptor containing SPI interface parameters + * @param assert Chip select state. + * The supported values are : + * -true (HIGH) + * -false (LOW) + */ +static void spi_engine_set_cs(struct spi_desc *desc, + bool assert) +{ + uint8_t mask; + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + mask = 0xFF; + /* Switch the state only of the selected chip select */ + if (!assert) + mask ^= BIT(desc->chip_select); + + spi_engine_write_cmd_reg(eng_desc, + SPI_ENGINE_CMD_ASSERT(eng_desc->cs_delay, + mask)); +} + +/** + * @brief Add a delay between the engine commands + * + * @param desc Decriptor containing SPI interface parameters + * @param sleep_time_ns Number of nanoseconds to sleep between commands + */ +static void spi_gen_sleep_ns(struct spi_desc *desc, + uint32_t sleep_time_ns) +{ + uint32_t sleep_div; + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + spi_get_sleep_div(desc, sleep_time_ns, &sleep_div); + + spi_engine_write_cmd_reg(eng_desc, SPI_ENGINE_CMD_SLEEP(sleep_div)); +} + +/** + * @brief Spi engine command interpreter + * + * @param desc Decriptor containing SPI interface parameters + * @param cmd Command to send to the engine + * @return int32_t - SUCCESS if the command is transferred + * - FAILURE if the command format is invalid + */ +static int32_t spi_engine_write_cmd(struct spi_desc *desc, + uint32_t cmd) +{ + uint8_t engine_command; + uint8_t parameter; + uint8_t modifier; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + engine_command = (cmd >> 12) & 0x0F; + modifier = (cmd >> 8) & 0x0F; + parameter = cmd & 0xFF; + + switch(engine_command) { + case SPI_ENGINE_INST_TRANSFER: + spi_engine_transfer(desc_extra, modifier, parameter); + break; + + case SPI_ENGINE_INST_ASSERT: + if(parameter == 0xFF) { + /* Set the CS HIGH */ + spi_engine_set_cs(desc, true); + } else if(parameter == 0x00) { + /* Set the CS LOW */ + spi_engine_set_cs(desc, false); + } + break; + + /* The SYNC and SLEEP commands got the same value but different + modifier */ + case SPI_ENGINE_INST_SYNC_SLEEP: + /* SYNC instruction */ + if(modifier == 0x00) { + spi_engine_write_cmd_reg(desc_extra, cmd); + } else if(modifier == 0x01) { + spi_gen_sleep_ns(desc, parameter); + } + break; + case SPI_ENGINE_INST_CONFIG: + spi_engine_write_cmd_reg(desc_extra, cmd); + + break; + + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Prepare the command queue before sending it to the engine + * + * @param desc Decriptor containing SPI interface parameters + * @param msg Structure used to store the transfer messages + * @return int32_t This function allways returns SUCCESS + */ +static int32_t spi_engine_compile_message(struct spi_desc *desc, + struct spi_engine_msg *msg) +{ + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + /* Configure the prescaler */ + spi_engine_queue_append_cmd(&msg->cmds, + SPI_ENGINE_CMD_CONFIG( + SPI_ENGINE_CMD_REG_CLK_DIV, + desc_extra->clk_div)); + + /* Set the data transfer length */ + spi_engine_queue_append_cmd(&msg->cmds, + SPI_ENGINE_CMD_CONFIG( + SPI_ENGINE_CMD_DATA_TRANSFER_LEN, + desc_extra->data_width)); + /* + * Configure the spi mode : + * - 3 wire + * - CPOL + * - CPHA + */ + spi_engine_queue_append_cmd(&msg->cmds, + SPI_ENGINE_CMD_CONFIG( + SPI_ENGINE_CMD_REG_CONFIG, + desc->mode)); + + /* Add a sync command to signal that the transfer has finished */ + spi_engine_queue_add_cmd(&msg->cmds, SPI_ENGINE_CMD_SYNC(_sync_id)); + + return SUCCESS; +} + +/** + * @brief Initiate a spi transfer (Blocking) + * + * @param desc Decriptor containing SPI interface parameters + * @param msg Structure used to store the transfer messages + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation failed + */ +static int32_t spi_engine_transfer_message(struct spi_desc *desc, + struct spi_engine_msg *msg) +{ + uint32_t i; + uint32_t data; + uint32_t sync_id; + bool offload_en; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + spi_engine_compile_message(desc, msg); + + offload_en = (desc_extra->offload_config & OFFLOAD_TX_EN) | + (desc_extra->offload_config & OFFLOAD_RX_EN); + + /* Write the command fifo buffer */ + while(msg->cmds != NULL) { + spi_engine_queue_get_cmd(&msg->cmds, &data); + spi_engine_write_cmd(desc, data); + } + + /* Write a number of tx_length WORDS on the SDO line */ + if(offload_en) { + for(i = 0; i < desc_extra->offload_tx_len; i++) + spi_engine_write(desc_extra, + SPI_ENGINE_REG_OFFLOAD_SDO_MEM(0), + msg->tx_buf[i]); + + } else { + if(msg->tx_buf != NULL){ + for(i = 0; i < msg->tx_length; i++) + spi_engine_write(desc_extra, + SPI_ENGINE_REG_SDO_DATA_FIFO, + msg->tx_buf[i]); + } + do { + spi_engine_read(desc_extra, + SPI_ENGINE_REG_SYNC_ID, + &sync_id); + } + /* Wait for the end sync signal */ + while(sync_id != _sync_id); + _sync_id++; + + /* Read a number of rx_length WORDS from the SDI line and store + them */ + for(i = 0; i < msg->rx_length; i++) { + spi_engine_read(desc_extra, + SPI_ENGINE_REG_SDI_DATA_FIFO, + &data); + /* Store the rx data if rx buffer valid, flush sdi_fifo if + rx buffer is invalid.*/ + if(msg->rx_buf != NULL){ + msg->rx_buf[i] = data; + } + } + } + + return SUCCESS; +} + +/** + * @brief Initialize the spi engine + * + * @param desc Decriptor containing SPI interface parameters + * @param param Structure containing the spi init parameters + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation failed + */ +int32_t spi_engine_init(struct spi_desc **desc, + const struct spi_init_param *param) +{ + uint32_t data_width = 0; + uint32_t spi_engine_version = 0; + struct spi_engine_desc *eng_desc; + struct spi_engine_init_param *spi_engine_init; + + if (!param) { + return FAILURE; + } + + *desc = malloc(sizeof(**desc)); + if(! *desc) { + free(*desc); + return FAILURE; + } + + eng_desc = (struct spi_engine_desc*)malloc(sizeof(*eng_desc)); + + if (!eng_desc) + return FAILURE; + + spi_engine_init = param->extra; + + (*desc)->max_speed_hz = param->max_speed_hz; + (*desc)->chip_select = param->chip_select; + (*desc)->mode = param->mode; + (*desc)->extra = eng_desc; + + eng_desc->offload_config = OFFLOAD_DISABLED; + eng_desc->spi_engine_baseaddr = spi_engine_init->spi_engine_baseaddr; + eng_desc->type = spi_engine_init->type; + eng_desc->cs_delay = spi_engine_init->cs_delay; + eng_desc->ref_clk_hz = spi_engine_init->ref_clk_hz; + eng_desc->clk_div = eng_desc->ref_clk_hz / + (2 * param->max_speed_hz) - 1; + + /* Perform a reset */ + spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x01); + usleep(1000); + spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x00); + + /* Get current data width */ + spi_engine_read(eng_desc, SPI_ENGINE_REG_DATA_WIDTH, &data_width); + eng_desc->max_data_width = data_width; + + spi_engine_set_transfer_width(*desc, spi_engine_init->data_width); + + /* Get spi engine version */ + spi_engine_read(eng_desc, SPI_ENGINE_REG_VERSION, &spi_engine_version); + + printf("Spi engine v%"PRIu32".%"PRIu32".%"PRIu32" successfully initialized.\n", + (spi_engine_version >> 16), + ((spi_engine_version >> 8) & 0xFF), + (spi_engine_version & 0xFF)); + + return SUCCESS; +} + +/** + * @brief Write and read on the spi interface in 4-wire mode (full-duplex) + * + * @param desc Decriptor containing SPI interface parameters + * @param data Pointer to data buffer + * @param bytes_number Number of bytes to transfer + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation or transfer failed + */ +int32_t spi_engine_spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number) +{ + uint8_t word_len; + uint8_t words_number; + int32_t ret; + struct spi_engine_msg msg; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + /* If we want to access SPI interface and SPI engine offload module was + * activated, we need to disable it + * This is set in spi_engine_offload_init() */ + desc_extra->offload_config = OFFLOAD_DISABLED; + /* This is set in spi_engine_offload_transfer() */ + spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0); + + words_number = spi_get_words_number(desc_extra, bytes_number); + + msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds)); + if (!msg.cmds) + return FAILURE; + + msg.tx_buf =(uint32_t*)calloc(words_number, sizeof(msg.tx_buf[0])); + msg.rx_buf =(uint32_t*)calloc(words_number, sizeof(msg.rx_buf[0])); + msg.tx_length = words_number; + msg.rx_length = words_number; + + /* Get the length of transferred word */ + word_len = spi_get_word_length(desc_extra); + + /* Make sure the CS is HIGH before starting a transaction */ + msg.cmds->next = NULL; + msg.cmds->cmd = CS_HIGH; + // Assert select. + spi_engine_queue_add_cmd(&msg.cmds, CS_LOW); + // add read/write command + spi_engine_queue_add_cmd(&msg.cmds, WRITE_READ(bytes_number)); + // Disable select. + spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH); + + /* Pack the bytes into engine WORDS */ + for (int i = 0; i < bytes_number; i++) + msg.tx_buf[i / word_len] |= data[i] << (desc_extra->data_width- + (i % word_len + 1) * 8); + + ret = spi_engine_transfer_message(desc, &msg); + + for (int i = 0; i < bytes_number; i++) + data[i] = msg.rx_buf[(i) / word_len] >> + (desc_extra->data_width - + ((i) % word_len + 1) * 8); + + spi_engine_queue_free(&msg.cmds); + free(msg.tx_buf); + free(msg.rx_buf); + + return ret; +} + +/** + * @brief Write and read on the spi interface in 3-wire mode (half-duplex) + * + * @param desc Decriptor containing SPI interface parameters + * @param data Pointer to data buffer + * @param bytes_number Number of bytes to transfer + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation or transfer failed + */ +int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number) +{ + uint8_t word_len; + uint8_t wr_words_number; + uint8_t rd_words_number; + int32_t ret; + struct spi_engine_msg msg; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + /* If we want to access SPI interface and SPI engine offload module was + * activated, we need to disable it + * This is set in spi_engine_offload_init() */ + desc_extra->offload_config = OFFLOAD_DISABLED; + /* This is set in spi_engine_offload_transfer() */ + spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0); + + wr_words_number = spi_get_words_number(desc_extra, write_bytes_number); + rd_words_number = spi_get_words_number(desc_extra, read_bytes_number); + + msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds)); + if (!msg.cmds) + return FAILURE; + + msg.tx_buf =(wr_words_number>0)?(uint32_t*)calloc(wr_words_number, sizeof(msg.tx_buf[0])):NULL; + msg.rx_buf =(rd_words_number>0)?(uint32_t*)calloc(rd_words_number, sizeof(msg.rx_buf[0])):NULL; + msg.tx_length = wr_words_number; + msg.rx_length = rd_words_number; + + /* Get the length of transferred word */ + word_len = spi_get_word_length(desc_extra); + + /* Make sure the CS is HIGH before starting a transaction */ + msg.cmds->next = NULL; + msg.cmds->cmd = CS_HIGH; + + // Assert select. + spi_engine_queue_add_cmd(&msg.cmds, CS_LOW); + + // add read/write command + if(write_bytes_number > 0) + spi_engine_queue_add_cmd(&msg.cmds, WRITE(write_bytes_number)); + if(read_bytes_number > 0) + spi_engine_queue_add_cmd(&msg.cmds, READ(read_bytes_number)); + + // Disable select. + spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH); + + /* Pack the bytes into engine WORDS */ + for (int i = 0; i < write_bytes_number; i++) + msg.tx_buf[i / word_len] |= write_data[i] << (desc_extra->data_width- + (i % word_len + 1) * 8); + + ret = spi_engine_transfer_message(desc, &msg); + + for (int i = 0; i < read_bytes_number; i++) + read_data[i] = msg.rx_buf[(i) / word_len] >> + (desc_extra->data_width - + ((i) % word_len + 1) * 8); + + spi_engine_queue_free(&msg.cmds); + free(msg.tx_buf); + free(msg.rx_buf); + + return ret; +} + +/** + * @brief Initialize the SPI engine's offload module + * + * @param desc Decriptor containing SPI interface parameters + * @param param Structure containing the offload init parameters + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_offload_init(struct spi_desc *desc, + const struct spi_engine_offload_init_param *param) +{ + struct spi_engine_desc *eng_desc; + struct axi_dmac_init dmac_init; + uint32_t dma_flags; + + eng_desc = desc->extra; + + eng_desc->offload_config = param->offload_config; + + if(!(param->dma_flags)) + dma_flags = DMA_CYCLIC; + else + dma_flags = *(param->dma_flags); + + if(param->offload_config & OFFLOAD_TX_EN) { + dmac_init.name = "DAC DMAC"; + dmac_init.base = param->tx_dma_baseaddr; + dmac_init.direction = DMA_MEM_TO_DEV; + dmac_init.flags = dma_flags; + axi_dmac_init(&eng_desc->offload_tx_dma, &dmac_init); + if(!eng_desc->offload_tx_dma) + return FAILURE; + } + if(param->offload_config & OFFLOAD_RX_EN) { + dmac_init.name = "ADC DMAC"; + dmac_init.base = param->rx_dma_baseaddr; + dmac_init.direction = DMA_DEV_TO_MEM; + dmac_init.flags = dma_flags; + axi_dmac_init(&eng_desc->offload_rx_dma, &dmac_init); + if(!eng_desc->offload_rx_dma) + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Initiate a SPI transfer in offload mode + * + * @param desc Decriptor containing SPI interface parameters + * @param msg Offload message that get's to be transferred + * @param no_samples Number of time the messages will be transferred + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_offload_transfer(struct spi_desc *desc, + struct spi_engine_offload_message msg, + uint32_t no_samples) +{ + struct spi_engine_msg transfer; + struct spi_engine_desc *eng_desc; + uint32_t i; + uint8_t word_length; + + eng_desc = desc->extra; + + /* Check if offload is disabled */ + if(!((eng_desc->offload_config & OFFLOAD_TX_EN) | + (eng_desc->offload_config & OFFLOAD_RX_EN))) + return FAILURE; + + spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 1); + spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 0); + + eng_desc->offload_tx_len = 0; + eng_desc->offload_rx_len = 0; + + transfer.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*transfer.cmds)); + + if (!transfer.cmds) + return FAILURE; + + transfer.tx_buf = msg.commands_data; + + /* Load the commands into the message */ + transfer.cmds->next = NULL; + transfer.cmds->cmd = msg.commands[0]; + i = 1; + while(i < msg.no_commands) { + spi_engine_queue_add_cmd(&transfer.cmds, msg.commands[i++]); + + } + + spi_engine_transfer_message(desc, &transfer); + + /* Start transfer */ + spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0x0001); + + word_length = spi_get_word_length(eng_desc); + if(eng_desc->offload_config & OFFLOAD_TX_EN) { + axi_dmac_transfer(eng_desc->offload_tx_dma, + msg.tx_addr, + word_length * eng_desc->offload_tx_len * + no_samples); + } + + if(eng_desc->offload_config & OFFLOAD_RX_EN) { + axi_dmac_transfer(eng_desc->offload_rx_dma, + msg.rx_addr, + word_length * eng_desc->offload_tx_len * + no_samples); + } + + usleep(1000); + + spi_engine_queue_free(&transfer.cmds); + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by spi_init(). + * + * @param desc Decriptor containing SPI interface parameters + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_remove(struct spi_desc *desc) +{ + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + if(eng_desc->offload_config & OFFLOAD_TX_EN) + axi_dmac_remove(eng_desc->offload_tx_dma); + if(eng_desc->offload_config & OFFLOAD_RX_EN) + axi_dmac_remove(eng_desc->offload_rx_dma); + free(desc->extra); + free(desc); + + return SUCCESS; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.h new file mode 100644 index 00000000..90dd18e9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.h @@ -0,0 +1,231 @@ +/******************************************************************************* + * @file spi_engine.h + * @brief Header file of SPI Engine core features. + * @author Sergiu Cuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef SPI_ENGINE_H +#define SPI_ENGINE_H + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +#include "spi_engine_private.h" +#include "../../platform/spi_extra.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define OFFLOAD_DISABLED 0x00 +#define OFFLOAD_TX_EN BIT(0) +#define OFFLOAD_RX_EN BIT(1) +#define OFFLOAD_TX_RX_EN OFFLOAD_TX_EN | OFFLOAD_RX_EN + +#define SPI_ENGINE_MSG_QUEUE_END 0xFFFFFFFF + +/* Spi engine commands */ +#define WRITE_OR_READ(mode, no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ +((mode) << 8) | (no_bytes)) + +#define WRITE(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ + (SPI_ENGINE_INSTRUCTION_TRANSFER_W << 8) | (no_bytes)) + +#define READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ + (SPI_ENGINE_INSTRUCTION_TRANSFER_R << 8) | (no_bytes)) + +#define WRITE_READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ + (SPI_ENGINE_INSTRUCTION_TRANSFER_RW << 8) | (no_bytes)) + + + +#define SLEEP(time) SPI_ENGINE_CMD_SLEEP(time & 0xF) + +/* The delay and chip select parmeters are passed over the engine descriptor +and will be used inside the function call */ +#define CS_HIGH SPI_ENGINE_CMD_ASSERT(0x00, 0xFF) +#define CS_LOW SPI_ENGINE_CMD_ASSERT(0x00, 0x00) + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @struct spi_engine_init_param + * @brief Structure containing the init parameters needed by the SPI engine + */ +struct spi_engine_init_param { + /** SPI engine reference clock */ + uint32_t ref_clk_hz; + /** Type of implementation */ + enum xil_spi_type type; + /** Base address where the HDL core is situated */ + uint32_t spi_engine_baseaddr; + /** Delay between the CS toggle and the start of SCLK */ + uint32_t cs_delay; + /** Data with of one SPI transfer ( in bits ) */ + uint8_t data_width; +}; + + +/** + * @struct spi_engine_desc + * @brief Structure representing an SPI engine device + */ +struct spi_engine_desc { + /** SPI engine reference clock */ + uint32_t ref_clk_hz; + /** Type of implementation */ + enum xil_spi_type type; + /** Pointer to a DMAC used in transmission */ + struct axi_dmac *offload_tx_dma; + /** Pointer to a DMAC used in reception */ + struct axi_dmac *offload_rx_dma; + /** Offload's module transfer direction : TX, RX or both */ + uint8_t offload_config; + /** Number of words that the module has to send */ + uint8_t offload_tx_len; + /** Number of words that the module has to receive */ + uint8_t offload_rx_len; + /** Base address where the HDL core is situated */ + uint32_t spi_engine_baseaddr; + /** Base address where the RX DMAC core is situated */ + uint32_t rx_dma_baseaddr; + /** Base address where the TX DMAC core is situated */ + uint32_t tx_dma_baseaddr; + /** Delay between the CS toggle and the start of SCLK */ + uint8_t cs_delay; + /** Clock divider used in transmission delays */ + uint32_t clk_div; + /** Data with of one SPI transfer ( in bits ) */ + uint8_t data_width; + /** The maximum data width supported by the engine */ + uint8_t max_data_width; +}; + + +/** + * @struct spi_engine_offload_init_param + * @brief Structure containing the init parameters needed by the offload module + */ +struct spi_engine_offload_init_param { + /** Base address where the RX DMAC core is situated */ + uint32_t rx_dma_baseaddr; + /** Base address where the TX DMAC core is situated */ + uint32_t tx_dma_baseaddr; + /** DMAC flags - if not initialized, the default value is DMA_CYCLIC */ + uint32_t *dma_flags; + /** Offload's module transfer direction : TX, RX or both */ + uint8_t offload_config; +}; + +/** + * @struct spi_engine_offload_message + * @brief Structure representing an offload message + */ +struct spi_engine_offload_message { + /** Pointer to the SPI engine commands buffer that will be sent. + * The available commands can be found at: + * https://wiki.analog.com/resources/fpga/peripherals/spi_engine/ + */ + uint32_t *commands; + /** Length of the SPI engine commands buffer */ + uint32_t no_commands; + /** Pointer of the data that will be sent over spi */ + uint32_t *commands_data; + /** The address where the data that will be transmitted is situated */ + uint32_t tx_addr; + /** The address where the data that will be received is situated */ + uint32_t rx_addr; +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/** + * @brief Spi engine platform specific SPI platform ops structure + */ +extern const struct spi_platform_ops xil_spi_ops; + +/* Write SPI Engine's axi registers */ +int32_t spi_engine_write(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t reg_data); + +/* Read SPI Engine's axi registers */ +int32_t spi_engine_read(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t *reg_data); +/* Initialize the SPI engine device */ +int32_t spi_engine_init(struct spi_desc **desc, + const struct spi_init_param *param); + +/* Write and read data over SPI using the SPI engine */ +int32_t spi_engine_spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number); + +/* Write and read data over SPI using the SPI engine in 3-wire mode */ +int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number); +/* Free the resources used by the SPI engine device */ +int32_t spi_engine_remove(struct spi_desc *desc); + +/* Initialize the SPI engine offload module */ +int32_t spi_engine_offload_init(struct spi_desc *desc, + const struct spi_engine_offload_init_param *param); + +/* Write and read data over SPI using the offload module */ +int32_t spi_engine_offload_transfer(struct spi_desc *desc, + struct spi_engine_offload_message msg, + uint32_t no_samples); + +/* Set SPI transfer width */ +int32_t spi_engine_set_transfer_width(struct spi_desc *desc, + uint8_t data_wdith); + +/* Set SPI transfer speed */ +void spi_engine_set_speed(struct spi_desc *desc, + uint32_t speed_hz); + +#endif // SPI_ENGINE_H diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h new file mode 100644 index 00000000..2c71ebfa --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h @@ -0,0 +1,154 @@ +/******************************************************************************* + * @file spi_engine_private.h + * @brief Private definitions of the SPI Engine + * @author Sergiu Cuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef SPI_ENGINE_PRIVATE_H +#define SPI_ENGINE_PRIVATE_H + +#include +#include + +#include "../../../include/spi.h" +#include "../../../include/util.h" + +/******************************************************************************/ +/*************************** Spi Engine registers *****************************/ +/******************************************************************************/ + +#define SPI_ENGINE_REG_VERSION 0x00 +#define SPI_ENGINE_REG_DATA_WIDTH 0x0C +#define SPI_ENGINE_REG_RESET 0x40 +#define SPI_ENGINE_REG_INT_ENABLE 0x80 +#define SPI_ENGINE_REG_INT_PENDING 0x84 +#define SPI_ENGINE_REG_INT_SOURCE 0x88 +#define SPI_ENGINE_REG_SYNC_ID 0xC0 +#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xD0 +#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xD4 +#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xD8 +#define SPI_ENGINE_REG_CMD_FIFO 0xE0 +#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xE4 +#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xE8 +#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xEC + +/******************************************************************************/ +/************************ Spi Engine register parameters **********************/ +/******************************************************************************/ + +#define SPI_ENGINE_INST_TRANSFER 0x00 +#define SPI_ENGINE_INST_ASSERT 0x01 +#define SPI_ENGINE_INST_CONFIG 0x02 +#define SPI_ENGINE_INST_SYNC_SLEEP 0x03 +#define SPI_ENGINE_INST_MISC 0x03 +#define SPI_ENGINE_CMD_REG_CLK_DIV 0x00 +#define SPI_ENGINE_CMD_REG_CONFIG 0x01 +#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN 0x02 +#define SPI_ENGINE_MISC_SYNC 0x00 +#define SPI_ENGINE_MISC_SLEEP 0x01 +#define SPI_ENGINE_SYNC_TRANSFER_BEGIN BIT(1) +#define SPI_ENGINE_SYNC_TRANSFER_END BIT(2) +#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0) +#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1) +#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2) +#define SPI_ENGINE_INT_SYNC BIT(3) +#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE BIT(0) +#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED BIT(0) +#define SPI_ENGINE_CONFIG_CPHA BIT(0) +#define SPI_ENGINE_CONFIG_CPOL BIT(1) +#define SPI_ENGINE_CONFIG_3WIRE BIT(2) +#define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff) +#define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff) +#define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff) + +/******************************************************************************/ +/**************************** Spi Engine commands *****************************/ +/******************************************************************************/ + +#define SPI_ENGINE_INSTRUCTION_TRANSFER_W 0x01 +#define SPI_ENGINE_INSTRUCTION_TRANSFER_R 0x02 +#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW 0x03 + +#define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_RESET(x) (0x108 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x) (0x110 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x) (0x114 + (0x20 * x)) + +#define SPI_ENGINE_CMD(inst, arg1, arg2) \ + (((inst & 0x03) << 12) | \ + ((arg1 & 0x03) << 8) | arg2 ) + +#define SPI_ENGINE_CMD_TRANSFER(readwrite, n) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, \ + (readwrite), (n)) + +#define SPI_ENGINE_CMD_ASSERT(delay, cs) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, \ + (delay), (cs)) + +#define SPI_ENGINE_CMD_CONFIG(reg, val) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_CONFIG, \ + (reg), (val)) + +#define SPI_ENGINE_CMD_SLEEP(delay) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \ + SPI_ENGINE_MISC_SLEEP, \ + (delay)) + +#define SPI_ENGINE_CMD_SYNC(id) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \ + SPI_ENGINE_MISC_SYNC, \ + (id)) + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +typedef struct spi_engine_cmd_queue { + uint32_t cmd; + struct spi_engine_cmd_queue *next; +} spi_engine_cmd_queue; + +typedef struct spi_engine_msg { + uint32_t *tx_buf; + uint32_t *rx_buf; + uint32_t tx_length; + uint32_t rx_length; + struct spi_engine_cmd_queue *cmds; +} spi_engine_msg; + +#endif // SPI_ENGINE_PRIVATE_H diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/frequency/hmc7044/hmc7044.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/frequency/hmc7044/hmc7044.c new file mode 100644 index 00000000..44129a52 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/frequency/hmc7044/hmc7044.c @@ -0,0 +1,928 @@ +/***************************************************************************//** + * @file hmc7044.c + * @brief Implementation of HMC7044, HMC7043 Driver. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018-2020(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include "hmc7044.h" +#include "../../../include/error.h" +#include "../../../include/util.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#define HMC7044_WRITE (0 << 15) +#define HMC7044_READ (1 << 15) +#define HMC7044_CNT(x) (((x) - 1) << 13) +#define HMC7044_ADDR(x) ((x) & 0xFFF) + +/* Global Control */ +#define HMC7044_REG_SOFT_RESET 0x0000 +#define HMC7044_SOFT_RESET BIT(0) + +#define HMC7044_REG_REQ_MODE_0 0x0001 +#define HMC7044_RESEED_REQ BIT(7) +#define HMC7044_HIGH_PERF_DISTRIB_PATH BIT(6) +#define HMC7044_HIGH_PERF_PLL_VCO BIT(5) +#define HMC7044_FORCE_HOLDOVER BIT(4) +#define HMC7044_MUTE_OUT_DIV BIT(3) +#define HMC7044_PULSE_GEN_REQ BIT(2) +#define HMC7044_RESTART_DIV_FSM BIT(1) +#define HMC7044_SLEEP_MODE BIT(0) + +#define HMC7044_REG_REQ_MODE_1 0x0002 +#define HMC7044_PLL2_AUTOTUNE_TRIG BIT(2) +#define HMC7044_SLIP_REQ BIT(1) + +#define HMC7044_REG_EN_CTRL_0 0x0003 +#define HMC7044_RF_RESEEDER_EN BIT(5) +#define HMC7044_VCO_SEL(x) (((x) & 0x3) << 3) +#define HMC7044_VCO_EXT 0 +#define HMC7044_VCO_HIGH 1 +#define HMC7044_VCO_LOW 2 +#define HMC7044_SYSREF_TIMER_EN BIT(2) +#define HMC7044_PLL2_EN BIT(1) +#define HMC7044_PLL1_EN BIT(0) + +#define HMC7044_REG_EN_CTRL_1 0x0004 +#define HMC7044_SEVEN_PAIRS(x) ((x) & 0x7f) + +#define HMC7044_REG_GLOB_MODE 0x0005 +#define HMC7044_REF_PATH_EN(x) ((x) & 0xf) +#define HMC7044_RFSYNC_EN BIT(4) +#define HMC7044_VCOIN_MODE_EN BIT(5) +#define HMC7044_SYNC_PIN_MODE(x) (((x) & 0x3) << 6) + +/* PLL1 */ +#define HMC7044_REG_CLKIN0_BUF_CTRL 0x000A +#define HMC7044_REG_CLKIN1_BUF_CTRL 0x000B +#define HMC7044_REG_CLKIN2_BUF_CTRL 0x000C +#define HMC7044_REG_CLKIN3_BUF_CTRL 0x000D +#define HMC7044_REG_OSCIN_BUF_CTRL 0x000E + +#define HMC7044_REG_PLL1_REF_PRIO_CTRL 0x0014 + +#define HMC7044_HIGH_Z_EN BIT(4) +#define HMC7044_LVPECL_EN BIT(3) +#define HMC7044_AC_COUPLING_EN BIT(2) +#define HMC7044_100_OHM_EN BIT(1) +#define HMC7044_BUF_EN BIT(0) + +#define HMC7044_REG_CLKIN_PRESCALER(x) (0x001C + (x)) +#define HMC7044_REG_OSCIN_PRESCALER 0x0020 + +#define HMC7044_REG_PLL1_R_LSB 0x0021 +#define HMC7044_R1_LSB(x) ((x) & 0xff) + +#define HMC7044_REG_PLL1_R_MSB 0x0022 +#define HMC7044_R1_MSB(x) (((x) & 0xff00) >> 8) + +#define HMC7044_REG_PLL1_N_LSB 0x0026 +#define HMC7044_N1_LSB(x) ((x) & 0xff) + +#define HMC7044_REG_PLL1_N_MSB 0x0027 +#define HMC7044_N1_MSB(x) (((x) & 0xff00) >> 8) + +#define HMC7044_REG_PLL1_LOCK_DETECT 0x0028 +#define HMC7044_LOCK_DETECT_SLIP BIT(5) +#define HMC7044_LOCK_DETECT_TIMER(x) ((x) & 0x1f) + +/* PLL2 */ +#define HMC7044_REG_PLL2_FREQ_DOUBLER 0x0032 +#define HMC7044_PLL2_FREQ_DOUBLER_DIS BIT(0) + +#define HMC7044_REG_PLL2_R_LSB 0x0033 +#define HMC7044_R2_LSB(x) ((x) & 0xff) + +#define HMC7044_REG_PLL2_R_MSB 0x0034 +#define HMC7044_R2_MSB(x) (((x) & 0xf00) >> 8) + +#define HMC7044_REG_PLL2_N_LSB 0x0035 +#define HMC7044_N2_LSB(x) ((x) & 0xff) + +#define HMC7044_REG_PLL2_N_MSB 0x0036 +#define HMC7044_N2_MSB(x) (((x) & 0xff00) >> 8) + +#define HMC7044_REG_OSCOUT_PATH 0x0039 +#define HMC7044_REG_OSCOUT_DRIVER_0 0x003A +#define HMC7044_REG_OSCOUT_DRIVER_1 0x003B + +/* GPIO/SDATA Control */ +#define HMC7044_REG_GPI_CTRL(x) (0x0046 + (x)) +#define HMC7044_REG_GPI_SEL(x) ((x) & 0xf) + +#define HMC7044_REG_GPO_CTRL(x) (0x0050 + (x)) +#define HMC7044_GPO_SEL(x) (((x) & 0x3f) << 2) +#define HMC7044_GPO_MODE BIT(1) +#define HMC7044_GPO_EN BIT(0) + +/* SYSREF/SYNC Control */ +#define HMC7044_REG_PULSE_GEN 0x005A +#define HMC7044_PULSE_GEN_MODE(x) ((x) & 0x7) + +#define HMC7044_REG_SYNC 0x005B +#define HMC7044_SYNC_RETIME BIT(2) +#define HMC7044_SYNC_THROUGH_PLL2 BIT(1) +#define HMC7044_SYNC_POLARITY BIT(0) + +#define HMC7044_REG_SYSREF_TIMER_LSB 0x005C +#define HMC7044_SYSREF_TIMER_LSB(x) ((x) & 0xff) + +#define HMC7044_REG_SYSREF_TIMER_MSB 0x005D +#define HMC7044_SYSREF_TIMER_MSB(x) (((x) & 0xf00) >> 8) + +#define HMC7044_CLK_INPUT_CTRL 0x0064 +#define HMC7044_LOW_FREQ_INPUT_MODE BIT(0) +#define HMC7044_DIV_2_INPUT_MODE BIT(1) + +/* Status and Alarm readback */ +#define HMC7044_REG_ALARM_READBACK 0x007D +#define HMC7044_REG_PLL1_STATUS 0x0082 + +#define HMC7044_PLL1_FSM_STATE(x) ((x) & 0x7) +#define HMC7044_PLL1_ACTIVE_CLKIN(x) (((x) >> 3) & 0x3) + +#define HMC7044_PLL2_LOCK_DETECT(x) ((x) & 0x1) +#define HMC7044_SYSREF_SYNC_STAT(x) ((x) & 0x2) +#define HMC7044_CLK_OUT_PH_STATUS(x) ((x) & 0x4) +#define HMC7044_PLL1_PLL2_LOCK_STAT(x) ((x) & 0x8) +#define HMC7044_SYNC_REQ_STATUS(x) ((x) & 0x10) + +/* Other Controls */ +#define HMC7044_REG_CLK_OUT_DRV_LOW_PW 0x009F +#define HMC7044_REG_CLK_OUT_DRV_HIGH_PW 0x00A0 +#define HMC7044_REG_PLL1_DELAY 0x00A5 +#define HMC7044_REG_PLL1_HOLDOVER 0x00A8 +#define HMC7044_REG_VTUNE_PRESET 0x00B0 + +/* Clock Distribution */ +#define HMC7044_REG_CH_OUT_CRTL_0(ch) (0x00C8 + 0xA * (ch)) +#define HMC7044_HI_PERF_MODE BIT(7) +#define HMC7044_SYNC_EN BIT(6) +#define HMC7044_CH_EN BIT(0) +#define HMC7044_START_UP_MODE_DYN_EN (BIT(3) | BIT(2)) + +#define HMC7044_REG_CH_OUT_CRTL_1(ch) (0x00C9 + 0xA * (ch)) +#define HMC7044_DIV_LSB(x) ((x) & 0xFF) + +#define HMC7044_REG_CH_OUT_CRTL_2(ch) (0x00CA + 0xA * (ch)) +#define HMC7044_DIV_MSB(x) (((x) >> 8) & 0xFF) + +#define HMC7044_REG_CH_OUT_CRTL_3(ch) (0x00CB + 0xA * (ch)) +#define HMC7044_REG_CH_OUT_CRTL_4(ch) (0x00CC + 0xA * (ch)) +#define HMC7044_REG_CH_OUT_CRTL_5(ch) (0x00CD + 0xA * (ch)) +#define HMC7044_REG_CH_OUT_CRTL_6(ch) (0x00CE + 0xA * (ch)) +#define HMC7044_REG_CH_OUT_CRTL_7(ch) (0x00CF + 0xA * (ch)) + +#define HMC7044_REG_CH_OUT_CRTL_8(ch) (0x00D0 + 0xA * (ch)) +#define HMC7044_DRIVER_MODE(x) (((x) & 0x3) << 3) +#define HMC7044_DRIVER_Z_MODE(x) (((x) & 0x3) << 0) +#define HMC7044_DYN_DRIVER_EN BIT(5) +#define HMC7044_FORCE_MUTE_EN BIT(7) + +#define HMC7044_NUM_CHAN 14 + +#define HMC7044_LOW_VCO_MIN 2150000 +#define HMC7044_LOW_VCO_MAX 2880000 +#define HMC7044_HIGH_VCO_MIN 2650000 +#define HMC7044_HIGH_VCO_MAX 3200000 + +#define HMC7044_RECOMM_LCM_MIN 30000 +#define HMC7044_RECOMM_LCM_MAX 70000 +#define HMC7044_RECOMM_FPD1 10000 + +#define HMC7044_R1_MAX 65535 +#define HMC7044_N1_MAX 65535 + +#define HMC7044_R2_MIN 1 +#define HMC7044_R2_MAX 4095 +#define HMC7044_N2_MIN 8 +#define HMC7044_N2_MAX 65535 + +#define HMC7044_OUT_DIV_MIN 1 +#define HMC7044_OUT_DIV_MAX 4094 + +/******************************************************************************/ +/************************** Functions Implementation **************************/ +/******************************************************************************/ + +/** + * SPI register write to device. + * @param dev - The device structure. + * @param reg - The register address. + * @param val - The register data. + * @return SUCCESS in case of success, negative error code otherwise. + */ +int32_t hmc7044_write(struct hmc7044_dev *dev, + uint16_t reg, + uint8_t val) +{ + uint8_t buf[3]; + uint16_t cmd; + + cmd = HMC7044_WRITE | HMC7044_CNT(1) | HMC7044_ADDR(reg); + buf[0] = cmd >> 8; + buf[1] = cmd & 0xFF; + buf[2] = val; + return spi_write_and_read_3wire(dev->spi_desc, buf, NULL, + ARRAY_SIZE(buf), 0); +} + +/** + * SPI register read from device. + * @param dev - The device structure. + * @param reg - The register address. + * @param val - The register data. + * @return SUCCESS in case of success, negative error code otherwise. + */ + +int32_t hmc7044_read(struct hmc7044_dev *dev, uint16_t reg, uint8_t *val) +{ + uint8_t wr_buf[2]; + uint8_t rd_data[1]; + uint16_t cmd; + int ret; + + cmd = HMC7044_READ | HMC7044_CNT(1) | HMC7044_ADDR(reg); + wr_buf[0] = cmd >> 8; + wr_buf[1] = cmd & 0xFF; + + ret = spi_write_and_read_3wire(dev->spi_desc, wr_buf, rd_data, + ARRAY_SIZE(wr_buf), ARRAY_SIZE(rd_data)); + if (ret != SUCCESS) + return ret; + + *val = rd_data[0]; + + return SUCCESS; +} + +/** + * Calculate the output channel divider. + * @param rate - The desired rate. + * @param parent_rate - The parent rate. + * @return The output divider. + */ +uint32_t hmc7044_calc_out_div(uint32_t rate, + uint32_t parent_rate) +{ + uint32_t div; + + div = DIV_ROUND_CLOSEST(parent_rate, rate); + + /* Supported odd divide ratios are 1, 3, and 5 */ + if ((div != 1) && (div != 3) && (div != 5) && (div % 2)) + div = DIV_ROUND_CLOSEST(parent_rate, rate * 2) * 2; + + div = clamp_t(unsigned int, + div, + HMC7044_OUT_DIV_MIN, + HMC7044_OUT_DIV_MAX); + + return div; +} + +/** + * Recalculate rate corresponding to a channel. + * @param dev - The device structure. + * @param chan_num - Channel number. + * @param rate - Channel rate. + * @return SUCCESS in case of success, negative error code otherwise. + */ +int32_t hmc7044_clk_recalc_rate(struct hmc7044_dev *dev, uint32_t chan_num, + uint64_t *rate) +{ + int i; + struct hmc7044_chan_spec *chan = NULL; + + /* Find the reqested channel number */ + for (i = 0; i < dev->num_channels; i++) { + if (dev->channels[i].num == chan_num) { + chan = &dev->channels[i]; + break; + } + } + if (chan == NULL ) + return FAILURE; + + *rate = dev->pll2_freq / chan->divider; + + return SUCCESS; +} + +/** + * Calculate closest possible rate + * @param dev - The device structure + * @param rate - The desired rate. + * @param rounded_rate - The closest possible rate of desired rate. + * @return SUCCESS in case of success, negative error code otherwise. + */ +int32_t hmc7044_clk_round_rate(struct hmc7044_dev *dev, uint32_t rate, + uint64_t *rounded_rate) +{ + uint32_t div = hmc7044_calc_out_div(rate, dev->pll2_freq); + + *rounded_rate = DIV_ROUND_CLOSEST(dev->pll2_freq, div); + + return SUCCESS; +} + +/** + * Set channel rate. + * @param dev - The device structure. + * @param chan_num - Channel number. + * @param rate - Channel rate. + * @return SUCCESS in case of success, negative error code otherwise. + */ +int32_t hmc7044_clk_set_rate(struct hmc7044_dev *dev, uint32_t chan_num, + uint64_t rate) +{ + uint32_t div; + int32_t ret; + int i; + struct hmc7044_chan_spec *chan = NULL; + + /* Find the reqested channel number */ + for (i = 0; i < dev->num_channels; i++) { + if (dev->channels[i].num == chan_num) { + chan = &dev->channels[i]; + break; + } + } + if (chan == NULL ) + return FAILURE; + + div = hmc7044_calc_out_div(rate, dev->pll2_freq); + chan->divider = div; + + ret = hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_1(chan->num), + HMC7044_DIV_LSB(div)); + if(ret < 0) + return ret; + + return hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_2(chan->num), + HMC7044_DIV_MSB(div)); +} + +/** + * Setup the device. + * @param dev - The device structure. + * @return SUCCESS in case of success, negative error code otherwise. + */ +static int32_t hmc7044_setup(struct hmc7044_dev *dev) +{ + struct hmc7044_chan_spec *chan; + bool high_vco_en; + bool pll2_freq_doubler_en; + uint32_t vcxo_freq, pll2_freq; + uint32_t clkin_freq[4]; + uint32_t lcm_freq; + uint32_t in_prescaler[5]; + uint32_t pll1_lock_detect; + uint32_t n1, r1; + uint32_t pfd1_freq; + uint32_t vco_limit; + uint32_t n2[2], r2[2]; + uint32_t i, ref_en = 0; + + vcxo_freq = dev->vcxo_freq / 1000; + pll2_freq = dev->pll2_freq / 1000; + + lcm_freq = vcxo_freq; + for (i = 0; i < ARRAY_SIZE(clkin_freq); i++) { + if (dev->clkin_freq_ccf[i]) + clkin_freq[i] = dev->clkin_freq_ccf[i] / 1000; + else + clkin_freq[i] = dev->clkin_freq[i] / 1000; + + if (clkin_freq[i]) { + lcm_freq = greatest_common_divisor(clkin_freq[i], lcm_freq); + ref_en |= BIT(i); + } + } + + while (lcm_freq > HMC7044_RECOMM_LCM_MAX) + lcm_freq /= 2; + + for (i = 0; i < ARRAY_SIZE(clkin_freq); i++) { + if (clkin_freq[i]) + in_prescaler[i] = clkin_freq[i] / lcm_freq; + else + in_prescaler[i] = 1; + } + in_prescaler[4] = vcxo_freq / lcm_freq; + + pll1_lock_detect = log_base_2((lcm_freq * 4000) / dev->pll1_loop_bw); + + /* fVCXO / N1 = fLCM / R1 */ + rational_best_approximation(vcxo_freq, lcm_freq, + HMC7044_N1_MAX, HMC7044_R1_MAX, + &n1, &r1); + + pfd1_freq = vcxo_freq / n1; + while ((pfd1_freq > HMC7044_RECOMM_FPD1) && + (n1 <= HMC7044_N1_MAX / 2) && + (r1 <= HMC7044_R1_MAX / 2)) { + pfd1_freq /= 2; + n1 *= 2; + r1 *= 2; + } + + dev->pll1_pfd = pfd1_freq; + + if (pll2_freq < HMC7044_LOW_VCO_MIN || + pll2_freq > HMC7044_HIGH_VCO_MAX) + return FAILURE; + + vco_limit = (HMC7044_LOW_VCO_MAX + HMC7044_HIGH_VCO_MIN) / 2; + if (pll2_freq >= vco_limit) + high_vco_en = true; + else + high_vco_en = false; + + /* fVCO / N2 = fVCXO * doubler / R2 */ + pll2_freq_doubler_en = true; + rational_best_approximation(pll2_freq, vcxo_freq * 2, + HMC7044_N2_MAX, HMC7044_R2_MAX, + &n2[0], &r2[0]); + + if (pll2_freq != vcxo_freq * n2[0] / r2[0]) { + rational_best_approximation(pll2_freq, vcxo_freq, + HMC7044_N2_MAX, HMC7044_R2_MAX, + &n2[1], &r2[1]); + + if (abs((int)pll2_freq - (int)(vcxo_freq * 2 * n2[0] / r2[0])) > + abs((int)pll2_freq - (int)(vcxo_freq * n2[1] / r2[1]))) { + n2[0] = n2[1]; + r2[0] = r2[1]; + pll2_freq_doubler_en = false; + } + } + + while ((n2[0] < HMC7044_N2_MIN) && (r2[0] <= HMC7044_R2_MAX / 2)) { + n2[0] *= 2; + r2[0] *= 2; + } + if (n2[0] < HMC7044_N2_MIN) + return -FAILURE; + + /* Resets all registers to default values */ + hmc7044_write(dev, HMC7044_REG_SOFT_RESET, HMC7044_SOFT_RESET); + mdelay(10); + hmc7044_write(dev, HMC7044_REG_SOFT_RESET, 0); + mdelay(10); + + /* Disable all channels */ + for (i = 0; i < HMC7044_NUM_CHAN; i++) + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(i), 0); + + /* Load the configuration updates (provided by Analog Devices) */ + hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_LOW_PW, 0x4d); + hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_HIGH_PW, 0xdf); + hmc7044_write(dev, HMC7044_REG_PLL1_DELAY, 0x06); + hmc7044_write(dev, HMC7044_REG_PLL1_HOLDOVER, 0x06); + hmc7044_write(dev, HMC7044_REG_VTUNE_PRESET, 0x04); + + uint8_t rd_back; + hmc7044_read(dev, HMC7044_REG_CLK_OUT_DRV_LOW_PW, &rd_back); + hmc7044_read(dev, HMC7044_REG_CLK_OUT_DRV_HIGH_PW, &rd_back); + hmc7044_read(dev, HMC7044_REG_PLL1_DELAY, &rd_back); + hmc7044_read(dev, HMC7044_REG_PLL1_HOLDOVER, &rd_back); + hmc7044_read(dev, HMC7044_REG_VTUNE_PRESET, &rd_back); + + + hmc7044_write(dev, HMC7044_REG_GLOB_MODE, + HMC7044_SYNC_PIN_MODE(dev->sync_pin_mode) | + (dev->clkin0_rfsync_en ? HMC7044_RFSYNC_EN : 0) | + (dev->clkin1_vcoin_en ? HMC7044_VCOIN_MODE_EN : 0) | + HMC7044_REF_PATH_EN(ref_en)); + + /* Program PLL2 */ + + /* Select the VCO range */ + hmc7044_write(dev, HMC7044_REG_EN_CTRL_0, + (dev->rf_reseeder_en ? HMC7044_RF_RESEEDER_EN : 0) | + HMC7044_VCO_SEL(high_vco_en ? + HMC7044_VCO_HIGH : + HMC7044_VCO_LOW) | + HMC7044_SYSREF_TIMER_EN | HMC7044_PLL2_EN | + HMC7044_PLL1_EN); + + /* Program the dividers */ + hmc7044_write(dev, HMC7044_REG_PLL2_R_LSB, + HMC7044_R2_LSB(r2[0])); + hmc7044_write(dev, HMC7044_REG_PLL2_R_MSB, + HMC7044_R2_MSB(r2[0])); + hmc7044_write(dev, HMC7044_REG_PLL2_N_LSB, + HMC7044_N2_LSB(n2[0])); + hmc7044_write(dev, HMC7044_REG_PLL2_N_MSB, + HMC7044_N2_MSB(n2[0])); + + /* Program the reference doubler */ + hmc7044_write(dev, HMC7044_REG_PLL2_FREQ_DOUBLER, + pll2_freq_doubler_en ? 0 : HMC7044_PLL2_FREQ_DOUBLER_DIS); + + /* Program PLL1 */ + + /* Set the lock detect timer threshold */ + hmc7044_write(dev, HMC7044_REG_PLL1_LOCK_DETECT, + HMC7044_LOCK_DETECT_TIMER(pll1_lock_detect)); + + /* Set the LCM */ + for (i = 0; i < ARRAY_SIZE(clkin_freq); i++) { + hmc7044_write(dev, HMC7044_REG_CLKIN_PRESCALER(i), + in_prescaler[i]); + } + hmc7044_write(dev, HMC7044_REG_OSCIN_PRESCALER, + in_prescaler[4]); + + /* Program the dividers */ + hmc7044_write(dev, HMC7044_REG_PLL1_R_LSB, + HMC7044_R2_LSB(r1)); + hmc7044_write(dev, HMC7044_REG_PLL1_R_MSB, + HMC7044_R2_MSB(r1)); + hmc7044_write(dev, HMC7044_REG_PLL1_N_LSB, + HMC7044_N2_LSB(n1)); + hmc7044_write(dev, HMC7044_REG_PLL1_N_MSB, + HMC7044_N2_MSB(n1)); + + hmc7044_write(dev, HMC7044_REG_PLL1_REF_PRIO_CTRL, + dev->pll1_ref_prio_ctrl); + + /* Program the SYSREF timer */ + + /* Set the divide ratio */ + hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_LSB, + HMC7044_SYSREF_TIMER_LSB(dev->sysref_timer_div)); + hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_MSB, + HMC7044_SYSREF_TIMER_MSB(dev->sysref_timer_div)); + + /* Set the pulse generator mode configuration */ + hmc7044_write(dev, HMC7044_REG_PULSE_GEN, + HMC7044_PULSE_GEN_MODE(dev->pulse_gen_mode)); + + /* Enable the input buffers */ + hmc7044_write(dev, HMC7044_REG_CLKIN0_BUF_CTRL, + dev->in_buf_mode[0]); + hmc7044_write(dev, HMC7044_REG_CLKIN1_BUF_CTRL, + dev->in_buf_mode[1]); + hmc7044_write(dev, HMC7044_REG_CLKIN2_BUF_CTRL, + dev->in_buf_mode[2]); + hmc7044_write(dev, HMC7044_REG_CLKIN3_BUF_CTRL, + dev->in_buf_mode[3]); + hmc7044_write(dev, HMC7044_REG_OSCIN_BUF_CTRL, + dev->in_buf_mode[4]); + + /* Set GPIOs */ + for (i = 0; i < ARRAY_SIZE(dev->gpi_ctrl); i++) { + hmc7044_write(dev, HMC7044_REG_GPI_CTRL(i), + dev->gpi_ctrl[i]); + } + + for (i = 0; i < ARRAY_SIZE(dev->gpo_ctrl); i++) { + hmc7044_write(dev, HMC7044_REG_GPO_CTRL(i), + dev->gpo_ctrl[i]); + } + + mdelay(10); + + /* Program the output channels */ + for (i = 0; i < dev->num_channels; i++) { + chan = &dev->channels[i]; + if (chan->num >= HMC7044_NUM_CHAN || chan->disable) + continue; + + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_1(chan->num), + HMC7044_DIV_LSB(chan->divider)); + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_2(chan->num), + HMC7044_DIV_MSB(chan->divider)); + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_8(chan->num), + HMC7044_DRIVER_MODE(chan->driver_mode) | + HMC7044_DRIVER_Z_MODE(chan->driver_impedance) | + (chan->dynamic_driver_enable ? + HMC7044_DYN_DRIVER_EN : 0) | + (chan->force_mute_enable ? + HMC7044_FORCE_MUTE_EN : 0)); + + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_3(chan->num), + chan->fine_delay & 0x1F); + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_4(chan->num), + chan->coarse_delay & 0x1F); + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_7(chan->num), + chan->out_mux_mode & 0x3); + + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(chan->num), + (chan->start_up_mode_dynamic_enable ? + HMC7044_START_UP_MODE_DYN_EN : 0) | + (chan->output_control0_rb4_enable ? BIT(4) : 0) | + (chan->high_performance_mode_dis ? + 0 : HMC7044_HI_PERF_MODE) | HMC7044_SYNC_EN | + HMC7044_CH_EN); + } + mdelay(10); + + /* Do a restart to reset the system and initiate calibration */ + hmc7044_write(dev, HMC7044_REG_REQ_MODE_0, + HMC7044_RESTART_DIV_FSM); + mdelay(1); + hmc7044_write(dev, HMC7044_REG_REQ_MODE_0, + (dev->high_performance_mode_clock_dist_en ? + HMC7044_HIGH_PERF_DISTRIB_PATH : 0)); + mdelay(1); + + return SUCCESS; +} + +/** + * Setup the device. + * @param dev - The device structure. + * @return SUCCESS in case of success, negative error code otherwise. + */ +static int32_t hmc7043_setup(struct hmc7044_dev *dev) +{ + struct hmc7044_chan_spec *chan; + uint32_t i; + + if (dev->clkin_freq_ccf[0]) + dev->pll2_freq = dev->clkin_freq_ccf[0]; + else + dev->pll2_freq = dev->clkin_freq[0]; + + if (!dev->pll2_freq) { + printf("%s: Failed to get valid parent rate\n", __func__); + return FAILURE; + } + + /* Resets all registers to default values */ + hmc7044_write(dev, HMC7044_REG_SOFT_RESET, HMC7044_SOFT_RESET); + mdelay(10); + hmc7044_write(dev, HMC7044_REG_SOFT_RESET, 0); + mdelay(10); + + /* Load the configuration updates (provided by Analog Devices) */ + hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_LOW_PW, 0x4d); + hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_HIGH_PW, 0xdf); + + /* Disable all channels */ + for (i = 0; i < HMC7044_NUM_CHAN; i++) + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(i), 0); + + if (dev->pll2_freq < 1000000000U) + hmc7044_write(dev, HMC7044_CLK_INPUT_CTRL, + HMC7044_LOW_FREQ_INPUT_MODE); + + hmc7044_write(dev, HMC7044_REG_EN_CTRL_0, + (dev->rf_reseeder_en ? HMC7044_RF_RESEEDER_EN : 0) | + HMC7044_SYSREF_TIMER_EN); + + /* Program the SYSREF timer */ + + /* Set the divide ratio */ + hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_LSB, + HMC7044_SYSREF_TIMER_LSB(dev->sysref_timer_div)); + hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_MSB, + HMC7044_SYSREF_TIMER_MSB(dev->sysref_timer_div)); + + /* Set the pulse generator mode configuration */ + hmc7044_write(dev, HMC7044_REG_PULSE_GEN, + HMC7044_PULSE_GEN_MODE(dev->pulse_gen_mode)); + + /* Enable the input buffers */ + hmc7044_write(dev, HMC7044_REG_CLKIN0_BUF_CTRL, + dev->in_buf_mode[0]); + hmc7044_write(dev, HMC7044_REG_CLKIN1_BUF_CTRL, + dev->in_buf_mode[1]); + + /* Set GPIOs */ + hmc7044_write(dev, HMC7044_REG_GPI_CTRL(0), + dev->gpi_ctrl[0]); + + hmc7044_write(dev, HMC7044_REG_GPO_CTRL(0), + dev->gpo_ctrl[0]); + + /* Program the output channels */ + for (i = 0; i < dev->num_channels; i++) { + chan = &dev->channels[i]; + + if (chan->num >= HMC7044_NUM_CHAN || chan->disable) + continue; + + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_1(chan->num), + HMC7044_DIV_LSB(chan->divider)); + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_2(chan->num), + HMC7044_DIV_MSB(chan->divider)); + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_8(chan->num), + HMC7044_DRIVER_MODE(chan->driver_mode) | + HMC7044_DRIVER_Z_MODE(chan->driver_impedance) | + (chan->dynamic_driver_enable ? + HMC7044_DYN_DRIVER_EN : 0) | + (chan->force_mute_enable ? + HMC7044_FORCE_MUTE_EN : 0)); + + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_3(chan->num), + chan->fine_delay & 0x1F); + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_4(chan->num), + chan->coarse_delay & 0x1F); + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_7(chan->num), + chan->out_mux_mode & 0x3); + + hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(chan->num), + (chan->start_up_mode_dynamic_enable ? + HMC7044_START_UP_MODE_DYN_EN : 0) | + (chan->output_control0_rb4_enable ? BIT(4) : 0) | + (chan->high_performance_mode_dis ? + 0 : HMC7044_HI_PERF_MODE) | HMC7044_SYNC_EN | + HMC7044_CH_EN); + } + mdelay(10); + + + /* Do a restart to reset the system and initiate calibration */ + hmc7044_write(dev, HMC7044_REG_REQ_MODE_0, + HMC7044_RESTART_DIV_FSM); + mdelay(1); + hmc7044_write(dev, HMC7044_REG_REQ_MODE_0, + (dev->high_performance_mode_clock_dist_en ? + HMC7044_HIGH_PERF_DISTRIB_PATH : 0)); + mdelay(1); + + return SUCCESS; +} + +/***************************************************************************//** + * @brief hmc7044_reg_init + *******************************************************************************/ +int32_t hmc7044_reg_init(struct hmc7044_dev **device, + const struct hmc7044_init_param *init_param) +{ + int ret = SUCCESS; + struct hmc7044_dev *dev; + + dev = (struct hmc7044_dev *)malloc(sizeof(*dev)); + if (!dev) + return FAILURE; + + /* SPI */ + ret = spi_init(&dev->spi_desc, init_param->spi_init); + + *device = dev; + + return ret; +} + +/** + * Initialize the device. + * @param device - The device structure. + * @param init_param - The structure that contains the device initial + * parameters. + * @return SUCCESS in case of success, negative error code otherwise. + */ +int32_t hmc7044_init(struct hmc7044_dev **device, + const struct hmc7044_init_param *init_param) +{ + struct hmc7044_dev *dev; + int32_t ret; + unsigned int i; + + dev = (struct hmc7044_dev *)malloc(sizeof(*dev)); + if (!dev) + return FAILURE; + + ret = spi_init(&dev->spi_desc, init_param->spi_init); + if (ret < 0) + return ret; + + dev->is_hmc7043 = init_param->is_hmc7043; + + dev->clkin_freq[0] = init_param->clkin_freq[0]; + dev->clkin_freq[1] = init_param->clkin_freq[1]; + dev->clkin_freq[2] = init_param->clkin_freq[2]; + dev->clkin_freq[3] = init_param->clkin_freq[3]; + + dev->clkin_freq_ccf[0] = init_param->clkin_freq_ccf[0]; + dev->clkin_freq_ccf[1] = init_param->clkin_freq_ccf[1]; + dev->clkin_freq_ccf[2] = init_param->clkin_freq_ccf[2]; + dev->clkin_freq_ccf[3] = init_param->clkin_freq_ccf[3]; + + dev->vcxo_freq = init_param->vcxo_freq; + dev->pll1_pfd = init_param->pll1_pfd; + dev->pll2_freq = init_param->pll2_freq; + dev->pll1_loop_bw = init_param->pll1_loop_bw; + + dev->sysref_timer_div = init_param->sysref_timer_div; + dev->pll1_ref_prio_ctrl = init_param->pll1_ref_prio_ctrl; + dev->clkin0_rfsync_en = init_param->clkin0_rfsync_en; + dev->clkin1_vcoin_en = init_param->clkin1_vcoin_en; + dev->high_performance_mode_clock_dist_en = + init_param->high_performance_mode_clock_dist_en; + dev->rf_reseeder_en = !init_param->rf_reseeder_disable; + dev->sync_pin_mode = init_param->sync_pin_mode; + dev->pulse_gen_mode = init_param->pulse_gen_mode; + + dev->in_buf_mode[0] = init_param->in_buf_mode[0]; + dev->in_buf_mode[1] = init_param->in_buf_mode[1]; + dev->in_buf_mode[2] = init_param->in_buf_mode[2]; + dev->in_buf_mode[3] = init_param->in_buf_mode[3]; + dev->in_buf_mode[4] = init_param->in_buf_mode[4]; + + dev->gpi_ctrl[0] = init_param->gpi_ctrl[0]; + dev->gpi_ctrl[1] = init_param->gpi_ctrl[1]; + dev->gpi_ctrl[2] = init_param->gpi_ctrl[2]; + dev->gpi_ctrl[3] = init_param->gpi_ctrl[3]; + + dev->gpo_ctrl[0] = init_param->gpo_ctrl[0]; + dev->gpo_ctrl[1] = init_param->gpo_ctrl[1]; + dev->gpo_ctrl[2] = init_param->gpo_ctrl[2]; + dev->gpo_ctrl[3] = init_param->gpo_ctrl[3]; + + dev->num_channels = init_param->num_channels; + dev->channels = (struct hmc7044_chan_spec *) + malloc(sizeof(*dev->channels) * dev->num_channels); + + for (i = 0; i < dev->num_channels; i++) { + dev->channels[i].num = init_param->channels[i].num; + dev->channels[i].disable = init_param->channels[i].disable; + dev->channels[i].divider = init_param->channels[i].divider; + dev->channels[i].driver_mode = + init_param->channels[i].driver_mode; + dev->channels[i].high_performance_mode_dis = + init_param->channels[i].high_performance_mode_dis; + dev->channels[i].start_up_mode_dynamic_enable = + init_param->channels[i].start_up_mode_dynamic_enable; + dev->channels[i].dynamic_driver_enable = + init_param->channels[i].dynamic_driver_enable; + dev->channels[i].output_control0_rb4_enable = + init_param->channels[i].output_control0_rb4_enable; + dev->channels[i].force_mute_enable = + init_param->channels[i].force_mute_enable; + dev->channels[i].driver_impedance = + init_param->channels[i].driver_impedance; + dev->channels[i].coarse_delay = + init_param->channels[i].coarse_delay; + dev->channels[i].fine_delay = + init_param->channels[i].fine_delay; + dev->channels[i].out_mux_mode = + init_param->channels[i].out_mux_mode; + } + + *device = dev; + + if (!dev->is_hmc7043) + return hmc7044_setup(dev); + else + return hmc7043_setup(dev); +} + +/** + * Remove the device - release resources. + * @param device - The device structure. + * @return SUCCESS in case of success, negative error code otherwise. + */ +int32_t hmc7044_remove(struct hmc7044_dev *device) +{ + int32_t ret; + + ret = spi_remove(device->spi_desc); + free(device->channels); + free(device); + + return ret; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/frequency/hmc7044/hmc7044.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/frequency/hmc7044/hmc7044.h new file mode 100644 index 00000000..47c233bb --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/frequency/hmc7044/hmc7044.h @@ -0,0 +1,276 @@ +/***************************************************************************//** + * @file hmc7044.h + * @brief Header file of HMC7044, HMC7043 Driver. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018-2020(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef HMC7044_H_ +#define HMC7044_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include "../../../include/delay.h" +#include "../../../include/spi.h" + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +// Enum to select SYNC pin configuration with respect to PLL2 (0x0005) +typedef enum +{ + SYNC_DISABLED = 0, + SYNC_MULTICHIP = 1, + SYNC_PULSE_GEN = 2, + SYNC_ALARM = 3 +} hmc7044SyncPinModeSelect_t; + +// Enum to select input buffer mode (0x000A, 0x000B, 0x000C, 0x000D, 0x000E) +typedef enum +{ + BUFFER_ENABLE = (1) << 0, + BUFFER_DISABLE = (0) << 0, + ENABLE_INTERNAL_TERM = (1) << 1, + ENABLE_AC_COUPLE = (1) << 2, + ENABLE_LVPECL = (1) << 3, + ENABLE_HIGH_Z = (1) << 4 +} hmc7044InputBufferMode_t; + +// Enum to select output driver mode (0x003A, 0x003B, 0x00D0, 0x00DA, 0x00E4, +// 0x00EE, 0x00F8, 0x0102, 0x010C, 0x0116, 0x0120, 0x012A, 0x0134, 0x013E, +// 0x0148, 0x0152) +typedef enum +{ + CML = 0, + LVPECL = 1, + LVDS = 2, + CMOS = 3 +} hmc7044DriverMode_t; + +// Enum to select the GPIx functionality. (0x0046, 0x0047, 0x0048, 0x0049) +typedef enum +{ + GPI_ENABLE = (1) << 0, + GPI_DISABLE = (0) << 0, + FORCE_PLL1_HOLDOVER = (0x01) << 1 | GPI_ENABLE, + SELECT_PLL1_REF_BIT1 = (0x02) << 1 | GPI_ENABLE, + SELECT_PLL1_REF_BIT2 = (0x03) << 1 | GPI_ENABLE, + CHIP_SLEEP_MODE = (0x04) << 1 | GPI_ENABLE, + MUTE_REQUSET = (0x05) << 1 | GPI_ENABLE, + SELECT_INTERNAL_VCO_TYPE = (0x06) << 1 | GPI_ENABLE, + SELECT_HI_PERF_MODE = (0x07) << 1 | GPI_ENABLE, + PULSE_GEN_REQUSET = (0x08) << 1 | GPI_ENABLE, + RESEED_REQUEST = (0x09) << 1 | GPI_ENABLE, + RESTART_REQUSET = (0x0A) << 1 | GPI_ENABLE, + FORCE_FANOUT_MODE = (0x0B) << 1 | GPI_ENABLE, + SLIP_REQUEST = (0x0D) << 1 | GPI_ENABLE, +} hmc7044GPIControl_t; + +// Enum to select the GPOx functionality. (0x0050, 0x0051, 0x0052, 0x0053) +typedef enum +{ + GPO_ENABLE = (1) << 0, + GPO_DISABLE = (0) << 0, + GPO_CMOS_MODE = (1) << 1, + GPO_OPEN_DRAIN_MODE = (0) << 1, + ALARM_SIGNAL = (0x00) << 3 | GPO_ENABLE, + SPI_SDATA = (0x01) << 3 | GPO_ENABLE, + CLKIN3_SIGNAL_LOSS = (0x02) << 3 | GPO_ENABLE, + CLKIN2_SIGNAL_LOSS = (0x03) << 3 | GPO_ENABLE, + CLKIN1_SIGNAL_LOSS = (0x04) << 3 | GPO_ENABLE, + CLKIN0_SIGNAL_LOSS = (0x05) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_ENABLE = (0x06) << 3 | GPO_ENABLE, + PLL1_LOCK_DETECT = (0x07) << 3 | GPO_ENABLE, + PLL1_ACQUIRING_LOCK = (0x08) << 3 | GPO_ENABLE, + PLL1_NEAR_CLOCK_ACQ_STAT = (0x09) << 3 | GPO_ENABLE, + PLL2_LOCK_DETECT = (0x0A) << 3 | GPO_ENABLE, + PLL2_SYSREF_SYNC = (0x0B) << 3 | GPO_ENABLE, + CLOCK_OUTPUT_PHASE_STAT = (0x0C) << 3 | GPO_ENABLE, + PLL1_PLL2_LOCKED = (0x0D) << 3 | GPO_ENABLE, + SYNC_REQUSRT_STAT = (0x0E) << 3 | GPO_ENABLE, + PLL1_ACTIVE_CLKIN0 = (0x0F) << 3 | GPO_ENABLE, + PLL1_ACTIVE_CLKIN1 = (0x10) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_IN_RANGE_STAT = (0x11) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_IN_STAT = (0x12) << 3 | GPO_ENABLE, + PLL1_VCXO_STAT = (0x13) << 3 | GPO_ENABLE, + PLL1_ACTIVE_CLKINx_STAT = (0x14) << 3 | GPO_ENABLE, + PLL1_FSM_BIT0 = (0x15) << 3 | GPO_ENABLE, + PLL1_FSM_BIT1 = (0x16) << 3 | GPO_ENABLE, + PLL1_FSM_BIT2 = (0x17) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_EXIT_PHASE_BIT0 = (0x18) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_EXIT_PHASE_BIT1 = (0x19) << 3 | GPO_ENABLE, + CHANNEL_OUTPUT_FSM_BUSY = (0x1A) << 3 | GPO_ENABLE, + SYSREF_FSM_STAT_BIT0 = (0x1B) << 3 | GPO_ENABLE, + SYSREF_FSM_STAT_BIT1 = (0x1C) << 3 | GPO_ENABLE, + SYSREF_FSM_STAT_BIT2 = (0x1D) << 3 | GPO_ENABLE, + SYSREF_FSM_STAT_BIT3 = (0x1E) << 3 | GPO_ENABLE, + FORCE_LOGIC_1 = (0x1F) << 3 | GPO_ENABLE, + FORCE_LOGIC_0 = (0x20) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_AVG_VALUE_BIT0 = (0x27) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_AVG_VALUE_BIT1 = (0x28) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_AVG_VALUE_BIT2 = (0x29) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_AVG_VALUE_BIT3 = (0x2A) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_CURR_VALUE_BIT0 = (0x2B) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_CURR_VALUE_BIT1 = (0x2C) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_CURR_VALUE_BIT2 = (0x2D) << 3 | GPO_ENABLE, + PLL1_HOLDOVER_CURR_VALUE_BIT3 = (0x2E) << 3 | GPO_ENABLE +} hmc7044GPOControl_t; + +// Enum to select output channel (0x00CF, 0x00D9, 0x00E3, 0x00ED, 0x00F7, +// 0x0101, 0x010B, 0x0115, 0x011F, 0x0129, 0x0133, 0x013D, 0x0147, 0x0151 +typedef enum +{ + CHANNEL_DIV = 0, + ANALOG_DELAY = 1, + OTHER_CHANNEL = 2, + VCO_CLOCK = 3 +} hmc7044OutputMuxSelect_t; + +// Enum to select output driver impedance selection for CML mode (0x00D0, +// 0x00DA, 0x00E4, 0x00EE, 0x00F8, 0x0102, 0x010C, 0x0116, 0x0120, 0x012A, +// 0x0134, 0x013E, 0x0148, 0x0152) +typedef enum +{ + INTERNAL_RES_DISABLE = 0, + INTERNAL_100OHM_PER_PIN = 1, +// INTERNAL_RES_RESERVED = 2, + INTERNAL_50OHM_PER_PIN = 3 +} hmc7044DriverImpedance_t; + +// Enum to select pulse generator mode (0x005A) +typedef enum +{ + PULSE_LEVEL_SENSITIVE = 0, + PULSE_ONE = 1, + PULSE_TWO = 2, + PULSE_FOUR = 3, + PULSE_EIGHT = 4, + PULSE_SIXTEEN = 5, +// PULSE_SIXTEEN = 6, + PULSE_CONTINOUS = 7 +} hmc7044SyncPulseGenControl_t; + +struct hmc7044_chan_spec { + unsigned int num; + bool disable; + bool high_performance_mode_dis; + bool start_up_mode_dynamic_enable; + bool dynamic_driver_enable; + bool output_control0_rb4_enable; + bool force_mute_enable; + unsigned int divider; + unsigned int coarse_delay; + unsigned int fine_delay; + hmc7044DriverMode_t driver_mode; + hmc7044DriverImpedance_t driver_impedance; + hmc7044OutputMuxSelect_t out_mux_mode; +}; + +struct hmc7044_config { + uint16_t addr; + uint8_t value; +}; + +struct hmc7044_dev { + spi_desc *spi_desc; + bool is_hmc7043; + uint32_t clkin_freq[4]; + uint32_t clkin_freq_ccf[4]; + uint32_t vcxo_freq; + uint32_t pll1_pfd; + uint32_t pll2_freq; + uint32_t pll1_loop_bw; + uint32_t sysref_timer_div; + unsigned int pll1_ref_prio_ctrl; + bool clkin0_rfsync_en; + bool clkin1_vcoin_en; + bool high_performance_mode_clock_dist_en; + bool rf_reseeder_en; + hmc7044SyncPinModeSelect_t sync_pin_mode; + hmc7044SyncPulseGenControl_t pulse_gen_mode; + uint32_t in_buf_mode[5]; + uint32_t gpi_ctrl[4]; + uint32_t gpo_ctrl[4]; + uint32_t num_channels; + struct hmc7044_chan_spec *channels; +}; + +struct hmc7044_init_param { + spi_init_param *spi_init; + bool is_hmc7043; + uint32_t clkin_freq[4]; + uint32_t clkin_freq_ccf[4]; + uint32_t vcxo_freq; + uint32_t pll1_pfd; + uint32_t pll2_freq; + uint32_t pll1_loop_bw; + uint32_t sysref_timer_div; + unsigned int pll1_ref_prio_ctrl; + bool clkin0_rfsync_en; + bool clkin1_vcoin_en; + bool high_performance_mode_clock_dist_en; + bool rf_reseeder_disable; + hmc7044SyncPinModeSelect_t sync_pin_mode; + hmc7044SyncPulseGenControl_t pulse_gen_mode; + uint32_t in_buf_mode[5]; + uint32_t gpi_ctrl[4]; + uint32_t gpo_ctrl[4]; + uint32_t num_channels; + struct hmc7044_chan_spec *channels; +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ +/* Initialize the device. */ +int32_t hmc7044_reg_init(struct hmc7044_dev **device, + const struct hmc7044_init_param *init_param); +int32_t hmc7044_init(struct hmc7044_dev **device, + const struct hmc7044_init_param *init_param); +/* Remove the device. */ +int32_t hmc7044_remove(struct hmc7044_dev *device); +int32_t hmc7044_write(struct hmc7044_dev *dev, + uint16_t reg, uint8_t val); +int32_t hmc7044_read(struct hmc7044_dev *dev, uint16_t reg, uint8_t *val); +int32_t hmc7044_clk_recalc_rate(struct hmc7044_dev *dev, uint32_t chan_num, + uint64_t *rate); +int32_t hmc7044_clk_round_rate(struct hmc7044_dev *dev, uint32_t rate, + uint64_t *rounded_rate); +int32_t hmc7044_clk_set_rate(struct hmc7044_dev *dev, uint32_t chan_num, + uint64_t rate); + +#endif // HMC7044_H_ diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/axi_io.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/axi_io.c new file mode 100644 index 00000000..d7b5a82f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/axi_io.c @@ -0,0 +1,79 @@ +/***************************************************************************//** + * @file xilinx/axi_io.c + * @brief Implementation of Xilinx AXI IO. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include "../../include/error.h" +#include "../../include/axi_io.h" + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief AXI IO Xilinx specific read function. + * @param base - Base address + * @param offset - Address offset + * @param data - variable where returned data is stored + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data) +{ + *data = Xil_In32(base + offset); + + return SUCCESS; +} + +/** + * @brief AXI IO Xilinx specific write function. + * @param base - Base address + * @param offset - Address offset + * @param data - data to be written. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data) +{ + Xil_Out32(base + offset, data); + + return SUCCESS; +} + diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/delay.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/delay.c new file mode 100644 index 00000000..ca06169b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/delay.c @@ -0,0 +1,77 @@ +/***************************************************************************//** + * @file xilinx/delay.c + * @brief Implementation of Xilinx Delay Functions. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include "../../include/delay.h" +#include + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Generate microseconds delay. + * @param usecs - Delay in microseconds. + * @return None. + */ +void udelay(uint32_t usecs) +{ +#ifdef _XPARAMETERS_PS_H_ + usleep(usecs); +#else + usleep(usecs / 20); // FIXME +#endif +} + +/** + * @brief Generate miliseconds delay. + * @param msecs - Delay in miliseconds. + * @return None. + */ +void mdelay(uint32_t msecs) +{ +#ifdef _XPARAMETERS_PS_H_ + usleep(msecs * 1000); +#else + usleep(msecs * 50); // FIXME +#endif +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/gpio_extra.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/gpio_extra.h new file mode 100644 index 00000000..dbc64b93 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/gpio_extra.h @@ -0,0 +1,95 @@ +/******************************************************************************* + * @file xilinx/gpio_extra.h + * @brief Header containing extra types used in the gpio driver + * @author scuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef GPIO_EXTRA_H_ +#define GPIO_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_gpio_type + * @brief Xilinx platform architecture sections + */ +typedef enum xil_gpio_type { + /** Programmable Logic */ + GPIO_PL, + /** Processing System */ + GPIO_PS +} xil_gpio_type; + +/** + * @struct xil_gpio_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific GPIO parameters. + */ +typedef struct xil_gpio_init_param { + /** Xilinx architecture */ + enum xil_gpio_type type; + /** Device ID */ + uint32_t device_id; +} xil_gpio_init_param; + +/** + * @struct xil_gpio_desc + * @brief Xilinx platform specific GPIO descriptor + */ +typedef struct xil_gpio_desc { + /** Xilinx architecture */ + enum xil_gpio_type type; + /** Xilinx GPIO configuration */ + void *config; + /** Xilinx GPIO Instance */ + void *instance; +} xil_gpio_desc; + +/** + * @brief Xilinx platform specific gpio platform ops structure + */ +extern const struct gpio_platform_ops xil_gpio_ops; + +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/irq_extra.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/irq_extra.h new file mode 100644 index 00000000..1c9b959f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/irq_extra.h @@ -0,0 +1,91 @@ +/******************************************************************************* + * @file irq_extra.h + * @brief Header containing types used in the irq driver. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef IRQ_EXTRA_H_ +#define IRQ_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include "../../include/irq.h" + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_irq_type + * @brief Xilinx platform architecture sections + */ +enum xil_irq_type { + /** Programmable Logic */ + IRQ_PL, + /** Processing System */ + IRQ_PS +}; + +/** + * @struct xil_irq_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific IRQ parameters. + */ +struct xil_irq_init_param { + /** Xilinx architecture */ + enum xil_irq_type type; +}; + +/** + * @struct xil_irq_desc + * @brief Xilinx platform specific IRQ descriptor + */ +struct xil_irq_desc { + /** Xilinx architecture */ + enum xil_irq_type type; + /** Xilinx IRQ Instance */ + void *instance; +}; + +/** + * @brief Xilinx specific IRQ platform ops structure + */ +extern const struct irq_platform_ops xil_irq_ops; + +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/spi_extra.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/spi_extra.h new file mode 100644 index 00000000..2edb42c1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/spi_extra.h @@ -0,0 +1,115 @@ +/******************************************************************************* + * @file xilinx/spi_extra.h + * @brief Header containing extra types used in the spi driver. + * @author scuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef SPI_EXTRA_H_ +#define SPI_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include "../../include/spi.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define SPI_CS_DECODE 0x01 +#define SPI_DEASSERT_CURRENT_SS 0x0F + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_spi_type + * @brief Xilinx platform architecture sections + */ +enum xil_spi_type { + /** Programmable Logic */ + SPI_PL, + /** Processing System */ + SPI_PS, + /** SPI Engine */ + SPI_ENGINE +}; + +/** + * @struct xil_spi_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific SPI parameters when using xil_spi_ops. + */ +typedef struct xil_spi_init_param { + /** Xilinx architecture */ + enum xil_spi_type type; + /** SPI flags */ + uint32_t flags; +} xil_spi_init_param; + +/** + * @struct xil_spi_desc + * @brief Xilinx platform specific SPI descriptor + */ +typedef struct xil_spi_desc { + /** Xilinx architecture */ + enum xil_spi_type type; + /** SPI flags */ + uint32_t flags; + /** SPI configuration */ + void *config; + /** SPI instance */ + void *instance; +} xil_spi_desc; + +/** + * @brief SPI engine platform ops structure + */ +extern const struct spi_platform_ops spi_eng_platform_ops; + +/** + * @brief Xilinx specific SPI platform ops structure + */ +extern const struct spi_platform_ops xil_spi_ops; + +/** + * @brief Xilinx SPI PS register functions. No extra param needed + */ +extern const struct spi_platform_ops xil_spi_reg_ops_pl; + +#endif // SPI_EXTRA_H_ diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/uart_extra.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/uart_extra.h new file mode 100644 index 00000000..c877ebf2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/uart_extra.h @@ -0,0 +1,107 @@ +/******************************************************************************* + * @file xilinx/uart_extra.h + * @brief Header containing types used in the uart driver. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef UART_EXTRA_H_ +#define UART_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define UART_BUFF_LENGTH 256 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_uart_type + * @brief Xilinx platform architecture sections + */ +enum xil_uart_type { + /** Programmable Logic */ + UART_PL, + /** Processing System */ + UART_PS +}; + +/** + * @struct xil_uart_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific UART parameters. + */ +struct xil_uart_init_param { + /** Xilinx architecture */ + enum xil_uart_type type; + /** Interrupt Request ID */ + uint32_t irq_id; + /** Interrupt Request Descriptor */ + struct irq_ctrl_desc *irq_desc; +}; + +/** + * @struct xil_uart_desc + * @brief Xilinx platform specific UART descriptor + */ +struct xil_uart_desc { + /** Xilinx architecture */ + enum xil_uart_type type; + /** Interrupt Request ID */ + uint32_t irq_id; + /** Interrupt Request Descriptor */ + struct irq_ctrl_desc *irq_desc; + /** FIFO */ + struct fifo_element *fifo; + /** FIFO read offset */ + uint32_t fifo_read_offset; + /** UART Buffer */ + char buff[UART_BUFF_LENGTH]; + /** Number of bytes received */ + uint32_t bytes_received; + /** Total number of errors */ + uint32_t total_error_count; + /** UART Instance */ + void *instance; +}; + +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_gpio.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_gpio.c new file mode 100644 index 00000000..08ed15f3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_gpio.c @@ -0,0 +1,464 @@ +/***************************************************************************//** + * @file xilinx/xilinx_gpio.c + * @brief Implementation of Xilinx GPIO Generic Driver. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +#include +#ifdef XPAR_XGPIO_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XGPIOPS_NUM_INSTANCES +#include +#endif + +#include "gpio_extra.h" +#include "../../include/error.h" +#include "../../include/gpio.h" + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Prepare the GPIO decriptor. + * @param desc - The GPIO descriptor. + * @param param - The structure that contains the GPIO parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t _gpio_init(struct gpio_desc *desc, + const struct gpio_init_param *param) +{ + int32_t ret; + struct xil_gpio_desc *xdesc; + struct xil_gpio_init_param *xinit; + + ret = FAILURE; + + xdesc = desc->extra; + xinit = param->extra; + + xdesc->type = xinit->type; + desc->number = param->number; + + switch (xinit->type) { + case GPIO_PL: +#ifdef XGPIO_H + xdesc->instance = (XGpio *)malloc(sizeof(XGpio)); + if(!xdesc->instance) + goto pl_error; + + xdesc->config = XGpio_LookupConfig(xinit->device_id); + if(xdesc->config == NULL) + goto pl_error; + + ret = XGpio_CfgInitialize(xdesc->instance, + xdesc->config, + ((XGpio_Config*)xdesc->config) + ->BaseAddress); + if(ret < 0) + goto pl_error; + + break; +pl_error: + free(xdesc->instance); +#endif + goto error; + case GPIO_PS: +#ifdef XGPIOPS_H + xdesc->instance = (XGpioPs *)malloc(sizeof(XGpioPs)); + if(!xdesc->instance) + goto ps_error; + + xdesc->config = XGpioPs_LookupConfig(xinit->device_id); + if(xdesc->config == NULL) + goto ps_error; + + ret = XGpioPs_CfgInitialize(xdesc->instance, + xdesc->config, + ((XGpioPs_Config*)xdesc->config)->BaseAddr); + if(ret < 0) + goto ps_error; + break; +ps_error: + free(xdesc->instance); +#endif + goto error; +error: + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Obtain the GPIO decriptor. + * @param desc - The GPIO descriptor. + * @param param - GPIO initialization parameters + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + struct gpio_desc *descriptor; + struct xil_gpio_desc *extra; + int32_t ret; + + descriptor = (struct gpio_desc *)malloc(sizeof(*descriptor)); + extra = (struct xil_gpio_desc*)malloc(sizeof(*extra)); + + if (!descriptor || !extra) + return FAILURE; + + descriptor->extra = extra; + ret = _gpio_init(descriptor, param); + + if(ret != SUCCESS) + goto error; + + *desc = descriptor; + + return SUCCESS; +error: + free(extra); + free(descriptor); + + return FAILURE; +} + +/** + * @brief Get the value of an optional GPIO. + * @param desc - The GPIO descriptor. + * @param param - GPIO Initialization parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get_optional(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + if(param == NULL) { + *desc = NULL; + return SUCCESS; + } + + return xil_gpio_get(desc, param); +} + +/** + * @brief Free the resources allocated by gpio_get(). + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_remove(struct gpio_desc *desc) +{ + if (desc != NULL) { + free(((xil_gpio_desc *)(desc->extra))->instance); + free(desc->extra); + free(desc); + } + + return SUCCESS; +} + +/** + * @brief Enable the input direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_direction_input(struct gpio_desc *desc) +{ + struct xil_gpio_desc *extra; +#ifdef XGPIO_H + uint8_t pin = desc->number; + uint32_t channel = 1; + uint32_t config = 0; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + /* We assume that pin 32 is the first pin from channel 2 */ + if (pin >= 32) { + channel = 2; + pin -= 32; + } + + config = XGpio_GetDataDirection((XGpio *)extra->instance, + channel); + config |= (1 << pin); + XGpio_SetDataDirection((XGpio *)extra->instance, + channel, + config); +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + XGpioPs_SetDirectionPin(extra->instance, + desc->number, + GPIO_IN); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Enable the output direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_direction_output(struct gpio_desc *desc, + uint8_t value) +{ + struct xil_gpio_desc *extra; +#ifdef XGPIO_H + uint8_t pin = desc->number; + uint8_t channel; + uint32_t reg_val; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + + reg_val = XGpio_GetDataDirection(extra->instance, + channel); + reg_val &= ~(1 << pin); + XGpio_SetDataDirection(extra->instance, + channel, + reg_val); + reg_val = XGpio_DiscreteRead(extra->instance, + channel); + if(value) + reg_val |= (1 << pin); + else + reg_val &= ~(1 << pin); + XGpio_DiscreteWrite(extra->instance, + channel, + reg_val); +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + XGpioPs_SetDirectionPin(extra->instance, + desc->number, + GPIO_OUT); + XGpioPs_SetOutputEnablePin(extra->instance, + desc->number, + GPIO_OUT); + XGpioPs_WritePin(extra->instance, + desc->number, + value); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Get the direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param direction - The direction. + * Example: GPIO_OUT + * GPIO_IN + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction) +{ + if (!desc) + return FAILURE; + + struct xil_gpio_desc *extra; + uint8_t pin = desc->number; + +#ifdef XGPIO_H + uint8_t channel; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + *direction = ((XGpio_GetDataDirection(extra->instance, + channel) >> pin) & 0x1) ^ 0x1; +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + *direction = XGpioPs_GetDirectionPin(extra->instance, pin); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Set the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_set_value(struct gpio_desc *desc, + uint8_t value) +{ + struct xil_gpio_desc *extra; +#ifdef XGPIO_H + uint8_t pin = desc->number; + uint8_t channel; + uint32_t reg_val; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + + reg_val = XGpio_DiscreteRead(extra->instance, channel); + if(value) + reg_val |= (1 << pin); + else + reg_val &= ~(1 << pin); + XGpio_DiscreteWrite(extra->instance, channel, reg_val); +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + XGpioPs_WritePin(extra->instance, desc->number, value); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Get the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get_value(struct gpio_desc *desc, + uint8_t *value) +{ + if (!desc) + return FAILURE; + + struct xil_gpio_desc *extra; + uint8_t pin = desc->number; + +#ifdef XGPIO_H + uint8_t channel; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + *value = (XGpio_DiscreteRead(extra->instance, channel) >> pin) & 0x01; +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + *value = XGpioPs_ReadPin(extra->instance, pin); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Xilinx platform specific GPIO platform ops structure + */ +const struct gpio_platform_ops xil_gpio_ops = { + .gpio_ops_get = &xil_gpio_get, + .gpio_ops_get_optional = &xil_gpio_get_optional, + .gpio_ops_remove = &xil_gpio_remove, + .gpio_ops_direction_input = &xil_gpio_direction_input, + .gpio_ops_direction_output = &xil_gpio_direction_output, + .gpio_ops_get_direction = &xil_gpio_get_direction, + .gpio_ops_set_value = &xil_gpio_set_value, + .gpio_ops_get_value = &xil_gpio_get_value, +}; diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_irq.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_irq.c new file mode 100644 index 00000000..e688a3ae --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_irq.c @@ -0,0 +1,384 @@ +/***************************************************************************//** + * @file xilinx/xilinx_irq.c + * @brief Implementation of Xilinx IRQ Generic Driver. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include +#include "irq_extra.h" +#include "../../include/irq.h" +#include "../../include/error.h" +#ifdef XPAR_XSCUGIC_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XINTC_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XTMRCTR_NUM_INSTANCES +#include +#endif + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Initialize the IRQ interrupts. + * @param desc - The IRQ controller descriptor. + * @param param - The structure that contains the IRQ parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_ctrl_init(struct irq_ctrl_desc **desc, + const struct irq_init_param *param) +{ + int32_t status; + struct irq_ctrl_desc *descriptor; + struct xil_irq_desc *xil_dev; +#ifdef XSCUGIC_H + void *config; +#endif + + descriptor = (struct irq_ctrl_desc *)calloc(1, sizeof *descriptor); + if(!descriptor) + return FAILURE; + xil_dev = (struct xil_irq_desc *)calloc(1, sizeof *xil_dev); + if(!xil_dev) { + free(descriptor); + return FAILURE; + } + + Xil_ExceptionInit(); + + descriptor->irq_ctrl_id = param->irq_ctrl_id; + descriptor->extra = xil_dev; + xil_dev->type = ((struct xil_irq_init_param *)param->extra)->type; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + xil_dev->instance = calloc(1, sizeof(XScuGic)); + if(!xil_dev->instance) + goto error; + + config = XScuGic_LookupConfig(descriptor->irq_ctrl_id); + if(!config) + goto ps_error; + + status = XScuGic_CfgInitialize(xil_dev->instance, config, + ((XScuGic_Config *)config)->CpuBaseAddress); + if (status != SUCCESS) + goto ps_error; + + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)XScuGic_InterruptHandler, + xil_dev->instance); + + break; +ps_error: + free(xil_dev->instance); +#endif + goto error; + case IRQ_PL: +#ifdef XINTC_H + xil_dev->instance = calloc(1, sizeof(XIntc)); + if(!xil_dev->instance) + goto error; + + status = XIntc_Initialize(xil_dev->instance, descriptor->irq_ctrl_id); + if(status != SUCCESS) + goto pl_error; + + status = XIntc_Start(xil_dev->instance, XIN_REAL_MODE); + if(status != SUCCESS) + goto pl_error; + + break; +pl_error: + free(xil_dev->instance); +#endif + goto error; + default: + goto error; + + break; + } + + *desc = descriptor; + + return SUCCESS; + +error: + free(xil_dev); + free(descriptor); + + return FAILURE; +} + +/** + * @brief Enable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_global_enable(struct irq_ctrl_desc *desc) +{ + /* Enable interrupts */ + Xil_ExceptionEnable(); + + return SUCCESS; +} + +/** + * @brief Disable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_global_disable(struct irq_ctrl_desc *desc) +{ + /* Disable interrupts */ + Xil_ExceptionDisable(); + + return SUCCESS; +} + +/** + * @brief Enable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + XScuGic_Enable(xil_dev->instance, irq_id); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + XIntc_Enable(xil_dev->instance, irq_id); +#endif + break; + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Disable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + XScuGic_Disable(xil_dev->instance, irq_id); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + XIntc_Disable(xil_dev->instance, irq_id); +#endif + break; + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Register a callback to handle the irq events. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param callback_desc - Callback descriptor + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + return XScuGic_Connect(xil_dev->instance, irq_id, + (Xil_InterruptHandler) callback_desc->callback, + callback_desc->ctx); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + if (irq_id == XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR) { + int32_t ret; + + ret = XIntc_Connect(xil_dev->instance, irq_id, + XTmrCtr_InterruptHandler, callback_desc->config); + if (IS_ERR_VALUE(ret)) + return FAILURE; + XTmrCtr_SetHandler(callback_desc->config, + (XTmrCtr_Handler)callback_desc->callback, + callback_desc->ctx); + + return SUCCESS; + } + return XIntc_Connect(xil_dev->instance, irq_id, + (XInterruptHandler) callback_desc->callback, + callback_desc->ctx); +#endif + break; + default: + break; + } + + return FAILURE; +} + +/** + * @brief Set interrupt trigger level. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param trig - New trigger level for the interrupt. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + if(trig == IRQ_EDGE_BOTH) + return -EINVAL; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + ; + uint8_t priority, trigger; + + XScuGic_GetPriorityTriggerType(xil_dev->instance, irq_id, &priority, + &trigger); + trigger = trig; + XScuGic_SetPriorityTriggerType(xil_dev->instance, irq_id, priority, + trigger); + + return SUCCESS; +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + /* Interrupt trigger determined in hardware. TODO: verify */ + return SUCCESS; +#endif + break; + default: + break; + } + + return FAILURE; +} + +/** + * @brief Unregisters a generic IRQ handling function. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + XScuGic_Disconnect(xil_dev->instance, irq_id); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + XIntc_Disconnect(xil_dev->instance, irq_id); +#endif + break; + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by irq_ctrl_init(). + * @param desc - The IRQ control descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_ctrl_remove(struct irq_ctrl_desc *desc) +{ + struct xil_irq_desc *xil_dev = desc->extra; + free(xil_dev->instance); + free(desc->extra); + free(desc); + + return SUCCESS; +} + +/** + * @brief Xilinx platform specific IRQ platform ops structure + */ +const struct irq_platform_ops xil_irq_ops = { + .init = &xil_irq_ctrl_init, + .register_callback = &xil_irq_register_callback, + .unregister = &xil_irq_unregister, + .global_enable = &xil_irq_global_enable, + .global_disable = &xil_irq_global_disable, + .trigger_level_set = &xil_irq_trigger_level_set, + .enable = &xil_irq_enable, + .disable = &xil_irq_disable, + .remove = &xil_irq_ctrl_remove +}; diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_spi.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_spi.c new file mode 100644 index 00000000..adc38325 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_spi.c @@ -0,0 +1,461 @@ +/***************************************************************************//** + * @file xilinx/xilinx_spi.c + * @brief Implementation of Xilinx SPI Generic Driver. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +#include +#ifdef XPAR_XSPI_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XSPIPS_NUM_INSTANCES +#include +#endif + +#include "../../include/error.h" +#include "../../include/spi.h" +#include "spi_extra.h" + +#if defined(PLATFORM_ZYNQ) +#define SPI_CLK_FREQ_HZ(dev) (XPAR_PS7_SPI_ ## dev ## _SPI_CLK_FREQ_HZ) +#define SPI_NUM_INSTANCES XPAR_XSPIPS_NUM_INSTANCES +#elif defined(PLATFORM_ZYNQMP) +#define SPI_CLK_FREQ_HZ(dev) (XPAR_PSU_SPI_ ## dev ## _SPI_CLK_FREQ_HZ) +#define SPI_NUM_INSTANCES XPAR_XSPIPS_NUM_INSTANCES +#else +#define SPI_NUM_INSTANCES 0 +#endif + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Initialize the hardware SPI peripherial + * + * @param xdesc Platform specific SPI descriptor + * @param xinit Platform specific SPI init param + * @return int32_t FAILURE if the device couldn't be found or configured + */ +static int32_t spi_init_pl(struct spi_desc *desc, + const struct spi_init_param *param) +{ +#ifdef XSPI_H + int32_t ret; + struct xil_spi_desc *xdesc; + struct xil_spi_init_param *xinit; + + xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc)); + if(!xdesc) { + free(xdesc); + return FAILURE; + } + + desc->extra = xdesc; + xinit = param->extra; + xdesc->type = xinit->type; + xdesc->flags = xinit->flags; + + xdesc->instance = (XSpi*)calloc(1, sizeof(XSpi)); + if(!xdesc->instance) + goto pl_error; + + xdesc->config = XSpi_LookupConfig(param->device_id); + if(xdesc->config == NULL) + goto pl_error; + + ret = XSpi_CfgInitialize(xdesc->instance, + xdesc->config, + ((XSpi_Config*)xdesc->config) + ->BaseAddress); + if(ret != SUCCESS) + goto pl_error; + + ret = XSpi_Initialize(xdesc->instance, param->device_id); + if (ret != SUCCESS) + goto pl_error; + + ret = XSpi_SetOptions(xdesc->instance, + XSP_MASTER_OPTION | + ((desc->mode & SPI_CPOL) ? + XSP_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSP_CLK_PHASE_1_OPTION : 0)); + if (ret != SUCCESS) + goto pl_error; + + ret = XSpi_Start(xdesc->instance); + if (ret != SUCCESS) + goto pl_error; + + XSpi_IntrGlobalDisable((XSpi *)(xdesc->instance)); + + return SUCCESS; + +pl_error: + free(xdesc->instance); + free(xdesc); +#endif + return FAILURE; +} + +/** + * @brief Initialize the hardware SPI peripherial + * + * @param xdesc Platform specific SPI descriptor + * @param xinit Platform specific SPI init param + * @return int32_t FAILURE if the device couldn't be found or configured + */ +static int32_t spi_init_ps(struct spi_desc *desc, + const struct spi_init_param *param) +{ +#ifdef XSPIPS_H + int32_t ret; + struct xil_spi_desc *xdesc; + struct xil_spi_init_param *xinit; + const uint32_t prescaler_default = XSPIPS_CLK_PRESCALE_64; + const uint32_t prescaler_min = XSPIPS_CLK_PRESCALE_4; + const uint32_t prescaler_max = XSPIPS_CLK_PRESCALE_256; + uint32_t prescaler = 0u; + uint32_t input_clock = 0u; + + xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc)); + if(!xdesc) { + free(xdesc); + return FAILURE; + } + + desc->extra = xdesc; + xinit = param->extra; + xdesc->type = xinit->type; + xdesc->flags = xinit->flags; + + xdesc->instance = (XSpiPs*)malloc(sizeof(XSpiPs)); + if(!xdesc->instance) + goto ps_error; + + xdesc->config = XSpiPs_LookupConfig(param->device_id); + if(xdesc->config == NULL) + goto ps_error; + + ret = XSpiPs_CfgInitialize(xdesc->instance, + xdesc->config, + ((XSpiPs_Config*)xdesc->config) + ->BaseAddress); + if(ret != SUCCESS) + goto ps_error; + + switch (param->device_id) { +#if (SPI_NUM_INSTANCES >= 1) + case 0: + input_clock = SPI_CLK_FREQ_HZ(0); + break; +#endif +#if (SPI_NUM_INSTANCES >= 2) + case 1: + input_clock = SPI_CLK_FREQ_HZ(1); + break; +#endif + default: + goto ps_error; + }; + + if (desc->max_speed_hz != 0u) { + uint32_t div = input_clock / desc->max_speed_hz; + uint32_t rem = input_clock % desc->max_speed_hz; + uint32_t po2 = !(div & (div - 1)) && !rem; + + // find the power of two just higher than div and + // store the exponent in prescaler + while(div) { + prescaler += 1; + div >>= 1u; + } + + // this exponent - 1 is needed because of the way + // xilinx stores it into registers + if (prescaler) + prescaler -= 1; + + // this exponent - 1 is needed when initial div was + // precisely a power of two + if (prescaler && po2) + prescaler -= 1; + + if (prescaler < prescaler_min) + prescaler = prescaler_min; + + if (prescaler > prescaler_max) + prescaler = prescaler_max; + } else + prescaler = prescaler_default; + + ret = XSpiPs_SetClkPrescaler(xdesc->instance, prescaler); + + if(ret != SUCCESS) + goto ps_error; + + return SUCCESS; + +ps_error: + free(xdesc->instance); + free(xdesc); +#endif + return FAILURE; +} + +/** + * @brief Initialize the SPI communication peripheral. + * @param desc - The SPI descriptor. + * @param param - The structure that contains the SPI parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_spi_init(struct spi_desc **desc, + const struct spi_init_param *param) +{ + int32_t ret; + enum xil_spi_type *spi_type; + + if (!param) { + return FAILURE; + } + + *desc = malloc(sizeof(**desc)); + if(! *desc) { + free(*desc); + return FAILURE; + } + + spi_type = param->extra; + + if(!spi_type) + goto init_error; + + (*desc)->max_speed_hz = param->max_speed_hz; + (*desc)->mode = param->mode; + (*desc)->bit_order = param->bit_order; + (*desc)->chip_select = param->chip_select; + + switch (*spi_type) { + case SPI_PL: + ret = spi_init_pl(*desc, param); + break; + case SPI_PS: + ret = spi_init_ps(*desc, param); + break; + + default: + goto init_error; + break; + } + + if (ret != SUCCESS) { +init_error: + free(*desc); + + return FAILURE; + } + + return ret; +} + +/** + * @brief Free the resources allocated by spi_init(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_spi_remove(struct spi_desc *desc) +{ +#ifdef XSPI_H + int32_t ret; +#endif + struct xil_spi_desc *xdesc = NULL; + enum xil_spi_type *spi_type; + + spi_type = desc->extra; + + if(!spi_type) + return FAILURE; + + switch (*spi_type ) { + case SPI_PL: +#ifdef XSPI_H + xdesc = desc->extra; + + if(!xdesc) + return FAILURE; + + ret = XSpi_Stop((XSpi *)(xdesc->instance)); + if(ret != SUCCESS) + goto error; +#endif + break; + case SPI_PS: +#ifdef XSPIPS_H + xdesc = desc->extra; + + if(!xdesc) + return FAILURE; +#endif + break; + + /* Intended fallthrough */ +#ifdef XSPI_H +error: +#endif + default: + return FAILURE; + } + + if(xdesc) + free(xdesc->instance); + free(desc->extra); + free(desc); + + return SUCCESS; +} + +/** + * @brief Write and read data to/from SPI. + * @param desc - The SPI descriptor. + * @param data - The buffer with the transmitted/received data. + * @param bytes_number - Number of bytes to write/read. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number) +{ + int32_t ret; +#ifdef XSPI_H + uint32_t ctrl_reg; +#endif + struct xil_spi_desc *xdesc; + enum xil_spi_type *spi_type; + + ret = FAILURE; + + spi_type = desc->extra; + + if(!spi_type) + return FAILURE; + + xdesc = desc->extra; + + switch (*spi_type) { + case SPI_PL: +#ifdef XSPI_H + ret = XSpi_SetOptions(xdesc->instance, + XSP_MASTER_OPTION | + ((desc->mode & SPI_CPOL) ? + XSP_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSP_CLK_PHASE_1_OPTION : 0)); + if (ret != SUCCESS) + goto error; + + ctrl_reg = XSpi_GetControlReg(((XSpi*)xdesc->instance)); + if (desc->bit_order == SPI_BIT_ORDER_LSB_FIRST) + ctrl_reg |= XSP_CR_LSB_MSB_FIRST_MASK; + else + ctrl_reg &= ~ XSP_CR_LSB_MSB_FIRST_MASK; + XSpi_SetControlReg(((XSpi*)xdesc->instance), ctrl_reg); + + ret = XSpi_SetSlaveSelect(xdesc->instance, + 0x01 << desc->chip_select); + if (ret != SUCCESS) + goto error; + + ret = XSpi_Transfer(xdesc->instance, + data, + data, + bytes_number); + if (ret != SUCCESS) + goto error; +#endif + break; + case SPI_PS: +#ifdef XSPIPS_H + ret = XSpiPs_SetOptions(xdesc->instance, + XSPIPS_MASTER_OPTION | + ((xdesc->flags & SPI_CS_DECODE) ? + XSPIPS_DECODE_SSELECT_OPTION : 0) | + XSPIPS_FORCE_SSELECT_OPTION | + ((desc->mode & SPI_CPOL) ? + XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSPIPS_CLK_PHASE_1_OPTION : 0)); + if (ret != SUCCESS) + goto error; + + ret = XSpiPs_SetSlaveSelect(xdesc->instance, + desc->chip_select); + if (ret != SUCCESS) + goto error; + ret = XSpiPs_PolledTransfer(xdesc->instance, + data, + data, + bytes_number); + if (ret != SUCCESS) + goto error; + ret = XSpiPs_SetSlaveSelect(xdesc->instance, SPI_DEASSERT_CURRENT_SS); + if (ret != SUCCESS) + goto error; +#endif + break; +error: + default: + return FAILURE; + } + + return ret; +} + +/** + * @brief Xilinx platform specific SPI platform ops structure + */ +const struct spi_platform_ops xil_spi_ops = { + .init = &xil_spi_init, + .write_and_read = &xil_spi_write_and_read, + .write_and_read_3wire = NULL, // Not support. + .remove = &xil_spi_remove +}; diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_spi_pl.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_spi_pl.c new file mode 100644 index 00000000..ed74cc84 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/platform/xilinx_spi_pl.c @@ -0,0 +1,531 @@ +/******************************************************************************* + * @file xilinx/xilinx_spi_pl.c + * @brief Driver for spi pl device using registers + * @author Mihail Chindris (mihail.chindris@analog.com) +******************************************************************************** + * Copyright 2021(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include + +#ifdef XPAR_XSPI_NUM_INSTANCES + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include +#include +#include "spi.h" +#include "error.h" +#include "delay.h" +#include "util.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define XPS_TYPE_WRITE 0x1 +#define XPS_TYPE_READ 0x2 +#define XSP_DEFAULT_SR_VALUE 0x25 +#define XSP_DUMMY_DATA 0xFF + +/* + * Used to store current spi device configuration in order to not update it for + * each spi transaction if not needed. + */ +static struct spi_desc g_spi_desc[XPAR_XSPI_NUM_INSTANCES]; + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/* Xilinx PL spi specific data */ +struct xspi_desc { + uint32_t base_addr; + uint32_t disable_slaves_mask; + uint32_t fifo_depth; + uint8_t cs_asserted; +}; + +/* Structure used to iterate over SPI messages */ +struct msg_iter { + struct spi_msg *msgs; + uint32_t len; + uint32_t i; + uint32_t buff_i; + uint8_t is_wr; +}; + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/* Read device register */ +static inline uint32_t _read(struct xspi_desc *xdesc, uint32_t reg) +{ + return Xil_In32(xdesc->base_addr + reg); +} + +/* Write device register */ +static inline void _write(struct xspi_desc *xdesc, uint32_t reg, uint32_t val) +{ + Xil_Out32(xdesc->base_addr + reg, val); +} + +/* Update device register. Only bits set to 1 in mask will be modified */ +static inline void _wr_mask(struct xspi_desc *xdesc, uint32_t reg, + uint32_t val, uint32_t mask) +{ + uint32_t tmp; + + tmp = _read(xdesc, reg); + tmp &= ~mask; + tmp |= val & mask; + _write(xdesc, reg, tmp); +} + +/* Update spi device configuration if needed */ +static void _update_mode(struct spi_desc *desc) +{ + uint32_t val; + uint32_t mask; + + if (desc->mode == g_spi_desc[desc->device_id].mode && + desc->bit_order == g_spi_desc[desc->device_id].bit_order) + return ; + + /* Update mode */ + val = desc->mode | SPI_CPOL ? XSP_CR_CLK_POLARITY_MASK : 0; + val |= desc->mode | SPI_CPHA ? XSP_CR_CLK_PHASE_MASK : 0; + mask = XSP_CR_CLK_POLARITY_MASK | XSP_CR_CLK_PHASE_MASK; + + val |= desc->bit_order == SPI_BIT_ORDER_LSB_FIRST ? + XSP_CR_LSB_MSB_FIRST_MASK : 0; + mask |= XSP_CR_LSB_MSB_FIRST_MASK; + + _wr_mask(desc->extra, XSP_CR_OFFSET, val, mask); + g_spi_desc[desc->device_id] = *desc; +} + +/* Configure SPI PL device */ +static int32_t _xil_spi_init_dev(struct xspi_desc *xdesc) +{ + uint32_t val; + + /* Software reset */ + _write(xdesc, XSP_SRR_OFFSET, XSP_SRR_RESET_MASK); + mdelay(1); + + /* Check if success reset */ + val = _read(xdesc, XSP_SR_OFFSET); + if (val != XSP_DEFAULT_SR_VALUE) + return -ENODEV; + + /* Disable interrupts. Drivers only works with pooled mode */ + _write(xdesc, XSP_IIER_OFFSET, 0); + + /* Deasert chip selects */ + _write(xdesc, XSP_SSR_OFFSET, 0xFFFFFFFF); + + /* Get fifo depth */ + while (!(_read(xdesc, XSP_SR_OFFSET) & XSP_SR_TX_FULL_MASK)) + _write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA); + xdesc->fifo_depth = _read(xdesc, XSP_TFO_OFFSET) + 1; + + /* Configure spi device */ + val = XSP_CR_ENABLE_MASK | + XSP_CR_MANUAL_SS_MASK | + XSP_CR_TXFIFO_RESET_MASK | + XSP_CR_RXFIFO_RESET_MASK | + XSP_CR_MASTER_MODE_MASK | + XSP_CR_TRANS_INHIBIT_MASK; + + _write(xdesc, XSP_CR_OFFSET, val); + + return SUCCESS; +} + +/* Initialize spi_desc structure and device */ +static int32_t xil_spi_init_pl(struct spi_desc **desc, + const struct spi_init_param *param) +{ + struct spi_desc *ldesc; + struct xspi_desc *xdesc; + int32_t err; + XSpi_Config *cfg; + + if (!desc || !param || param->device_id >= XPAR_XSPI_NUM_INSTANCES) + return -EINVAL; + + cfg = XSpi_LookupConfig(param->device_id); + if (!cfg) + return -EINVAL; + + if (param->chip_select > cfg->NumSlaveBits) + return -EINVAL; + + ldesc = (struct spi_desc *)calloc(1, sizeof(*ldesc)); + if (!ldesc) + return -ENOMEM; + + xdesc = (struct xspi_desc *)calloc(1, sizeof(*xdesc)); + if (!xdesc) { + err = -ENOMEM; + goto error; + } + + ldesc->bit_order = param->bit_order; + ldesc->chip_select = param->chip_select; + ldesc->mode = param->mode; + xdesc->base_addr = cfg->BaseAddress; + xdesc->disable_slaves_mask = (1 << cfg->NumSlaveBits) - 1; + xdesc->cs_asserted = 0; + + err = _xil_spi_init_dev(xdesc); + if (IS_ERR_VALUE(err)) + goto error; + + ldesc->extra = xdesc; + *desc = ldesc; + + return SUCCESS; + +error: + free(xdesc); + free(ldesc); + + return err; +} + +/* Remove allocated resources */ +static int32_t xil_spi_remove_pl(struct spi_desc *desc) +{ + if (!desc) + return -EINVAL; + + free(desc->extra); + free(desc); + + return SUCCESS; +} + +/* + * Fill fifo until fifo is full or no more data available. + * Return the number of written bytes. + */ +static uint32_t _wr_fifo(struct xspi_desc *xdesc, uint8_t *data, + uint32_t len) +{ + uint32_t i; + uint32_t to_write; + uint32_t tx_available; + + tx_available = xdesc->fifo_depth - _read(xdesc, XSP_TFO_OFFSET); + to_write = min(tx_available, len); + for (i = 0; i < to_write; ++i) + if (data) + _write(xdesc, XSP_DTR_OFFSET, data[i]); + else + _write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA); + + return to_write; +} + +/* + * Read fifo until fifo is empty or no more buffer available to read into + * Returns the number of read bytes + */ +static uint32_t _rd_fifo(struct xspi_desc *xdesc, uint8_t *data, + uint32_t len) +{ + uint32_t rx_available; + uint32_t to_read; + uint32_t tmp; + uint32_t i; + + tmp = _read(xdesc, XSP_SR_OFFSET); + if (tmp & XSP_SR_RX_EMPTY_MASK) + return 0; + + rx_available = _read(xdesc, XSP_RFO_OFFSET) + 1; + to_read = min(rx_available, len); + for (i = 0; i < to_read; ++i) { + tmp = _read(xdesc, XSP_DRR_OFFSET); + if (data) + data[i] = tmp; + } + + return to_read; +} + +/* If start is 0 stop transfer, else start it. + * CS will be asserted if needed. If different CS othere than the one needed + * is asserted. Deassert it and assert correct one */ +static void _xil_spi_start_transfer(struct spi_desc *desc, uint8_t start) +{ + struct xspi_desc *xdesc; + + xdesc = desc->extra; + if (start) { + if (xdesc->cs_asserted) { + if (desc->chip_select == + g_spi_desc[desc->device_id].chip_select) + return ; + else + /* Stop transfer to start again with new CS */ + _xil_spi_start_transfer(desc, 0); + } + _write(xdesc, XSP_SSR_OFFSET, ~(1 << desc->chip_select)); + _wr_mask(xdesc, XSP_CR_OFFSET, 0, XSP_CR_TRANS_INHIBIT_MASK); + } else { + _wr_mask(xdesc, XSP_CR_OFFSET, XSP_CR_TRANS_INHIBIT_MASK, + XSP_CR_TRANS_INHIBIT_MASK); + _write(xdesc, XSP_SSR_OFFSET, xdesc->disable_slaves_mask); + } + xdesc->cs_asserted = start; +} + + +/* SPI polled transfer */ +static int32_t xil_spi_write_and_read_pl(struct spi_desc *desc, uint8_t *data, + uint16_t bytes_number) +{ + struct xspi_desc *xdesc; + uint32_t rx; + uint32_t tx; + + if (!desc || !desc->extra) + return -EINVAL; + + xdesc = desc->extra; + _update_mode(desc); + + _xil_spi_start_transfer(desc, 1); + rx = 0; + tx = 0; + while (rx < bytes_number) { + if (tx < bytes_number) + tx += _wr_fifo(xdesc, data + tx, bytes_number - tx); + rx += _rd_fifo(xdesc, data + rx, bytes_number - rx); + } + _xil_spi_start_transfer(desc, 0); + + return SUCCESS; +} + +/* Get type of message. It can be READ, WRITE or both */ +static uint32_t _get_msg_type(struct spi_msg *msg) +{ + uint32_t type; + + type = 0; + if (msg->tx_buff) + type |= XPS_TYPE_WRITE; + if (msg->rx_buff) + type |= XPS_TYPE_READ; + + return type; +} + +/* Get information based on current iterator position */ +static void _get_data(struct msg_iter *it, uint8_t **buff, uint32_t *len, + uint32_t *type) +{ + struct spi_msg *msg; + + if (it->i == it->len) { + *len = 0; + return ; + } + + msg = it->msgs + it->i; + if (it->is_wr) + *buff = msg->tx_buff; + else + *buff = msg->rx_buff; + + if (*buff) + *buff += it->buff_i; + + *len = msg->bytes_number - it->buff_i; + if (type) + *type = _get_msg_type(msg); +} + +/* + * Increment iterator position with desired length. + * If the new position has a different message type, new_type will be set to 1 + * If a CS change is needed, cs_change is set + */ +static void _increment_iter(struct msg_iter *it, uint32_t len, + uint8_t *cs_change, uint8_t *new_type) +{ + struct spi_msg *msg; + uint32_t type; + uint32_t extra_len; + + if (!len) + return ; + + *cs_change = 0; + *new_type = 0; + msg = it->msgs + it->i; + if (it->buff_i + len > msg->bytes_number) + extra_len = it->buff_i + len - msg->bytes_number; + else + extra_len = 0; + len -= extra_len; + it->buff_i += len; + if (it->buff_i == msg->bytes_number) { + type = _get_msg_type(msg); + ++it->i; + it->buff_i = 0; + if (cs_change && msg->cs_change) + *cs_change = 1; + if (new_type) + if (it->i == it->len || + type != _get_msg_type(it->msgs + it->i)) + *new_type = 1; + } + if (extra_len) + _increment_iter(it, extra_len, cs_change, new_type); +} + +/* + * SPI polling transfer of multiple messages. + */ +static int32_t xil_spi_transfer_pl(struct spi_desc *desc, struct spi_msg *msgs, + uint32_t len) + +{ + struct xspi_desc *xdesc; + uint8_t cs_change; + uint8_t new_type; + struct msg_iter rx = {.msgs = msgs, .len = len, .is_wr = 0}; + struct msg_iter tx = {.msgs = msgs, .len = len, .is_wr = 1}; + uint8_t *buff; + uint32_t bytes; + uint32_t type; + /* Bytes to increment rx when only a write transaction is executed */ + uint32_t to_inc_rx; + /* Difference between rx and tx iterators in bytes */ + uint32_t tx_advance; + /* Save bytes sent during a write loop */ + uint32_t tx_sent; + /* Used to loop if need to empty the RX FIFO */ + uint32_t loop; + + if (!desc || !desc->extra) + return -EINVAL; + + xdesc = desc->extra; + _update_mode(desc); + + tx_advance = 0; + to_inc_rx = 0; + buff = NULL; + type = 0; + do { + _xil_spi_start_transfer(desc, 1); + + tx_sent = 0; + /* Writing loop */ + do { + _get_data(&tx, &buff, &bytes, &type); + if (type & XPS_TYPE_READ) + /* + * Do not write more bytes than fifo_depth if + * they haven't been read. + */ + bytes = min(bytes, + xdesc->fifo_depth - tx_advance); + bytes = _wr_fifo(xdesc, buff, bytes); + tx_sent += bytes; + _increment_iter(&tx, bytes, &cs_change, &new_type); + tx_advance += bytes; + } while (!cs_change && !new_type && bytes); + + if (type & XPS_TYPE_READ) { + loop = 1; + /* + * Loop only when no more data to write otherwise read + * only available data. + */ + while (loop) { + if (!new_type) + loop = 0; + _get_data(&rx, &buff, &bytes, NULL); + bytes = _rd_fifo(xdesc, buff, bytes); + _increment_iter(&rx, bytes, &cs_change, &new_type); + tx_advance -= bytes; + if (loop && new_type) + break; + } + } else { + /* Clean RX FIFO if it was only a WRITE message */ + to_inc_rx += tx_sent; + if (new_type) { + /* Wait for TX to be sent */ + while (!(_read(xdesc, XSP_SR_OFFSET) & + XSP_SR_TX_EMPTY_MASK)) + ; + /* Reset fifo. Only write was performed */ + _wr_mask(xdesc, XSP_CR_OFFSET, + XSP_CR_RXFIFO_RESET_MASK, + XSP_CR_RXFIFO_RESET_MASK); + + _increment_iter(&rx, to_inc_rx, NULL, NULL); + tx_advance -= to_inc_rx; + to_inc_rx = 0; + } + } + + if ((cs_change && rx.i != len) || (!cs_change && rx.i == len)) + _xil_spi_start_transfer(desc, 0); + } while (rx.i < len); + + return SUCCESS; +} + +const struct spi_platform_ops xil_spi_reg_ops_pl = { + .init = xil_spi_init_pl, + .remove = xil_spi_remove_pl, + .write_and_read = xil_spi_write_and_read_pl, + .write_and_read_3wire = NULL, // Not support. + .transfer = xil_spi_transfer_pl +}; + +#endif // XPAR_XSPI_NUM_INSTANCES diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361.c new file mode 100644 index 00000000..78f90851 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361.c @@ -0,0 +1,7475 @@ +/***************************************************************************//** + * @file ad9361.c + * @brief Implementation of AD9361 Driver. +******************************************************************************** + * Copyright 2014-2015(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include "ad9361.h" +#include "ad9361_util.h" +#include "../../../include/spi.h" +#include "../../../include/gpio.h" +#include "../../../include/delay.h" +#include "../../../include/util.h" +#include "../../../../app_config.h" + +#define diff_abs(x, y) ((x) > (y) ? (x - y) : (y - x)) + +#define NO_GAIN_TABLE ((uint32_t)-1) + +/* Used for static code size optimization: please see app_config.h */ +const bool has_split_gt = HAVE_SPLIT_GAIN_TABLE; +const bool have_tdd_tables = HAVE_TDD_SYNTH_TABLE; + +#define SYNTH_LUT_SIZE 53 + +static const struct SynthLUT SynthLUT_FDD[LUT_FTDD_ENT][SYNTH_LUT_SIZE] = { + { + {12605, 13, 1, 4, 2, 15, 12, 7, 14, 6, 14, 5, 15}, /* 40 MHz */ + {12245, 13, 1, 4, 2, 15, 12, 7, 14, 6, 14, 5, 15}, + {11906, 13, 1, 4, 2, 15, 12, 7, 15, 6, 14, 5, 15}, + {11588, 13, 1, 4, 2, 15, 12, 8, 15, 6, 14, 5, 15}, + {11288, 13, 1, 4, 2, 15, 12, 8, 15, 6, 14, 5, 15}, + {11007, 13, 1, 4, 2, 15, 12, 9, 15, 6, 14, 5, 15}, + {10742, 13, 1, 4, 2, 15, 12, 9, 15, 6, 14, 5, 15}, + {10492, 13, 1, 6, 2, 15, 12, 10, 15, 6, 14, 5, 15}, + {10258, 13, 1, 6, 2, 15, 12, 10, 15, 6, 14, 5, 15}, + {10036, 13, 1, 6, 2, 15, 12, 11, 15, 6, 14, 5, 15}, + {9827, 13, 1, 6, 2, 14, 12, 11, 15, 6, 14, 5, 15}, + {9631, 13, 1, 6, 2, 13, 12, 12, 15, 6, 14, 5, 15}, + {9445, 13, 1, 6, 2, 12, 12, 12, 15, 6, 14, 5, 15}, + {9269, 13, 1, 6, 2, 12, 12, 13, 15, 6, 14, 5, 15}, + {9103, 13, 1, 6, 2, 12, 12, 13, 15, 6, 14, 5, 15}, + {8946, 13, 1, 6, 2, 12, 12, 14, 15, 6, 14, 5, 15}, + {8797, 12, 1, 7, 2, 12, 12, 13, 15, 6, 14, 5, 15}, + {8655, 12, 1, 7, 2, 12, 12, 14, 15, 6, 14, 5, 15}, + {8520, 12, 1, 7, 2, 12, 12, 14, 15, 6, 14, 5, 15}, + {8392, 12, 1, 7, 2, 12, 12, 15, 15, 6, 14, 5, 15}, + {8269, 12, 1, 7, 2, 12, 12, 15, 15, 6, 14, 5, 15}, + {8153, 12, 1, 7, 2, 12, 12, 16, 15, 6, 14, 5, 15}, + {8041, 12, 1, 7, 2, 13, 12, 16, 15, 6, 14, 5, 15}, + {7934, 11, 1, 7, 2, 12, 12, 16, 15, 6, 14, 5, 15}, + {7831, 11, 1, 7, 2, 12, 12, 16, 15, 6, 14, 5, 15}, + {7733, 10, 1, 7, 3, 13, 12, 16, 15, 6, 14, 5, 15}, + {7638, 10, 1, 7, 2, 12, 12, 16, 15, 6, 14, 5, 15}, + {7547, 10, 1, 7, 2, 12, 12, 17, 15, 6, 14, 5, 15}, + {7459, 10, 1, 7, 2, 12, 12, 17, 15, 6, 14, 5, 15}, + {7374, 10, 2, 7, 3, 14, 13, 14, 15, 6, 14, 5, 15}, + {7291, 10, 2, 7, 3, 14, 13, 14, 15, 6, 14, 5, 15}, + {7212, 10, 2, 7, 3, 14, 13, 14, 15, 6, 14, 5, 15}, + {7135, 10, 2, 7, 3, 14, 13, 15, 15, 7, 14, 5, 15}, + {7061, 10, 2, 7, 3, 14, 13, 15, 15, 6, 14, 5, 15}, + {6988, 10, 1, 7, 3, 12, 14, 20, 15, 6, 14, 5, 15}, + {6918, 9, 2, 7, 3, 14, 13, 15, 15, 6, 14, 5, 15}, + {6850, 9, 2, 7, 3, 14, 13, 15, 15, 6, 14, 5, 15}, + {6784, 9, 2, 7, 2, 13, 13, 15, 15, 6, 14, 5, 15}, + {6720, 9, 2, 7, 2, 13, 13, 16, 15, 6, 14, 5, 15}, + {6658, 8, 2, 7, 3, 14, 13, 15, 15, 6, 14, 5, 15}, + {6597, 8, 2, 7, 2, 13, 13, 15, 15, 6, 14, 5, 15}, + {6539, 8, 2, 7, 2, 13, 13, 15, 15, 6, 14, 5, 15}, + {6482, 8, 2, 7, 2, 13, 13, 16, 15, 6, 14, 5, 15}, + {6427, 7, 2, 7, 3, 14, 13, 15, 15, 6, 14, 5, 15}, + {6373, 7, 2, 7, 3, 15, 13, 15, 15, 6, 14, 5, 15}, + {6321, 7, 2, 7, 3, 15, 13, 15, 15, 6, 14, 5, 15}, + {6270, 7, 2, 7, 3, 15, 13, 16, 15, 6, 14, 5, 15}, + {6222, 7, 2, 7, 3, 15, 13, 16, 15, 6, 14, 5, 15}, + {6174, 6, 2, 7, 3, 15, 13, 15, 15, 6, 14, 5, 15}, + {6128, 6, 2, 7, 3, 15, 13, 15, 15, 6, 14, 5, 15}, + {6083, 6, 2, 7, 3, 15, 13, 16, 15, 6, 14, 5, 15}, + {6040, 6, 2, 7, 3, 15, 13, 16, 15, 6, 14, 5, 15}, + {5997, 6, 2, 7, 3, 15, 13, 16, 15, 6, 14, 5, 15}, + }, { + {12605, 13, 1, 4, 2, 15, 12, 13, 15, 12, 12, 5, 14}, /* 60 MHz */ + {12245, 13, 1, 4, 2, 15, 12, 13, 15, 12, 12, 5, 14}, + {11906, 13, 1, 4, 2, 15, 12, 13, 15, 13, 12, 5, 13}, + {11588, 13, 1, 4, 2, 15, 12, 14, 15, 13, 12, 5, 13}, + {11288, 13, 1, 5, 2, 15, 12, 15, 15, 13, 12, 5, 13}, + {11007, 13, 1, 5, 2, 15, 12, 16, 15, 13, 12, 5, 13}, + {10742, 13, 1, 5, 2, 15, 12, 16, 15, 12, 12, 5, 14}, + {10492, 13, 1, 6, 2, 15, 12, 17, 15, 12, 12, 5, 14}, + {10258, 13, 1, 6, 2, 15, 12, 18, 15, 13, 12, 5, 13}, + {10036, 13, 1, 6, 2, 15, 12, 19, 15, 13, 12, 5, 13}, + {9827, 13, 1, 6, 2, 14, 12, 20, 15, 13, 12, 5, 13}, + {9631, 13, 1, 6, 2, 13, 12, 21, 15, 13, 12, 5, 13}, + {9445, 13, 1, 6, 2, 12, 12, 22, 15, 13, 12, 5, 13}, + {9269, 13, 1, 6, 2, 12, 12, 22, 15, 12, 12, 5, 14}, + {9103, 13, 1, 6, 2, 12, 12, 23, 15, 13, 12, 5, 13}, + {8946, 13, 1, 6, 2, 12, 12, 24, 15, 13, 12, 5, 13}, + {8797, 12, 1, 7, 2, 12, 12, 24, 15, 13, 12, 5, 13}, + {8655, 12, 1, 7, 2, 12, 12, 25, 15, 13, 12, 5, 13}, + {8520, 12, 1, 7, 2, 12, 12, 25, 15, 13, 12, 5, 13}, + {8392, 12, 1, 7, 2, 12, 12, 26, 15, 13, 12, 5, 13}, + {8269, 12, 1, 7, 2, 12, 12, 27, 15, 13, 12, 5, 13}, + {8153, 12, 1, 7, 2, 12, 12, 28, 15, 13, 12, 5, 13}, + {8041, 12, 1, 7, 2, 13, 12, 29, 15, 13, 12, 5, 13}, + {7934, 11, 1, 7, 2, 12, 12, 28, 15, 13, 12, 5, 13}, + {7831, 11, 1, 7, 2, 12, 12, 29, 15, 13, 12, 5, 13}, + {7733, 10, 1, 7, 3, 13, 12, 28, 15, 13, 12, 5, 13}, + {7638, 10, 1, 7, 2, 12, 12, 29, 15, 13, 12, 5, 13}, + {7547, 10, 1, 7, 2, 12, 12, 29, 15, 13, 12, 5, 13}, + {7459, 10, 1, 7, 2, 12, 12, 30, 15, 13, 12, 5, 13}, + {7374, 10, 2, 7, 3, 14, 13, 24, 15, 13, 12, 5, 13}, + {7291, 10, 2, 7, 3, 14, 13, 25, 15, 13, 12, 5, 13}, + {7212, 10, 2, 7, 3, 14, 13, 25, 15, 13, 12, 5, 13}, + {7135, 10, 2, 7, 3, 14, 13, 26, 15, 13, 12, 5, 13}, + {7061, 10, 2, 7, 3, 14, 13, 26, 15, 13, 12, 5, 13}, + {6988, 10, 1, 7, 3, 12, 14, 35, 15, 13, 12, 5, 13}, + {6918, 9, 1, 7, 3, 12, 14, 33, 15, 13, 12, 5, 13}, + {6850, 9, 1, 7, 3, 12, 14, 34, 15, 13, 12, 5, 13}, + {6784, 9, 1, 7, 2, 11, 14, 35, 15, 13, 12, 5, 13}, + {6720, 9, 1, 7, 2, 11, 14, 35, 15, 13, 12, 5, 13}, + {6658, 8, 2, 7, 3, 15, 13, 26, 15, 13, 12, 5, 13}, + {6597, 8, 2, 7, 2, 15, 13, 27, 15, 13, 12, 5, 13}, + {6539, 8, 2, 7, 2, 15, 13, 27, 15, 13, 12, 5, 13}, + {6482, 8, 2, 7, 2, 15, 13, 28, 15, 13, 12, 5, 13}, + {6427, 7, 2, 7, 3, 14, 13, 27, 15, 13, 12, 5, 13}, + {6373, 7, 2, 7, 3, 15, 13, 27, 15, 13, 12, 5, 13}, + {6321, 7, 2, 7, 3, 15, 13, 27, 15, 13, 12, 5, 13}, + {6270, 7, 2, 7, 3, 15, 13, 28, 15, 13, 12, 5, 13}, + {6222, 7, 2, 7, 3, 15, 13, 28, 15, 13, 12, 5, 13}, + {6174, 6, 2, 7, 3, 15, 13, 27, 15, 13, 12, 5, 13}, + {6128, 6, 2, 7, 3, 15, 13, 27, 15, 13, 12, 5, 13}, + {6083, 6, 2, 7, 3, 15, 13, 28, 15, 13, 12, 5, 13}, + {6040, 6, 2, 7, 3, 15, 13, 28, 15, 13, 12, 5, 13}, + {5997, 6, 2, 7, 3, 15, 13, 29, 15, 13, 12, 5, 13}, + }, { + {12605, 13, 1, 4, 2, 15, 12, 7, 15, 6, 13, 5, 14}, /* 80 MHz */ + {12245, 13, 1, 4, 2, 15, 12, 7, 15, 6, 13, 5, 14}, + {11906, 13, 1, 4, 2, 15, 12, 7, 15, 6, 13, 5, 14}, + {11588, 13, 1, 4, 2, 15, 12, 7, 14, 6, 14, 4, 14}, + {11288, 13, 1, 4, 2, 15, 12, 8, 15, 6, 13, 5, 14}, + {11007, 13, 1, 4, 2, 15, 12, 8, 14, 6, 13, 5, 14}, + {10742, 13, 1, 4, 2, 15, 12, 9, 15, 6, 13, 5, 14}, + {10492, 13, 1, 6, 2, 15, 12, 9, 14, 6, 13, 5, 14}, + {10258, 13, 1, 6, 2, 15, 12, 10, 15, 6, 13, 5, 14}, + {10036, 13, 1, 6, 2, 15, 12, 10, 15, 6, 13, 5, 14}, + {9827, 13, 1, 6, 2, 14, 12, 11, 15, 6, 13, 5, 14}, + {9631, 13, 1, 6, 2, 13, 12, 11, 15, 6, 13, 5, 14}, + {9445, 13, 1, 6, 2, 12, 12, 12, 15, 6, 13, 5, 14}, + {9269, 13, 1, 6, 2, 12, 12, 12, 15, 6, 13, 5, 14}, + {9103, 13, 1, 6, 2, 12, 12, 13, 15, 6, 13, 5, 14}, + {8946, 13, 1, 6, 2, 12, 12, 13, 15, 6, 13, 5, 14}, + {8797, 12, 1, 7, 2, 12, 12, 13, 15, 6, 13, 5, 14}, + {8655, 12, 1, 7, 2, 12, 12, 14, 15, 6, 13, 5, 14}, + {8520, 12, 1, 7, 2, 12, 12, 14, 15, 6, 13, 5, 14}, + {8392, 12, 1, 7, 2, 12, 12, 15, 15, 7, 13, 5, 14}, + {8269, 12, 1, 7, 2, 12, 12, 15, 15, 6, 13, 5, 14}, + {8153, 12, 1, 7, 2, 12, 12, 15, 15, 6, 13, 5, 14}, + {8041, 12, 1, 7, 2, 13, 12, 16, 15, 6, 13, 5, 14}, + {7934, 11, 1, 7, 2, 12, 12, 15, 15, 6, 13, 5, 14}, + {7831, 11, 1, 7, 2, 12, 12, 16, 15, 6, 13, 5, 14}, + {7733, 10, 1, 7, 3, 13, 12, 15, 15, 6, 13, 5, 14}, + {7638, 10, 1, 7, 2, 12, 12, 16, 15, 6, 13, 5, 14}, + {7547, 10, 1, 7, 2, 12, 12, 16, 15, 6, 13, 5, 14}, + {7459, 10, 1, 7, 2, 12, 12, 17, 15, 6, 13, 5, 14}, + {7374, 10, 2, 7, 3, 14, 13, 13, 15, 6, 13, 5, 14}, + {7291, 10, 2, 7, 3, 14, 13, 14, 15, 6, 13, 5, 14}, + {7212, 10, 2, 7, 3, 14, 13, 14, 15, 6, 13, 5, 14}, + {7135, 10, 2, 7, 3, 14, 13, 14, 15, 6, 13, 5, 14}, + {7061, 10, 2, 7, 3, 14, 13, 15, 15, 6, 13, 5, 14}, + {6988, 10, 1, 7, 3, 12, 14, 19, 15, 6, 13, 5, 14}, + {6918, 9, 2, 7, 3, 14, 13, 14, 15, 6, 13, 5, 14}, + {6850, 9, 2, 7, 3, 14, 13, 15, 15, 6, 13, 5, 14}, + {6784, 9, 2, 7, 2, 13, 13, 15, 15, 6, 13, 5, 14}, + {6720, 9, 2, 7, 2, 13, 13, 15, 15, 6, 13, 5, 14}, + {6658, 8, 2, 7, 3, 14, 13, 15, 15, 6, 13, 5, 14}, + {6597, 8, 2, 7, 2, 13, 13, 15, 15, 6, 13, 5, 14}, + {6539, 8, 2, 7, 2, 13, 13, 15, 15, 6, 13, 5, 14}, + {6482, 8, 2, 7, 2, 13, 13, 15, 15, 6, 13, 5, 14}, + {6427, 7, 2, 7, 3, 14, 13, 15, 15, 6, 13, 5, 14}, + {6373, 7, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, + {6321, 7, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, + {6270, 7, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, + {6222, 7, 2, 7, 3, 15, 13, 16, 15, 6, 13, 5, 14}, + {6174, 6, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, + {6128, 6, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, + {6083, 6, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, + {6040, 6, 2, 7, 3, 15, 13, 16, 15, 6, 13, 5, 14}, + {5997, 6, 2, 7, 3, 15, 13, 16, 15, 6, 13, 5, 14}, + } +}; + +static const struct SynthLUT SynthLUT_TDD[LUT_FTDD_ENT][SYNTH_LUT_SIZE] = { + { + {12605, 13, 1, 4, 2, 15, 12, 27, 12, 15, 12, 4, 13}, /* 40 MHz */ + {12245, 13, 1, 4, 2, 15, 12, 27, 12, 15, 12, 4, 13}, + {11906, 13, 1, 4, 2, 15, 12, 26, 11, 15, 12, 4, 13}, + {11588, 13, 1, 4, 2, 15, 12, 28, 12, 15, 12, 4, 13}, + {11288, 13, 1, 4, 2, 15, 12, 30, 12, 15, 12, 4, 13}, + {11007, 13, 1, 4, 2, 15, 12, 32, 12, 15, 12, 4, 13}, + {10742, 13, 1, 4, 2, 15, 12, 33, 12, 15, 12, 4, 13}, + {10492, 13, 1, 6, 2, 15, 12, 35, 12, 15, 12, 4, 13}, + {10258, 13, 1, 6, 2, 15, 12, 37, 12, 15, 12, 4, 13}, + {10036, 13, 1, 6, 2, 15, 12, 38, 12, 15, 12, 4, 13}, + {9827, 13, 1, 6, 2, 14, 12, 40, 12, 15, 12, 4, 13}, + {9631, 13, 1, 6, 2, 13, 12, 42, 12, 15, 12, 4, 13}, + {9445, 13, 1, 6, 2, 12, 12, 44, 12, 15, 12, 4, 13}, + {9269, 13, 1, 6, 2, 12, 12, 45, 12, 15, 12, 4, 13}, + {9103, 13, 1, 6, 2, 12, 12, 47, 12, 15, 12, 4, 13}, + {8946, 13, 1, 6, 2, 12, 12, 49, 12, 15, 12, 4, 13}, + {8797, 12, 1, 7, 2, 12, 12, 48, 12, 15, 12, 4, 13}, + {8655, 12, 1, 7, 2, 12, 12, 50, 12, 15, 12, 4, 13}, + {8520, 12, 1, 7, 2, 12, 12, 51, 12, 15, 12, 4, 13}, + {8392, 12, 1, 7, 2, 12, 12, 53, 12, 15, 12, 4, 13}, + {8269, 12, 1, 7, 2, 12, 12, 55, 12, 15, 12, 4, 13}, + {8153, 12, 1, 7, 2, 12, 12, 56, 12, 15, 12, 4, 13}, + {8041, 12, 1, 7, 2, 13, 12, 58, 12, 15, 12, 4, 13}, + {7934, 11, 1, 7, 2, 12, 12, 57, 12, 15, 12, 4, 13}, + {7831, 11, 1, 7, 2, 12, 12, 58, 12, 15, 12, 4, 13}, + {7733, 10, 1, 7, 3, 13, 12, 56, 12, 15, 12, 4, 13}, + {7638, 10, 1, 7, 2, 12, 12, 58, 12, 15, 12, 4, 13}, + {7547, 10, 1, 7, 2, 12, 12, 59, 12, 15, 12, 4, 13}, + {7459, 10, 1, 7, 2, 12, 12, 61, 12, 15, 12, 4, 13}, + {7374, 10, 2, 7, 3, 14, 13, 49, 12, 15, 12, 4, 13}, + {7291, 10, 2, 7, 3, 14, 13, 50, 12, 15, 12, 4, 13}, + {7212, 10, 2, 7, 3, 14, 13, 51, 12, 15, 12, 4, 13}, + {7135, 10, 2, 7, 3, 14, 13, 52, 12, 15, 12, 4, 13}, + {7061, 10, 2, 7, 3, 14, 13, 53, 12, 15, 12, 4, 13}, + {6988, 10, 1, 7, 3, 12, 14, 63, 11, 14, 12, 3, 13}, + {6918, 9, 2, 7, 3, 14, 13, 52, 12, 15, 12, 4, 13}, + {6850, 9, 2, 7, 3, 14, 13, 53, 12, 15, 12, 4, 13}, + {6784, 9, 2, 7, 2, 13, 13, 54, 12, 15, 12, 4, 13}, + {6720, 9, 2, 7, 2, 13, 13, 56, 12, 15, 12, 4, 13}, + {6658, 8, 2, 7, 3, 14, 13, 53, 12, 15, 12, 4, 13}, + {6597, 8, 2, 7, 2, 13, 13, 54, 12, 15, 12, 4, 13}, + {6539, 8, 2, 7, 2, 13, 13, 55, 12, 15, 12, 4, 13}, + {6482, 8, 2, 7, 2, 13, 13, 56, 12, 15, 12, 4, 13}, + {6427, 7, 2, 7, 3, 14, 13, 54, 12, 15, 12, 4, 13}, + {6373, 7, 2, 7, 3, 15, 13, 54, 12, 15, 12, 4, 13}, + {6321, 7, 2, 7, 3, 15, 13, 55, 12, 15, 12, 4, 13}, + {6270, 7, 2, 7, 3, 15, 13, 56, 12, 15, 12, 4, 13}, + {6222, 7, 2, 7, 3, 15, 13, 57, 12, 15, 12, 4, 13}, + {6174, 6, 2, 7, 3, 15, 13, 54, 12, 15, 12, 4, 13}, + {6128, 6, 2, 7, 3, 15, 13, 55, 12, 15, 12, 4, 13}, + {6083, 6, 2, 7, 3, 15, 13, 56, 12, 15, 12, 4, 13}, + {6040, 6, 2, 7, 3, 15, 13, 57, 12, 15, 12, 4, 13}, + {5997, 6, 2, 7, 3, 15, 13, 58, 12, 15, 12, 4, 13}, + }, { + {12605, 13, 1, 4, 2, 15, 12, 26, 11, 15, 11, 4, 13}, /* 60 MHz */ + {12245, 13, 1, 4, 2, 15, 12, 26, 11, 15, 11, 4, 13}, + {11906, 13, 1, 4, 2, 15, 12, 26, 12, 15, 11, 4, 12}, + {11588, 13, 1, 4, 2, 15, 12, 30, 12, 15, 11, 4, 12}, + {11288, 13, 1, 4, 2, 15, 12, 32, 12, 15, 10, 4, 12}, + {11007, 13, 1, 4, 2, 15, 12, 31, 12, 15, 11, 4, 12}, + {10742, 13, 1, 4, 2, 15, 12, 33, 12, 15, 10, 4, 12}, + {10492, 13, 1, 6, 2, 15, 12, 37, 12, 15, 10, 4, 12}, + {10258, 13, 1, 6, 2, 15, 12, 38, 12, 15, 11, 4, 13}, + {10036, 13, 1, 6, 2, 15, 12, 38, 12, 15, 10, 4, 12}, + {9827, 13, 1, 6, 2, 14, 12, 42, 12, 15, 11, 4, 12}, + {9631, 13, 1, 6, 2, 13, 12, 41, 12, 15, 11, 4, 12}, + {9445, 13, 1, 6, 2, 12, 12, 45, 12, 15, 11, 4, 12}, + {9269, 13, 1, 6, 2, 12, 12, 47, 12, 15, 11, 4, 12}, + {9103, 13, 1, 6, 2, 12, 12, 46, 12, 15, 11, 4, 12}, + {8946, 13, 1, 6, 2, 12, 12, 48, 12, 15, 10, 4, 12}, + {8797, 12, 1, 7, 2, 12, 12, 49, 12, 15, 11, 4, 13}, + {8655, 12, 1, 7, 2, 12, 12, 51, 12, 15, 11, 4, 12}, + {8520, 12, 1, 7, 2, 12, 12, 50, 12, 15, 11, 4, 12}, + {8392, 12, 1, 7, 2, 12, 12, 52, 12, 15, 10, 4, 12}, + {8269, 12, 1, 7, 2, 12, 12, 56, 12, 15, 10, 4, 12}, + {8153, 12, 1, 7, 2, 12, 12, 55, 12, 15, 11, 4, 12}, + {8041, 12, 1, 7, 2, 13, 12, 57, 12, 15, 10, 4, 12}, + {7934, 11, 1, 7, 2, 12, 12, 55, 12, 15, 11, 4, 12}, + {7831, 11, 1, 7, 2, 12, 12, 57, 12, 15, 10, 4, 12}, + {7733, 10, 1, 7, 3, 13, 12, 55, 12, 15, 11, 4, 12}, + {7638, 10, 1, 7, 2, 12, 12, 59, 12, 15, 10, 4, 12}, + {7547, 10, 1, 7, 2, 12, 12, 60, 12, 15, 11, 4, 12}, + {7459, 10, 1, 7, 2, 12, 12, 48, 12, 15, 11, 4, 12}, + {7374, 10, 2, 7, 3, 14, 13, 47, 12, 15, 11, 4, 13}, + {7291, 10, 2, 7, 3, 14, 13, 49, 12, 15, 10, 4, 12}, + {7212, 10, 2, 7, 3, 14, 13, 50, 12, 15, 10, 4, 12}, + {7135, 10, 2, 7, 3, 14, 13, 52, 12, 15, 11, 4, 13}, + {7061, 10, 2, 7, 3, 14, 13, 52, 12, 15, 11, 4, 12}, + {6988, 10, 1, 7, 3, 12, 14, 63, 11, 15, 11, 4, 13}, + {6918, 9, 1, 7, 3, 12, 14, 63, 11, 15, 11, 4, 13}, + {6850, 9, 1, 7, 3, 12, 14, 63, 11, 15, 11, 4, 13}, + {6784, 9, 1, 7, 2, 11, 14, 63, 11, 15, 11, 4, 13}, + {6720, 9, 1, 7, 2, 11, 14, 63, 11, 14, 11, 3, 13}, + {6658, 8, 1, 7, 3, 12, 14, 63, 11, 15, 11, 4, 13}, + {6597, 8, 1, 7, 2, 11, 14, 63, 11, 14, 11, 3, 13}, + {6539, 8, 1, 7, 2, 11, 14, 63, 10, 14, 11, 3, 13}, + {6482, 8, 1, 7, 2, 11, 14, 63, 10, 14, 11, 3, 13}, + {6427, 7, 2, 7, 3, 14, 13, 54, 12, 15, 10, 4, 12}, + {6373, 7, 2, 7, 3, 15, 13, 53, 12, 15, 11, 4, 12}, + {6321, 7, 2, 7, 3, 15, 13, 54, 12, 15, 11, 4, 12}, + {6270, 7, 2, 7, 3, 15, 13, 55, 12, 15, 11, 4, 12}, + {6222, 7, 2, 7, 3, 15, 13, 56, 12, 15, 11, 4, 12}, + {6174, 6, 2, 7, 3, 15, 13, 53, 12, 15, 11, 4, 12}, + {6128, 6, 2, 7, 3, 15, 13, 55, 12, 15, 11, 4, 12}, + {6083, 6, 2, 7, 3, 15, 13, 55, 12, 15, 10, 4, 12}, + {6040, 6, 2, 7, 3, 15, 13, 56, 12, 15, 10, 4, 12}, + {5997, 6, 2, 7, 3, 15, 13, 57, 12, 15, 10, 4, 12}, + }, { + {12605, 13, 1, 4, 2, 15, 12, 21, 12, 15, 11, 4, 13}, /* 80 MHz */ + {12245, 13, 1, 4, 2, 15, 12, 21, 12, 15, 11, 4, 13}, + {11906, 13, 1, 4, 2, 15, 12, 20, 11, 15, 11, 4, 13}, + {11588, 13, 1, 4, 2, 15, 12, 22, 12, 15, 11, 4, 12}, + {11288, 13, 1, 5, 2, 15, 12, 23, 12, 15, 11, 4, 13}, + {11007, 13, 1, 5, 2, 15, 12, 25, 12, 15, 10, 4, 12}, + {10742, 13, 1, 5, 2, 15, 12, 26, 12, 15, 11, 4, 13}, + {10492, 13, 1, 6, 2, 15, 12, 27, 11, 15, 11, 4, 13}, + {10258, 13, 1, 6, 2, 15, 12, 29, 12, 15, 10, 4, 12}, + {10036, 13, 1, 6, 2, 15, 12, 30, 12, 15, 11, 4, 12}, + {9827, 13, 1, 6, 2, 14, 12, 31, 12, 15, 11, 4, 13}, + {9631, 13, 1, 6, 2, 13, 12, 33, 12, 15, 10, 4, 12}, + {9445, 13, 1, 6, 2, 12, 12, 34, 12, 15, 11, 4, 12}, + {9269, 13, 1, 6, 2, 12, 12, 35, 12, 15, 11, 4, 13}, + {9103, 13, 1, 6, 2, 12, 12, 37, 12, 15, 10, 4, 12}, + {8946, 13, 1, 6, 2, 12, 12, 38, 12, 15, 11, 4, 12}, + {8797, 12, 1, 7, 2, 12, 12, 37, 12, 15, 11, 4, 13}, + {8655, 12, 1, 7, 2, 12, 12, 39, 12, 15, 11, 4, 12}, + {8520, 12, 1, 7, 2, 12, 12, 40, 12, 15, 11, 4, 12}, + {8392, 12, 1, 7, 2, 12, 12, 41, 12, 15, 11, 4, 13}, + {8269, 12, 1, 7, 2, 12, 12, 43, 12, 15, 10, 4, 12}, + {8153, 12, 1, 7, 2, 12, 12, 44, 12, 15, 11, 4, 12}, + {8041, 12, 1, 7, 2, 13, 12, 45, 12, 15, 11, 4, 12}, + {7934, 11, 1, 7, 2, 12, 12, 44, 12, 15, 11, 4, 12}, + {7831, 11, 1, 7, 2, 12, 12, 45, 12, 15, 11, 4, 13}, + {7733, 10, 1, 7, 3, 13, 12, 44, 12, 15, 11, 4, 12}, + {7638, 10, 1, 7, 2, 12, 12, 45, 12, 15, 11, 4, 12}, + {7547, 10, 1, 7, 2, 12, 12, 46, 12, 15, 11, 4, 12}, + {7459, 10, 1, 7, 2, 12, 12, 47, 12, 15, 11, 4, 13}, + {7374, 10, 2, 7, 3, 14, 13, 38, 12, 15, 11, 4, 12}, + {7291, 10, 2, 7, 3, 14, 13, 39, 12, 15, 10, 4, 12}, + {7212, 10, 2, 7, 3, 14, 13, 40, 12, 15, 10, 4, 12}, + {7135, 10, 2, 7, 3, 14, 13, 41, 12, 15, 10, 4, 12}, + {7061, 10, 2, 7, 3, 14, 13, 41, 12, 15, 11, 4, 13}, + {6988, 10, 1, 7, 3, 12, 14, 54, 12, 15, 11, 4, 12}, + {6918, 9, 2, 7, 3, 14, 13, 41, 12, 15, 10, 4, 12}, + {6850, 9, 2, 7, 3, 14, 13, 42, 12, 15, 10, 4, 12}, + {6784, 9, 2, 7, 2, 13, 13, 42, 12, 15, 11, 4, 13}, + {6720, 9, 2, 7, 2, 13, 13, 43, 12, 15, 11, 4, 13}, + {6658, 8, 2, 7, 3, 14, 13, 41, 12, 15, 11, 4, 13}, + {6597, 8, 2, 7, 2, 13, 13, 42, 12, 15, 11, 4, 12}, + {6539, 8, 2, 7, 2, 13, 13, 43, 12, 15, 11, 4, 12}, + {6482, 8, 2, 7, 2, 13, 13, 44, 12, 15, 11, 4, 12}, + {6427, 7, 2, 7, 3, 14, 13, 42, 12, 15, 10, 4, 12}, + {6373, 7, 2, 7, 3, 15, 13, 42, 12, 15, 11, 4, 13}, + {6321, 7, 2, 7, 3, 15, 13, 43, 12, 15, 11, 4, 12}, + {6270, 7, 2, 7, 3, 15, 13, 44, 12, 15, 11, 4, 12}, + {6222, 7, 2, 7, 3, 15, 13, 45, 12, 15, 10, 4, 12}, + {6174, 6, 2, 7, 3, 15, 13, 42, 12, 15, 11, 4, 13}, + {6128, 6, 2, 7, 3, 15, 13, 43, 12, 15, 11, 4, 12}, + {6083, 6, 2, 7, 3, 15, 13, 44, 12, 15, 10, 4, 12}, + {6040, 6, 2, 7, 3, 15, 13, 44, 12, 15, 11, 4, 13}, + {5997, 6, 2, 7, 3, 15, 13, 45, 12, 15, 11, 4, 12}, + } +}; + +/* Rx Gain Tables */ + +#define SIZE_FULL_TABLE 77 + +static const uint8_t full_gain_table[RXGAIN_TBLS_END][SIZE_FULL_TABLE][3] = { + { /* 800 MHz */ + {0x00, 0x00, 0x20}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, + {0x00, 0x01, 0x00}, {0x00, 0x02, 0x00}, {0x00, 0x03, 0x00}, + {0x00, 0x04, 0x00}, {0x00, 0x05, 0x00}, {0x01, 0x03, 0x20}, + {0x01, 0x04, 0x00}, {0x01, 0x05, 0x00}, {0x01, 0x06, 0x00}, + {0x01, 0x07, 0x00}, {0x01, 0x08, 0x00}, {0x01, 0x09, 0x00}, + {0x01, 0x0A, 0x00}, {0x01, 0x0B, 0x00}, {0x01, 0x0C, 0x00}, + {0x01, 0x0D, 0x00}, {0x01, 0x0E, 0x00}, {0x02, 0x09, 0x20}, + {0x02, 0x0A, 0x00}, {0x02, 0x0B, 0x00}, {0x02, 0x0C, 0x00}, + {0x02, 0x0D, 0x00}, {0x02, 0x0E, 0x00}, {0x02, 0x0F, 0x00}, + {0x02, 0x10, 0x00}, {0x02, 0x2B, 0x20}, {0x02, 0x2C, 0x00}, + {0x04, 0x28, 0x20}, {0x04, 0x29, 0x00}, {0x04, 0x2A, 0x00}, + {0x04, 0x2B, 0x00}, {0x24, 0x20, 0x20}, {0x24, 0x21, 0x00}, + {0x44, 0x20, 0x20}, {0x44, 0x21, 0x00}, {0x44, 0x22, 0x00}, + {0x44, 0x23, 0x00}, {0x44, 0x24, 0x00}, {0x44, 0x25, 0x00}, + {0x44, 0x26, 0x00}, {0x44, 0x27, 0x00}, {0x44, 0x28, 0x00}, + {0x44, 0x29, 0x00}, {0x44, 0x2A, 0x00}, {0x44, 0x2B, 0x00}, + {0x44, 0x2C, 0x00}, {0x44, 0x2D, 0x00}, {0x44, 0x2E, 0x00}, + {0x44, 0x2F, 0x00}, {0x44, 0x30, 0x00}, {0x44, 0x31, 0x00}, + {0x44, 0x32, 0x00}, {0x64, 0x2E, 0x20}, {0x64, 0x2F, 0x00}, + {0x64, 0x30, 0x00}, {0x64, 0x31, 0x00}, {0x64, 0x32, 0x00}, + {0x64, 0x33, 0x00}, {0x64, 0x34, 0x00}, {0x64, 0x35, 0x00}, + {0x64, 0x36, 0x00}, {0x64, 0x37, 0x00}, {0x64, 0x38, 0x00}, + {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, + {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, + {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, + {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20} + },{ /* 2300 MHz */ + {0x00, 0x00, 0x20}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, + {0x00, 0x01, 0x00}, {0x00, 0x02, 0x00}, {0x00, 0x03, 0x00}, + {0x00, 0x04, 0x00}, {0x00, 0x05, 0x00}, {0x01, 0x03, 0x20}, + {0x01, 0x04, 0x00}, {0x01, 0x05, 0x00}, {0x01, 0x06, 0x00}, + {0x01, 0x07, 0x00}, {0x01, 0x08, 0x00}, {0x01, 0x09, 0x00}, + {0x01, 0x0A, 0x00}, {0x01, 0x0B, 0x00}, {0x01, 0x0C, 0x00}, + {0x01, 0x0D, 0x00}, {0x01, 0x0E, 0x00}, {0x02, 0x09, 0x20}, + {0x02, 0x0A, 0x00}, {0x02, 0x0B, 0x00}, {0x02, 0x0C, 0x00}, + {0x02, 0x0D, 0x00}, {0x02, 0x0E, 0x00}, {0x02, 0x0F, 0x00}, + {0x02, 0x10, 0x00}, {0x02, 0x2B, 0x20}, {0x02, 0x2C, 0x00}, + {0x04, 0x27, 0x20}, {0x04, 0x28, 0x00}, {0x04, 0x29, 0x00}, + {0x04, 0x2A, 0x00}, {0x04, 0x2B, 0x00}, {0x24, 0x21, 0x20}, + {0x24, 0x22, 0x00}, {0x44, 0x20, 0x20}, {0x44, 0x21, 0x00}, + {0x44, 0x22, 0x00}, {0x44, 0x23, 0x00}, {0x44, 0x24, 0x00}, + {0x44, 0x25, 0x00}, {0x44, 0x26, 0x00}, {0x44, 0x27, 0x00}, + {0x44, 0x28, 0x00}, {0x44, 0x29, 0x00}, {0x44, 0x2A, 0x00}, + {0x44, 0x2B, 0x00}, {0x44, 0x2C, 0x00}, {0x44, 0x2D, 0x00}, + {0x44, 0x2E, 0x00}, {0x44, 0x2F, 0x00}, {0x44, 0x30, 0x00}, + {0x44, 0x31, 0x00}, {0x64, 0x2E, 0x20}, {0x64, 0x2F, 0x00}, + {0x64, 0x30, 0x00}, {0x64, 0x31, 0x00}, {0x64, 0x32, 0x00}, + {0x64, 0x33, 0x00}, {0x64, 0x34, 0x00}, {0x64, 0x35, 0x00}, + {0x64, 0x36, 0x00}, {0x64, 0x37, 0x00}, {0x64, 0x38, 0x00}, + {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, + {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, + {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, + {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20}, + },{ /* 5500 MHz */ + {0x00, 0x00, 0x20}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x01, 0x00}, + {0x00, 0x02, 0x00}, {0x00, 0x03, 0x00}, {0x01, 0x01, 0x20}, + {0x01, 0x02, 0x00}, {0x01, 0x03, 0x00}, {0x01, 0x04, 0x20}, + {0x01, 0x05, 0x00}, {0x01, 0x06, 0x00}, {0x01, 0x07, 0x00}, + {0x01, 0x08, 0x00}, {0x01, 0x09, 0x00}, {0x01, 0x0A, 0x00}, + {0x01, 0x0B, 0x00}, {0x01, 0x0C, 0x00}, {0x02, 0x08, 0x20}, + {0x02, 0x09, 0x00}, {0x02, 0x0A, 0x00}, {0x02, 0x0B, 0x20}, + {0x02, 0x0C, 0x00}, {0x02, 0x0D, 0x00}, {0x02, 0x0E, 0x00}, + {0x02, 0x0F, 0x00}, {0x02, 0x2A, 0x20}, {0x02, 0x2B, 0x00}, + {0x04, 0x27, 0x20}, {0x04, 0x28, 0x00}, {0x04, 0x29, 0x00}, + {0x04, 0x2A, 0x00}, {0x04, 0x2B, 0x00}, {0x04, 0x2C, 0x00}, + {0x04, 0x2D, 0x00}, {0x24, 0x20, 0x20}, {0x24, 0x21, 0x00}, + {0x24, 0x22, 0x00}, {0x44, 0x20, 0x20}, {0x44, 0x21, 0x00}, + {0x44, 0x22, 0x00}, {0x44, 0x23, 0x00}, {0x44, 0x24, 0x00}, + {0x44, 0x25, 0x00}, {0x44, 0x26, 0x00}, {0x44, 0x27, 0x00}, + {0x44, 0x28, 0x00}, {0x44, 0x29, 0x00}, {0x44, 0x2A, 0x00}, + {0x44, 0x2B, 0x00}, {0x44, 0x2C, 0x00}, {0x44, 0x2D, 0x00}, + {0x44, 0x2E, 0x00}, {0x64, 0x2E, 0x20}, {0x64, 0x2F, 0x00}, + {0x64, 0x30, 0x00}, {0x64, 0x31, 0x00}, {0x64, 0x32, 0x00}, + {0x64, 0x33, 0x00}, {0x64, 0x34, 0x00}, {0x64, 0x35, 0x00}, + {0x64, 0x36, 0x00}, {0x64, 0x37, 0x00}, {0x64, 0x38, 0x00}, + {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, + {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, + {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, + {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20} + } +}; + +static const int8_t full_gain_table_abs_gain[RXGAIN_TBLS_END][SIZE_FULL_TABLE] = { + { /* 800 MHz */ + -1, -1, -1, 0, 1, 2, 3, 4, + 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, + 29, 30, 31, 32, 33, 34, 35, 36, + 37, 38, 39, 40, 41, 42, 43, 44, + 45, 46, 47, 48, 49, 50, 51, 52, + 53, 54, 55, 56, 57, 58, 59, 60, + 61, 62, 63, 64, 65, 66, 67, 68, + 69, 70, 71, 72, 73 + }, { /* 2300 MHz */ + -3, -3, -3, -2, -1, 0, 1, 2, + 3, 4, 5, 6, 7, 8, 9, 10, + 11, 12, 13, 14, 15, 16, 17, 18, + 19, 20, 21, 22, 23, 24, 25, 26, + 27, 28, 29, 30, 31, 32, 33, 34, + 35, 36, 37, 38, 39, 40, 41, 42, + 43, 44, 45, 46, 47, 48, 49, 50, + 51, 52, 53, 54, 55, 56, 57, 58, + 59, 60, 61, 62, 63, 64, 65, 66, + 67, 68, 69, 70, 71 + }, { /* 5500 MHz */ + -10, -10, -10, -10, -10, -9, -8, -7, + -6, -5, -4, -3, -2, -1, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25, + 26, 27, 28, 29, 30, 31, 32, 33, + 34, 35, 36, 37, 38, 39, 40, 41, + 42, 43, 44, 45, 46, 47, 48, 49, + 50, 51, 52, 53, 54, 55, 56, 57, + 58, 59, 60, 61, 62 + } +}; + +#define SIZE_SPLIT_TABLE 41 + +#if HAVE_SPLIT_GAIN_TABLE +static const uint8_t split_gain_table[RXGAIN_TBLS_END][SIZE_SPLIT_TABLE][3] = { + { /* 800 MHz */ + {0x00, 0x18, 0x20}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, + {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, + {0x00, 0x18, 0x20}, {0x01, 0x18, 0x20}, {0x02, 0x18, 0x20}, + {0x04, 0x18, 0x20}, {0x04, 0x38, 0x20}, {0x05, 0x38, 0x20}, + {0x06, 0x38, 0x20}, {0x07, 0x38, 0x20}, {0x08, 0x38, 0x20}, + {0x09, 0x38, 0x20}, {0x0A, 0x38, 0x20}, {0x0B, 0x38, 0x20}, + {0x0C, 0x38, 0x20}, {0x0D, 0x38, 0x20}, {0x0E, 0x38, 0x20}, + {0x0F, 0x38, 0x20}, {0x24, 0x38, 0x20}, {0x25, 0x38, 0x20}, + {0x44, 0x38, 0x20}, {0x45, 0x38, 0x20}, {0x46, 0x38, 0x20}, + {0x47, 0x38, 0x20}, {0x48, 0x38, 0x20}, {0x64, 0x38, 0x20}, + {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, + {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, + {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, + {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20}, + },{ /* 2300 MHz */ + {0x00, 0x18, 0x20}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, + {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, + {0x00, 0x18, 0x00}, {0x00, 0x18, 0x20}, {0x01, 0x18, 0x20}, + {0x02, 0x18, 0x20}, {0x04, 0x18, 0x20}, {0x04, 0x38, 0x20}, + {0x05, 0x38, 0x20}, {0x06, 0x38, 0x20}, {0x07, 0x38, 0x20}, + {0x08, 0x38, 0x20}, {0x09, 0x38, 0x20}, {0x0A, 0x38, 0x20}, + {0x0B, 0x38, 0x20}, {0x0C, 0x38, 0x20}, {0x0D, 0x38, 0x20}, + {0x0E, 0x38, 0x20}, {0x0F, 0x38, 0x20}, {0x25, 0x38, 0x20}, + {0x26, 0x38, 0x20}, {0x44, 0x38, 0x20}, {0x45, 0x38, 0x20}, + {0x46, 0x38, 0x20}, {0x47, 0x38, 0x20}, {0x64, 0x38, 0x20}, + {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, + {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, + {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, + {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20}, + },{ /* 5500 MHz */ + {0x00, 0x18, 0x20}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, + {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, + {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, + {0x00, 0x18, 0x00}, {0x01, 0x18, 0x20}, {0x02, 0x18, 0x20}, + {0x04, 0x18, 0x20}, {0x04, 0x38, 0x20}, {0x05, 0x38, 0x20}, + {0x06, 0x38, 0x20}, {0x07, 0x38, 0x20}, {0x08, 0x38, 0x20}, + {0x09, 0x38, 0x20}, {0x0A, 0x38, 0x20}, {0x0B, 0x38, 0x20}, + {0x0C, 0x38, 0x20}, {0x0D, 0x38, 0x20}, {0x0E, 0x38, 0x20}, + {0x0F, 0x38, 0x20}, {0x62, 0x38, 0x20}, {0x25, 0x38, 0x20}, + {0x26, 0x38, 0x20}, {0x44, 0x38, 0x20}, {0x64, 0x38, 0x20}, + {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, + {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, + {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, + {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20}, + } +}; + +static const uint8_t +split_gain_table_abs_gain[RXGAIN_TBLS_END][SIZE_SPLIT_TABLE] = { + { /* 800 MHz */ + -1, -1, -1, -1, -1, -1, -1, 2, + 8, 13, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32, + 33, 34, 35, 36, 37, 38, 39, 40, + 41, 42, 43, 44, 45, 46, 47, 48, + 49 + }, { /* 2300 MHz */ + -3, -3, -3, -3, -3, -3, -3, -3, + 0, 6, 12, 18, 19, 20, 21, 22, + 23, 24, 25, 26, 27, 28, 29, 30, + 31, 32, 33, 34, 35, 36, 37, 38, + 39, 40, 41, 42, 43, 44, 45, 46, + 47 + }, { /* 5500 MHz */ + -10, -10, -10, -10, -10, -10, -10, -10, + -10, -10, -7, -2, 3, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 19, + 20, 22, 24, 25, 26, 27, 28, 29, + 30, 31, 32, 33, 34, 35, 36, 37, + 38 + } +}; +#endif + +struct gain_table_info ad9361_adi_gt_info[] = { + { + .start = 0, + .end = 1300000000ULL, + .max_index = SIZE_FULL_TABLE, + .abs_gain_tbl = (int8_t *) &full_gain_table_abs_gain[TBL_200_1300_MHZ], + .tab = (uint8_t (*)[3]) full_gain_table[TBL_200_1300_MHZ], + },{ + .start = 1300000000ULL, + .end = 4000000000ULL, + .max_index = SIZE_FULL_TABLE, + .abs_gain_tbl = (int8_t *) &full_gain_table_abs_gain[TBL_1300_4000_MHZ], + .tab = (uint8_t (*)[3]) full_gain_table[TBL_1300_4000_MHZ], + },{ + .start = 4000000000ULL, + .end = 6000000000ULL, + .max_index = SIZE_FULL_TABLE, + .abs_gain_tbl = (int8_t *) &full_gain_table_abs_gain[TBL_4000_6000_MHZ], + .tab = (uint8_t (*)[3]) full_gain_table[TBL_4000_6000_MHZ], +#if HAVE_SPLIT_GAIN_TABLE + },{ + .start = 0, + .end = 1300000000ULL, + .max_index = SIZE_SPLIT_TABLE, + .split_table = 1, + .abs_gain_tbl = (int8_t *) &split_gain_table_abs_gain[TBL_200_1300_MHZ], + .tab = (uint8_t (*)[3]) split_gain_table[TBL_200_1300_MHZ], + },{ + .start = 1300000000ULL, + .end = 4000000000ULL, + .max_index = SIZE_SPLIT_TABLE, + .split_table = 1, + .abs_gain_tbl = (int8_t *) &split_gain_table_abs_gain[TBL_1300_4000_MHZ], + .tab = (uint8_t (*)[3]) split_gain_table[TBL_1300_4000_MHZ], + },{ + .start = 4000000000ULL, + .end = 6000000000ULL, + .max_index = SIZE_SPLIT_TABLE, + .split_table = 1, + .abs_gain_tbl = (int8_t *) &split_gain_table_abs_gain[TBL_4000_6000_MHZ], + .tab = (uint8_t (*)[3]) split_gain_table[TBL_4000_6000_MHZ], +#endif + },{ + .start = 0, + .end = 0, + .max_index = 0, + .split_table = 0, + .abs_gain_tbl = NULL, + .tab = NULL, + }, /* Don't Remove */ +}; + +/* Mixer GM Sub-table */ + +static const uint8_t gm_st_gain[16]= {0x78, 0x74, 0x70, 0x6C, 0x68, 0x64, 0x60, + 0x5C, 0x58, 0x54, 0x50, 0x4C, 0x48, 0x30, 0x18, 0x0}; +static const uint8_t gm_st_ctrl[16]= {0x0, 0xD, 0x15, 0x1B, 0x21, 0x25, 0x29, + 0x2C, 0x2F, 0x31, 0x33, 0x34, 0x35, 0x3A, 0x3D, 0x3E}; + + +static const int8_t lna_table[RXGAIN_TBLS_END][4] = { + {5, 17, 19, 24}, {3, 14, 17, 21}, {-4, 10, 13, 14}}; +static const int8_t tia_table[] = {-6, 0}; +static const int8_t mixer_table[RXGAIN_TBLS_END][16] = { + {0, 3, 9, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}, + {0, 3, 9, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26}, + {0, 3, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24} +}; + +static const uint32_t gain_step_calib_reg_val[4][5] = { + {0xC0, 0x2E, 0x10, 0x06, 0x00}, // LO Frequency Range: 600 to 1300 MHz + {0xC0, 0x2C, 0x10, 0x06, 0x00}, // LO Frequency Range: 1300 to 3300 MHz + {0xB8, 0x2C, 0x10, 0x06, 0x00}, // LO Frequency Range: 2700 to 4100 MHz + {0xA0, 0x24, 0x10, 0x06, 0x00}, // LO Frequency Range: 4000 to 6000 MHz +}; + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +const char *ad9361_ensm_states[] = { + "sleep", "", "", "", "", "alert", "tx", "tx flush", + "rx", "rx_flush", "fdd", "fdd_flush" +}; + +/** + * SPI multiple bytes register read. + * @param spi + * @param reg The register address. + * @param rbuf The data buffer. + * @param num The number of bytes to read. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_spi_readm(struct spi_desc *spi, uint32_t reg, + uint8_t *rbuf, uint32_t num) +{ + int32_t ret = 0; + uint16_t cmd; + uint8_t *rbuffer; + if (num > MAX_MBYTE_SPI) + return -EINVAL; + + cmd = AD_READ | AD_CNT(num) | AD_ADDR(reg); + rbuffer = malloc(num + 2); + if(!rbuffer) + return -ENOMEM; + rbuffer[0] = cmd >> 8; + rbuffer[1] = cmd & 0xFF; + ret = spi_write_and_read(spi, &rbuffer[0], 2 + num); + + if (ret < 0) + dev_err(&spi->dev, "Read Error %"PRId32, ret); + else + memcpy(rbuf, &rbuffer[2], num); + + free(rbuffer); +#ifdef _DEBUG + { + int32_t i; + for (i = 0; i < num; i++) + dev_dbg(&spi->dev, "%s: reg 0x%"PRIX32" val 0x%X", + __func__, reg--, rbuf[i]); + } +#endif + + return ret; +} + +/** + * SPI register read. + * @param spi + * @param reg The register address. + * @return The register value or negative error code in case of failure. + */ +int32_t ad9361_spi_read(struct spi_desc *spi, uint32_t reg) +{ + uint8_t buf; + int32_t ret; + + ret = ad9361_spi_readm(spi, reg, &buf, 1); + if (ret < 0) + return ret; + + return buf; +} + +/** + * SPI register bits read. + * @param spi + * @param reg The register address. + * @param mask The bits mask. + * @param offset The mask offset. + * @return The bits value or negative error code in case of failure. + */ +static int32_t __ad9361_spi_readf(struct spi_desc *spi, uint32_t reg, + uint32_t mask, uint32_t offset) +{ + uint8_t buf; + int32_t ret; + + if (!mask) + return -EINVAL; + + ret = ad9361_spi_readm(spi, reg, &buf, 1); + if (ret < 0) + return ret; + + buf &= mask; + buf >>= offset; + + return buf; +} + +/** + * SPI register bits read. + * @param spi + * @param reg The register address. + * @param mask The bits mask. + * @return The bits value or negative error code in case of failure. + */ +#define ad9361_spi_readf(spi, reg, mask) \ + __ad9361_spi_readf(spi, reg, mask, find_first_bit(mask)) + +/** + * SPI register write. + * @param spi + * @param reg The register address. + * @param val The value of the register. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_spi_write(struct spi_desc *spi, + uint32_t reg, uint32_t val) +{ + uint8_t buf[3]; + int32_t ret; + uint16_t cmd; + + cmd = AD_WRITE | AD_CNT(1) | AD_ADDR(reg); + buf[0] = cmd >> 8; + buf[1] = cmd & 0xFF; + buf[2] = val; + + ret = spi_write_and_read(spi, buf, 3); + if (ret < 0) { + dev_err(&spi->dev, "Write Error %"PRId32, ret); + return ret; + } + +#ifdef _DEBUG + dev_dbg(&spi->dev, "%s: reg 0x%"PRIX32" val 0x%X", __func__, reg, buf[2]); +#endif + + return 0; +} + +/** + * SPI register bits write. + * @param spi + * @param reg The register address. + * @param mask The bits mask. + * @param offset The mask offset. + * @param val The bits value. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t __ad9361_spi_writef(struct spi_desc *spi, uint32_t reg, + uint32_t mask, uint32_t offset, uint32_t val) +{ + uint8_t buf; + int32_t ret; + + if (!mask) + return -EINVAL; + + ret = ad9361_spi_readm(spi, reg, &buf, 1); + if (ret < 0) + return ret; + + buf &= ~mask; + buf |= ((val << offset) & mask); + + return ad9361_spi_write(spi, reg, buf); +} + +/** + * SPI register bits write. + * @param spi + * @param reg The register address. + * @param mask The bits mask. + * @param val The bits value. + * @return 0 in case of success, negative error code otherwise. + */ +#define ad9361_spi_writef(spi, reg, mask, val) \ + __ad9361_spi_writef(spi, reg, mask, find_first_bit(mask), val) + +/** + * SPI multiple bytes register write. + * @param spi + * @param reg The register address. + * @param tbuf The data buffer. + * @param num The number of bytes to read. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_spi_writem(struct spi_desc *spi, + uint32_t reg, uint8_t *tbuf, uint32_t num) +{ + uint8_t buf[10]; + int32_t ret; + uint16_t cmd; + + if (num > MAX_MBYTE_SPI) + return -EINVAL; + + cmd = AD_WRITE | AD_CNT(num) | AD_ADDR(reg); + buf[0] = cmd >> 8; + buf[1] = cmd & 0xFF; + +#ifndef ALTERA_PLATFORM + memcpy(&buf[2], tbuf, num); +#else + int32_t i; + for (i = 0; i < num; i++) + buf[2 + i] = tbuf[i]; +#endif + ret = spi_write_and_read(spi, buf, num + 2); + if (ret < 0) { + dev_err(&spi->dev, "Write Error %"PRId32, ret); + return ret; + } + +#ifdef _DEBUG + { + int32_t i; + for (i = 0; i < num; i++) + dev_dbg(&spi->dev, "Reg 0x%"PRIX32" val 0x%X", reg--, tbuf[i]); + } +#endif + + return 0; +} + +/** + * Validate RF BW frequency. + * @param phy The AD9361 state structure. + * @param bw The RF BW frequency. + * @return The validated RF BW frequency. + */ +uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw) +{ + switch (phy->dev_sel) { + case ID_AD9363A: + return clamp_t(uint32_t, bw, 200000UL, 20000000UL); + default: + return clamp_t(uint32_t, bw, 200000UL, 56000000UL); + } +} + +/** + * Validate RF PLL frequency. + * @param phy The AD9361 state structure. + * @param is_tx TX enabled. + * @param freq The RF PLL frequency. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_validate_rfpll(struct ad9361_rf_phy *phy, bool is_tx, + uint64_t freq) +{ + switch (phy->dev_sel) { + case ID_AD9363A: + if (freq > AD9363A_MAX_CARRIER_FREQ_HZ || + freq < AD9363A_MIN_CARRIER_FREQ_HZ) + return -EINVAL; + break; + default: + if (freq > MAX_CARRIER_FREQ_HZ || freq < (is_tx ? + MIN_TX_CARRIER_FREQ_HZ : MIN_RX_CARRIER_FREQ_HZ)) + return -EINVAL; + } + + return 0; +} + +/** + * Find optimal value. + * @param field + * @param size + * @param ret_start + * @return The optimal delay in case of success, negative error code otherwise. + */ +int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start) +{ + int32_t i, cnt = 0, max_cnt = 0, start, max_start = 0; + + for(i = 0, start = -1; i < (int64_t)size; i++) { + if (field[i] == 0) { + if (start == -1) + start = i; + cnt++; + } else { + if (cnt > max_cnt) { + max_cnt = cnt; + max_start = start; + } + start = -1; + cnt = 0; + } + } + + if (cnt > max_cnt) { + max_cnt = cnt; + max_start = start; + } + + *ret_start = max_start; + + return max_cnt; +} + +/** + * Select the channel mapping in 1rx1tx mode. + * @param phy The AD9361 state structure. + * @param tx TX + * @param channel Channel + * @return The channel number. + */ +int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx, + int32_t channel) +{ + uint32_t map; + + if (phy->pdata->rx2tx2) + return channel; + + if (tx) + map = phy->pdata->rx1tx1_mode_use_tx_num; + else + map = phy->pdata->rx1tx1_mode_use_rx_num; + + if (map == 2) + return channel + 1; + + return channel; +} + +/** + * AD9361 Device Reset + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_reset(struct ad9361_rf_phy *phy) +{ + if (phy->gpio_desc_resetb) { + gpio_set_value(phy->gpio_desc_resetb, 0); + mdelay(1); + gpio_set_value(phy->gpio_desc_resetb, 1); + mdelay(1); + dev_dbg(&phy->spi->dev, "%s: by GPIO", __func__); + return 0; + } + + /* SPI Soft Reset was removed from the register map, since it doesn't + * work reliably. Without a prober HW reset randomness may happen. + * Please specify a RESET GPIO. + */ + + ad9361_spi_write(phy->spi, REG_SPI_CONF, SOFT_RESET | _SOFT_RESET); + ad9361_spi_write(phy->spi, REG_SPI_CONF, 0x0); + dev_err(&phy->spi->dev, + "%s: by SPI, this may cause unpredicted behavior!", __func__); + + return -ENODEV; +} + +/** + * Enable/disable the desired TX channel. + * @param phy The AD9361 state structure. + * @param tx_if The desired channel number [1, 2]. + * @param enable Enable/disable option. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_en_dis_tx(struct ad9361_rf_phy *phy, uint32_t tx_if, + uint32_t enable) +{ + if ((tx_if & enable) > 1 && AD9364_DEVICE && enable) + return -EINVAL; + + return ad9361_spi_writef(phy->spi, REG_TX_ENABLE_FILTER_CTRL, + TX_CHANNEL_ENABLE(tx_if), enable); +} + +/** + * Enable/disable the desired RX channel. + * @param phy The AD9361 state structure. + * @param rx_if The desired channel number [1, 2]. + * @param enable Enable/disable option. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if, + uint32_t enable) +{ + if ((rx_if & enable) > 1 && AD9364_DEVICE && enable) + return -EINVAL; + + return ad9361_spi_writef(phy->spi, REG_RX_ENABLE_FILTER_CTRL, + RX_CHANNEL_ENABLE(rx_if), enable); +} + +/** + * Loopback works only TX1->RX1 or RX2->RX2. + * @param phy The AD9361 state structure. + * @param enable Enable. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_int_loopback_fix_ch_cross(struct ad9361_rf_phy *phy, + bool enable) +{ + /* Loopback works only TX1->RX1 or RX2->RX2 */ + if (!phy->pdata->rx2tx2 && phy->pdata->rx1tx1_mode_use_rx_num != + phy->pdata->rx1tx1_mode_use_tx_num) + return ad9361_en_dis_tx(phy, TX_1 | TX_2, + enable ? phy->pdata->rx1tx1_mode_use_rx_num : + phy->pdata->rx1tx1_mode_use_tx_num); + + return 0; +} + +/** + * BIST loopback mode. + * @param phy The AD9361 state structure. + * @param mode BIST loopback mode. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode) +{ + uint32_t sp_hd, reg; + + dev_dbg(&phy->spi->dev, "%s: mode %"PRId32, __func__, mode); + + reg = ad9361_spi_read(phy->spi, REG_OBSERVE_CONFIG); + + phy->bist_loopback_mode = mode; + + switch (mode) { + case 0: + ad9361_hdl_loopback(phy, false); + ad9361_int_loopback_fix_ch_cross(phy, false); + reg &= ~(DATA_PORT_SP_HD_LOOP_TEST_OE | + DATA_PORT_LOOP_TEST_ENABLE); + return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg); + case 1: + /* loopback (AD9361 internal) TX->RX */ + ad9361_hdl_loopback(phy, false); + ad9361_int_loopback_fix_ch_cross(phy, true); + sp_hd = ad9361_spi_read(phy->spi, REG_PARALLEL_PORT_CONF_3); + if ((sp_hd & SINGLE_PORT_MODE) && (sp_hd & HALF_DUPLEX_MODE)) + reg |= DATA_PORT_SP_HD_LOOP_TEST_OE; + else + reg &= ~DATA_PORT_SP_HD_LOOP_TEST_OE; + + reg |= DATA_PORT_LOOP_TEST_ENABLE; + + return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg); + case 2: + /* loopback (FPGA internal) RX->TX */ + ad9361_hdl_loopback(phy, true); + ad9361_int_loopback_fix_ch_cross(phy, false); + reg &= ~(DATA_PORT_SP_HD_LOOP_TEST_OE | + DATA_PORT_LOOP_TEST_ENABLE); + return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg); + default: + return -EINVAL; + } +} + +/** + * Get BIST loopback mode. + * @param phy The AD9361 state structure. + * @param mode BIST loopback mode. + * @return 0 in case of success, negative error code otherwise. + */ +void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode) +{ + *mode = phy->bist_loopback_mode; +} + +/** + * BIST mode. + * @param phy The AD9361 state structure. + * @param mode Bist mode. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode) +{ + uint32_t reg = 0; + + dev_dbg(&phy->spi->dev, "%s: mode %d", __func__, mode); + + phy->bist_prbs_mode = mode; + + switch (mode) { + case BIST_DISABLE: + reg = 0; + break; + case BIST_INJ_TX: + reg = BIST_CTRL_POINT(0) | BIST_ENABLE; + break; + case BIST_INJ_RX: + reg = BIST_CTRL_POINT(2) | BIST_ENABLE; + break; + }; + + phy->bist_config = reg; + + return ad9361_spi_write(phy->spi, REG_BIST_CONFIG, reg); +} + +/** + * Get BIST mode settings. + * @param phy The AD9361 state structure. + * @param mode Bist mode. + * @return 0 in case of success, negative error code otherwise. + */ +void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy, + enum ad9361_bist_mode *mode) +{ + *mode = phy->bist_prbs_mode; +} + +/** + * BIST tone. + * @param phy The AD9361 state structure. + * @param mode Bist tone mode. + * @param freq_Hz Bist tone frequency. + * @param level_dB Bist tone level. + * @param mask Bist reg mask. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_bist_tone(struct ad9361_rf_phy *phy, + enum ad9361_bist_mode mode, uint32_t freq_Hz, + uint32_t level_dB, uint32_t mask) +{ + uint32_t clk = 0; + uint32_t reg = 0, reg1, reg_mask; + + dev_dbg(&phy->spi->dev, "%s: mode %d", __func__, mode); + + phy->bist_tone_mode = mode; + phy->bist_tone_freq_Hz = freq_Hz; + phy->bist_tone_level_dB = level_dB; + phy->bist_tone_mask = mask; + + switch (mode) { + case BIST_DISABLE: + reg = 0; + break; + case BIST_INJ_TX: + clk = clk_get_rate(phy, phy->ref_clk_scale[TX_SAMPL_CLK]); + reg = BIST_CTRL_POINT(0) | BIST_ENABLE; + break; + case BIST_INJ_RX: + clk = clk_get_rate(phy, phy->ref_clk_scale[RX_SAMPL_CLK]); + reg = BIST_CTRL_POINT(2) | BIST_ENABLE; + break; + }; + + reg |= TONE_PRBS; + reg |= TONE_LEVEL(level_dB / 6); + + if (freq_Hz < 4) { + reg |= TONE_FREQ(freq_Hz); + } else { + if (clk) + reg |= TONE_FREQ(DIV_ROUND_CLOSEST(freq_Hz * 32, clk) - 1); + } + + reg_mask = BIST_MASK_CHANNEL_1_I_DATA | BIST_MASK_CHANNEL_1_Q_DATA | + BIST_MASK_CHANNEL_2_I_DATA | BIST_MASK_CHANNEL_2_Q_DATA; + + reg1 = ((mask << 2) & reg_mask); + ad9361_spi_write(phy->spi, REG_BIST_AND_DATA_PORT_TEST_CONFIG, reg1); + + phy->bist_config = reg; + + return ad9361_spi_write(phy->spi, REG_BIST_CONFIG, reg); +} + +/** + * Get BIST tone settings. + * @param phy The AD9361 state structure. + * @param mode Bist tone mode. + * @param freq_Hz Bist tone frequency. + * @param level_dB Bist tone level. + * @param mask Bist reg mask. + * @return 0 in case of success, negative error code otherwise. + */ +void ad9361_get_bist_tone(struct ad9361_rf_phy *phy, + enum ad9361_bist_mode *mode, uint32_t *freq_Hz, + uint32_t *level_dB, uint32_t *mask) +{ + *mode = phy->bist_tone_mode; + *freq_Hz = phy->bist_tone_freq_Hz; + *level_dB = phy->bist_tone_level_dB; + *mask = phy->bist_tone_mask; +} + +/** + * Check the calibration done bit. + * @param phy The AD9361 state structure. + * @param reg The register address. + * @param mask The bit mask. + * @param done_state The done state [0,1]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_check_cal_done(struct ad9361_rf_phy *phy, uint32_t reg, + uint32_t mask, uint32_t done_state) +{ + uint32_t timeout = 20000; /* RFDC_CAL can take long */ + uint32_t state; + + do { + state = ad9361_spi_readf(phy->spi, reg, mask); + if (state == done_state) + return 0; + + if (reg == REG_CALIBRATION_CTRL) + udelay(1200); + else + udelay(120); + } while (timeout--); + + dev_err(&phy->spi->dev, "Calibration TIMEOUT (0x%"PRIX32", 0x%"PRIX32")", reg, + mask); + + return -ETIMEDOUT; +} + +/** + * Run an AD9361 calibration and check the calibration done bit. + * @param phy The AD9361 state structure. + * @param mask The calibration bit mask[RX_BB_TUNE_CAL, TX_BB_TUNE_CAL, + * RX_QUAD_CAL, TX_QUAD_CAL, RX_GAIN_STEP_CAL, TXMON_CAL, + * RFDC_CAL, BBDC_CAL]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_run_calibration(struct ad9361_rf_phy *phy, uint32_t mask) +{ + int32_t ret = ad9361_spi_write(phy->spi, REG_CALIBRATION_CTRL, mask); + if (ret < 0) + return ret; + + dev_dbg(&phy->spi->dev, "%s: CAL Mask 0x%"PRIx32, __func__, mask); + + return ad9361_check_cal_done(phy, REG_CALIBRATION_CTRL, mask, 0); +} + +/** + * Choose the right RX gain table index for the selected frequency. + * @param freq The frequency value [Hz]. + * @return The index to the RX gain table. + */ +static int32_t ad9361_gt_tableindex(struct ad9361_rf_phy *phy, uint64_t freq) +{ + int32_t i; + + for (i = 0; phy->gt_info[i].tab != NULL; i++) { + if ((phy->pdata->split_gt == phy->gt_info[i].split_table) && + (phy->gt_info[i].start < freq) && + (freq <= phy->gt_info[i].end)) { + return i; + } + } + + dev_err(&phy->spi->dev, + "%s: Failed to find suitable gain table (%"PRIu64")", __func__, freq); + + return 0; +} + +/** + * Return the current gain table index. + * @param phy The AD9361 state structure. + * @return The current gain table index or 0 if the table was not chosen. + */ +uint32_t ad9361_gt(struct ad9361_rf_phy *phy) +{ + if (phy->current_table == NO_GAIN_TABLE) { + dev_err(&phy->spi->dev, "%s: ERROR", __func__); + return 0; + } + + return phy->current_table; +} + +/** + * Shift the real frequency value, so it fits type unsigned long + * Note: PLL operates between 47 .. 6000 MHz which is > 2^32. + * @param freq The frequency value [Hz]. + * @return The shifted frequency value. + */ +uint32_t ad9361_to_clk(uint64_t freq) +{ + return (uint32_t)(freq >> 1); +} + +/** + * Shift back the frequency value, so it reflects the real value. + * Note: PLL operates between 47 .. 6000 MHz which is > 2^32. + * @param freq The frequency value [Hz]. + * @return The shifted frequency value. + */ +uint64_t ad9361_from_clk(uint32_t freq) +{ + return ((uint64_t)freq << 1); +} + +/** + * Find the corresponding table index for a specific gain value. + * @param phy The AD9361 state structure. + * @param gain The gain value. + * @return The table index. + */ +static int find_table_index(struct ad9361_rf_phy *phy, int gain) +{ + uint32_t i, nm1, n; + + for (i = 0; i < phy->gt_info[ad9361_gt(phy)].max_index; i++) { + if (phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[i] >= gain) { + nm1 = abs(phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[ + (i > 0) ? i - 1 : i] - gain); + n = abs(phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[i] + - gain); + if (nm1 < n) + return (i > 0) ? i - 1 : i; + else + return i; + } + } + + return -EINVAL; +} + +/** + * Load the gain table for the selected frequency range and receiver. + * @param phy The AD9361 state structure. + * @param freq The frequency value [Hz]. + * @param dest The destination [GT_RX1, GT_RX2]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_load_gt(struct ad9361_rf_phy *phy, uint64_t freq, + uint32_t dest) +{ + struct spi_desc *spi = phy->spi; + uint8_t (*tab)[3]; + uint32_t band, index_max, i, lna, lpf_tia_mask, set_gain; + int32_t ret, rx1_gain, rx2_gain; + + dev_dbg(&phy->spi->dev, "%s: frequency %"PRIu64, __func__, freq); + + band = ad9361_gt_tableindex(phy, freq); + + dev_dbg(&phy->spi->dev, "%s: frequency %"PRIu64" (band %"PRIu32")", + __func__, freq, band); + + /* check if table is present */ + if (phy->current_table == band) + return 0; + + tab = phy->gt_info[band].tab; + index_max = phy->gt_info[band].max_index; + + ad9361_spi_writef(spi, REG_AGC_CONFIG_2, + AGC_USE_FULL_GAIN_TABLE, !phy->pdata->split_gt); + + ad9361_spi_write(spi, REG_MAX_LMT_FULL_GAIN, + index_max - 1); /* Max Full/LMT Gain Table Index */ + + set_gain = ad9361_spi_readf(spi, REG_RX1_MANUAL_LMT_FULL_GAIN, + RX_FULL_TBL_IDX_MASK); + + if (phy->current_table != NO_GAIN_TABLE) { + rx1_gain = phy->gt_info[phy->current_table].abs_gain_tbl[set_gain]; + } else { + if (set_gain > (index_max - 1)) + set_gain = index_max - 1; + + rx1_gain = phy->gt_info[band].abs_gain_tbl[set_gain]; + } + + set_gain = ad9361_spi_readf(spi, REG_RX2_MANUAL_LMT_FULL_GAIN, + RX_FULL_TBL_IDX_MASK); + + if (phy->current_table != NO_GAIN_TABLE) { + rx2_gain = phy->gt_info[phy->current_table].abs_gain_tbl[set_gain]; + } else { + if (set_gain > (index_max - 1)) + set_gain = index_max - 1; + + rx2_gain = phy->gt_info[band].abs_gain_tbl[set_gain]; + } + + lna = phy->pdata->elna_ctrl.elna_in_gaintable_all_index_en ? + EXT_LNA_CTRL : 0; + + ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, START_GAIN_TABLE_CLOCK | + RECEIVER_SELECT(dest)); /* Start Gain Table Clock */ + + /* TX QUAD Calibration */ + if (phy->pdata->split_gt) + lpf_tia_mask = 0x20; + else + lpf_tia_mask = 0x3F; + + phy->tx_quad_lpf_tia_match = -EINVAL; + + for (i = 0; i < index_max; i++) { + ad9361_spi_write(spi, REG_GAIN_TABLE_ADDRESS, i); /* Gain Table Index */ + ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA1, + tab[i][0] | lna); /* Ext LNA, Int LNA, & Mixer Gain Word */ + ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA2, + tab[i][1]); /* TIA & LPF Word */ + ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA3, + tab[i][2]); /* DC Cal bit & Dig Gain Word */ + ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, + START_GAIN_TABLE_CLOCK | + WRITE_GAIN_TABLE | + RECEIVER_SELECT(dest)); /* Gain Table Index */ + ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, + 0); /* Dummy Write to delay 3 ADCCLK/16 cycles */ + ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, + 0); /* Dummy Write to delay ~1u */ + + if ((tab[i][1] & lpf_tia_mask) == 0x20) + phy->tx_quad_lpf_tia_match = i; + + } + + ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, START_GAIN_TABLE_CLOCK | + RECEIVER_SELECT(dest)); /* Clear Write Bit */ + ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, + 0); /* Dummy Write to delay ~1u */ + ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, + 0); /* Dummy Write to delay ~1u */ + ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, 0); /* Stop Gain Table Clock */ + + phy->current_table = band; + + ret = find_table_index(phy, rx1_gain); + if (ret < 0) + ret = phy->gt_info[band].max_index - 1; + + ad9361_spi_writef(spi, REG_RX1_MANUAL_LMT_FULL_GAIN, + RX_FULL_TBL_IDX_MASK, ret); /* Rx1 Full/LMT Gain Index */ + + ret = find_table_index(phy, rx2_gain); + if (ret < 0) + ret = phy->gt_info[band].max_index - 1; + + ad9361_spi_write(spi, REG_RX2_MANUAL_LMT_FULL_GAIN, + ret); /* Rx2 Full/LMT Gain Index */ + + return 0; +} + +/** + * Setup the external low-noise amplifier (LNA). + * @param phy The AD9361 state structure. + * @param ctrl Pointer to eLNA control structure. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_setup_ext_lna(struct ad9361_rf_phy *phy, + struct elna_control *ctrl) +{ + ad9361_spi_writef(phy->spi, REG_EXTERNAL_LNA_CTRL, EXTERNAL_LNA1_CTRL, + ctrl->elna_1_control_en); + + ad9361_spi_writef(phy->spi, REG_EXTERNAL_LNA_CTRL, EXTERNAL_LNA2_CTRL, + ctrl->elna_2_control_en); + + ad9361_spi_write(phy->spi, REG_EXT_LNA_HIGH_GAIN, + EXT_LNA_HIGH_GAIN(ctrl->gain_mdB / 500)); + + return ad9361_spi_write(phy->spi, REG_EXT_LNA_LOW_GAIN, + EXT_LNA_LOW_GAIN(ctrl->bypass_loss_mdB / 500)); +} + +/** + * Set the clock output mode. + * @param phy The AD9361 state structure. + * @param mode The clock output mode []. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_clkout_control(struct ad9361_rf_phy *phy, + enum ad9361_clkout mode) +{ + if (mode == CLKOUT_DISABLE) + return ad9361_spi_writef(phy->spi, REG_BBPLL, CLKOUT_ENABLE, 0); + + return ad9361_spi_writef(phy->spi, REG_BBPLL, + CLKOUT_ENABLE | CLKOUT_SELECT(~0), + ((mode - 1) << 1) | 0x1); +} + +/** + * Load the Gm Sub Table. + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_load_mixer_gm_subtable(struct ad9361_rf_phy *phy) +{ + int32_t i, addr; + dev_dbg(&phy->spi->dev, "%s", __func__); + + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_CONFIG, + START_GM_SUB_TABLE_CLOCK); /* Start Clock */ + + for (i = 0, addr = ARRAY_SIZE(gm_st_ctrl); i < (int64_t)ARRAY_SIZE(gm_st_ctrl); + i++) { + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_ADDRESS, + --addr); /* Gain Table Index */ + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_BIAS_WRITE, 0); /* Bias */ + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_GAIN_WRITE, + gm_st_gain[i]); /* Gain */ + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_CTRL_WRITE, + gm_st_ctrl[i]); /* Control */ + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_CONFIG, + WRITE_GM_SUB_TABLE | START_GM_SUB_TABLE_CLOCK); /* Write Words */ + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_GAIN_READ, 0); /* Dummy Delay */ + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_GAIN_READ, 0); /* Dummy Delay */ + } + + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_CONFIG, + START_GM_SUB_TABLE_CLOCK); /* Clear Write */ + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_GAIN_READ, 0); /* Dummy Delay */ + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_GAIN_READ, 0); /* Dummy Delay */ + ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_CONFIG, 0); /* Stop Clock */ + + return 0; +} + +/** + * Set the attenuation for the selected TX channels. + * @param phy The AD9361 state structure. + * @param atten_mdb Attenuation value [mdB]. + * @param tx1 Set true, the attenuation of the TX1 will be affected. + * @param tx2 Set true, the attenuation of the TX2 will be affected. + * @param immed Set true, an immediate update will take place. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb, + bool tx1, bool tx2, bool immed) +{ + uint8_t buf[2]; + int32_t ret = 0; + + dev_dbg(&phy->spi->dev, "%s : attenuation %"PRIu32" mdB tx1=%d tx2=%d", + __func__, atten_mdb, tx1, tx2); + + if (atten_mdb > MAX_TX_ATTENUATION_DB) /* 89.75 dB */ + return -EINVAL; + + atten_mdb /= 250; /* Scale to 0.25dB / LSB */ + + buf[0] = atten_mdb >> 8; + buf[1] = atten_mdb & 0xFF; + + ad9361_spi_writef(phy->spi, REG_TX2_DIG_ATTEN, + IMMEDIATELY_UPDATE_TPC_ATTEN, 0); + + if (tx1) + ret = ad9361_spi_writem(phy->spi, REG_TX1_ATTEN_1, buf, 2); + + if (tx2) + ret = ad9361_spi_writem(phy->spi, REG_TX2_ATTEN_1, buf, 2); + + if (immed) + ad9361_spi_writef(phy->spi, REG_TX2_DIG_ATTEN, + IMMEDIATELY_UPDATE_TPC_ATTEN, 1); + + return ret; +} + +/** + * Get the attenuation for the selected TX channel. + * @param phy The AD9361 state structure. + * @param tx_num The selected channel [1, 2]. + * @return The attenuation value [mdB] or negative error code in case of failure. + */ +int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num) +{ + uint8_t buf[2]; + int32_t ret = 0; + uint32_t code; + + ret = ad9361_spi_readm(phy->spi, (tx_num == 1) ? + REG_TX1_ATTEN_1 : REG_TX2_ATTEN_1, buf, 2); + + if (ret < 0) + return ret; + + code = (buf[0] << 8) | buf[1]; + + code *= 250; + + return code; +} + +/** + * Mute TX. + * @param phy The AD9361 state structure. + * @param state The state - 0 mute; 1 - unmute. + * @return 0 in case of success + */ +int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state) +{ + int32_t ret; + + if (state) { + phy->tx1_atten_cached = ad9361_get_tx_atten(phy, 1); + phy->tx2_atten_cached = ad9361_get_tx_atten(phy, 2); + + return ad9361_set_tx_atten(phy, 89750, true, true, true); + } else { + if (phy->tx1_atten_cached == phy->tx2_atten_cached) + return ad9361_set_tx_atten(phy, phy->tx1_atten_cached, + true, true, true); + + ret = ad9361_set_tx_atten(phy, phy->tx1_atten_cached, + true, false, true); + ret |= ad9361_set_tx_atten(phy, phy->tx2_atten_cached, + false, true, true); + + return ret; + } +} + +/** + * Choose the right RF VCO table index for the selected frequency. + * @param freq The frequency value [Hz]. + * @return The index from the RF VCO table. + */ +static uint32_t ad9361_rfvco_tableindex(uint32_t freq) +{ + if (freq < 50000000UL) + return LUT_FTDD_40; + + if (freq <= 70000000UL) + return LUT_FTDD_60; + + return LUT_FTDD_80; +} + +/** + * Initialize the RFPLL VCO. + * @param phy The AD9361 state structure. + * @param tx Set true for TX_RFPLL. + * @param vco_freq The VCO frequency [Hz]. + * @param ref_clk The reference clock frequency [Hz]. + * @return 0 in case of success + */ +static int32_t ad9361_rfpll_vco_init(struct ad9361_rf_phy *phy, + bool tx, uint64_t vco_freq, + uint32_t ref_clk) +{ + struct spi_desc *spi = phy->spi; + const struct SynthLUT(*tab); + int32_t i = 0; + uint32_t range, offs = 0; + + range = ad9361_rfvco_tableindex(ref_clk); + + dev_dbg(&phy->spi->dev, + "%s : vco_freq %"PRIu64" : ref_clk %"PRIu32" : range %"PRIu32, + __func__, vco_freq, ref_clk, range); + + do_div(&vco_freq, 1000000UL); /* vco_freq in MHz */ + + if ((phy->pdata->fdd && !phy->pdata->fdd_independent_mode) + && (phy->current_tx_lo_freq != phy->current_rx_lo_freq)) { + tab = &SynthLUT_FDD[range][0]; + if (tx) + phy->current_tx_use_tdd_table = false; + else + phy->current_rx_use_tdd_table = false; + } else { + if (have_tdd_tables) { + tab = &SynthLUT_TDD[range][0]; + if (tx) + phy->current_tx_use_tdd_table = true; + else + phy->current_rx_use_tdd_table = true; + } + } + + if (tx) + offs = REG_TX_VCO_OUTPUT - REG_RX_VCO_OUTPUT; + + while (i < SYNTH_LUT_SIZE && tab[i].VCO_MHz > vco_freq) + i++; + + dev_dbg(&phy->spi->dev, "%s : freq %d MHz : index %"PRId32, + __func__, tab[i].VCO_MHz, i); + + ad9361_spi_write(spi, REG_RX_VCO_OUTPUT + offs, + VCO_OUTPUT_LEVEL(tab[i].VCO_Output_Level) | + PORB_VCO_LOGIC); + ad9361_spi_writef(spi, REG_RX_ALC_VARACTOR + offs, + VCO_VARACTOR(~0), tab[i].VCO_Varactor); + ad9361_spi_write(spi, REG_RX_VCO_BIAS_1 + offs, + VCO_BIAS_REF(tab[i].VCO_Bias_Ref) | + VCO_BIAS_TCF(tab[i].VCO_Bias_Tcf)); + + ad9361_spi_write(spi, REG_RX_FORCE_VCO_TUNE_1 + offs, + VCO_CAL_OFFSET(tab[i].VCO_Cal_Offset)); + ad9361_spi_write(spi, REG_RX_VCO_VARACTOR_CTRL_1 + offs, + VCO_VARACTOR_REFERENCE( + tab[i].VCO_Varactor_Reference)); + + ad9361_spi_write(spi, REG_RX_VCO_CAL_REF + offs, VCO_CAL_REF_TCF(0)); + + ad9361_spi_write(spi, REG_RX_VCO_VARACTOR_CTRL_0 + offs, + VCO_VARACTOR_OFFSET(0) | + VCO_VARACTOR_REFERENCE_TCF(7)); + + ad9361_spi_writef(spi, REG_RX_CP_CURRENT + offs, CHARGE_PUMP_CURRENT(~0), + tab[i].Charge_Pump_Current); + ad9361_spi_write(spi, REG_RX_LOOP_FILTER_1 + offs, + LOOP_FILTER_C2(tab[i].LF_C2) | + LOOP_FILTER_C1(tab[i].LF_C1)); + ad9361_spi_write(spi, REG_RX_LOOP_FILTER_2 + offs, + LOOP_FILTER_R1(tab[i].LF_R1) | + LOOP_FILTER_C3(tab[i].LF_C3)); + ad9361_spi_write(spi, REG_RX_LOOP_FILTER_3 + offs, + LOOP_FILTER_R3(tab[i].LF_R3)); + + return 0; +} + +/** + * Get the current gain in Split Gain Table Mode + * @param phy The AD9361 state structure. + * @param idx_reg Register base address for the selected receiver + * @param rx_gain A rf_rx_gain struct to store the RF gain. + * @return 0 in case of success, + */ +static int32_t ad9361_get_split_table_gain(struct ad9361_rf_phy *phy, + uint32_t idx_reg, + struct rf_rx_gain *rx_gain) +{ + struct spi_desc *spi = phy->spi; + uint32_t val, tbl_addr; + int32_t rc = 0; + + + rx_gain->fgt_lmt_index = ad9361_spi_readf(spi, idx_reg, + FULL_TABLE_GAIN_INDEX(~0)); + tbl_addr = ad9361_spi_read(spi, REG_GAIN_TABLE_ADDRESS); + + ad9361_spi_write(spi, REG_GAIN_TABLE_ADDRESS, rx_gain->fgt_lmt_index); + + val = ad9361_spi_read(spi, REG_GAIN_TABLE_READ_DATA1); + rx_gain->lna_index = TO_LNA_GAIN(val); + rx_gain->mixer_index = TO_MIXER_GM_GAIN(val); + + rx_gain->tia_index = ad9361_spi_readf(spi, REG_GAIN_TABLE_READ_DATA2, TIA_GAIN); + + rx_gain->lmt_gain = lna_table[ad9361_gt(phy) - RXGAIN_TBLS_END][rx_gain->lna_index] + + mixer_table[ad9361_gt(phy) - RXGAIN_TBLS_END][rx_gain->mixer_index] + + tia_table[rx_gain->tia_index]; + + ad9361_spi_write(spi, REG_GAIN_TABLE_ADDRESS, tbl_addr); + + /* Read LPF Index */ + rx_gain->lpf_gain = ad9361_spi_readf(spi, idx_reg + 1, LPF_GAIN_RX(~0)); + + /* Read Digital Gain */ + rx_gain->digital_gain = ad9361_spi_readf(spi, idx_reg + 2, + DIGITAL_GAIN_RX(~0)); + + rx_gain->gain_db = rx_gain->lmt_gain + rx_gain->lpf_gain + + rx_gain->digital_gain; + return rc; +} + +/** + * Get the current gain in Full Gain Table Mode + * @param phy The AD9361 state structure. + * @param idx_reg Register base address for the selected receiver + * @param rx_gain A rf_rx_gain struct to store the RF gain. + * @return 0 in case of success + */ +static int32_t ad9361_get_full_table_gain(struct ad9361_rf_phy *phy, + uint32_t idx_reg, + struct rf_rx_gain *rx_gain) +{ + struct spi_desc *spi = phy->spi; + uint32_t val; + + rx_gain->fgt_lmt_index = val = ad9361_spi_readf(spi, idx_reg, + FULL_TABLE_GAIN_INDEX(~0)); + /* Read Digital Gain */ + rx_gain->digital_gain = ad9361_spi_readf(spi, idx_reg + 2, + DIGITAL_GAIN_RX(~0)); + + rx_gain->gain_db = phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[val]; + + return 0; +} + +/** + * Get current RX gain for the selected channel. + * @param phy The AD9361 state structure. + * @param rx_id The desired channel number (0, 1). + * @param rx_gain A rf_rx_gain struct to store the RF gain. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy, + uint32_t rx_id, struct rf_rx_gain *rx_gain) +{ + struct spi_desc *spi = phy->spi; + uint32_t val, idx_reg; + uint8_t gain_ctl_shift, rx_enable_mask; + uint8_t fast_atk_shift; + int32_t rc = 0; + + if (rx_id == 1) { + gain_ctl_shift = RX1_GAIN_CTRL_SHIFT; + idx_reg = REG_GAIN_RX1; + rx_enable_mask = RX_CHANNEL_ENABLE(RX_1); + fast_atk_shift = RX1_FAST_ATK_SHIFT; + + } else if (rx_id == 2) { + gain_ctl_shift = RX2_GAIN_CTRL_SHIFT; + idx_reg = REG_GAIN_RX2; + rx_enable_mask = RX_CHANNEL_ENABLE(RX_2); + fast_atk_shift = RX2_FAST_ATK_SHIFT; + } else { + dev_err(dev, "Unknown Rx path %"PRIu32, rx_id); + rc = -EINVAL; + goto out; + } + + val = ad9361_spi_readf(spi, REG_RX_ENABLE_FILTER_CTRL, rx_enable_mask); + + if (!val) { + dev_dbg(dev, "Rx%"PRIu32" is not enabled", rx_gain->ant); + rc = -EAGAIN; + goto out; + } + + val = ad9361_spi_read(spi, REG_AGC_CONFIG_1); + + val = (val >> gain_ctl_shift) & RX_GAIN_CTL_MASK; + + if (val == RX_GAIN_CTL_AGC_FAST_ATK) { + /* In fast attack mode check whether Fast attack state machine + * has locked gain, if not then we can not read gain. + */ + val = ad9361_spi_read(spi, REG_FAST_ATTACK_STATE); + val = (val >> fast_atk_shift) & FAST_ATK_MASK; + if (val != FAST_ATK_GAIN_LOCKED) { + dev_warn(dev, "Failed to read gain, state m/c at %"PRIx32, + val); + rc = -EAGAIN; + goto out; + } + } + + if (has_split_gt && phy->pdata->split_gt) + rc = ad9361_get_split_table_gain(phy, idx_reg, rx_gain); + else + rc = ad9361_get_full_table_gain(phy, idx_reg, rx_gain); + +out: + return rc; +} + +/** + * Get Enable State Machine (ENSM) state. + * @param phy The AD9361 state structure. + * @return The state. + */ +uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy) +{ + return ad9361_spi_readf(phy->spi, REG_STATE, ENSM_STATE(~0)); +} + +/** + * Force Enable State Machine (ENSM) to the desired state (internally used only). + * @param phy The AD9361 state structure. + * @param ensm_state The ENSM state [ENSM_STATE_SLEEP_WAIT, ENSM_STATE_ALERT, + * ENSM_STATE_TX, ENSM_STATE_TX_FLUSH, ENSM_STATE_RX, + * ENSM_STATE_RX_FLUSH, ENSM_STATE_FDD, ENSM_STATE_FDD_FLUSH]. + * @return None. + */ +void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state) +{ + struct spi_desc *spi = phy->spi; + uint8_t dev_ensm_state; + int32_t rc, timeout = 10; + uint32_t val; + + dev_ensm_state = ad9361_spi_readf(spi, REG_STATE, ENSM_STATE(~0)); + + phy->prev_ensm_state = dev_ensm_state; + + if (dev_ensm_state == ensm_state) { + dev_dbg(dev, "Nothing to do, device is already in %d state", + ensm_state); + goto out; + } + + dev_dbg(dev, "Device is in %x state, forcing to %x", dev_ensm_state, + ensm_state); + + val = ad9361_spi_read(spi, REG_ENSM_CONFIG_1); + + /* Enable control through SPI writes, and take out from + * Alert + */ + if (val & ENABLE_ENSM_PIN_CTRL) { + val &= ~ENABLE_ENSM_PIN_CTRL; + phy->ensm_pin_ctl_en = true; + } else { + phy->ensm_pin_ctl_en = false; + } + + if (dev_ensm_state) + val &= ~(TO_ALERT); + + switch (ensm_state) { + + case ENSM_STATE_TX: + case ENSM_STATE_FDD: + val |= FORCE_TX_ON; + break; + case ENSM_STATE_RX: + val |= FORCE_RX_ON; + break; + case ENSM_STATE_ALERT: + val &= ~(FORCE_TX_ON | FORCE_RX_ON); + val |= TO_ALERT | FORCE_ALERT_STATE; + break; + default: + dev_err(dev, "No handling for forcing %d ensm state", + ensm_state); + goto out; + } + + ad9361_spi_write(spi, REG_ENSM_CONFIG_1, TO_ALERT | FORCE_ALERT_STATE); + + rc = ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val); + if (rc) { + dev_err(dev, "Failed to write ENSM_CONFIG_1\n"); + goto out; + } + + while (ad9361_ensm_get_state(phy) != ensm_state && --timeout) { + mdelay(1); + } + + if (timeout == 0) + dev_err(dev, "Failed to restore state"); + +out: + return; + +} + +/** + * Restore an Enable State Machine (ENSM) state. + * @param phy The AD9361 state structure. + * @param ensm_state The state. + * @return None. + */ +void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state) +{ + struct spi_desc *spi = phy->spi; + int32_t rc; + uint32_t val; + + val = ad9361_spi_read(spi, REG_ENSM_CONFIG_1); + + /* We are restoring state only, so clear State bits first + * which might have set while forcing a particular state + */ + val &= ~(FORCE_TX_ON | FORCE_RX_ON | FORCE_ALERT_STATE); + val |= TO_ALERT; + + switch (ensm_state) { + case ENSM_STATE_TX: + case ENSM_STATE_FDD: + val |= FORCE_TX_ON; + break; + case ENSM_STATE_RX: + val |= FORCE_RX_ON; + break; + case ENSM_STATE_ALERT: + val |= TO_ALERT; + break; + case ENSM_STATE_INVALID: + dev_dbg(dev, "No need to restore, ENSM state wasn't saved"); + return; + default: + dev_dbg(dev, "Could not restore to %d ENSM state", + ensm_state); + return; + } + + ad9361_spi_write(spi, REG_ENSM_CONFIG_1, TO_ALERT | FORCE_ALERT_STATE); + + rc = ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val); + if (rc) { + dev_err(dev, "Failed to write ENSM_CONFIG_1"); + return; + } + + if (phy->ensm_pin_ctl_en) { + val |= ENABLE_ENSM_PIN_CTRL; + rc = ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val); + if (rc) + dev_err(dev, "Failed to write ENSM_CONFIG_1"); + } +} + +/** + * Restore the previous Enable State Machine (ENSM) state. + * @param phy The AD9361 state structure. + * @return None. + */ +void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy) +{ + return ad9361_ensm_restore_state(phy, phy->prev_ensm_state); +} + +/** + * Set gain in Split Gain Table Mode (used only in Manual Gain Control Mode). + * @param phy The AD9361 state structure. + * @param idx_reg Register base address for the selected receiver + * @param rx_gain The rf_rx_gain struct containing the RF gain. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t set_split_table_gain(struct ad9361_rf_phy *phy, uint32_t idx_reg, + struct rf_rx_gain *rx_gain) +{ + struct spi_desc *spi = phy->spi; + int32_t rc = 0; + + if ((rx_gain->fgt_lmt_index > MAX_LMT_INDEX) || + (rx_gain->lpf_gain > MAX_LPF_GAIN) || + (rx_gain->digital_gain > MAX_DIG_GAIN)) { + dev_err(dev, "LMT_INDEX missing or greater than max value %d", + MAX_LMT_INDEX); + dev_err(dev, "LPF_GAIN missing or greater than max value %d", + MAX_LPF_GAIN); + dev_err(dev, "DIGITAL_GAIN cannot be more than %d", + MAX_DIG_GAIN); + rc = -EINVAL; + goto out; + } + + rc = find_table_index(phy, rx_gain->gain_db); + if (rc < 0) { + dev_err(dev, "Invalid gain %"PRId32", supported range [%d - %d]\n", + rx_gain->gain_db, phy->gt_info[ad9361_gt(phy)]. + abs_gain_tbl[0], + phy->gt_info[ad9361_gt(phy)].abs_gain_tbl + [phy->gt_info[ad9361_gt(phy)].max_index - 1]); + goto out; + } + + rx_gain->fgt_lmt_index = rc; + + rc = ad9361_spi_writef(spi, idx_reg, RX_FULL_TBL_IDX_MASK, + rx_gain->fgt_lmt_index); + if (rc < 0) + goto out; + rc = ad9361_spi_writef(spi, idx_reg + 1, RX_LPF_IDX_MASK, rx_gain->lpf_gain); + if (rc < 0) + goto out; + if (phy->pdata->gain_ctrl.dig_gain_en) { + rc = ad9361_spi_writef(spi, idx_reg + 2, RX_DIGITAL_IDX_MASK, + rx_gain->digital_gain); + } else if (rx_gain->digital_gain > 0) { + dev_err(dev, "Digital gain is disabled and cannot be set"); + } +out: + return rc; +} + +/** + * Set gain in Full Gain Table Mode (used only in Manual Gain Control Mode). + * @param phy The AD9361 state structure. + * @param idx_reg Register base address for the selected receiver + * @param rx_gain The rf_rx_gain struct containing the RF gain. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t set_full_table_gain(struct ad9361_rf_phy *phy, uint32_t idx_reg, + struct rf_rx_gain *rx_gain) +{ + struct spi_desc *spi = phy->spi; + int rc = 0; + + if (rx_gain->fgt_lmt_index != ((uint32_t)~0) || + rx_gain->lpf_gain != ((uint32_t)~0) || + rx_gain->digital_gain > 0) + dev_dbg(dev, + "Ignoring lmt/lpf/digital gains in Single Table mode"); + + rc = find_table_index(phy, rx_gain->gain_db); + if (rc < 0) { + dev_err(dev, "Invalid gain %"PRId32", supported range [%d - %d]\n", + rx_gain->gain_db, phy->gt_info[ad9361_gt(phy)]. + abs_gain_tbl[0], + phy->gt_info[ad9361_gt(phy)].abs_gain_tbl + [phy->gt_info[ad9361_gt(phy)].max_index - 1]); + goto out; + } + + rc = ad9361_spi_writef(spi, idx_reg, RX_FULL_TBL_IDX_MASK, rc); +out: + return rc; +} + +/** + * Set the RX gain for the selected channel. + * @param phy The AD9361 state structure. + * @param rx_id The desired channel number (0, 1). + * @param rx_gain The rf_rx_gain struct containing the RF gain. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy, + uint32_t rx_id, struct rf_rx_gain *rx_gain) +{ + struct spi_desc *spi = phy->spi; + uint32_t val, idx_reg; + uint8_t gain_ctl_shift; + int32_t rc = 0; + + if (rx_id == 1) { + gain_ctl_shift = RX1_GAIN_CTRL_SHIFT; + idx_reg = REG_RX1_MANUAL_LMT_FULL_GAIN; + + } else if (rx_id == 2) { + gain_ctl_shift = RX2_GAIN_CTRL_SHIFT; + idx_reg = REG_RX2_MANUAL_LMT_FULL_GAIN; + } else { + dev_err(dev, "Unknown Rx path %"PRIu32, rx_id); + rc = -EINVAL; + goto out; + + } + + val = ad9361_spi_read(spi, REG_AGC_CONFIG_1); + val = (val >> gain_ctl_shift) & RX_GAIN_CTL_MASK; + + if (val != RX_GAIN_CTL_MGC) { + dev_dbg(dev, "Rx gain can be set in MGC mode only"); + rc = -EOPNOTSUPP; + goto out; + } + + if (has_split_gt && phy->pdata->split_gt) + rc = set_split_table_gain(phy, idx_reg, rx_gain); + else + rc = set_full_table_gain(phy, idx_reg, rx_gain); + + if (rc) { + dev_err(dev, "Unable to write gain tbl idx reg: %"PRIu32, idx_reg); + goto out; + } + +out: + return rc; + +} + +/** + * Update the Gain Control. + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_gc_update(struct ad9361_rf_phy *phy) +{ + struct spi_desc *spi = phy->spi; + uint32_t clkrf; + uint32_t reg, delay_lna, settling_delay, dec_pow_meas_dur; + int32_t ret; + uint32_t fir_div; + + clkrf = clk_get_rate(phy, phy->ref_clk_scale[CLKRF_CLK]); + delay_lna = phy->pdata->elna_ctrl.settling_delay_ns; + + /* + * AGC Attack Delay (us)=ceiling((((0.2+Delay_LNA)*ClkRF+14))/(2*ClkRF))+1 + * ClkRF in MHz, delay in us + */ + + reg = (200 + delay_lna) / 2 + (14000000UL / (clkrf / 500U)); + reg = DIV_ROUND_UP(reg, 1000UL) + + phy->pdata->gain_ctrl.agc_attack_delay_extra_margin_us; + reg = clamp_t(uint8_t, reg, 0U, 31U); + ret = ad9361_spi_writef(spi, REG_AGC_ATTACK_DELAY, + AGC_ATTACK_DELAY(~0), reg); + + /* + * Peak Overload Wait Time (ClkRF cycles)=ceiling((0.1+Delay_LNA) *clkRF+1) + */ + + reg = (delay_lna + 100UL) * (clkrf / 1000UL); + reg = DIV_ROUND_UP(reg, 1000000UL) + 1; + reg = clamp_t(uint8_t, reg, 0U, 31U); + ret |= ad9361_spi_writef(spi, REG_PEAK_WAIT_TIME, + PEAK_OVERLOAD_WAIT_TIME(~0), reg); + + /* + * Settling Delay in 0x111. Applies to all gain control modes: + * 0x111[D4:D0]= ceiling(((0.2+Delay_LNA)*clkRF + dodebug = false;+14)/2) + */ + + reg = (delay_lna + 200UL) * (clkrf / 2000UL); + reg = DIV_ROUND_UP(reg, 1000000UL) + 7; + reg = settling_delay = clamp_t(uint8_t, reg, 0U, 31U); + ret |= ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, + SETTLING_DELAY(~0), reg); + + /* + * Gain Update Counter [15:0]= round((((time*ClkRF-0x111[D4:D0]*2)-2))/2) + */ + reg = phy->pdata->gain_ctrl.gain_update_interval_us * (clkrf / 1000UL) - + settling_delay * 2000UL - 2000UL; + + reg = DIV_ROUND_CLOSEST(reg, 2000UL); + reg = clamp_t(uint32_t, reg, 0U, 131071UL); + + if (phy->agc_mode[0] == RF_GAIN_FASTATTACK_AGC || + phy->agc_mode[1] == RF_GAIN_FASTATTACK_AGC) { + dec_pow_meas_dur = + phy->pdata->gain_ctrl.f_agc_dec_pow_measuremnt_duration; + } else { + fir_div = DIV_ROUND_CLOSEST(clkrf, + clk_get_rate(phy, phy->ref_clk_scale[RX_SAMPL_CLK])); + dec_pow_meas_dur = phy->pdata->gain_ctrl.dec_pow_measuremnt_duration; + + if (((reg * 2 / fir_div) / dec_pow_meas_dur) < 2) { + dec_pow_meas_dur = reg / fir_div; + } + } + + /* Power Measurement Duration */ + ad9361_spi_writef(spi, REG_DEC_POWER_MEASURE_DURATION_0, + DEC_POWER_MEASUREMENT_DURATION(~0), + ilog2(dec_pow_meas_dur / 16)); + + + ret |= ad9361_spi_writef(spi, REG_DIGITAL_SAT_COUNTER, + DOUBLE_GAIN_COUNTER, reg > 65535); + + if (reg > 65535) + reg /= 2; + + ret |= ad9361_spi_write(spi, REG_GAIN_UPDATE_COUNTER1, reg & 0xFF); + ret |= ad9361_spi_write(spi, REG_GAIN_UPDATE_COUNTER2, reg >> 8); + + /* + * Fast AGC State Wait Time - Energy Detect Count + */ + + reg = DIV_ROUND_CLOSEST(phy->pdata->gain_ctrl.f_agc_state_wait_time_ns * + (clkrf / 1000UL), 1000000UL); + reg = clamp_t(uint32_t, reg, 0U, 31U); + ret |= ad9361_spi_writef(spi, REG_FAST_ENERGY_DETECT_COUNT, + ENERGY_DETECT_COUNT(~0), reg); + + return ret; +} + +/** + * Set the gain control mode. + * @param phy The AD9361 state structure. + * @param gain_ctrl A rf_gain_ctrl struct that contains the the desired + * channel information and the gain control mode. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy, + struct rf_gain_ctrl *gain_ctrl) +{ + struct spi_desc *spi = phy->spi; + int32_t rc = 0; + uint32_t gain_ctl_shift, mode; + uint8_t val; + + rc = ad9361_spi_readm(spi, REG_AGC_CONFIG_1, &val, 1); + if (rc) { + dev_err(dev, "Unable to read AGC config1 register: %x", + REG_AGC_CONFIG_1); + goto out; + } + + switch (gain_ctrl->mode) { + case RF_GAIN_MGC: + mode = RX_GAIN_CTL_MGC; + break; + case RF_GAIN_FASTATTACK_AGC: + mode = RX_GAIN_CTL_AGC_FAST_ATK; + break; + case RF_GAIN_SLOWATTACK_AGC: + mode = RX_GAIN_CTL_AGC_SLOW_ATK; + break; + case RF_GAIN_HYBRID_AGC: + mode = RX_GAIN_CTL_AGC_SLOW_ATK_HYBD; + break; + default: + rc = -EINVAL; + goto out; + } + + if (gain_ctrl->ant == 1) { + gain_ctl_shift = RX1_GAIN_CTRL_SHIFT; + } else if (gain_ctrl->ant == 2) { + gain_ctl_shift = RX2_GAIN_CTRL_SHIFT; + } else { + dev_err(dev, "Unknown Rx path %"PRIu32, gain_ctrl->ant); + rc = -EINVAL; + goto out; + } + + rc = ad9361_en_dis_rx(phy, gain_ctrl->ant, RX_DISABLE); + if (rc) { + dev_err(dev, "Unable to disable rx%"PRIu32, gain_ctrl->ant); + goto out; + } + + val &= ~(RX_GAIN_CTL_MASK << gain_ctl_shift); + val |= mode << gain_ctl_shift; + if (mode == RX_GAIN_CTL_AGC_SLOW_ATK_HYBD) + val |= SLOW_ATTACK_HYBRID_MODE; + else + val &= ~SLOW_ATTACK_HYBRID_MODE; + + rc = ad9361_spi_write(spi, REG_AGC_CONFIG_1, val); + if (rc) { + dev_err(dev, "Unable to write AGC config1 register: %x", + REG_AGC_CONFIG_1); + goto out; + } + + ad9361_en_dis_rx(phy, gain_ctrl->ant, RX_ENABLE); + rc = ad9361_gc_update(phy); +out: + return rc; +} + +/** + * Get the RSSI. + * @param phy The AD9361 state structure. + * @param rssi A rf_rssi struct to store the RSSI. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi) +{ + struct spi_desc *spi = phy->spi; + uint8_t reg_val_buf[6]; + int32_t rc; + + rc = ad9361_spi_readm(spi, REG_PREAMBLE_LSB, + reg_val_buf, ARRAY_SIZE(reg_val_buf)); + if (rssi->ant == 1) { + rssi->symbol = RSSI_RESOLUTION * + ((reg_val_buf[5] << RSSI_LSB_SHIFT) + + (reg_val_buf[1] & RSSI_LSB_MASK1)); + rssi->preamble = RSSI_RESOLUTION * + ((reg_val_buf[4] << RSSI_LSB_SHIFT) + + (reg_val_buf[0] & RSSI_LSB_MASK1)); + } else if (rssi->ant == 2) { + rssi->symbol = RSSI_RESOLUTION * + ((reg_val_buf[3] << RSSI_LSB_SHIFT) + + ((reg_val_buf[1] & RSSI_LSB_MASK2) >> 1)); + rssi->preamble = RSSI_RESOLUTION * + ((reg_val_buf[2] << RSSI_LSB_SHIFT) + + ((reg_val_buf[0] & RSSI_LSB_MASK2) >> 1)); + } else + rc = -EFAULT; + + rssi->multiplier = RSSI_MULTIPLIER; + + return rc; +} + +/** + * Setup the RX ADC. + * @param phy The AD9361 state structure. + * @param bbpll_freq The BBPLL frequency [Hz]. + * @param adc_sampl_freq_Hz The ADC sampling frequency [Hz]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_rx_adc_setup(struct ad9361_rf_phy *phy, + uint32_t bbpll_freq, + uint32_t adc_sampl_freq_Hz) +{ + + uint32_t scale_snr_1e3, maxsnr, sqrt_inv_rc_tconst_1e3, tmp_1e3, + scaled_adc_clk_1e6, inv_scaled_adc_clk_1e3, sqrt_term_1e3, + min_sqrt_term_1e3, bb_bw_Hz; + uint64_t tmp, invrc_tconst_1e6; + uint8_t data[40]; + uint32_t i; + int32_t ret; + + uint8_t c3_msb = ad9361_spi_read(phy->spi, REG_RX_BBF_C3_MSB); + uint8_t c3_lsb = ad9361_spi_read(phy->spi, REG_RX_BBF_C3_LSB); + uint8_t r2346 = ad9361_spi_read(phy->spi, REG_RX_BBF_R2346); + + /* + * BBBW = (BBPLL / RxTuneDiv) * ln(2) / (1.4 * 2PI ) + * We assume ad9361_rx_bb_analog_filter_calib() is always run prior + */ + + tmp = bbpll_freq * 10000ULL; + do_div(&tmp, 126906UL * phy->rxbbf_div); + bb_bw_Hz = tmp; + + dev_dbg(&phy->spi->dev, "%s : BBBW %"PRIu32" : ADCfreq %"PRIu32, + __func__, bb_bw_Hz, adc_sampl_freq_Hz); + + dev_dbg(&phy->spi->dev, "c3_msb 0x%X : c3_lsb 0x%X : r2346 0x%X : ", + c3_msb, c3_lsb, r2346); + + bb_bw_Hz = clamp(bb_bw_Hz, 200000UL, 28000000UL); + + if (adc_sampl_freq_Hz < 80000000) + scale_snr_1e3 = 1000; + else + scale_snr_1e3 = 1585; /* pow(10, scale_snr_dB/10); */ + + if (bb_bw_Hz >= 18000000) { + invrc_tconst_1e6 = (160975ULL * r2346 * + (160 * c3_msb + 10 * c3_lsb + 140) * + (bb_bw_Hz)* (1000 + (10 * (bb_bw_Hz - 18000000) / 1000000))); + + do_div(&invrc_tconst_1e6, 1000UL); + + } else { + invrc_tconst_1e6 = (160975ULL * r2346 * + (160 * c3_msb + 10 * c3_lsb + 140) * + (bb_bw_Hz)); + } + + do_div(&invrc_tconst_1e6, 1000000000UL); + + if (invrc_tconst_1e6 > ULONG_MAX) + dev_err(&phy->spi->dev, "invrc_tconst_1e6 > ULONG_MAX"); + + sqrt_inv_rc_tconst_1e3 = int_sqrt((uint32_t)invrc_tconst_1e6); + maxsnr = 640 / 160; + scaled_adc_clk_1e6 = DIV_ROUND_CLOSEST(adc_sampl_freq_Hz, 640); + inv_scaled_adc_clk_1e3 = DIV_ROUND_CLOSEST(640000000, + DIV_ROUND_CLOSEST(adc_sampl_freq_Hz, 1000)); + tmp_1e3 = DIV_ROUND_CLOSEST(980000 + 20 * max_t(uint32_t, 1000U, + DIV_ROUND_CLOSEST(inv_scaled_adc_clk_1e3, maxsnr)), 1000); + sqrt_term_1e3 = int_sqrt(scaled_adc_clk_1e6); + min_sqrt_term_1e3 = min_t(uint32_t, 1000U, + int_sqrt(maxsnr * scaled_adc_clk_1e6)); + + dev_dbg(&phy->spi->dev, + "invrc_tconst_1e6 %"PRIu64", sqrt_inv_rc_tconst_1e3 %"PRIu32, + invrc_tconst_1e6, sqrt_inv_rc_tconst_1e3); + dev_dbg(&phy->spi->dev, + "scaled_adc_clk_1e6 %"PRIu32", inv_scaled_adc_clk_1e3 %"PRIu32, + scaled_adc_clk_1e6, inv_scaled_adc_clk_1e3); + dev_dbg(&phy->spi->dev, + "tmp_1e3 %"PRIu32", sqrt_term_1e3 %"PRIu32", min_sqrt_term_1e3 %"PRIu32, + tmp_1e3, sqrt_term_1e3, min_sqrt_term_1e3); + + data[0] = 0; + data[1] = 0; + data[2] = 0; + data[3] = 0x24; + data[4] = 0x24; + data[5] = 0; + data[6] = 0; + + tmp = -50000000 + 8ULL * scale_snr_1e3 * sqrt_inv_rc_tconst_1e3 * + min_sqrt_term_1e3; + do_div(&tmp, 100000000UL); + data[7] = min_t(uint64_t, 124U, tmp); + + tmp = (invrc_tconst_1e6 >> 1) + 20 * inv_scaled_adc_clk_1e3 * + data[7] / 80 * 1000ULL; + do_div(&tmp, invrc_tconst_1e6); + data[8] = min_t(uint64_t, 255U, tmp); + + tmp = (-500000 + 77ULL * sqrt_inv_rc_tconst_1e3 * min_sqrt_term_1e3); + do_div(&tmp, 1000000UL); + data[10] = min_t(uint64_t, 127U, tmp); + + data[9] = min_t(uint32_t, 127U, ((800 * data[10]) / 1000)); + tmp = ((invrc_tconst_1e6 >> 1) + (20 * inv_scaled_adc_clk_1e3 * + data[10] * 1000ULL)); + do_div(&tmp, invrc_tconst_1e6 * 77); + data[11] = min_t(uint64_t, 255U, tmp); + data[12] = min_t(uint32_t, 127U, (-500000 + 80 * sqrt_inv_rc_tconst_1e3 * + min_sqrt_term_1e3) / 1000000UL); + + tmp = -3 * (long)(invrc_tconst_1e6 >> 1) + inv_scaled_adc_clk_1e3 * + data[12] * (1000ULL * 20 / 80); + do_div(&tmp, invrc_tconst_1e6); + data[13] = min_t(uint64_t, 255, tmp); + + data[14] = 21 * (inv_scaled_adc_clk_1e3 / 10000); + data[15] = min_t(uint32_t, 127U, (500 + 1025 * data[7]) / 1000); + data[16] = min_t(uint32_t, 127U, (data[15] * tmp_1e3) / 1000); + data[17] = data[15]; + data[18] = min_t(uint32_t, 127U, (500 + 975 * data[10]) / 1000); + data[19] = min_t(uint32_t, 127U, (data[18] * tmp_1e3) / 1000); + data[20] = data[18]; + data[21] = min_t(uint32_t, 127U, (500 + 975 * data[12]) / 1000); + data[22] = min_t(uint32_t, 127, (data[21] * tmp_1e3) / 1000); + data[23] = data[21]; + data[24] = 0x2E; + data[25] = (128 + min_t(uint32_t, 63000U, DIV_ROUND_CLOSEST(63 * + scaled_adc_clk_1e6, 1000)) / 1000); + data[26] = min_t(uint32_t, 63U, 63 * scaled_adc_clk_1e6 / 1000000 * + (920 + 80 * inv_scaled_adc_clk_1e3 / 1000) / 1000); + data[27] = min_t(uint32_t, 63, (32 * sqrt_term_1e3) / 1000); + data[28] = data[25]; + data[29] = data[26]; + data[30] = data[27]; + data[31] = data[25]; + data[32] = data[26]; + data[33] = min_t(uint32_t, 63U, 63 * sqrt_term_1e3 / 1000); + data[34] = min_t(uint32_t, 127U, 64 * sqrt_term_1e3 / 1000); + data[35] = 0x40; + data[36] = 0x40; + data[37] = 0x2C; + data[38] = 0x00; + data[39] = 0x00; + + for (i = 0; i < 40; i++) { + ret = ad9361_spi_write(phy->spi, 0x200 + i, data[i]); + if (ret < 0) + return ret; + } + + return 0; +} + +/** + * Perform a RX TIA calibration. + * @param phy The AD9361 state structure. + * @param bb_bw_Hz The baseband bandwidth [Hz]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_rx_tia_calib(struct ad9361_rf_phy *phy, uint32_t bb_bw_Hz) +{ + uint32_t Cbbf, R2346; + uint64_t CTIA_fF; + + uint8_t reg1EB = ad9361_spi_read(phy->spi, REG_RX_BBF_C3_MSB); + uint8_t reg1EC = ad9361_spi_read(phy->spi, REG_RX_BBF_C3_LSB); + uint8_t reg1E6 = ad9361_spi_read(phy->spi, REG_RX_BBF_R2346); + uint8_t reg1DB, reg1DF, reg1DD, reg1DC, reg1DE, temp; + + dev_dbg(&phy->spi->dev, "%s : bb_bw_Hz %"PRIu32, + __func__, bb_bw_Hz); + + bb_bw_Hz = clamp(bb_bw_Hz, 200000UL, 20000000UL); + + Cbbf = (reg1EB * 160) + (reg1EC * 10) + 140; /* fF */ + R2346 = 18300 * RX_BBF_R2346(reg1E6); + + CTIA_fF = Cbbf * R2346 * 560ULL; + do_div(&CTIA_fF, 3500000UL); + + if (bb_bw_Hz <= 3000000UL) + reg1DB = 0xE0; + else if (bb_bw_Hz <= 10000000UL) + reg1DB = 0x60; + else + reg1DB = 0x20; + + if (CTIA_fF > 2920ULL) { + reg1DC = 0x40; + reg1DE = 0x40; + temp = min(127U, DIV_ROUND_CLOSEST((uint32_t)CTIA_fF - 400, 320U)); + reg1DD = temp; + reg1DF = temp; + } else { + temp = DIV_ROUND_CLOSEST((uint32_t)CTIA_fF - 400, 40U) + 0x40; + reg1DC = temp; + reg1DE = temp; + reg1DD = 0; + reg1DF = 0; + } + + ad9361_spi_write(phy->spi, REG_RX_TIA_CONFIG, reg1DB); + ad9361_spi_write(phy->spi, REG_TIA1_C_LSB, reg1DC); + ad9361_spi_write(phy->spi, REG_TIA1_C_MSB, reg1DD); + ad9361_spi_write(phy->spi, REG_TIA2_C_LSB, reg1DE); + ad9361_spi_write(phy->spi, REG_TIA2_C_MSB, reg1DF); + + return 0; +} + +/** + * Perform a baseband RX analog filter calibration. + * @param phy The AD9361 state structure. + * @param rx_bb_bw The baseband bandwidth [Hz]. + * @param bbpll_freq The BBPLL frequency [Hz]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_rx_bb_analog_filter_calib(struct ad9361_rf_phy *phy, + uint32_t rx_bb_bw, + uint32_t bbpll_freq) +{ + uint32_t target; + uint8_t tmp; + int32_t ret; + + dev_dbg(&phy->spi->dev, "%s : rx_bb_bw %"PRIu32" bbpll_freq %"PRIu32, + __func__, rx_bb_bw, bbpll_freq); + + rx_bb_bw = clamp(rx_bb_bw, 200000UL, 28000000UL); + + /* 1.4 * BBBW * 2PI / ln(2) */ + target = 126906UL * (rx_bb_bw / 10000UL); + phy->rxbbf_div = min_t(uint32_t, 511UL, DIV_ROUND_UP(bbpll_freq, target)); + + /* Set RX baseband filter divide value */ + ad9361_spi_write(phy->spi, REG_RX_BBF_TUNE_DIVIDE, phy->rxbbf_div); + ad9361_spi_writef(phy->spi, REG_RX_BBF_TUNE_CONFIG, BIT(0), + phy->rxbbf_div >> 8); + + /* Write the BBBW into registers 0x1FB and 0x1FC */ + ad9361_spi_write(phy->spi, REG_RX_BBBW_MHZ, rx_bb_bw / 1000000UL); + + tmp = DIV_ROUND_CLOSEST((rx_bb_bw % 1000000UL) * 128, 1000000UL); + ad9361_spi_write(phy->spi, REG_RX_BBBW_KHZ, min_t(uint8_t, 127, tmp)); + + ad9361_spi_write(phy->spi, REG_RX_MIX_LO_CM, + RX_MIX_LO_CM(0x3F)); /* Set Rx Mix LO CM */ + ad9361_spi_write(phy->spi, REG_RX_MIX_GM_CONFIG, + RX_MIX_GM_PLOAD(3)); /* Set GM common mode */ + + /* Enable the RX BBF tune circuit by writing 0x1E2=0x02 and 0x1E3=0x02 */ + ad9361_spi_write(phy->spi, REG_RX1_TUNE_CTRL, RX1_TUNE_RESAMPLE); + ad9361_spi_write(phy->spi, REG_RX2_TUNE_CTRL, RX2_TUNE_RESAMPLE); + + /* Start the RX Baseband Filter calibration in register 0x016[7] */ + /* Calibration is complete when register 0x016[7] self clears */ + ret = ad9361_run_calibration(phy, RX_BB_TUNE_CAL); + + /* Disable the RX baseband filter tune circuit, write 0x1E2=3, 0x1E3=3 */ + ad9361_spi_write(phy->spi, REG_RX1_TUNE_CTRL, + RX1_TUNE_RESAMPLE | RX1_PD_TUNE); + ad9361_spi_write(phy->spi, REG_RX2_TUNE_CTRL, + RX2_TUNE_RESAMPLE | RX2_PD_TUNE); + + return ret; +} + +/** + * Perform a baseband TX analog filter calibration. + * @param phy The AD9361 state structure. + * @param tx_bb_bw The baseband bandwidth [Hz]. + * @param bbpll_freq The BBPLL frequency [Hz]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_tx_bb_analog_filter_calib(struct ad9361_rf_phy *phy, + uint32_t tx_bb_bw, + uint32_t bbpll_freq) +{ + uint32_t target, txbbf_div; + int32_t ret; + + dev_dbg(&phy->spi->dev, "%s : tx_bb_bw %"PRIu32" bbpll_freq %"PRIu32, + __func__, tx_bb_bw, bbpll_freq); + + tx_bb_bw = clamp(tx_bb_bw, 625000UL, 20000000UL); + + /* 1.6 * BBBW * 2PI / ln(2) */ + target = 145036 * (tx_bb_bw / 10000UL); + txbbf_div = min_t(uint32_t, 511UL, DIV_ROUND_UP(bbpll_freq, target)); + + /* Set TX baseband filter divide value */ + ad9361_spi_write(phy->spi, REG_TX_BBF_TUNE_DIVIDER, txbbf_div); + ad9361_spi_writef(phy->spi, REG_TX_BBF_TUNE_MODE, + TX_BBF_TUNE_DIVIDER, txbbf_div >> 8); + + /* Enable the TX baseband filter tune circuit by setting 0x0CA=0x22. */ + ad9361_spi_write(phy->spi, REG_TX_TUNE_CTRL, TUNER_RESAMPLE | TUNE_CTRL(1)); + + /* Start the TX Baseband Filter calibration in register 0x016[6] */ + /* Calibration is complete when register 0x016[] self clears */ + ret = ad9361_run_calibration(phy, TX_BB_TUNE_CAL); + + /* Disable the TX baseband filter tune circuit by writing 0x0CA=0x26. */ + ad9361_spi_write(phy->spi, REG_TX_TUNE_CTRL, + TUNER_RESAMPLE | TUNE_CTRL(1) | PD_TUNE); + + return ret; +} + +/** + * Perform a baseband TX secondary filter calibration. + * @param phy The AD9361 state structure. + * @param tx_rf_bw The RF bandwidth [Hz]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_tx_bb_second_filter_calib(struct ad9361_rf_phy *phy, + uint32_t tx_bb_bw) +{ + uint64_t cap; + uint32_t corner, res, div; + uint32_t reg_conf, reg_res; + int32_t ret, i; + + dev_dbg(&phy->spi->dev, "%s : tx_bb_bw %"PRIu32, + __func__, tx_bb_bw); + + tx_bb_bw = clamp(tx_bb_bw, 530000UL, 20000000UL); + + /* BBBW * 5PI */ + corner = 15708 * (tx_bb_bw / 10000UL); + + for (i = 0, res = 1; i < 4; i++) { + div = corner * res; + cap = (500000000ULL) + (div >> 1); + do_div(&cap, div); + cap -= 12ULL; + if (cap < 64ULL) + break; + + res <<= 1; + } + + if (cap > 63ULL) + cap = 63ULL; + + if (tx_bb_bw <= 4500000UL) + reg_conf = 0x59; + else if (tx_bb_bw <= 12000000UL) + reg_conf = 0x56; + else + reg_conf = 0x57; + + switch (res) { + case 1: + reg_res = 0x0C; + break; + case 2: + reg_res = 0x04; + break; + case 4: + reg_res = 0x03; + break; + case 8: + reg_res = 0x01; + break; + default: + reg_res = 0x01; + } + + ret = ad9361_spi_write(phy->spi, REG_CONFIG0, reg_conf); + ret |= ad9361_spi_write(phy->spi, REG_RESISTOR, reg_res); + ret |= ad9361_spi_write(phy->spi, REG_CAPACITOR, (uint8_t)cap); + + return ret; +} + +/** + * Perform a RF synthesizer charge pump calibration. + * @param phy The AD9361 state structure. + * @param ref_clk_hz The reference clock rate [Hz]. + * @param tx The Synthesizer TX = 1, RX = 0. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_txrx_synth_cp_calib(struct ad9361_rf_phy *phy, + uint32_t ref_clk_hz, bool tx) +{ + uint32_t offs = tx ? 0x40 : 0; + uint32_t vco_cal_cnt; + dev_dbg(&phy->spi->dev, "%s : ref_clk_hz %"PRIu32" : is_tx %d", + __func__, ref_clk_hz, tx); + + /* REVIST: */ + ad9361_spi_write(phy->spi, REG_RX_CP_LEVEL_DETECT + offs, 0x17); + + ad9361_spi_write(phy->spi, REG_RX_DSM_SETUP_1 + offs, 0x0); + + ad9361_spi_write(phy->spi, REG_RX_LO_GEN_POWER_MODE + offs, 0x00); + ad9361_spi_write(phy->spi, REG_RX_VCO_LDO + offs, 0x0B); + ad9361_spi_write(phy->spi, REG_RX_VCO_PD_OVERRIDES + offs, 0x02); + ad9361_spi_write(phy->spi, REG_RX_CP_CURRENT + offs, 0x80); + ad9361_spi_write(phy->spi, REG_RX_CP_CONFIG + offs, CP_OFFSET_OFF); + + /* see Table 70 Example Calibration Times for RF VCO Cal */ + if (phy->pdata->fdd) { + vco_cal_cnt = VCO_CAL_EN | VCO_CAL_COUNT(3) | FB_CLOCK_ADV(2); + } else { + if (ref_clk_hz > 40000000UL) + vco_cal_cnt = VCO_CAL_EN | VCO_CAL_COUNT(1) | + FB_CLOCK_ADV(2); + else + vco_cal_cnt = VCO_CAL_EN | VCO_CAL_COUNT(0) | + FB_CLOCK_ADV(2); + } + + ad9361_spi_write(phy->spi, REG_RX_VCO_CAL + offs, vco_cal_cnt); + + /* Enable FDD mode during calibrations */ + + if (!phy->pdata->fdd) { + ad9361_spi_writef(phy->spi, REG_PARALLEL_PORT_CONF_3, + HALF_DUPLEX_MODE, 0); + } + + ad9361_spi_write(phy->spi, REG_ENSM_CONFIG_2, DUAL_SYNTH_MODE); + ad9361_spi_write(phy->spi, REG_ENSM_CONFIG_1, + FORCE_ALERT_STATE | + TO_ALERT); + ad9361_spi_write(phy->spi, REG_ENSM_MODE, FDD_MODE); + + ad9361_spi_write(phy->spi, REG_RX_CP_CONFIG + offs, + CP_OFFSET_OFF | CP_CAL_ENABLE); + + return ad9361_check_cal_done(phy, REG_RX_CAL_STATUS + offs, + CP_CAL_VALID, 1); +} + +/** + * Perform a baseband DC offset calibration. + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_bb_dc_offset_calib(struct ad9361_rf_phy *phy) +{ + dev_dbg(&phy->spi->dev, "%s", __func__); + + ad9361_spi_write(phy->spi, REG_BB_DC_OFFSET_COUNT, 0x3F); + ad9361_spi_write(phy->spi, REG_BB_DC_OFFSET_SHIFT, BB_DC_M_SHIFT(0xF)); + ad9361_spi_write(phy->spi, REG_BB_DC_OFFSET_ATTEN, BB_DC_OFFSET_ATTEN(1)); + + return ad9361_run_calibration(phy, BBDC_CAL); +} + +/** + * Perform a RF DC offset calibration. + * @param phy The AD9361 state structure. + * @param ref_clk_hz The RX LO frequency [Hz]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_rf_dc_offset_calib(struct ad9361_rf_phy *phy, + uint64_t rx_freq) +{ + struct spi_desc *spi = phy->spi; + + dev_dbg(&phy->spi->dev, "%s : rx_freq %"PRIu64, + __func__, rx_freq); + + ad9361_spi_write(spi, REG_WAIT_COUNT, 0x20); + + if (rx_freq <= 4000000000ULL) { + ad9361_spi_write(spi, REG_RF_DC_OFFSET_COUNT, + phy->pdata->rf_dc_offset_count_low); + ad9361_spi_write(spi, REG_RF_DC_OFFSET_CONFIG_1, + RF_DC_CALIBRATION_COUNT(4) | DAC_FS(2)); + ad9361_spi_write(spi, REG_RF_DC_OFFSET_ATTEN, + RF_DC_OFFSET_ATTEN( + phy->pdata->dc_offset_attenuation_low)); + } else { + ad9361_spi_write(spi, REG_RF_DC_OFFSET_COUNT, + phy->pdata->rf_dc_offset_count_high); + ad9361_spi_write(spi, REG_RF_DC_OFFSET_CONFIG_1, + RF_DC_CALIBRATION_COUNT(4) | DAC_FS(3)); + ad9361_spi_write(spi, REG_RF_DC_OFFSET_ATTEN, + RF_DC_OFFSET_ATTEN( + phy->pdata->dc_offset_attenuation_high)); + } + + ad9361_spi_write(spi, REG_DC_OFFSET_CONFIG2, + USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL | + DC_OFFSET_UPDATE(3)); + + if (phy->pdata->rx1rx2_phase_inversion_en || + (phy->pdata->port_ctrl.pp_conf[1] & INVERT_RX2)) { + ad9361_spi_write(spi, REG_INVERT_BITS, + INVERT_RX1_RF_DC_CGOUT_WORD); + } else { + ad9361_spi_write(spi, REG_INVERT_BITS, + INVERT_RX1_RF_DC_CGOUT_WORD | + INVERT_RX2_RF_DC_CGOUT_WORD); + } + + return ad9361_run_calibration(phy, RFDC_CAL); +} + +/** + * Update RF bandwidth. + * @param phy The AD9361 state structure. + * @param rf_rx_bw RF RX bandwidth [Hz]. + * @param rf_tx_bw RF TX bandwidth [Hz]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t __ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, + uint32_t rf_rx_bw, uint32_t rf_tx_bw) +{ + uint32_t real_rx_bandwidth = rf_rx_bw / 2; + uint32_t real_tx_bandwidth = rf_tx_bw / 2; + uint32_t bbpll_freq; + int32_t ret; + + dev_dbg(&phy->spi->dev, "%s: %"PRIu32" %"PRIu32, + __func__, rf_rx_bw, rf_tx_bw); + + bbpll_freq = clk_get_rate(phy, phy->ref_clk_scale[BBPLL_CLK]); + + ret = ad9361_rx_bb_analog_filter_calib(phy, + real_rx_bandwidth, + bbpll_freq); + if (ret < 0) + return ret; + + ret = ad9361_tx_bb_analog_filter_calib(phy, + real_tx_bandwidth, + bbpll_freq); + if (ret < 0) + return ret; + + ret = ad9361_rx_tia_calib(phy, real_rx_bandwidth); + if (ret < 0) + return ret; + + ret = ad9361_tx_bb_second_filter_calib(phy, real_tx_bandwidth); + if (ret < 0) + return ret; + + ret = ad9361_rx_adc_setup(phy, + bbpll_freq, + clk_get_rate(phy, phy->ref_clk_scale[ADC_CLK])); + if (ret < 0) + return ret; + + return 0; +} + +/** + * TX Quad Calib. + * @param phy The AD9361 state structure. + * @param phase phase + * @param rxnco_word Rx NCO word. + * @param decim decim + * @param res res + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t __ad9361_tx_quad_calib(struct ad9361_rf_phy *phy, uint32_t phase, + uint32_t rxnco_word, uint32_t decim, uint8_t *res) +{ + int32_t ret; + + ad9361_spi_write(phy->spi, REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET, + RX_NCO_FREQ(rxnco_word) | RX_NCO_PHASE_OFFSET(phase)); + ad9361_spi_write(phy->spi, REG_QUAD_CAL_CTRL, + SETTLE_MAIN_ENABLE | DC_OFFSET_ENABLE | QUAD_CAL_SOFT_RESET | + GAIN_ENABLE | PHASE_ENABLE | M_DECIM(decim)); + ad9361_spi_write(phy->spi, REG_QUAD_CAL_CTRL, + SETTLE_MAIN_ENABLE | DC_OFFSET_ENABLE | + GAIN_ENABLE | PHASE_ENABLE | M_DECIM(decim)); + + ret = ad9361_run_calibration(phy, TX_QUAD_CAL); + if (ret < 0) + return ret; + + if (res) { + *res = ad9361_spi_read(phy->spi, + (phy->pdata->rx1tx1_mode_use_tx_num == 2) ? + REG_QUAD_CAL_STATUS_TX2 : REG_QUAD_CAL_STATUS_TX1) & + (TX1_LO_CONV | TX1_SSB_CONV); + if (phy->pdata->rx2tx2) + *res &= ad9361_spi_read(phy->spi, REG_QUAD_CAL_STATUS_TX2) & + (TX2_LO_CONV | TX2_SSB_CONV); + } + + return 0; +} + +/** + * Loop through all possible phase offsets in case the QUAD CAL doesn't converge. + * @param phy The AD9361 state structure. + * @param rxnco_word Rx NCO word. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_tx_quad_phase_search(struct ad9361_rf_phy *phy, + uint32_t rxnco_word, uint8_t decim) +{ + int32_t i, ret; + uint8_t field[64], val; + uint32_t start; + + dev_dbg(&phy->spi->dev, "%s", __func__); + + for (i = 0; i < (int64_t)(ARRAY_SIZE(field) / 2); i++) { + ret = __ad9361_tx_quad_calib(phy, i, rxnco_word, decim, &val); + if (ret < 0) + return ret; + + /* Handle 360/0 wrap around */ + field[i] = field[i + 32] = !((val & TX1_LO_CONV) && (val & TX1_SSB_CONV)); + } + + ret = ad9361_find_opt(field, ARRAY_SIZE(field), &start); + + phy->last_tx_quad_cal_phase = (start + ret / 2) & 0x1F; + +#ifdef _DEBUG + for (i = 0; i < 64; i++) { + printk("%c", (field[i] ? '#' : 'o')); + } +#ifdef WIN32 + printk(" RX_NCO_PHASE_OFFSET(%d, 0x%X) \n", phy->last_tx_quad_cal_phase, + phy->last_tx_quad_cal_phase); +#else + printk(" RX_NCO_PHASE_OFFSET(%"PRIu32", 0x%"PRIX32") \n", + phy->last_tx_quad_cal_phase, + phy->last_tx_quad_cal_phase); +#endif +#endif + + ret = __ad9361_tx_quad_calib(phy, phy->last_tx_quad_cal_phase, rxnco_word, + decim, NULL); + if (ret < 0) + return ret; + + return 0; +} + +/** + * Perform a TX quadrature calibration. + * @param phy The AD9361 state structure. + * @param bw The bandwidth [Hz]. + * @param rx_phase The optional RX phase value overwrite (set to zero). + * @return 0 in case of success, negative error code otherwise. + */ + +static int ad9361_tx_quad_calib(struct ad9361_rf_phy *phy, + uint32_t bw_rx, uint32_t bw_tx, + int32_t rx_phase) +{ + struct spi_desc *spi = phy->spi; + uint32_t clktf, clkrf; + int32_t txnco_word, rxnco_word, txnco_freq, ret; + uint8_t __rx_phase = 0, reg_inv_bits = 0, val, decim; + bool phase_inversion_en; + + ret = 0; + if (phy->cached_synth_pd[0] & TX_LO_POWER_DOWN) { + if (phy->pdata->lo_powerdown_managed_en) { + ad9361_spi_writef(spi, REG_TX_SYNTH_POWER_DOWN_OVERRIDE, + TX_LO_POWER_DOWN, 0); + } else { + dev_err(dev, + "%s : Tx QUAD Cal abort due to TX LO in powerdown\n", + __func__); + return -EFAULT; + } + } + /* + * Find NCO frequency that matches this equation: + * BW / 4 = Rx NCO freq = Tx NCO freq: + * Rx NCO = ClkRF * (rxNCO <1:0> + 1) / 32 + * Tx NCO = ClkTF * (txNCO <1:0> + 1) / 32 + */ + + clkrf = clk_get_rate(phy, phy->ref_clk_scale[CLKRF_CLK]); + clktf = clk_get_rate(phy, phy->ref_clk_scale[CLKTF_CLK]); + + dev_dbg(&phy->spi->dev, "%s : bw_tx %"PRIu32" clkrf %"PRIu32" clktf %"PRIu32, + __func__, bw_tx, clkrf, clktf); + + txnco_word = DIV_ROUND_CLOSEST(bw_tx * 8, clktf) - 1; + txnco_word = clamp_t(int, txnco_word, 0, 3); + rxnco_word = txnco_word; + + dev_dbg(dev, "Tx NCO frequency: %"PRIu32" (BW/4: %"PRIu32") txnco_word %"PRId32, + clktf * (txnco_word + 1) / 32, bw_tx / 4, txnco_word); + + if (clktf <= 4000000UL) + decim = 2; + else + decim = 3; + + if (clkrf == (2 * clktf)) { + __rx_phase = 0x0E; + switch (txnco_word) { + case 0: + txnco_word++; + break; + case 1: + rxnco_word--; + break; + case 2: + rxnco_word -= 2; + txnco_word--; + break; + case 3: + rxnco_word -= 2; /* REVISIT */ + __rx_phase = 0x08; + break; + } + } else if (clkrf == clktf) { + switch (txnco_word) { + case 0: + case 3: + __rx_phase = 0x15; + break; + case 2: + __rx_phase = 0x1F; + break; + case 1: + if (ad9361_spi_readf(spi, + REG_TX_ENABLE_FILTER_CTRL, 0x3F) == 0x22) + __rx_phase = 0x15; /* REVISIT */ + else + __rx_phase = 0x1A; + break; + } + } else + dev_err(dev, "Unhandled case in %s line %d clkrf %"PRIu32" clktf %"PRIu32, + __func__, __LINE__, clkrf, clktf); + + if (rx_phase >= 0) + __rx_phase = rx_phase; + + txnco_freq = clktf * (txnco_word + 1) / 32; + + if (txnco_freq > (int64_t)(bw_rx / 4) || txnco_freq > (int64_t)(bw_tx / 4)) { + /* Make sure the BW during calibration is wide enough */ + ret = __ad9361_update_rf_bandwidth(phy, txnco_freq * 8, txnco_freq * 8); + if (ret < 0) + goto out_restore; + } + + phase_inversion_en = phy->pdata->rx1rx2_phase_inversion_en || + (phy->pdata->port_ctrl.pp_conf[1] & INVERT_RX2); + + if (phase_inversion_en) { + ad9361_spi_writef(spi, REG_PARALLEL_PORT_CONF_2, INVERT_RX2, 0); + + reg_inv_bits = ad9361_spi_read(spi, REG_INVERT_BITS); + + ad9361_spi_write(spi, REG_INVERT_BITS, + INVERT_RX1_RF_DC_CGOUT_WORD | + INVERT_RX2_RF_DC_CGOUT_WORD); + } + + ad9361_spi_writef(spi, REG_KEXP_2, TX_NCO_FREQ(~0), txnco_word); + ad9361_spi_write(spi, REG_QUAD_CAL_COUNT, 0xFF); + ad9361_spi_write(spi, REG_KEXP_1, KEXP_TX(1) | KEXP_TX_COMP(3) | + KEXP_DC_I(3) | KEXP_DC_Q(3)); + ad9361_spi_write(spi, REG_MAG_FTEST_THRESH, 0x03); + ad9361_spi_write(spi, REG_MAG_FTEST_THRESH_2, 0x03); + + if (phy->tx_quad_lpf_tia_match < 0) /* set in ad9361_load_gt() */ + dev_err(dev, "failed to find suitable LPF TIA value in gain table\n"); + else + ad9361_spi_write(spi, REG_TX_QUAD_FULL_LMT_GAIN, + phy->tx_quad_lpf_tia_match); + + ad9361_spi_write(spi, REG_QUAD_SETTLE_COUNT, 0xF0); + ad9361_spi_write(spi, REG_TX_QUAD_LPF_GAIN, 0x00); + + if (rx_phase != -2) { + ret = __ad9361_tx_quad_calib(phy, __rx_phase, rxnco_word, decim, &val); + + dev_dbg(dev, "LO leakage: %d Quadrature Calibration: %d : rx_phase %d\n", + !!(val & TX1_LO_CONV), !!(val & TX1_SSB_CONV), __rx_phase); + + /* Calibration failed -> try last phase offset */ + if (val != (TX1_LO_CONV | TX1_SSB_CONV)) { + if (phy->last_tx_quad_cal_phase < 31) + ret = __ad9361_tx_quad_calib(phy, phy->last_tx_quad_cal_phase, + rxnco_word, decim, &val); + } else { + phy->last_tx_quad_cal_phase = __rx_phase; + } + } else { + /* force phase search */ + val = 0; + } + /* Calibration failed -> loop through all 32 phase offsets */ + if (val != (TX1_LO_CONV | TX1_SSB_CONV)) + ret = ad9361_tx_quad_phase_search(phy, rxnco_word, decim); + + if (phase_inversion_en) { + ad9361_spi_writef(spi, REG_PARALLEL_PORT_CONF_2, INVERT_RX2, 1); + ad9361_spi_write(spi, REG_INVERT_BITS, reg_inv_bits); + } + + if (txnco_freq > (int64_t)(bw_rx / 4) || txnco_freq > (int64_t)(bw_tx / 4)) { + __ad9361_update_rf_bandwidth(phy, + phy->current_rx_bw_Hz, + phy->current_tx_bw_Hz); + } + +out_restore: + /* Restore synthesizer powerdown configuration */ + if (phy->pdata->lo_powerdown_managed_en && + (phy->cached_synth_pd[0] & TX_LO_POWER_DOWN)) + ad9361_synth_lo_powerdown(phy, LO_DONTCARE, LO_DONTCARE); + + return ret; +} + +/** + * Setup RX tracking calibrations. + * @param phy The AD9361 state structure. + * @param bbdc_track Set true, will enable the BBDC tracking. + * @param rfdc_track Set true, will enable the RFDC tracking. + * @param rxquad_track Set true, will enable the RXQUAD tracking. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track, + bool rfdc_track, bool rxquad_track) +{ + struct spi_desc *spi = phy->spi; + uint32_t qtrack = 0; + + dev_dbg(&spi->dev, "%s : bbdc_track=%d, rfdc_track=%d, rxquad_track=%d", + __func__, bbdc_track, rfdc_track, rxquad_track); + + ad9361_spi_write(spi, REG_CALIBRATION_CONFIG_2, + CALIBRATION_CONFIG2_DFLT | K_EXP_PHASE(0x15)); + ad9361_spi_write(spi, REG_CALIBRATION_CONFIG_3, + PREVENT_POS_LOOP_GAIN | K_EXP_AMPLITUDE(0x15)); + + ad9361_spi_write(spi, REG_DC_OFFSET_CONFIG2, + USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL | + DC_OFFSET_UPDATE(phy->pdata->dc_offset_update_events) | + (bbdc_track ? ENABLE_BB_DC_OFFSET_TRACKING : 0) | + (rfdc_track ? ENABLE_RF_OFFSET_TRACKING : 0)); + + ad9361_spi_writef(spi, REG_RX_QUAD_GAIN2, + CORRECTION_WORD_DECIMATION_M(~0), + phy->pdata->qec_tracking_slow_mode_en ? 4 : 0); + + if (rxquad_track) { + if (phy->pdata->rx2tx2) + qtrack = ENABLE_TRACKING_MODE_CH1 | ENABLE_TRACKING_MODE_CH2; + else + qtrack = (phy->pdata->rx1tx1_mode_use_rx_num == 1) ? + ENABLE_TRACKING_MODE_CH1 : ENABLE_TRACKING_MODE_CH2; + } + + ad9361_spi_write(spi, REG_CALIBRATION_CONFIG_1, + ENABLE_PHASE_CORR | ENABLE_GAIN_CORR | + FREE_RUN_MODE | ENABLE_CORR_WORD_DECIMATION | + qtrack); + + return 0; +} + +/** + * Enable/disable the VCO cal. + * @param phy The AD9361 state structure. + * @param rx Set true for rx. + * @param enable Set true to enable. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_trx_vco_cal_control(struct ad9361_rf_phy *phy, + bool tx, bool enable) +{ + dev_dbg(&phy->spi->dev, "%s : state %d", + __func__, enable); + + return ad9361_spi_writef(phy->spi, + tx ? REG_TX_PFD_CONFIG : REG_RX_PFD_CONFIG, + BYPASS_LD_SYNTH, !enable); +} + +/** + * Enable/disable the ext. LO. + * @param phy The AD9361 state structure. + * @param rx Set true for rx. + * @param enable Set true to enable. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_trx_ext_lo_control(struct ad9361_rf_phy *phy, + bool tx, bool enable) +{ + uint32_t val = enable ? ~0 : 0; + int32_t ret; + + /* REVIST: + * POWER_DOWN_TRX_SYNTH and MCS_RF_ENABLE somehow conflict + */ + + bool mcs_rf_enable = ad9361_spi_readf(phy->spi, + REG_MULTICHIP_SYNC_AND_TX_MON_CTRL, + MCS_RF_ENABLE); + + dev_dbg(&phy->spi->dev, "%s : %s state %d", __func__, + tx ? "TX" : "RX", enable); + + if (tx) { + ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, + POWER_DOWN_TX_SYNTH, mcs_rf_enable ? 0 : enable); + + ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, + TX_SYNTH_READY_MASK, enable); + + ret |= ad9361_spi_writef(phy->spi, REG_RFPLL_DIVIDERS, + TX_VCO_DIVIDER(~0), enable ? 7 : + phy->cached_tx_rfpll_div); + + if (enable) + phy->cached_synth_pd[0] |= TX_SYNTH_VCO_ALC_POWER_DOWN | + TX_SYNTH_PTAT_POWER_DOWN | + TX_SYNTH_VCO_POWER_DOWN; + else + phy->cached_synth_pd[0] &= ~(TX_SYNTH_VCO_ALC_POWER_DOWN | + TX_SYNTH_PTAT_POWER_DOWN | + TX_SYNTH_VCO_POWER_DOWN); + + + ret |= ad9361_spi_write(phy->spi, REG_TX_SYNTH_POWER_DOWN_OVERRIDE, + phy->cached_synth_pd[0]); + + ret |= ad9361_spi_writef(phy->spi, REG_ANALOG_POWER_DOWN_OVERRIDE, + TX_EXT_VCO_BUFFER_POWER_DOWN, !enable); + + ret |= ad9361_spi_write(phy->spi, REG_TX_LO_GEN_POWER_MODE, + TX_LO_GEN_POWER_MODE(val)); + } else { + ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, + POWER_DOWN_RX_SYNTH, mcs_rf_enable ? 0 : enable); + + ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, + RX_SYNTH_READY_MASK, enable); + + ret |= ad9361_spi_writef(phy->spi, REG_RFPLL_DIVIDERS, + RX_VCO_DIVIDER(~0), enable ? 7 : + phy->cached_rx_rfpll_div); + + if (enable) + phy->cached_synth_pd[1] |= RX_SYNTH_VCO_ALC_POWER_DOWN | + RX_SYNTH_PTAT_POWER_DOWN | + RX_SYNTH_VCO_POWER_DOWN; + else + phy->cached_synth_pd[1] &= ~(TX_SYNTH_VCO_ALC_POWER_DOWN | + RX_SYNTH_PTAT_POWER_DOWN | + RX_SYNTH_VCO_POWER_DOWN); + + ret |= ad9361_spi_write(phy->spi, REG_RX_SYNTH_POWER_DOWN_OVERRIDE, + phy->cached_synth_pd[1]); + + ret |= ad9361_spi_writef(phy->spi, REG_ANALOG_POWER_DOWN_OVERRIDE, + RX_EXT_VCO_BUFFER_POWER_DOWN, !enable); + + ret |= ad9361_spi_write(phy->spi, REG_RX_LO_GEN_POWER_MODE, + RX_LO_GEN_POWER_MODE(val)); + } + + return ret; +} + +/** + * Power down the TX and/or RX Local Oscillators. + * @param phy The AD9361 state structure. + * @param rx The RX LO setting. + * @param tx The TX LO setting. + * @return 0 in case of success, negative error code otherwise. + */ +int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy, + enum synth_pd_ctrl rx, + enum synth_pd_ctrl tx) +{ + dev_dbg(&phy->spi->dev, "%s : RX(%d) TX(%d)", __func__, rx, tx); + + switch (rx) { + case LO_OFF: + phy->cached_synth_pd[1] |= RX_LO_POWER_DOWN; + break; + case LO_ON: + phy->cached_synth_pd[1] &= ~RX_LO_POWER_DOWN; + break; + case LO_DONTCARE: + break; + } + + switch (tx) { + case LO_OFF: + phy->cached_synth_pd[0] |= TX_LO_POWER_DOWN; + break; + case LO_ON: + phy->cached_synth_pd[0] &= ~TX_LO_POWER_DOWN; + break; + case LO_DONTCARE: + break; + } + + return ad9361_spi_writem(phy->spi, REG_TX_SYNTH_POWER_DOWN_OVERRIDE, + phy->cached_synth_pd, 2); +} + +/** + * Setup the reference clock delay unit counter register. + * @param phy The AD9361 state structure. + * @param ref_clk_hz The reference clock frequency [Hz]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_set_ref_clk_cycles(struct ad9361_rf_phy *phy, + uint32_t ref_clk_hz) +{ + dev_dbg(&phy->spi->dev, "%s : ref_clk_hz %"PRIu32, + __func__, ref_clk_hz); + + return ad9361_spi_write(phy->spi, REG_REFERENCE_CLOCK_CYCLES, + REFERENCE_CLOCK_CYCLES_PER_US((ref_clk_hz / 1000000UL) - 1)); +} + +/** + * Setup the DCXO tune. + * @param phy The AD9361 state structure. + * @param coarse The DCXO tune coarse. + * @param fine The DCXO tune fine. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy, + uint32_t coarse, uint32_t fine) +{ + dev_dbg(&phy->spi->dev, "%s : coarse %"PRIu32" fine %"PRIu32, + __func__, coarse, fine); + + if (phy->pdata->use_extclk) + return -ENODEV; + + ad9361_spi_write(phy->spi, REG_DCXO_COARSE_TUNE, + DCXO_TUNE_COARSE(coarse)); + ad9361_spi_write(phy->spi, REG_DCXO_FINE_TUNE_LOW, + DCXO_TUNE_FINE_LOW(fine)); + return ad9361_spi_write(phy->spi, REG_DCXO_FINE_TUNE_HIGH, + DCXO_TUNE_FINE_HIGH(fine)); +} + +/** + * Setup TXMON. + * @param phy The AD9361 state structure. + * @param ctrl The TXMON settings. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_txmon_setup(struct ad9361_rf_phy *phy, + struct tx_monitor_control *ctrl) +{ + struct spi_desc *spi = phy->spi; + + dev_dbg(&phy->spi->dev, "%s", __func__); + + ad9361_spi_write(spi, REG_TPM_MODE_ENABLE, + (ctrl->one_shot_mode_en ? ONE_SHOT_MODE : 0) | + TX_MON_DURATION(ilog2(ctrl->tx_mon_duration / 16))); + + ad9361_spi_write(spi, REG_TX_MON_DELAY, ctrl->tx_mon_delay & 0xFF); + ad9361_spi_writef(spi, REG_TX_LEVEL_THRESH, + TX_MON_DELAY_COUNTER(~0), ctrl->tx_mon_delay >> 8); + + ad9361_spi_write(spi, REG_TX_MON_1_CONFIG, + TX_MON_1_LO_CM(ctrl->tx1_mon_lo_cm) | + TX_MON_1_GAIN(ctrl->tx1_mon_front_end_gain)); + ad9361_spi_write(spi, REG_TX_MON_2_CONFIG, + TX_MON_2_LO_CM(ctrl->tx2_mon_lo_cm) | + TX_MON_2_GAIN(ctrl->tx2_mon_front_end_gain)); + + ad9361_spi_write(spi, REG_TX_ATTEN_THRESH, + ctrl->low_high_gain_threshold_mdB / 250); + + ad9361_spi_write(spi, REG_TX_MON_HIGH_GAIN, + TX_MON_HIGH_GAIN(ctrl->high_gain_dB)); + + ad9361_spi_write(spi, REG_TX_MON_LOW_GAIN, + (ctrl->tx_mon_track_en ? TX_MON_TRACK : 0) | + TX_MON_LOW_GAIN(ctrl->low_gain_dB)); + + return 0; +} + +/** + * Enable TXMON. + * @param phy The AD9361 state structure. + * @param en_mask The enable mask. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_txmon_control(struct ad9361_rf_phy *phy, + int32_t en_mask) +{ + dev_dbg(&phy->spi->dev, "%s: mask 0x%"PRIx32, __func__, en_mask); + +#if 0 + if (!phy->pdata->fdd && en_mask) { + ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_1, + ENABLE_RX_DATA_PORT_FOR_CAL, 1); + phy->txmon_tdd_en = true; + } else { + ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_1, + ENABLE_RX_DATA_PORT_FOR_CAL, 0); + phy->txmon_tdd_en = false; + } +#endif + + ad9361_spi_writef(phy->spi, REG_ANALOG_POWER_DOWN_OVERRIDE, + TX_MONITOR_POWER_DOWN(~0), ~en_mask); + + ad9361_spi_writef(phy->spi, REG_TPM_MODE_ENABLE, + TX1_MON_ENABLE, !!(en_mask & TX_1)); + + return ad9361_spi_writef(phy->spi, REG_TPM_MODE_ENABLE, + TX2_MON_ENABLE, !!(en_mask & TX_2)); +} + +/** +* Setup the RF port. +* Note: +* val +* 0 (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced +* 1 (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced +* 2 (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced +* +* 3 RX1A_N and RX2A_N enabled; unbalanced +* 4 RX1A_P and RX2A_P enabled; unbalanced +* 5 RX1B_N and RX2B_N enabled; unbalanced +* 6 RX1B_P and RX2B_P enabled; unbalanced +* 7 RX1C_N and RX2C_N enabled; unbalanced +* 8 RX1C_P and RX2C_P enabled; unbalanced +* 9 TX_MON1 +* 10 TX_MON2 +* 11 TX_MON1 & TX_MON2 +* @param phy The AD9361 state structure. +* @param is_out TX RF output port enabled. +* @param rx_inputs RX input option identifier +* @param txb TX output option identifier +* @return 0 in case of success, negative error code otherwise. +*/ +int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out, + uint32_t rx_inputs, uint32_t txb) +{ + uint32_t val; + + if (rx_inputs > 11) + return -EINVAL; + + if (!is_out) { + if (rx_inputs > 8) + return ad9361_txmon_control(phy, rx_inputs & (TX_1 | TX_2)); + else + ad9361_txmon_control(phy, 0); + } + + if (rx_inputs < 3) + val = 3 << (rx_inputs * 2); + else + val = 1 << (rx_inputs - 3); + + if (txb) + val |= TX_OUTPUT; /* Select TX1B, TX2B */ + + dev_dbg(&phy->spi->dev, "%s : INPUT_SELECT 0x%"PRIx32, + __func__, val); + + return ad9361_spi_write(phy->spi, REG_INPUT_SELECT, val); +} + +/** + * Setup the Parallel Port (Digital Data Interface). + * @param phy The AD9361 state structure. + * @param restore_c3 Set true, will restore the Parallel Port Configuration 3 + * register. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_pp_port_setup(struct ad9361_rf_phy *phy, bool restore_c3) +{ + struct spi_desc *spi = phy->spi; + struct ad9361_phy_platform_data *pd = phy->pdata; + + dev_dbg(&phy->spi->dev, "%s", __func__); + + if (restore_c3) { + return ad9361_spi_write(spi, REG_PARALLEL_PORT_CONF_3, + pd->port_ctrl.pp_conf[2]); + } + + /* Sanity check */ + if (pd->port_ctrl.pp_conf[2] & LVDS_MODE) + pd->port_ctrl.pp_conf[2] &= + ~(HALF_DUPLEX_MODE | SINGLE_DATA_RATE | SINGLE_PORT_MODE); + + if (pd->port_ctrl.pp_conf[2] & FULL_PORT) + pd->port_ctrl.pp_conf[2] &= ~(HALF_DUPLEX_MODE | SINGLE_PORT_MODE); + + ad9361_spi_write(spi, REG_PARALLEL_PORT_CONF_1, pd->port_ctrl.pp_conf[0]); + ad9361_spi_write(spi, REG_PARALLEL_PORT_CONF_2, pd->port_ctrl.pp_conf[1]); + ad9361_spi_write(spi, REG_PARALLEL_PORT_CONF_3, pd->port_ctrl.pp_conf[2]); + ad9361_spi_write(spi, REG_RX_CLOCK_DATA_DELAY, pd->port_ctrl.rx_clk_data_delay); + ad9361_spi_write(spi, REG_TX_CLOCK_DATA_DELAY, pd->port_ctrl.tx_clk_data_delay); + + ad9361_spi_write(spi, REG_LVDS_BIAS_CTRL, pd->port_ctrl.lvds_bias_ctrl); + // ad9361_spi_write(spi, REG_DIGITAL_IO_CTRL, pd->port_ctrl.digital_io_ctrl); + ad9361_spi_write(spi, REG_LVDS_INVERT_CTRL1, pd->port_ctrl.lvds_invert[0]); + ad9361_spi_write(spi, REG_LVDS_INVERT_CTRL2, pd->port_ctrl.lvds_invert[1]); + + if (pd->rx1rx2_phase_inversion_en || + (pd->port_ctrl.pp_conf[1] & INVERT_RX2)) { + + ad9361_spi_writef(spi, REG_PARALLEL_PORT_CONF_2, INVERT_RX2, 1); + ad9361_spi_writef(spi, REG_INVERT_BITS, + INVERT_RX2_RF_DC_CGOUT_WORD, 0); + } + + return 0; +} + +/** + * Setup the Gain Control Blocks (common function for MGC, AGC modes) + * @param phy The AD9361 state structure. + * @param ctrl The gain control settings. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_gc_setup(struct ad9361_rf_phy *phy, + struct gain_control *ctrl) +{ + struct spi_desc *spi = phy->spi; + uint32_t reg, tmp1, tmp2; + + dev_dbg(&phy->spi->dev, "%s", __func__); + + reg = DEC_PWR_FOR_GAIN_LOCK_EXIT | DEC_PWR_FOR_LOCK_LEVEL | + DEC_PWR_FOR_LOW_PWR; + + if (ctrl->rx1_mode == RF_GAIN_HYBRID_AGC || + ctrl->rx2_mode == RF_GAIN_HYBRID_AGC) + reg |= SLOW_ATTACK_HYBRID_MODE; + + reg |= RX1_GAIN_CTRL_SETUP(ctrl->rx1_mode) | + RX2_GAIN_CTRL_SETUP(ctrl->rx2_mode); + + phy->agc_mode[0] = ctrl->rx1_mode; + phy->agc_mode[1] = ctrl->rx2_mode; + + ad9361_spi_write(spi, REG_AGC_CONFIG_1, reg); // Gain Control Mode Select + + /* AGC_USE_FULL_GAIN_TABLE handled in ad9361_load_gt() */ + ad9361_spi_writef(spi, REG_AGC_CONFIG_2, MAN_GAIN_CTRL_RX1, + ctrl->mgc_rx1_ctrl_inp_en); + ad9361_spi_writef(spi, REG_AGC_CONFIG_2, MAN_GAIN_CTRL_RX2, + ctrl->mgc_rx2_ctrl_inp_en); + ad9361_spi_writef(spi, REG_AGC_CONFIG_2, DIG_GAIN_EN, + ctrl->dig_gain_en); + + ctrl->adc_ovr_sample_size = clamp_t(uint8_t, ctrl->adc_ovr_sample_size, 1U, 8U); + reg = ADC_OVERRANGE_SAMPLE_SIZE(ctrl->adc_ovr_sample_size - 1); + + if (has_split_gt && phy->pdata->split_gt && + (ctrl->mgc_rx1_ctrl_inp_en || ctrl->mgc_rx2_ctrl_inp_en)) { + switch (ctrl->mgc_split_table_ctrl_inp_gain_mode) { + case 1: + reg &= ~INCDEC_LMT_GAIN; + break; + case 2: + reg |= INCDEC_LMT_GAIN; + break; + default: + case 0: + reg |= USE_AGC_FOR_LMTLPF_GAIN; + break; + } + } + + ctrl->mgc_inc_gain_step = clamp_t(uint8_t, ctrl->mgc_inc_gain_step, 1U, 8U); + reg |= MANUAL_INCR_STEP_SIZE(ctrl->mgc_inc_gain_step - 1); + ad9361_spi_write(spi, REG_AGC_CONFIG_3, + reg); // Incr Step Size, ADC Overrange Size + + ctrl->mgc_dec_gain_step = clamp_t(uint8_t, ctrl->mgc_dec_gain_step, 1U, 8U); + reg = MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(ctrl->mgc_dec_gain_step - 1); + ad9361_spi_write(spi, REG_PEAK_WAIT_TIME, + reg); // Decr Step Size, Peak Overload Time + + if (ctrl->dig_gain_en) + ad9361_spi_write(spi, REG_DIGITAL_GAIN, + MAXIMUM_DIGITAL_GAIN(ctrl->max_dig_gain) | + DIG_GAIN_STP_SIZE(ctrl->dig_gain_step_size)); + + if (ctrl->adc_large_overload_thresh >= ctrl->adc_small_overload_thresh) { + ad9361_spi_write(spi, REG_ADC_SMALL_OVERLOAD_THRESH, + ctrl->adc_small_overload_thresh); // ADC Small Overload Threshold + ad9361_spi_write(spi, REG_ADC_LARGE_OVERLOAD_THRESH, + ctrl->adc_large_overload_thresh); // ADC Large Overload Threshold + } else { + ad9361_spi_write(spi, REG_ADC_SMALL_OVERLOAD_THRESH, + ctrl->adc_large_overload_thresh); // ADC Small Overload Threshold + ad9361_spi_write(spi, REG_ADC_LARGE_OVERLOAD_THRESH, + ctrl->adc_small_overload_thresh); // ADC Large Overload Threshold + } + + reg = (ctrl->lmt_overload_high_thresh / 16) - 1; + reg = clamp(reg, 0U, 63U); + ad9361_spi_write(spi, REG_LARGE_LMT_OVERLOAD_THRESH, reg); + reg = (ctrl->lmt_overload_low_thresh / 16) - 1; + reg = clamp(reg, 0U, 63U); + ad9361_spi_writef(spi, REG_SMALL_LMT_OVERLOAD_THRESH, + SMALL_LMT_OVERLOAD_THRESH(~0), reg); + + if (has_split_gt && phy->pdata->split_gt) { + /* REVIST */ + ad9361_spi_write(spi, REG_RX1_MANUAL_LPF_GAIN, 0x58); // Rx1 LPF Gain Index + ad9361_spi_write(spi, REG_RX2_MANUAL_LPF_GAIN, 0x18); // Rx2 LPF Gain Index + ad9361_spi_write(spi, REG_FAST_INITIAL_LMT_GAIN_LIMIT, + 0x27); // Initial LMT Gain Limit + } + + ad9361_spi_write(spi, REG_RX1_MANUAL_DIGITALFORCED_GAIN, + 0x00); // Rx1 Digital Gain Index + ad9361_spi_write(spi, REG_RX2_MANUAL_DIGITALFORCED_GAIN, + 0x00); // Rx2 Digital Gain Index + + reg = clamp_t(uint8_t, ctrl->low_power_thresh, 0U, 64U) * 2; + ad9361_spi_write(spi, REG_FAST_LOW_POWER_THRESH, reg); // Low Power Threshold + ad9361_spi_write(spi, REG_TX_SYMBOL_ATTEN_CONFIG, + 0x00); // Tx Symbol Gain Control + + ad9361_spi_writef(spi, REG_DEC_POWER_MEASURE_DURATION_0, + USE_HB1_OUT_FOR_DEC_PWR_MEAS, + !ctrl->use_rx_fir_out_for_dec_pwr_meas); // USE HB1 or FIR output for power measurements + + ad9361_spi_writef(spi, REG_DEC_POWER_MEASURE_DURATION_0, + ENABLE_DEC_PWR_MEAS, 1); // Power Measurement Duration + + if (ctrl->rx1_mode == RF_GAIN_FASTATTACK_AGC || + ctrl->rx2_mode == RF_GAIN_FASTATTACK_AGC) + reg = ilog2(ctrl->f_agc_dec_pow_measuremnt_duration / 16); + else + reg = ilog2(ctrl->dec_pow_measuremnt_duration / 16); + + ad9361_spi_writef(spi, REG_DEC_POWER_MEASURE_DURATION_0, + DEC_POWER_MEASUREMENT_DURATION(~0), reg); // Power Measurement Duration + + /* AGC */ + + tmp1 = reg = clamp_t(uint8_t, ctrl->agc_inner_thresh_high, 0U, 127U); + ad9361_spi_writef(spi, REG_AGC_LOCK_LEVEL, + AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW(~0), + reg); + + tmp2 = reg = clamp_t(uint8_t, ctrl->agc_inner_thresh_low, 0U, 127U); + reg |= (ctrl->adc_lmt_small_overload_prevent_gain_inc ? + PREVENT_GAIN_INC : 0); + ad9361_spi_write(spi, REG_AGC_INNER_LOW_THRESH, reg); + + reg = AGC_OUTER_HIGH_THRESH(tmp1 - ctrl->agc_outer_thresh_high) | + AGC_OUTER_LOW_THRESH(ctrl->agc_outer_thresh_low - tmp2); + ad9361_spi_write(spi, REG_OUTER_POWER_THRESHS, reg); + + reg = AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(ctrl->agc_outer_thresh_high_dec_steps) + | + AGC_OUTER_LOW_THRESH_EXED_STP_SIZE(ctrl->agc_outer_thresh_low_inc_steps); + ad9361_spi_write(spi, REG_GAIN_STP_2, reg); + + reg = ((ctrl->immed_gain_change_if_large_adc_overload) ? + IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD : 0) | + ((ctrl->immed_gain_change_if_large_lmt_overload) ? + IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD : 0) | + AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(ctrl->agc_inner_thresh_high_dec_steps) | + AGC_INNER_LOW_THRESH_EXED_STP_SIZE(ctrl->agc_inner_thresh_low_inc_steps); + ad9361_spi_write(spi, REG_GAIN_STP1, reg); + + reg = LARGE_ADC_OVERLOAD_EXED_COUNTER(ctrl->adc_large_overload_exceed_counter) | + SMALL_ADC_OVERLOAD_EXED_COUNTER(ctrl->adc_small_overload_exceed_counter); + ad9361_spi_write(spi, REG_ADC_OVERLOAD_COUNTERS, reg); + + reg = DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE( + ctrl->f_agc_large_overload_inc_steps) | + LARGE_LPF_GAIN_STEP(ctrl->adc_large_overload_inc_steps); + ad9361_spi_write(spi, REG_GAIN_STP_CONFIG_2, reg); + + reg = LARGE_LMT_OVERLOAD_EXED_COUNTER(ctrl->lmt_overload_large_exceed_counter) | + SMALL_LMT_OVERLOAD_EXED_COUNTER(ctrl->lmt_overload_small_exceed_counter); + ad9361_spi_write(spi, REG_LMT_OVERLOAD_COUNTERS, reg); + + ad9361_spi_writef(spi, REG_GAIN_STP_CONFIG1, + DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(~0), + ctrl->lmt_overload_large_inc_steps); + + reg = DIG_SATURATION_EXED_COUNTER(ctrl->dig_saturation_exceed_counter) | + (ctrl->sync_for_gain_counter_en ? + ENABLE_SYNC_FOR_GAIN_COUNTER : 0); + ad9361_spi_write(spi, REG_DIGITAL_SAT_COUNTER, reg); + + /* + * Fast AGC + */ + + /* Fast AGC - Low Power */ + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + ENABLE_INCR_GAIN, + ctrl->f_agc_allow_agc_gain_increase); + + ad9361_spi_write(spi, REG_FAST_INCREMENT_TIME, + ctrl->f_agc_lp_thresh_increment_time); + + reg = ctrl->f_agc_lp_thresh_increment_steps - 1; + reg = clamp_t(uint32_t, reg, 0U, 7U); + ad9361_spi_writef(spi, REG_FAST_ENERGY_DETECT_COUNT, + INCREMENT_GAIN_STP_LPFLMT(~0), reg); + + /* Fast AGC - Lock Level */ + /* Dual use see also agc_inner_thresh_high */ + ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, + ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL, + ctrl->f_agc_lock_level_lmt_gain_increase_en); + + reg = ctrl->f_agc_lock_level_gain_increase_upper_limit; + reg = clamp_t(uint32_t, reg, 0U, 63U); + ad9361_spi_writef(spi, REG_FAST_AGCLL_UPPER_LIMIT, + AGCLL_MAX_INCREASE(~0), reg); + + /* Fast AGC - Peak Detectors and Final Settling */ + reg = ctrl->f_agc_lpf_final_settling_steps; + reg = clamp_t(uint32_t, reg, 0U, 3U); + ad9361_spi_writef(spi, REG_FAST_ENERGY_LOST_THRESH, + POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE(~0), + reg); + + reg = ctrl->f_agc_lmt_final_settling_steps; + reg = clamp_t(uint32_t, reg, 0U, 3U); + ad9361_spi_writef(spi, REG_FAST_STRONGER_SIGNAL_THRESH, + POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(~0), reg); + + reg = ctrl->f_agc_final_overrange_count; + reg = clamp_t(uint32_t, reg, 0U, 7U); + ad9361_spi_writef(spi, REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN, + FINAL_OVER_RANGE_COUNT(~0), reg); + + /* Fast AGC - Final Power Test */ + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + ENABLE_GAIN_INC_AFTER_GAIN_LOCK, + ctrl->f_agc_gain_increase_after_gain_lock_en); + + /* Fast AGC - Unlocking the Gain */ + /* 0 = MAX Gain, 1 = Optimized Gain, 2 = Set Gain */ + + reg = ctrl->f_agc_gain_index_type_after_exit_rx_mode; + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + GOTO_SET_GAIN_IF_EXIT_RX_STATE, reg == SET_GAIN); + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE, + reg == OPTIMIZED_GAIN); + + ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, + USE_LAST_LOCK_LEVEL_FOR_SET_GAIN, + ctrl->f_agc_use_last_lock_level_for_set_gain_en); + + reg = ctrl->f_agc_optimized_gain_offset; + reg = clamp_t(uint32_t, reg, 0U, 15U); + ad9361_spi_writef(spi, REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN, + OPTIMIZE_GAIN_OFFSET(~0), reg); + + tmp1 = !ctrl->f_agc_rst_gla_stronger_sig_thresh_exceeded_en || + !ctrl->f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en || + !ctrl->f_agc_rst_gla_large_adc_overload_en || + !ctrl->f_agc_rst_gla_large_lmt_overload_en || + ctrl->f_agc_rst_gla_en_agc_pulled_high_en; + + ad9361_spi_writef(spi, REG_AGC_CONFIG_2, + AGC_GAIN_UNLOCK_CTRL, tmp1); + + reg = !ctrl->f_agc_rst_gla_stronger_sig_thresh_exceeded_en; + ad9361_spi_writef(spi, REG_FAST_STRONG_SIGNAL_FREEZE, + DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL, reg); + + reg = ctrl->f_agc_rst_gla_stronger_sig_thresh_above_ll; + reg = clamp_t(uint32_t, reg, 0U, 63U); + ad9361_spi_writef(spi, REG_FAST_STRONGER_SIGNAL_THRESH, + STRONGER_SIGNAL_THRESH(~0), reg); + + reg = ctrl->f_agc_rst_gla_engergy_lost_sig_thresh_below_ll; + reg = clamp_t(uint32_t, reg, 0U, 63U); + ad9361_spi_writef(spi, REG_FAST_ENERGY_LOST_THRESH, + ENERGY_LOST_THRESH(~0), reg); + + reg = ctrl->f_agc_rst_gla_engergy_lost_goto_optim_gain_en; + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH, reg); + + reg = !ctrl->f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en; + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + DONT_UNLOCK_GAIN_IF_ENERGY_LOST, reg); + + reg = ctrl->f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt; + reg = clamp_t(uint32_t, reg, 0U, 63U); + ad9361_spi_writef(spi, REG_FAST_GAIN_LOCK_EXIT_COUNT, + GAIN_LOCK_EXIT_COUNT(~0), reg); + + reg = !ctrl->f_agc_rst_gla_large_adc_overload_en || + !ctrl->f_agc_rst_gla_large_lmt_overload_en; + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG, reg); + + reg = !ctrl->f_agc_rst_gla_large_adc_overload_en; + ad9361_spi_writef(spi, REG_FAST_LOW_POWER_THRESH, + DONT_UNLOCK_GAIN_IF_ADC_OVRG, reg); + + /* 0 = Max Gain, 1 = Set Gain, 2 = Optimized Gain, 3 = No Gain Change */ + + if (ctrl->f_agc_rst_gla_en_agc_pulled_high_en) { + switch (ctrl->f_agc_rst_gla_if_en_agc_pulled_high_mode) { + case MAX_GAIN: + ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, + GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH, 1); + + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + GOTO_SET_GAIN_IF_EN_AGC_HIGH, 0); + + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH, 0); + break; + case SET_GAIN: + ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, + GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH, 0); + + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + GOTO_SET_GAIN_IF_EN_AGC_HIGH, 1); + break; + case OPTIMIZED_GAIN: + ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, + GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH, 1); + + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + GOTO_SET_GAIN_IF_EN_AGC_HIGH, 0); + + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH, 1); + break; + case NO_GAIN_CHANGE: + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + GOTO_SET_GAIN_IF_EN_AGC_HIGH, 0); + ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, + GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH, 0); + break; + } + } else { + ad9361_spi_writef(spi, REG_FAST_CONFIG_1, + GOTO_SET_GAIN_IF_EN_AGC_HIGH, 0); + ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, + GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH, 0); + } + + reg = ilog2(ctrl->f_agc_power_measurement_duration_in_state5 / 16); + reg = clamp_t(uint32_t, reg, 0U, 15U); + ad9361_spi_writef(spi, REG_RX1_MANUAL_LPF_GAIN, + POWER_MEAS_IN_STATE_5(~0), reg); + ad9361_spi_writef(spi, REG_RX1_MANUAL_LMT_FULL_GAIN, + POWER_MEAS_IN_STATE_5_MSB, reg >> 3); + + return ad9361_gc_update(phy); +} + +/** + * Set the Aux DAC. + * @param phy The AD9361 state structure. + * @param dac The DAC. + * @param val_mV The value. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_auxdac_set(struct ad9361_rf_phy *phy, int32_t dac, + int32_t val_mV) +{ + struct spi_desc *spi = phy->spi; + uint32_t val, tmp; + + dev_dbg(&phy->spi->dev, "%s DAC%"PRId32" = %"PRId32" mV", __func__, dac, + val_mV); + + /* Disable DAC if val == 0, Ignored in ENSM Auto Mode */ + ad9361_spi_writef(spi, REG_AUXDAC_ENABLE_CTRL, + AUXDAC_MANUAL_BAR(dac), val_mV ? 0 : 1); + + if (val_mV < 306) + val_mV = 306; + + if (val_mV < 1888) { + val = ((val_mV - 306) * 1000) / 1469; /* Vref = 1V, Step = 2 */ + tmp = AUXDAC_1_VREF(0); + } else { + val = ((val_mV - 1761) * 1000) / 1512; /* Vref = 2.5V, Step = 2 */ + tmp = AUXDAC_1_VREF(3); + } + + val = clamp_t(uint32_t, val, 0, 1023); + + switch (dac) { + case 1: + ad9361_spi_write(spi, REG_AUXDAC_1_WORD, val >> 2); + ad9361_spi_write(spi, REG_AUXDAC_1_CONFIG, AUXDAC_1_WORD_LSB(val) | tmp); + phy->auxdac1_value = val_mV; + break; + case 2: + ad9361_spi_write(spi, REG_AUXDAC_2_WORD, val >> 2); + ad9361_spi_write(spi, REG_AUXDAC_2_CONFIG, AUXDAC_2_WORD_LSB(val) | tmp); + phy->auxdac2_value = val_mV; + break; + default: + return -EINVAL; + } + + return 0; +} + +/** + * Get the Aux DAC value. + * @param phy The AD9361 state structure. + * @param dac The DAC. + * @return The value in case of success, negative error code otherwise. + */ +int32_t ad9361_auxdac_get(struct ad9361_rf_phy *phy, int32_t dac) +{ + + switch (dac) { + case 1: + return phy->auxdac1_value; + case 2: + return phy->auxdac2_value; + default: + return -EINVAL; + } + + return 0; +} + +/** + * Setup the AuxDAC. + * @param phy The AD9361 state structure. + * @param ctrl Pointer to auxdac_control structure. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_auxdac_setup(struct ad9361_rf_phy *phy, + struct auxdac_control *ctrl) +{ + struct spi_desc *spi = phy->spi; + uint8_t tmp; + + dev_dbg(&phy->spi->dev, "%s", __func__); + + ad9361_auxdac_set(phy, 1, ctrl->dac1_default_value); + ad9361_auxdac_set(phy, 2, ctrl->dac2_default_value); + + tmp = ~(AUXDAC_AUTO_TX_BAR(ctrl->dac2_in_tx_en << 1 | ctrl->dac1_in_tx_en) | + AUXDAC_AUTO_RX_BAR(ctrl->dac2_in_rx_en << 1 | ctrl->dac1_in_rx_en) | + AUXDAC_INIT_BAR(ctrl->dac2_in_alert_en << 1 | ctrl->dac1_in_alert_en)); + + ad9361_spi_writef(spi, REG_AUXDAC_ENABLE_CTRL, + AUXDAC_AUTO_TX_BAR(~0) | + AUXDAC_AUTO_RX_BAR(~0) | + AUXDAC_INIT_BAR(~0), + tmp); /* Auto Control */ + + ad9361_spi_writef(spi, REG_EXTERNAL_LNA_CTRL, + AUXDAC_MANUAL_SELECT, ctrl->auxdac_manual_mode_en); + ad9361_spi_write(spi, REG_AUXDAC1_RX_DELAY, ctrl->dac1_rx_delay_us); + ad9361_spi_write(spi, REG_AUXDAC1_TX_DELAY, ctrl->dac1_tx_delay_us); + ad9361_spi_write(spi, REG_AUXDAC2_RX_DELAY, ctrl->dac2_rx_delay_us); + ad9361_spi_write(spi, REG_AUXDAC2_TX_DELAY, ctrl->dac2_tx_delay_us); + + return 0; +} + +/** + * Setup the AuxADC. + * @param phy The AD9361 state structure. + * @param ctrl The AuxADC settings. + * @param bbpll_freq The BBPLL frequency [Hz]. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_auxadc_setup(struct ad9361_rf_phy *phy, + struct auxadc_control *ctrl, + uint32_t bbpll_freq) +{ + struct spi_desc *spi = phy->spi; + uint32_t val; + + dev_dbg(&phy->spi->dev, "%s", __func__); + + val = DIV_ROUND_CLOSEST(ctrl->temp_time_inteval_ms * + (bbpll_freq / 1000UL), (1 << 29)); + + ad9361_spi_write(spi, REG_TEMP_OFFSET, ctrl->offset); + ad9361_spi_write(spi, REG_START_TEMP_READING, 0x00); + ad9361_spi_write(spi, REG_TEMP_SENSE2, + MEASUREMENT_TIME_INTERVAL(val) | + (ctrl->periodic_temp_measuremnt ? + TEMP_SENSE_PERIODIC_ENABLE : 0)); + ad9361_spi_write(spi, REG_TEMP_SENSOR_CONFIG, + TEMP_SENSOR_DECIMATION( + ilog2(ctrl->temp_sensor_decimation) - 8)); + ad9361_spi_write(spi, REG_AUXADC_CLOCK_DIVIDER, + bbpll_freq / ctrl->auxadc_clock_rate); + ad9361_spi_write(spi, REG_AUXADC_CONFIG, + AUX_ADC_DECIMATION( + ilog2(ctrl->auxadc_decimation) - 8)); + + return 0; +} + +/** + * Get the measured temperature of the device. + * @param phy The AD9361 state structure. + * @return The measured temperature of the device. + */ +int32_t ad9361_get_temp(struct ad9361_rf_phy *phy) +{ + uint32_t val; + + ad9361_spi_writef(phy->spi, REG_AUXADC_CONFIG, AUXADC_POWER_DOWN, 1); + val = ad9361_spi_read(phy->spi, REG_TEMPERATURE); + ad9361_spi_writef(phy->spi, REG_AUXADC_CONFIG, AUXADC_POWER_DOWN, 0); + + return DIV_ROUND_CLOSEST(val * 1000000, 1140); +} + +/** + * Get the Aux ADC value. + * @param phy The AD9361 state structure. + * @return The value in case of success, negative error code otherwise. + */ +int32_t ad9361_get_auxadc(struct ad9361_rf_phy *phy) +{ + uint8_t buf[2]; + + ad9361_spi_writef(phy->spi, REG_AUXADC_CONFIG, AUXADC_POWER_DOWN, 1); + ad9361_spi_readm(phy->spi, REG_AUXADC_LSB, buf, 2); + ad9361_spi_writef(phy->spi, REG_AUXADC_CONFIG, AUXADC_POWER_DOWN, 0); + + return (buf[1] << 4) | AUXADC_WORD_LSB(buf[0]); +} + +/** + * Setup the Control Output pins. + * @param phy The AD9361 state structure. + * @param ctrl The Control Output pins settings. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, + struct ctrl_outs_control *ctrl) +{ + struct spi_desc *spi = phy->spi; + + dev_dbg(&phy->spi->dev, "%s", __func__); + + ad9361_spi_write(spi, REG_CTRL_OUTPUT_POINTER, ctrl->index); // Ctrl Out index + return ad9361_spi_write(spi, REG_CTRL_OUTPUT_ENABLE, + ctrl->en_mask); // Ctrl Out [7:0] output enable +} + +/** + * Setup the GPO pins. + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_gpo_setup(struct ad9361_rf_phy *phy, + struct gpo_control *ctrl) +{ + struct spi_desc *spi = phy->spi; + + dev_dbg(&phy->spi->dev, "%s", __func__); + + ad9361_spi_write(spi, REG_AUTO_GPO, + GPO_ENABLE_AUTO_RX(ctrl->gpo0_slave_rx_en | + (ctrl->gpo1_slave_rx_en << 1) | + (ctrl->gpo2_slave_rx_en << 2) | + (ctrl->gpo3_slave_rx_en << 3)) | + GPO_ENABLE_AUTO_TX(ctrl->gpo0_slave_tx_en | + (ctrl->gpo1_slave_tx_en << 1) | + (ctrl->gpo2_slave_tx_en << 2) | + (ctrl->gpo3_slave_tx_en << 3))); + + ad9361_spi_write(spi, REG_GPO_FORCE_AND_INIT, + GPO_MANUAL_CTRL(ctrl->gpo_manual_mode_enable_mask) | + GPO_INIT_STATE(ctrl->gpo0_inactive_state_high_en | + (ctrl->gpo1_inactive_state_high_en << 1) | + (ctrl->gpo2_inactive_state_high_en << 2) | + (ctrl->gpo3_inactive_state_high_en << 3))); + + ad9361_spi_write(spi, REG_GPO0_RX_DELAY, ctrl->gpo0_rx_delay_us); + ad9361_spi_write(spi, REG_GPO0_TX_DELAY, ctrl->gpo0_tx_delay_us); + ad9361_spi_write(spi, REG_GPO1_RX_DELAY, ctrl->gpo1_rx_delay_us); + ad9361_spi_write(spi, REG_GPO1_TX_DELAY, ctrl->gpo1_tx_delay_us); + ad9361_spi_write(spi, REG_GPO2_RX_DELAY, ctrl->gpo2_rx_delay_us); + ad9361_spi_write(spi, REG_GPO2_TX_DELAY, ctrl->gpo2_tx_delay_us); + ad9361_spi_write(spi, REG_GPO3_RX_DELAY, ctrl->gpo3_rx_delay_us); + ad9361_spi_write(spi, REG_GPO3_TX_DELAY, ctrl->gpo3_tx_delay_us); + + /* + * GPO manual mode conflicts with automatic ENSM slave and eLNA mode + */ + ad9361_spi_writef(phy->spi, REG_EXTERNAL_LNA_CTRL, GPO_MANUAL_SELECT, + ctrl->gpo_manual_mode_en); + + return 0; +} + +/** + * Setup the RSSI. + * @param phy The AD9361 state structure. + * @param ctrl The RSSI settings. + * @param is_update True if update + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_rssi_setup(struct ad9361_rf_phy *phy, + struct rssi_control *ctrl, + bool is_update) +{ + struct spi_desc *spi = phy->spi; + uint32_t total_weight, weight[4], total_dur = 0, temp; + uint8_t dur_buf[4] = { 0 }; + int32_t val, ret, i, j = 0; + uint32_t rssi_delay; + uint32_t rssi_wait; + int32_t rssi_duration; + uint32_t rate; + + dev_dbg(&phy->spi->dev, "%s", __func__); + + if (ctrl->rssi_unit_is_rx_samples) { + if (is_update) + return 0; /* no update required */ + + rssi_delay = ctrl->rssi_delay; + rssi_wait = ctrl->rssi_wait; + rssi_duration = ctrl->rssi_duration; + } else { + /* update sample based on RX rate */ + rate = DIV_ROUND_CLOSEST( + clk_get_rate(phy, phy->ref_clk_scale[RX_SAMPL_CLK]), 1000); + /* units are in us */ + rssi_delay = DIV_ROUND_CLOSEST(ctrl->rssi_delay * rate, 1000); + rssi_wait = DIV_ROUND_CLOSEST(ctrl->rssi_wait * rate, 1000); + rssi_duration = DIV_ROUND_CLOSEST( + ctrl->rssi_duration * rate, 1000); + } + + if (ctrl->restart_mode == EN_AGC_PIN_IS_PULLED_HIGH) + rssi_delay = 0; + + rssi_delay = clamp(rssi_delay / 8, 0U, 255U); + rssi_wait = clamp(rssi_wait / 4, 0U, 255U); + + do { + for (i = 14; rssi_duration > 0 && i >= 0; i--) { + val = 1 << i; + if ((int64_t)rssi_duration >= val) { + dur_buf[j++] = i; + total_dur += val; + rssi_duration -= val; + break; + } + } + + } while (j < 4 && rssi_duration > 0); + + for (i = 0, total_weight = 0; i < 4; i++) { + if (i < j) + total_weight += weight[i] = + DIV_ROUND_CLOSEST(RSSI_MAX_WEIGHT * + (1 << dur_buf[i]), total_dur); + else + total_weight += weight[i] = 0; + } + + /* total of all weights must be 0xFF */ + val = total_weight - 0xFF; + weight[j - 1] -= val; + + ad9361_spi_write(spi, REG_MEASURE_DURATION_01, + (dur_buf[1] << 4) | dur_buf[0]); // RSSI Measurement Duration 0, 1 + ad9361_spi_write(spi, REG_MEASURE_DURATION_23, + (dur_buf[3] << 4) | dur_buf[2]); // RSSI Measurement Duration 2, 3 + ad9361_spi_write(spi, REG_RSSI_WEIGHT_0, + weight[0]); // RSSI Weighted Multiplier 0 + ad9361_spi_write(spi, REG_RSSI_WEIGHT_1, + weight[1]); // RSSI Weighted Multiplier 1 + ad9361_spi_write(spi, REG_RSSI_WEIGHT_2, + weight[2]); // RSSI Weighted Multiplier 2 + ad9361_spi_write(spi, REG_RSSI_WEIGHT_3, + weight[3]); // RSSI Weighted Multiplier 3 + ad9361_spi_write(spi, REG_RSSI_DELAY, rssi_delay); // RSSI Delay + ad9361_spi_write(spi, REG_RSSI_WAIT_TIME, rssi_wait); // RSSI Wait + + temp = RSSI_MODE_SELECT(ctrl->restart_mode); + if (ctrl->restart_mode == SPI_WRITE_TO_REGISTER) + temp |= START_RSSI_MEAS; + + if (rssi_duration == 0 && j == 1) /* Power of two */ + temp |= DEFAULT_RSSI_MEAS_MODE; + + ret = ad9361_spi_write(spi, REG_RSSI_CONFIG, temp); // RSSI Mode Select + + if (ret < 0) + dev_err(&phy->spi->dev, "Unable to write rssi config"); + + return 0; +} + +/** + * This function needs to be called whenever BBPLL changes. + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_bb_clk_change_handler(struct ad9361_rf_phy *phy) +{ + int32_t ret; + + ret = ad9361_gc_update(phy); + ret |= ad9361_rssi_setup(phy, &phy->pdata->rssi_ctrl, true); + ret |= ad9361_auxadc_setup(phy, &phy->pdata->auxadc_ctrl, + clk_get_rate(phy, phy->ref_clk_scale[BBPLL_CLK])); + + return ret; +} + +/** + * Set the desired Enable State Machine (ENSM) state. + * @param phy The AD9361 state structure. + * @param ensm_state The ENSM state [ENSM_STATE_SLEEP_WAIT, ENSM_STATE_ALERT, + * ENSM_STATE_TX, ENSM_STATE_TX_FLUSH, ENSM_STATE_RX, + * ENSM_STATE_RX_FLUSH, ENSM_STATE_FDD, ENSM_STATE_FDD_FLUSH]. + * @param pinctrl Set true, will enable the ENSM pin control. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_ensm_set_state(struct ad9361_rf_phy *phy, uint8_t ensm_state, + bool pinctrl) +{ + struct spi_desc *spi = phy->spi; + int32_t rc = 0; + uint32_t val; + uint32_t tmp; + + dev_dbg(dev, "Device is in %x state, moving to %x", phy->curr_ensm_state, + ensm_state); + + + if (phy->curr_ensm_state == ENSM_STATE_SLEEP) { + ad9361_spi_write(spi, REG_CLOCK_ENABLE, + DIGITAL_POWER_UP | CLOCK_ENABLE_DFLT | BBPLL_ENABLE | + (phy->pdata->use_extclk ? XO_BYPASS : 0)); /* Enable Clocks */ + udelay(20); + ad9361_spi_write(spi, REG_ENSM_CONFIG_1, TO_ALERT | FORCE_ALERT_STATE); + ad9361_trx_vco_cal_control(phy, false, true); /* Enable VCO Cal */ + ad9361_trx_vco_cal_control(phy, true, true); + } + + val = (phy->pdata->ensm_pin_pulse_mode ? 0 : LEVEL_MODE) | + (pinctrl ? ENABLE_ENSM_PIN_CTRL : 0) | + (phy->txmon_tdd_en ? ENABLE_RX_DATA_PORT_FOR_CAL : 0) | + TO_ALERT; + + switch (ensm_state) { + case ENSM_STATE_TX: + val |= FORCE_TX_ON; + if (phy->pdata->fdd) + rc = -EINVAL; + else if (phy->curr_ensm_state != ENSM_STATE_ALERT) + rc = -EINVAL; + break; + case ENSM_STATE_RX: + val |= FORCE_RX_ON; + if (phy->pdata->fdd) + rc = -EINVAL; + else if (phy->curr_ensm_state != ENSM_STATE_ALERT) + rc = -EINVAL; + break; + case ENSM_STATE_FDD: + val |= FORCE_TX_ON; + if (!phy->pdata->fdd) + rc = -EINVAL; + break; + case ENSM_STATE_ALERT: + val &= ~(FORCE_TX_ON | FORCE_RX_ON); + val |= TO_ALERT | FORCE_ALERT_STATE; + break; + case ENSM_STATE_SLEEP_WAIT: + break; + case ENSM_STATE_SLEEP: + ad9361_trx_vco_cal_control(phy, false, false); /* Disable VCO Cal */ + ad9361_trx_vco_cal_control(phy, true, false); + ad9361_spi_write(spi, REG_ENSM_CONFIG_1, 0); /* Clear To Alert */ + ad9361_spi_write(spi, REG_ENSM_CONFIG_1, + phy->pdata->fdd ? FORCE_TX_ON : FORCE_RX_ON); + /* Delay Flush Time 384 ADC clock cycles */ + udelay(384000000UL / clk_get_rate(phy, phy->ref_clk_scale[ADC_CLK])); + ad9361_spi_write(spi, REG_ENSM_CONFIG_1, 0); /* Move to Wait*/ + udelay(1); /* Wait for ENSM settle */ + ad9361_spi_write(spi, REG_CLOCK_ENABLE, + (phy->pdata->use_extclk ? XO_BYPASS : 0)); /* Turn off all clocks */ + phy->curr_ensm_state = ensm_state; + return 0; + + default: + dev_err(dev, "No handling for forcing %d ensm state", + ensm_state); + goto out; + } + + if (rc) { + if ((phy->curr_ensm_state != ENSM_STATE_ALERT) + && (val & (FORCE_RX_ON | FORCE_TX_ON))) { + uint32_t val2 = val; + + val2 &= ~(FORCE_TX_ON | FORCE_RX_ON); + val2 |= TO_ALERT | FORCE_ALERT_STATE; + ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val2); + + ad9361_check_cal_done(phy, REG_STATE, ENSM_STATE(~0), ENSM_STATE_ALERT); + } else { + dev_err(dev, "Invalid ENSM state transition in %s mode", + phy->pdata->fdd ? "FDD" : "TDD"); + goto out; + } + } + + if (!phy->pdata->fdd && !pinctrl && !phy->pdata->tdd_use_dual_synth && + (ensm_state == ENSM_STATE_TX || ensm_state == ENSM_STATE_RX)) { + uint32_t reg, check; + + if (ensm_state == ENSM_STATE_TX) { + reg = REG_TX_CP_OVERRANGE_VCO_LOCK; + check = !(phy->cached_synth_pd[0] & + TX_SYNTH_VCO_POWER_DOWN); + } else { + reg = REG_RX_CP_OVERRANGE_VCO_LOCK; + check = !(phy->cached_synth_pd[1] & + RX_SYNTH_VCO_POWER_DOWN); + } + + ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, + TXNRX_SPI_CTRL, ensm_state == ENSM_STATE_TX); + + if (check) + ad9361_check_cal_done(phy, reg, VCO_LOCK, 1); + } + + rc = ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val); + if (rc) + dev_err(dev, "Failed to restore state"); + + if ((val & FORCE_RX_ON) && + (phy->agc_mode[0] == RF_GAIN_MGC || + phy->agc_mode[1] == RF_GAIN_MGC)) { + tmp = ad9361_spi_read(spi, REG_SMALL_LMT_OVERLOAD_THRESH); + ad9361_spi_write(spi, REG_SMALL_LMT_OVERLOAD_THRESH, + (tmp & SMALL_LMT_OVERLOAD_THRESH(~0)) | + (phy->agc_mode[0] == RF_GAIN_MGC ? FORCE_PD_RESET_RX1 : 0) | + (phy->agc_mode[1] == RF_GAIN_MGC ? FORCE_PD_RESET_RX2 : 0)); + ad9361_spi_write(spi, REG_SMALL_LMT_OVERLOAD_THRESH, + tmp & SMALL_LMT_OVERLOAD_THRESH(~0)); + } + + phy->curr_ensm_state = ensm_state; + +out: + return rc; + +} + +/** + * Check if at least one of the clock rates is equal to the DATA_CLK (lvds) rate. + * @param phy The AD9361 state structure. + * @param rx_path_clks RX path rates buffer. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_validate_trx_clock_chain(struct ad9361_rf_phy *phy, + uint32_t *rx_path_clks, uint32_t *tx_path_clks) +{ + static const uint32_t max_rx_rates[] = {MAX_BBPLL_FREQ, MAX_ADC_CLK, + MAX_RX_HB3, MAX_RX_HB2, MAX_RX_HB1, MAX_BASEBAND_RATE + }; + static const uint32_t max_tx_rates[] = {MAX_BBPLL_FREQ, MAX_DAC_CLK, + MAX_TX_HB3, MAX_TX_HB2, MAX_TX_HB1, MAX_BASEBAND_RATE + }; + uint32_t i; + uint32_t data_clk; + + data_clk = (phy->pdata->rx2tx2 ? 4 : 2) / + ((phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) ? 1 : 2) * + rx_path_clks[RX_SAMPL_FREQ]; + + /* CMOS Mode */ + if (!(phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) && + (data_clk > MAX_BASEBAND_RATE)) { + dev_err(&phy->spi->dev, + "%s: Failed CMOS MODE DATA_CLK > 61.44MSPS", __func__); + return -EINVAL; + } + + /* Validate MAX PLL, ADC, DAC and HB filter rates */ + for (i = 0; i < ARRAY_SIZE(max_rx_rates); i++) { + if (rx_path_clks[i] > max_rx_rates[i]) { + dev_err(&phy->spi->dev, + "%s: Failed RX max rate check (%"PRIu32" > %"PRIu32")", + __func__, rx_path_clks[i], max_rx_rates[i]); + return -EINVAL; + } + + if (tx_path_clks[i] > max_tx_rates[i]) { + dev_err(&phy->spi->dev, + "%s: Failed TX max rate check (%"PRIu32" > %"PRIu32")", + __func__, tx_path_clks[i], max_tx_rates[i]); + return -EINVAL; + } + } + + /* Validate that DATA_CLK exist within the clock chain */ + for (i = 1; i <= 3; i++) { + if (diff_abs(rx_path_clks[ADC_FREQ] / i, data_clk) < 4) + return 0; + } + + for (i = 1; i <= 4; i++) { + if (diff_abs((rx_path_clks[R2_FREQ] >> i), data_clk) < 4) + return 0; + } + + dev_err(&phy->spi->dev, "%s: Failed - at least one of the clock rates" + " must be equal to the DATA_CLK (lvds) rate", __func__); + + return -EINVAL; +} + +/** + * Set the RX and TX path rates. + * @param phy The AD9361 state structure. + * @param rx_path_clks RX path rates buffer. + * @param tx_path_clks TX path rates buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, + uint32_t *rx_path_clks, + uint32_t *tx_path_clks) +{ + int32_t ret, i, j, n; + + dev_dbg(&phy->spi->dev, "%s", __func__); + + if (!rx_path_clks || !tx_path_clks) + return -EINVAL; + + dev_dbg(&phy->spi->dev, + "%s: %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32, + __func__, rx_path_clks[BBPLL_FREQ], rx_path_clks[ADC_FREQ], + rx_path_clks[R2_FREQ], rx_path_clks[R1_FREQ], + rx_path_clks[CLKRF_FREQ], rx_path_clks[RX_SAMPL_FREQ]); + + dev_dbg(&phy->spi->dev, + "%s: %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32, + __func__, tx_path_clks[BBPLL_FREQ], tx_path_clks[ADC_FREQ], + tx_path_clks[R2_FREQ], tx_path_clks[R1_FREQ], + tx_path_clks[CLKRF_FREQ], tx_path_clks[RX_SAMPL_FREQ]); + + ret = ad9361_validate_trx_clock_chain(phy, rx_path_clks, tx_path_clks); + if (ret < 0) + return ret; + + ret = clk_set_rate(phy, phy->ref_clk_scale[BBPLL_CLK], + rx_path_clks[BBPLL_FREQ]); + if (ret < 0) + return ret; + + phy->current_rx_path_clks[BBPLL_FREQ] = rx_path_clks[BBPLL_FREQ]; + + for (i = ADC_CLK, j = DAC_CLK, n = ADC_FREQ; + i <= RX_SAMPL_CLK; i++, j++, n++) { + ret = clk_set_rate(phy, phy->ref_clk_scale[i], rx_path_clks[n]); + if (ret < 0) { + dev_err(dev, "Failed to set BB ref clock rate (%"PRId32")", + ret); + return ret; + } + phy->current_rx_path_clks[n] = rx_path_clks[n]; + ret = clk_set_rate(phy, phy->ref_clk_scale[j], tx_path_clks[n]); + if (ret < 0) { + dev_err(dev, "Failed to set BB ref clock rate (%"PRId32")", + ret); + return ret; + } + phy->current_tx_path_clks[n] = tx_path_clks[n]; + } + + /* + * Workaround for clock framework since clocks don't change we + * manually need to enable the filter + */ + + if (phy->rx_fir_dec == 1 || phy->bypass_rx_fir) { + ad9361_spi_writef(phy->spi, REG_RX_ENABLE_FILTER_CTRL, + RX_FIR_ENABLE_DECIMATION(~0), !phy->bypass_rx_fir); + } + + if (phy->tx_fir_int == 1 || phy->bypass_tx_fir) { + ad9361_spi_writef(phy->spi, REG_TX_ENABLE_FILTER_CTRL, + TX_FIR_ENABLE_INTERPOLATION(~0), !phy->bypass_tx_fir); + } + + /* The FIR filter once enabled causes the interface timing to change. + * It's typically not a problem if the timing margin is big enough. + * However at 61.44 MSPS it causes problems on some systems. + * So we always run the digital tune in case the filter is enabled. + * If it is disabled we restore the values from the initial calibration. + */ + + if (!phy->pdata->dig_interface_tune_fir_disable && + !(phy->bypass_tx_fir && phy->bypass_rx_fir)) + ret = ad9361_dig_tune(phy, 0, SKIP_STORE_RESULT); + + return ad9361_bb_clk_change_handler(phy); +} + +/** + * Get the RX and TX path rates. + * @param phy The AD9361 state structure. + * @param rx_path_clks RX path rates buffer. + * @param tx_path_clks TX path rates buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy, + uint32_t *rx_path_clks, + uint32_t *tx_path_clks) +{ + int32_t i, j, n; + uint32_t bbpll_freq; + + if (!rx_path_clks && !tx_path_clks) + return -EINVAL; + + bbpll_freq = clk_get_rate(phy, phy->ref_clk_scale[BBPLL_CLK]); + + if (rx_path_clks) + rx_path_clks[BBPLL_FREQ] = bbpll_freq; + + if (tx_path_clks) + tx_path_clks[BBPLL_FREQ] = bbpll_freq; + + for (i = ADC_CLK, j = DAC_CLK, n = ADC_FREQ; + i <= RX_SAMPL_CLK; i++, j++, n++) { + if (rx_path_clks) + rx_path_clks[n] = clk_get_rate(phy, phy->ref_clk_scale[i]); + if (tx_path_clks) + tx_path_clks[n] = clk_get_rate(phy, phy->ref_clk_scale[j]); + } + + return 0; +} + +/** + * Calculate the RX and TX path rates to obtain the desired sample rate. + * @param phy The AD9361 state structure. + * @param tx_sample_rate The desired sample rate. + * @param rate_gov The rate governor option. + * @param rx_path_clks RX path rates buffer. + * @param tx_path_clks TX path rates buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy, + uint32_t tx_sample_rate, + uint32_t rate_gov, + uint32_t *rx_path_clks, + uint32_t *tx_path_clks) +{ + uint32_t clktf, clkrf, adc_rate = 0, dac_rate = 0; + uint64_t bbpll_rate; + int32_t i, index_rx = -1, index_tx = -1, tmp; + uint32_t div, tx_intdec, rx_intdec, recursion = 1; + const int8_t clk_dividers[][4] = { + { 12, 3, 2, 2 }, + { 8, 2, 2, 2 }, + { 6, 3, 1, 2 }, + { 4, 2, 2, 1 }, + { 3, 3, 1, 1 }, + { 2, 2, 1, 1 }, + { 1, 1, 1, 1 }, + }; + + if (phy->bypass_rx_fir) + rx_intdec = 1; + else + rx_intdec = phy->rx_fir_dec; + + if (phy->bypass_tx_fir) + tx_intdec = 1; + else + tx_intdec = phy->tx_fir_int; + + if ((rate_gov == 1) && ((rx_intdec * tx_sample_rate * 8) < MIN_ADC_CLK)) { + recursion = 0; + rate_gov = 0; + } + + dev_dbg(&phy->spi->dev, + "%s: requested rate %"PRIu32" TXFIR int %"PRIu32" RXFIR dec %"PRIu32" mode %s", + __func__, tx_sample_rate, tx_intdec, rx_intdec, + rate_gov ? "Nominal" : "Highest OSR"); + + if (tx_sample_rate > MAX_BASEBAND_RATE) + return -EINVAL; + + clktf = tx_sample_rate * tx_intdec; + clkrf = tx_sample_rate * rx_intdec * (phy->rx_eq_2tx ? 2 : 1); + + for (i = rate_gov; i < 7; i++) { + adc_rate = clkrf * clk_dividers[i][0]; + dac_rate = clktf * clk_dividers[i][0]; + + if ((adc_rate <= MAX_ADC_CLK) && (adc_rate >= MIN_ADC_CLK)) { + + + if (dac_rate > adc_rate) + tmp = (dac_rate / adc_rate) * -1; + else + tmp = adc_rate / dac_rate; + + if (adc_rate <= MAX_DAC_CLK) { + index_rx = i; + index_tx = i - ((tmp == 1) ? 0 : tmp); + dac_rate = adc_rate; /* ADC_CLK */ + break; + } else { + dac_rate = adc_rate / 2; /* ADC_CLK/2 */ + index_rx = i; + + if (i == 4 && tmp >= 0) + index_tx = 7; /* STOP: 3/2 != 1 */ + else + index_tx = i + ((i == 5 && tmp >= 0) ? 1 : 2) - + ((tmp == 1) ? 0 : tmp); + + break; + } + } + } + + if ((index_tx < 0 || index_tx > 6 || index_rx < 0 || index_rx > 6) + && rate_gov < 7 && recursion) { + return ad9361_calculate_rf_clock_chain(phy, tx_sample_rate, + ++rate_gov, rx_path_clks, tx_path_clks); + } else if ((index_tx < 0 || index_tx > 6 || index_rx < 0 || index_rx > 6)) { + dev_err(&phy->spi->dev, "%s: Failed to find suitable dividers: %s", + __func__, (adc_rate < MIN_ADC_CLK) ? "ADC clock below limit" : + "BBPLL rate above limit"); + + return -EINVAL; + } + + /* Calculate target BBPLL rate */ + div = MAX_BBPLL_DIV; + + do { + bbpll_rate = (uint64_t)adc_rate * div; + div >>= 1; + + } while ((bbpll_rate > MAX_BBPLL_FREQ) && (div >= MIN_BBPLL_DIV)); + + rx_path_clks[BBPLL_FREQ] = bbpll_rate; + rx_path_clks[ADC_FREQ] = adc_rate; + rx_path_clks[R2_FREQ] = rx_path_clks[ADC_FREQ] / clk_dividers[index_rx][1]; + rx_path_clks[R1_FREQ] = rx_path_clks[R2_FREQ] / clk_dividers[index_rx][2]; + rx_path_clks[CLKRF_FREQ] = rx_path_clks[R1_FREQ] / clk_dividers[index_rx][3]; + rx_path_clks[RX_SAMPL_FREQ] = rx_path_clks[CLKRF_FREQ] / rx_intdec; + + tx_path_clks[BBPLL_FREQ] = bbpll_rate; + tx_path_clks[DAC_FREQ] = dac_rate; + tx_path_clks[T2_FREQ] = tx_path_clks[DAC_FREQ] / clk_dividers[index_tx][1]; + tx_path_clks[T1_FREQ] = tx_path_clks[T2_FREQ] / clk_dividers[index_tx][2]; + tx_path_clks[CLKTF_FREQ] = tx_path_clks[T1_FREQ] / clk_dividers[index_tx][3]; + tx_path_clks[TX_SAMPL_FREQ] = tx_path_clks[CLKTF_FREQ] / tx_intdec; + + return 0; +} + +/** + * Set the desired sample rate. + * @param phy The AD9361 state structure. + * @param freq The desired sample rate. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, + uint32_t freq) +{ + uint32_t rx[6], tx[6]; + int32_t ret; + + ret = ad9361_calculate_rf_clock_chain(phy, freq, + phy->rate_governor, rx, tx); + if (ret < 0) + return ret; + return ad9361_set_trx_clock_chain(phy, rx, tx); +} + +/** + * Internal ENSM mode options helper function. + * @param phy The AD9361 state structure. + * @param fdd + * @param pinctrl + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl) +{ + struct ad9361_phy_platform_data *pd = phy->pdata; + int32_t ret; + uint32_t val = 0; + + ad9361_spi_write(phy->spi, REG_ENSM_MODE, fdd ? FDD_MODE : 0); + + val = ad9361_spi_read(phy->spi, REG_ENSM_CONFIG_2); + val &= POWER_DOWN_RX_SYNTH | POWER_DOWN_TX_SYNTH | + RX_SYNTH_READY_MASK | TX_SYNTH_READY_MASK; + + if (fdd) + ret = ad9361_spi_write(phy->spi, REG_ENSM_CONFIG_2, + val | DUAL_SYNTH_MODE | + (pd->fdd_independent_mode ? FDD_EXTERNAL_CTRL_ENABLE : 0)); + else + ret = ad9361_spi_write(phy->spi, REG_ENSM_CONFIG_2, val | + (pd->tdd_use_dual_synth ? DUAL_SYNTH_MODE : 0) | + (pd->tdd_use_dual_synth ? 0 : + (pinctrl ? SYNTH_ENABLE_PIN_CTRL_MODE : 0))); + + return ret; +} + +/** + * Fastlock read value. + * @param spi + * @param tx + * @param profile + * @param word + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_fastlock_readval(struct spi_desc *spi, bool tx, + uint32_t profile, uint32_t word) +{ + uint32_t offs = 0; + + if (tx) + offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; + + ad9361_spi_write(spi, REG_RX_FAST_LOCK_PROGRAM_ADDR + offs, + RX_FAST_LOCK_PROFILE_ADDR(profile) | + RX_FAST_LOCK_PROFILE_WORD(word)); + + return ad9361_spi_read(spi, REG_RX_FAST_LOCK_PROGRAM_READ + offs); +} + +/** + * Fastlock write value. + * @param spi + * @param tx + * @param profile + * @param word + * @param val + * @param last + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_fastlock_writeval(struct spi_desc *spi, bool tx, + uint32_t profile, uint32_t word, uint8_t val, bool last) +{ + uint32_t offs = 0; + int32_t ret; + + if (tx) + offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; + + ret = ad9361_spi_write(spi, REG_RX_FAST_LOCK_PROGRAM_ADDR + offs, + RX_FAST_LOCK_PROFILE_ADDR(profile) | + RX_FAST_LOCK_PROFILE_WORD(word)); + ret |= ad9361_spi_write(spi, REG_RX_FAST_LOCK_PROGRAM_DATA + offs, val); + ret |= ad9361_spi_write(spi, REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, + RX_FAST_LOCK_PROGRAM_WRITE | + RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE); + + if (last) /* Stop Clocks */ + ret |= ad9361_spi_write(spi, + REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, 0); + + return ret; +} + +/** + * Fastlock load values. + * @param phy The AD9361 state structure. + * @param tx + * @param profile + * @param values + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx, + uint32_t profile, uint8_t *values) +{ + uint32_t offs = 0; + int32_t i, ret = 0; + uint8_t buf[4]; + + dev_dbg(&phy->spi->dev, "%s: %s Profile %"PRIu32":", + __func__, tx ? "TX" : "RX", profile); + + if (tx) + offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; + + buf[0] = values[0]; + buf[1] = RX_FAST_LOCK_PROFILE_ADDR(profile) | RX_FAST_LOCK_PROFILE_WORD(0); + ad9361_spi_writem(phy->spi, REG_RX_FAST_LOCK_PROGRAM_DATA + offs, buf, 2); + + for (i = 1; i < RX_FAST_LOCK_CONFIG_WORD_NUM; i++) { + buf[0] = RX_FAST_LOCK_PROGRAM_WRITE | RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE; + buf[1] = 0; + buf[2] = values[i]; + buf[3] = RX_FAST_LOCK_PROFILE_ADDR(profile) | RX_FAST_LOCK_PROFILE_WORD(i); + ad9361_spi_writem(phy->spi, REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, buf, 4); + } + + ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, + RX_FAST_LOCK_PROGRAM_WRITE | RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE); + ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, 0); + + phy->fastlock.entry[tx][profile].flags = FASTLOOK_INIT; + phy->fastlock.entry[tx][profile].alc_orig = values[15]; + phy->fastlock.entry[tx][profile].alc_written = values[15]; + + return ret; +} + +/** + * Fastlock store. + * @param phy The AD9361 state structure. + * @param tx + * @param profile + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx, + uint32_t profile) +{ + struct spi_desc *spi = phy->spi; + uint8_t val[16]; + uint32_t offs = 0, x, y; + + dev_dbg(&phy->spi->dev, "%s: %s Profile %"PRIu32":", + __func__, tx ? "TX" : "RX", profile); + + if (tx) + offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; + + val[0] = ad9361_spi_read(spi, REG_RX_INTEGER_BYTE_0 + offs); + val[1] = ad9361_spi_read(spi, REG_RX_INTEGER_BYTE_1 + offs); + val[2] = ad9361_spi_read(spi, REG_RX_FRACT_BYTE_0 + offs); + val[3] = ad9361_spi_read(spi, REG_RX_FRACT_BYTE_1 + offs); + val[4] = ad9361_spi_read(spi, REG_RX_FRACT_BYTE_2 + offs); + + x = ad9361_spi_readf(spi, REG_RX_VCO_BIAS_1 + offs, VCO_BIAS_REF(~0)); + y = ad9361_spi_readf(spi, REG_RX_ALC_VARACTOR + offs, VCO_VARACTOR(~0)); + val[5] = (x << 4) | y; + + x = ad9361_spi_readf(spi, REG_RX_VCO_BIAS_1 + offs, VCO_BIAS_TCF(~0)); + y = ad9361_spi_readf(spi, REG_RX_CP_CURRENT + offs, CHARGE_PUMP_CURRENT(~0)); + /* Wide BW option: N = 1 + * Set init and steady state values to the same - let user space handle it + */ + val[6] = (x << 3) | y; + val[7] = y; + + x = ad9361_spi_readf(spi, REG_RX_LOOP_FILTER_3 + offs, LOOP_FILTER_R3(~0)); + val[8] = (x << 4) | x; + + x = ad9361_spi_readf(spi, REG_RX_LOOP_FILTER_2 + offs, LOOP_FILTER_C3(~0)); + val[9] = (x << 4) | x; + + x = ad9361_spi_readf(spi, REG_RX_LOOP_FILTER_1 + offs, LOOP_FILTER_C1(~0)); + y = ad9361_spi_readf(spi, REG_RX_LOOP_FILTER_1 + offs, LOOP_FILTER_C2(~0)); + val[10] = (x << 4) | y; + + x = ad9361_spi_readf(spi, REG_RX_LOOP_FILTER_2 + offs, LOOP_FILTER_R1(~0)); + val[11] = (x << 4) | x; + + x = ad9361_spi_readf(spi, REG_RX_VCO_VARACTOR_CTRL_0 + offs, + VCO_VARACTOR_REFERENCE_TCF(~0)); + y = ad9361_spi_readf(spi, REG_RFPLL_DIVIDERS, + tx ? TX_VCO_DIVIDER(~0) : RX_VCO_DIVIDER(~0)); + val[12] = (x << 4) | y; + + x = ad9361_spi_readf(spi, REG_RX_FORCE_VCO_TUNE_1 + offs, VCO_CAL_OFFSET(~0)); + y = ad9361_spi_readf(spi, REG_RX_VCO_VARACTOR_CTRL_1 + offs, + VCO_VARACTOR_REFERENCE(~0)); + val[13] = (x << 4) | y; + + val[14] = ad9361_spi_read(spi, REG_RX_FORCE_VCO_TUNE_0 + offs); + + x = ad9361_spi_readf(spi, REG_RX_FORCE_ALC + offs, FORCE_ALC_WORD(~0)); + y = ad9361_spi_readf(spi, REG_RX_FORCE_VCO_TUNE_1 + offs, FORCE_VCO_TUNE); + val[15] = (x << 1) | y; + + return ad9361_fastlock_load(phy, tx, profile, val); +} + +/** + * Fastlock prepare. + * @param phy The AD9361 state structure. + * @param tx + * @param profile + * @param prepare + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_fastlock_prepare(struct ad9361_rf_phy *phy, bool tx, + uint32_t profile, bool prepare) +{ + uint32_t offs, ready_mask; + bool is_prepared; + + dev_dbg(&phy->spi->dev, "%s: %s Profile %"PRIu32": %s", + __func__, tx ? "TX" : "RX", profile, + prepare ? "Prepare" : "Un-Prepare"); + + if (tx) { + offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; + ready_mask = TX_SYNTH_READY_MASK; + } else { + offs = 0; + ready_mask = RX_SYNTH_READY_MASK; + } + + is_prepared = !!phy->fastlock.current_profile[tx]; + + if (prepare && !is_prepared) { + ad9361_spi_write(phy->spi, + REG_RX_FAST_LOCK_SETUP_INIT_DELAY + offs, + (tx ? phy->pdata->tx_fastlock_delay_ns : + phy->pdata->rx_fastlock_delay_ns) / 250); + ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_SETUP + offs, + RX_FAST_LOCK_PROFILE(profile) | + RX_FAST_LOCK_MODE_ENABLE); + ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, + 0); + + ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, ready_mask, 1); + ad9361_trx_vco_cal_control(phy, tx, false); + } else if (!prepare && is_prepared) { + ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_SETUP + offs, 0); + + /* Workaround: Exiting Fastlock Mode */ + ad9361_spi_writef(phy->spi, REG_RX_FORCE_ALC + offs, FORCE_ALC_ENABLE, 1); + ad9361_spi_writef(phy->spi, REG_RX_FORCE_VCO_TUNE_1 + offs, FORCE_VCO_TUNE, 1); + ad9361_spi_writef(phy->spi, REG_RX_FORCE_ALC + offs, FORCE_ALC_ENABLE, 0); + ad9361_spi_writef(phy->spi, REG_RX_FORCE_VCO_TUNE_1 + offs, FORCE_VCO_TUNE, 0); + + ad9361_trx_vco_cal_control(phy, tx, true); + ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, ready_mask, 0); + + phy->fastlock.current_profile[tx] = 0; + } + + return 0; +} + +/** + * Fastlock recall. + * @param phy The AD9361 state structure. + * @param tx + * @param profile + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx, + uint32_t profile) +{ + uint32_t offs = 0; + uint8_t curr, _new, orig, current_profile; + + dev_dbg(&phy->spi->dev, "%s: %s Profile %"PRIu32":", + __func__, tx ? "TX" : "RX", profile); + + if (tx) + offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; + + if (phy->fastlock.entry[tx][profile].flags != FASTLOOK_INIT) + return -EINVAL; + + /* Workaround: Lock problem with same ALC word */ + + current_profile = phy->fastlock.current_profile[tx]; + _new = phy->fastlock.entry[tx][profile].alc_written; + + if (current_profile == 0) + curr = ad9361_spi_readf(phy->spi, REG_RX_FORCE_ALC + offs, + FORCE_ALC_WORD(~0)) << 1; + else + curr = phy->fastlock.entry[tx][current_profile - 1].alc_written; + + if ((curr >> 1) == (_new >> 1)) { + orig = phy->fastlock.entry[tx][profile].alc_orig; + + if ((orig >> 1) == (_new >> 1)) + phy->fastlock.entry[tx][profile].alc_written += 2; + else + phy->fastlock.entry[tx][profile].alc_written = orig; + + ad9361_fastlock_writeval(phy->spi, tx, profile, 0xF, + phy->fastlock.entry[tx][profile].alc_written, true); + } + + ad9361_fastlock_prepare(phy, tx, profile, true); + phy->fastlock.current_profile[tx] = profile + 1; + + return ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_SETUP + offs, + RX_FAST_LOCK_PROFILE(profile) | + (phy->pdata->trx_fastlock_pinctrl_en[tx] ? + RX_FAST_LOCK_PROFILE_PIN_SELECT : 0) | + RX_FAST_LOCK_MODE_ENABLE); +} + +/** + * Fastlock save. + * @param phy The AD9361 state structure. + * @param tx + * @param profile + * @param values + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx, + uint32_t profile, uint8_t *values) +{ + int32_t i; + + dev_dbg(&phy->spi->dev, "%s: %s Profile %"PRIu32":", + __func__, tx ? "TX" : "RX", profile); + + for (i = 0; i < RX_FAST_LOCK_CONFIG_WORD_NUM; i++) + values[i] = ad9361_fastlock_readval(phy->spi, tx, profile, i); + + return 0; +} + +/** + * Multi Chip Sync (MCS) config. + * @param phy The AD9361 state structure. + * @param step MCS step. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_mcs(struct ad9361_rf_phy *phy, int32_t step) +{ + int32_t mcs_mask = MCS_RF_ENABLE | MCS_BBPLL_ENABLE | + MCS_DIGITAL_CLK_ENABLE | MCS_BB_ENABLE; + + dev_dbg(&phy->spi->dev, "%s: MCS step %"PRId32, __func__, step); + + switch (step) { + case 1: + /* REVIST: + * POWER_DOWN_TRX_SYNTH and MCS_RF_ENABLE somehow conflict + */ + ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, + POWER_DOWN_TX_SYNTH | POWER_DOWN_RX_SYNTH, 0); + + ad9361_spi_writef(phy->spi, REG_MULTICHIP_SYNC_AND_TX_MON_CTRL, + mcs_mask, MCS_BB_ENABLE | MCS_BBPLL_ENABLE | MCS_RF_ENABLE); + ad9361_spi_writef(phy->spi, REG_CP_BLEED_CURRENT, + MCS_REFCLK_SCALE_EN, 1); + break; + case 2: + if(!phy->gpio_desc_sync) + break; + /* + * NOTE: This is not a regular GPIO - + * HDL ensures Multi-chip Synchronization SYNC_IN Pulse Timing + * relative to rising and falling edge of REF_CLK + */ + gpio_set_value(phy->gpio_desc_sync, 1); + gpio_set_value(phy->gpio_desc_sync, 0); + break; + case 3: + ad9361_spi_writef(phy->spi, REG_MULTICHIP_SYNC_AND_TX_MON_CTRL, + mcs_mask, MCS_BB_ENABLE | MCS_DIGITAL_CLK_ENABLE | MCS_RF_ENABLE); + break; + case 4: + if(!phy->gpio_desc_sync) + break; + gpio_set_value(phy->gpio_desc_sync, 1); + gpio_set_value(phy->gpio_desc_sync, 0); + break; + case 5: + ad9361_spi_writef(phy->spi, REG_MULTICHIP_SYNC_AND_TX_MON_CTRL, + mcs_mask, MCS_RF_ENABLE); + break; + } + + return 0; +} + +/** + * Clear state. + * @param phy The AD9361 state structure. + * @return None. + */ +void ad9361_clear_state(struct ad9361_rf_phy *phy) +{ + phy->current_table = NO_GAIN_TABLE; + phy->bypass_tx_fir = true; + phy->bypass_rx_fir = true; + phy->rate_governor = 1; + phy->rfdc_track_en = true; + phy->bbdc_track_en = true; + phy->quad_track_en = true; + phy->prev_ensm_state = 0; + phy->curr_ensm_state = 0; + phy->auto_cal_en = false; + phy->manual_tx_quad_cal_en = false; + phy->last_tx_quad_cal_freq = 0; + phy->flags = 0; + phy->current_rx_bw_Hz = 0; + phy->current_tx_bw_Hz = 0; + phy->rxbbf_div = 0; + phy->tx_fir_int = 0; + phy->tx_fir_ntaps = 0; + phy->rx_fir_dec = 0; + phy->rx_fir_ntaps = 0; + phy->ensm_pin_ctl_en = false; + phy->txmon_tdd_en = 0; + phy->current_tx_lo_freq = 0; + phy->current_rx_lo_freq = 0; + phy->current_tx_use_tdd_table = false; + phy->current_rx_use_tdd_table = false; + phy->cached_synth_pd[0] = 0; + phy->cached_synth_pd[1] = 0; + + memset(&phy->fastlock, 0, sizeof(phy->fastlock)); +} + +/** + * Determine the reference frequency value. + * @param refin_Hz Maximum allowed frequency. + * @param max Reference in frequency value. + * @return Reference frequency value. + */ +static uint32_t ad9361_ref_div_sel(uint32_t refin_Hz, uint32_t max) +{ + if (refin_Hz <= (max / 2)) + return 2 * refin_Hz; + else if (refin_Hz <= max) + return refin_Hz; + else if (refin_Hz <= (max * 2)) + return refin_Hz / 2; + else if (refin_Hz <= (max * 4)) + return refin_Hz / 4; + else + return 0; +} + +/** + * Setup the AD9361 device. + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_setup(struct ad9361_rf_phy *phy) +{ + uint32_t refin_Hz, ref_freq, bbpll_freq; + struct spi_desc *spi = phy->spi; + struct ad9361_phy_platform_data *pd = phy->pdata; + int32_t ret; + uint32_t real_rx_bandwidth, real_tx_bandwidth; + bool tmp_use_ext_rx_lo = pd->use_ext_rx_lo; + bool tmp_use_ext_tx_lo = pd->use_ext_tx_lo; + + dev_dbg(dev, "%s", __func__); + + pd->rf_rx_bandwidth_Hz = ad9361_validate_rf_bw(phy, pd->rf_rx_bandwidth_Hz); + pd->rf_tx_bandwidth_Hz = ad9361_validate_rf_bw(phy, pd->rf_tx_bandwidth_Hz); + + real_rx_bandwidth = pd->rf_rx_bandwidth_Hz / 2; + real_tx_bandwidth = pd->rf_tx_bandwidth_Hz / 2; + + if (pd->fdd) { + pd->tdd_skip_vco_cal = false; + if (pd->ensm_pin_ctrl && pd->fdd_independent_mode) { + dev_warn(dev, + "%s: Either set ENSM PINCTRL or FDD Independent Mode", + __func__); + pd->ensm_pin_ctrl = false; + } + } + + ret = ad9361_auxdac_setup(phy, &pd->auxdac_ctrl); + if (ret < 0) + return ret; + + ret = ad9361_gpo_setup(phy, &pd->gpo_ctrl); + if (ret < 0) + return ret; + + if (pd->port_ctrl.pp_conf[2] & FDD_RX_RATE_2TX_RATE) + phy->rx_eq_2tx = true; + + ad9361_spi_write(spi, REG_CTRL, CTRL_ENABLE); + ad9361_spi_write(spi, REG_BANDGAP_CONFIG0, + MASTER_BIAS_TRIM(0x0E)); /* Enable Master Bias */ + ad9361_spi_write(spi, REG_BANDGAP_CONFIG1, + BANDGAP_TEMP_TRIM(0x0E)); /* Set Bandgap Trim */ + + ad9361_set_dcxo_tune(phy, pd->dcxo_coarse, pd->dcxo_fine); + + refin_Hz = phy->clk_refin->rate; + + ref_freq = ad9361_ref_div_sel(refin_Hz, MAX_BBPLL_FREF); + if (!ref_freq) + return -EINVAL; + + ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_1, RX_REF_RESET_BAR, 1); + ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_2, TX_REF_RESET_BAR, 1); + ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_2, + TX_REF_DOUBLER_FB_DELAY(~0), 3); /* FB DELAY */ + ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_2, + RX_REF_DOUBLER_FB_DELAY(~0), 3); /* FB DELAY */ + + ad9361_spi_write(spi, REG_CLOCK_ENABLE, + DIGITAL_POWER_UP | CLOCK_ENABLE_DFLT | BBPLL_ENABLE | + (pd->use_extclk ? XO_BYPASS : 0)); /* Enable Clocks */ + + ret = clk_set_rate(phy, phy->ref_clk_scale[BB_REFCLK], ref_freq); + if (ret < 0) { + dev_err(dev, "Failed to set BB ref clock rate (%"PRId32")", + ret); + return ret; + } + + ret = clk_prepare_enable(phy->clks[BB_REFCLK]); + if (ret < 0) { + dev_err(dev, "Failed to enable BB ref clock rate (%"PRId32")", + ret); + return ret; + } + + ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_2, 0x12); + ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_3, 0x34); + + ret = ad9361_set_trx_clock_chain(phy, pd->rx_path_clks, + pd->tx_path_clks); + if (ret < 0) + return ret; + + if (!pd->rx2tx2) { + pd->rx1tx1_mode_use_tx_num = + clamp_t(uint32_t, pd->rx1tx1_mode_use_tx_num, TX_1, TX_2); + pd->rx1tx1_mode_use_rx_num = + clamp_t(uint32_t, pd->rx1tx1_mode_use_rx_num, RX_1, RX_2); + + ad9361_en_dis_tx(phy, TX_1 | TX_2, pd->rx1tx1_mode_use_tx_num); + ad9361_en_dis_rx(phy, TX_1 | TX_2, pd->rx1tx1_mode_use_rx_num); + } else { + ad9361_en_dis_tx(phy, TX_1 | TX_2, TX_1 | TX_2); + ad9361_en_dis_rx(phy, RX_1 | RX_2, RX_1 | RX_2); + } + + ret = ad9361_rf_port_setup(phy, true, pd->rf_rx_input_sel, + pd->rf_tx_output_sel); + if (ret < 0) + return ret; + + ret = ad9361_pp_port_setup(phy, false); + if (ret < 0) + return ret; + + bbpll_freq = clk_get_rate(phy, phy->ref_clk_scale[BBPLL_CLK]); + ret = ad9361_auxadc_setup(phy, &pd->auxadc_ctrl, bbpll_freq); + if (ret < 0) + return ret; + + ret = ad9361_ctrl_outs_setup(phy, &pd->ctrl_outs_ctrl); + if (ret < 0) + return ret; + + ret = ad9361_set_ref_clk_cycles(phy, refin_Hz); + if (ret < 0) + return ret; + + ret = ad9361_setup_ext_lna(phy, &pd->elna_ctrl); + if (ret < 0) + return ret; + + /* + * This allows forcing a lower F_REF window + * (worse phase noise, better fractional spurs) + */ + pd->trx_synth_max_fref = clamp_t(uint32_t, pd->trx_synth_max_fref, + MIN_SYNTH_FREF, MAX_SYNTH_FREF); + + ref_freq = ad9361_ref_div_sel(refin_Hz, pd->trx_synth_max_fref); + if (!ref_freq) + return -EINVAL; + + ret = clk_set_rate(phy, phy->ref_clk_scale[RX_REFCLK], ref_freq); + if (ret < 0) { + dev_err(dev, "Failed to set RX Synth ref clock rate (%"PRId32")", ret); + return ret; + } + + ret = clk_set_rate(phy, phy->ref_clk_scale[TX_REFCLK], ref_freq); + if (ret < 0) { + dev_err(dev, "Failed to set TX Synth ref clock rate (%"PRId32")", ret); + return ret; + } + + ret = ad9361_txrx_synth_cp_calib(phy, ref_freq, false); /* RXCP */ + if (ret < 0) + return ret; + + ret = ad9361_txrx_synth_cp_calib(phy, ref_freq, true); /* TXCP */ + if (ret < 0) + return ret; + + phy->pdata->use_ext_rx_lo = 0; + phy->pdata->use_ext_tx_lo = 0; + + ret = clk_set_rate(phy, phy->ref_clk_scale[RX_RFPLL], + ad9361_to_clk(pd->rx_synth_freq)); + if (ret < 0) { + dev_err(dev, "Failed to set RX Synth rate (%"PRId32")", + ret); + return ret; + } + + ret = clk_prepare_enable(phy->clks[RX_REFCLK]); + if (ret < 0) { + dev_err(dev, "Failed to enable RX Synth ref clock (%"PRId32")", ret); + return ret; + } + + ret = clk_prepare_enable(phy->clks[RX_RFPLL]); + if (ret < 0) + return ret; + + /* Skip quad cal here we do it later again */ + phy->last_tx_quad_cal_freq = pd->tx_synth_freq; + ret = clk_set_rate(phy, phy->ref_clk_scale[TX_RFPLL], + ad9361_to_clk(pd->tx_synth_freq)); + if (ret < 0) { + dev_err(dev, "Failed to set TX Synth rate (%"PRId32")", + ret); + return ret; + } + + ret = clk_prepare_enable(phy->clks[TX_REFCLK]); + if (ret < 0) { + dev_err(dev, "Failed to enable TX Synth ref clock (%"PRId32")", ret); + return ret; + } + + ret = clk_prepare_enable(phy->clks[TX_RFPLL]); + if (ret < 0) + return ret; + + phy->pdata->use_ext_rx_lo = tmp_use_ext_rx_lo; + phy->pdata->use_ext_tx_lo = tmp_use_ext_tx_lo; + + ad9361_clk_mux_set_parent(phy->ref_clk_scale[RX_RFPLL], + pd->use_ext_rx_lo); + + ad9361_clk_mux_set_parent(phy->ref_clk_scale[TX_RFPLL], + pd->use_ext_tx_lo); + + ret = ad9361_load_mixer_gm_subtable(phy); + if (ret < 0) + return ret; + + ret = ad9361_gc_setup(phy, &pd->gain_ctrl); + if (ret < 0) + return ret; + + ret = ad9361_rx_bb_analog_filter_calib(phy, + real_rx_bandwidth, + bbpll_freq); + if (ret < 0) + return ret; + + ret = ad9361_tx_bb_analog_filter_calib(phy, + real_tx_bandwidth, + bbpll_freq); + if (ret < 0) + return ret; + + ret = ad9361_rx_tia_calib(phy, real_rx_bandwidth); + if (ret < 0) + return ret; + + ret = ad9361_tx_bb_second_filter_calib(phy, real_tx_bandwidth); + if (ret < 0) + return ret; + + ret = ad9361_rx_adc_setup(phy, + bbpll_freq, + clk_get_rate(phy, phy->ref_clk_scale[ADC_CLK])); + if (ret < 0) + return ret; + + ret = ad9361_bb_dc_offset_calib(phy); + if (ret < 0) + return ret; + + ret = ad9361_rf_dc_offset_calib(phy, + ad9361_from_clk(clk_get_rate(phy, phy->ref_clk_scale[RX_RFPLL]))); + if (ret < 0) + return ret; + + phy->current_rx_bw_Hz = pd->rf_rx_bandwidth_Hz; + phy->current_tx_bw_Hz = pd->rf_tx_bandwidth_Hz; + phy->last_tx_quad_cal_phase = ~0; + ret = ad9361_tx_quad_calib(phy, real_rx_bandwidth, real_tx_bandwidth, -1); + if (ret < 0) + return ret; + + ret = ad9361_tracking_control(phy, phy->bbdc_track_en, + phy->rfdc_track_en, phy->quad_track_en); + if (ret < 0) + return ret; + + ad9361_pp_port_setup(phy, true); + + ret = ad9361_set_ensm_mode(phy, pd->fdd, pd->ensm_pin_ctrl); + if (ret < 0) + return ret; + + ad9361_spi_writef(phy->spi, REG_TX_ATTEN_OFFSET, + MASK_CLR_ATTEN_UPDATE, 0); + + ret = ad9361_set_tx_atten(phy, pd->tx_atten, + pd->rx2tx2 ? true : pd->rx1tx1_mode_use_tx_num == 1, + pd->rx2tx2 ? true : pd->rx1tx1_mode_use_tx_num == 2, true); + if (ret < 0) + return ret; + + if (!pd->rx2tx2) { + ret = ad9361_set_tx_atten(phy, 89750, + pd->rx1tx1_mode_use_tx_num == 2, + pd->rx1tx1_mode_use_tx_num == 1, true); + if (ret < 0) + return ret; + } + + ret = ad9361_rssi_setup(phy, &pd->rssi_ctrl, false); + if (ret < 0) + return ret; + + ret = ad9361_clkout_control(phy, pd->ad9361_clkout_mode); + if (ret < 0) + return ret; + + ret = ad9361_txmon_setup(phy, &pd->txmon_ctrl); + if (ret < 0) + return ret; + + phy->curr_ensm_state = ad9361_spi_readf(spi, REG_STATE, ENSM_STATE(~0)); + ad9361_ensm_set_state(phy, pd->fdd ? ENSM_STATE_FDD : ENSM_STATE_RX, + pd->ensm_pin_ctrl); + + phy->auto_cal_en = true; + phy->cal_threshold_freq = 100000000ULL; /* 100 MHz */ + + return 0; + +} + +/** + * Perform the selected calibration + * @param phy The AD9361 state structure. + * @param cal The selected calibration. + * @param arg The argument of the calibration. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal, + int32_t arg) +{ + int32_t ret; + + dev_dbg(&phy->spi->dev, "%s: CAL %"PRIu32" ARG %"PRId32, __func__, cal, arg); + + ret = ad9361_tracking_control(phy, false, false, false); + if (ret < 0) + return ret; + + ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); + + switch (cal) { + case TX_QUAD_CAL: + ret = ad9361_tx_quad_calib(phy, phy->current_rx_bw_Hz / 2, + phy->current_tx_bw_Hz / 2, arg); + break; + case RFDC_CAL: + ret = ad9361_rf_dc_offset_calib(phy, + ad9361_from_clk(clk_get_rate(phy, phy->ref_clk_scale[RX_RFPLL]))); + break; + default: + ret = -EINVAL; + break; + } + + ret = ad9361_tracking_control(phy, phy->bbdc_track_en, + phy->rfdc_track_en, phy->quad_track_en); + ad9361_ensm_restore_prev_state(phy); + + return ret; +} + +/** + * Set the RF bandwidth. + * @param phy The AD9361 state structure. + * @param rf_rx_bw The desired RX bandwidth [Hz]. + * @param rf_tx_bw The desired TX bandwidth [Hz]. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, + uint32_t rf_rx_bw, uint32_t rf_tx_bw) +{ + int32_t ret; + + ret = ad9361_tracking_control(phy, false, false, false); + if (ret < 0) + return ret; + + ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); + + ret = __ad9361_update_rf_bandwidth(phy, rf_rx_bw, rf_tx_bw); + if (ret < 0) + return ret; + + phy->current_rx_bw_Hz = rf_rx_bw; + phy->current_tx_bw_Hz = rf_tx_bw; + + if (phy->manual_tx_quad_cal_en == false) { + ret = ad9361_tx_quad_calib(phy, rf_rx_bw / 2, rf_tx_bw / 2, -1); + if (ret < 0) + return ret; + } + + ret = ad9361_tracking_control(phy, phy->bbdc_track_en, + phy->rfdc_track_en, phy->quad_track_en); + if (ret < 0) + return ret; + + ad9361_ensm_restore_prev_state(phy); + + return 0; +} + +/** + * Verify the FIR filter coefficients. + * @param phy The AD9361 state structure. + * @param dest Destination identifier (RX1,2 / TX1,2). + * @param ntaps Number of filter Taps. + * @param coef Pointer to filter coefficients. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_verify_fir_filter_coef(struct ad9361_rf_phy *phy, + enum fir_dest dest, + uint32_t ntaps, short *coef) +{ + struct spi_desc *spi = phy->spi; + uint32_t val, offs = 0, gain = 0, conf, sel, cnt; + int32_t ret = 0; + +#ifndef DEBUG + return 0; +#endif + dev_dbg(&phy->spi->dev, "%s: TAPS %"PRIu32", dest %d", + __func__, ntaps, dest); + + if (dest & FIR_IS_RX) { + gain = ad9361_spi_read(spi, REG_RX_FILTER_GAIN); + offs = REG_RX_FILTER_COEF_ADDR - REG_TX_FILTER_COEF_ADDR; + ad9361_spi_write(spi, REG_RX_FILTER_GAIN, 0); + } + + conf = ad9361_spi_read(spi, REG_TX_FILTER_CONF + offs); + + if ((dest & 3) == 3) { + sel = 1; + cnt = 2; + } else { + sel = (dest & 3); + cnt = 1; + } + + for (; cnt > 0; cnt--, sel++) { + + ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, + FIR_NUM_TAPS(ntaps / 16 - 1) | + FIR_SELECT(sel) | FIR_START_CLK); + for (val = 0; val < ntaps; val++) { + short tmp; + ad9361_spi_write(spi, REG_TX_FILTER_COEF_ADDR + offs, val); + + tmp = (ad9361_spi_read(spi, REG_TX_FILTER_COEF_READ_DATA_1 + offs) & 0xFF) | + (ad9361_spi_read(spi, REG_TX_FILTER_COEF_READ_DATA_2 + offs) << 8); + + if (tmp != coef[val]) { + dev_err(&phy->spi->dev,"%s%"PRIu32" read verify failed TAP%"PRIu32" %d =! %d", + (dest & FIR_IS_RX) ? "RX" : "TX", sel, + val, tmp, coef[val]); + ret = -EIO; + } + } + } + + if (dest & FIR_IS_RX) { + ad9361_spi_write(spi, REG_RX_FILTER_GAIN, gain); + } + + ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, conf); + + return ret; +} + +/** + * Load the FIR filter coefficients. + * @param phy The AD9361 state structure. + * @param dest Destination identifier (RX1,2 / TX1,2). + * @param gain_dB Gain option. + * @param ntaps Number of filter Taps. + * @param coef Pointer to filter coefficients. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy, + enum fir_dest dest, int32_t gain_dB, + uint32_t ntaps, int16_t *coef) +{ + struct spi_desc *spi = phy->spi; + uint32_t val, offs = 0, fir_conf = 0, fir_enable = 0; + int32_t ret; + + dev_dbg(&phy->spi->dev, "%s: TAPS %"PRIu32", gain %"PRId32", dest %d", + __func__, ntaps, gain_dB, dest); + + if (coef == NULL || !ntaps || ntaps > 128 || ntaps % 16) { + dev_err(&phy->spi->dev, + "%s: Invalid parameters: TAPS %"PRIu32", gain %"PRId32", dest 0x%X", + __func__, ntaps, gain_dB, dest); + + return -EINVAL; + } + + ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); + + if (dest & FIR_IS_RX) { + val = 3 - (gain_dB + 12) / 6; + ad9361_spi_write(spi, REG_RX_FILTER_GAIN, val & 0x3); + offs = REG_RX_FILTER_COEF_ADDR - REG_TX_FILTER_COEF_ADDR; + phy->rx_fir_ntaps = ntaps; + fir_enable = ad9361_spi_readf(phy->spi, + REG_RX_ENABLE_FILTER_CTRL, RX_FIR_ENABLE_DECIMATION(~0)); + ad9361_spi_writef(phy->spi, REG_RX_ENABLE_FILTER_CTRL, + RX_FIR_ENABLE_DECIMATION(~0), + (phy->rx_fir_dec == 4) ? 3 : phy->rx_fir_dec); + } else { + if (gain_dB == -6) + fir_conf = TX_FIR_GAIN_6DB; + phy->tx_fir_ntaps = ntaps; + fir_enable = ad9361_spi_readf(phy->spi, + REG_TX_ENABLE_FILTER_CTRL, TX_FIR_ENABLE_INTERPOLATION(~0)); + ad9361_spi_writef(phy->spi, REG_TX_ENABLE_FILTER_CTRL, + TX_FIR_ENABLE_INTERPOLATION(~0), + (phy->tx_fir_int == 4) ? 3 : phy->tx_fir_int); + } + + val = ntaps / 16 - 1; + + fir_conf |= FIR_NUM_TAPS(val) | FIR_SELECT(dest) | FIR_START_CLK; + + ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, fir_conf); + + for (val = 0; val < ntaps; val++) { + ad9361_spi_write(spi, REG_TX_FILTER_COEF_ADDR + offs, val); + ad9361_spi_write(spi, REG_TX_FILTER_COEF_WRITE_DATA_1 + offs, + coef[val] & 0xFF); + ad9361_spi_write(spi, REG_TX_FILTER_COEF_WRITE_DATA_2 + offs, + coef[val] >> 8); + ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, + fir_conf | FIR_WRITE); + ad9361_spi_write(spi, REG_TX_FILTER_COEF_READ_DATA_2 + offs, 0); + ad9361_spi_write(spi, REG_TX_FILTER_COEF_READ_DATA_2 + offs, 0); + } + + ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, fir_conf); + fir_conf &= ~FIR_START_CLK; + ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, fir_conf); + + ret = ad9361_verify_fir_filter_coef(phy, dest, ntaps, coef); + + if (dest & FIR_IS_RX) + ad9361_spi_writef(phy->spi, REG_RX_ENABLE_FILTER_CTRL, + RX_FIR_ENABLE_DECIMATION(~0), fir_enable); + else + ad9361_spi_writef(phy->spi, REG_TX_ENABLE_FILTER_CTRL, + TX_FIR_ENABLE_INTERPOLATION(~0), fir_enable); + + ad9361_ensm_restore_prev_state(phy); + + return ret; +} + +/** + * Parse the FIR filter file/buffer. + * @param phy The AD9361 state structure. + * @param data Pointer to buffer. + * @param size Buffer size. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_parse_fir(struct ad9361_rf_phy *phy, + char *data, uint32_t size) +{ + char *line; + int32_t i = 0, ret, txc, rxc; + int32_t tx = -1, tx_gain = 0, tx_int = 0; + int32_t rx = -1, rx_gain = 0, rx_dec = 0; + int32_t rtx = -1, rrx = -1; + int16_t coef_tx[128]; + int16_t coef_rx[128]; + char *ptr = data; + + phy->filt_rx_bw_Hz = 0; + phy->filt_tx_bw_Hz = 0; + phy->filt_valid = false; + + while ((line = strsep(&ptr, "\n"))) { + if (line >= data + size) { + break; + } + + if (line[0] == '#') + continue; + + if (tx < 0) { +#ifdef WIN32 + ret = sscanf_s(line, "TX %d GAIN %d INT %d", + &tx, &tx_gain, &tx_int); +#else + ret = sscanf(line, "TX %"PRId32" GAIN %"PRId32" INT %"PRId32, + &tx, &tx_gain, &tx_int); +#endif + if (ret == 3) + continue; + else + tx = -1; + } + if (rx < 0) { +#ifdef WIN32 + ret = sscanf_s(line, "RX %d GAIN %d DEC %d", + &rx, &rx_gain, &rx_dec); +#else + ret = sscanf(line, "RX %"PRId32" GAIN %"PRId32" DEC %"PRId32, + &rx, &rx_gain, &rx_dec); +#endif + if (ret == 3) + continue; + else + tx = -1; + } + + if (rtx < 0) { +#ifdef WIN32 + ret = sscanf(line, "RTX %lu %lu %lu %lu %lu %lu", +#else + ret = sscanf(line, + "RTX %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32, +#endif + &phy->filt_tx_path_clks[0], + &phy->filt_tx_path_clks[1], + &phy->filt_tx_path_clks[2], + &phy->filt_tx_path_clks[3], + &phy->filt_tx_path_clks[4], + &phy->filt_tx_path_clks[5]); + if (ret == 6) { + rtx = 0; + continue; + } else { + rtx = -1; + } + } + + if (rrx < 0) { +#ifdef WIN32 + ret = sscanf(line, "RRX %lu %lu %lu %lu %lu %lu", +#else + ret = sscanf(line, + "RRX %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32, +#endif + &phy->filt_rx_path_clks[0], + &phy->filt_rx_path_clks[1], + &phy->filt_rx_path_clks[2], + &phy->filt_rx_path_clks[3], + &phy->filt_rx_path_clks[4], + &phy->filt_rx_path_clks[5]); + if (ret == 6) { + rrx = 0; + continue; + } else { + rrx = -1; + } + } + + if (!phy->filt_rx_bw_Hz) { +#ifdef WIN32 + ret = sscanf(line, "BWRX %d", &phy->filt_rx_bw_Hz); +#else + ret = sscanf(line, "BWRX %"PRId32, &phy->filt_rx_bw_Hz); +#endif + if (ret == 1) + continue; + else + phy->filt_rx_bw_Hz = 0; + } + + if (!phy->filt_tx_bw_Hz) { +#ifdef WIN32 + ret = sscanf(line, "BWTX %d", &phy->filt_tx_bw_Hz); +#else + ret = sscanf(line, "BWTX %"PRId32, &phy->filt_tx_bw_Hz); +#endif + if (ret == 1) + continue; + else + phy->filt_tx_bw_Hz = 0; + } + +#ifdef WIN32 + ret = sscanf_s(line, "%d,%d", &txc, &rxc); +#else + ret = sscanf(line, "%"PRId32",%"PRId32, &txc, &rxc); +#endif + if (ret == 1) { + coef_tx[i] = coef_rx[i] = (int16_t)txc; + i++; + continue; + } else if (ret == 2) { + coef_tx[i] = (int16_t)txc; + coef_rx[i] = (int16_t)rxc; + i++; + continue; + } + } + + switch (tx) { + case FIR_TX1: + case FIR_TX2: + case FIR_TX1_TX2: + phy->tx_fir_int = tx_int; + ret = ad9361_load_fir_filter_coef(phy, (enum fir_dest)tx, tx_gain, i, coef_tx); + break; + default: + ret = -EINVAL; + } + + switch (rx | FIR_IS_RX) { + case FIR_RX1: + case FIR_RX2: + case FIR_RX1_RX2: + phy->rx_fir_dec = rx_dec; + ret = ad9361_load_fir_filter_coef(phy, (enum fir_dest)(rx | FIR_IS_RX), + rx_gain, i, coef_rx); + break; + default: + ret = -EINVAL; + } + + if (ret < 0) + return ret; + + if (!(rrx | rtx)) + phy->filt_valid = true; + + return size; +} + +/** + * Validate FIR filter configuration - on pass enable. + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_validate_enable_fir(struct ad9361_rf_phy *phy) +{ + int32_t ret; + uint32_t rx[6], tx[6]; + uint32_t max, min, valid; + + dev_dbg(dev, "%s: TX FIR EN=%d/TAPS%d/INT%d, RX FIR EN=%d/TAPS%d/DEC%d", + __func__, !phy->bypass_tx_fir, phy->tx_fir_ntaps, phy->tx_fir_int, + !phy->bypass_rx_fir, phy->rx_fir_ntaps, phy->rx_fir_dec); + + if (!phy->bypass_tx_fir) { + if (!(phy->tx_fir_int == 1 || phy->tx_fir_int == 2 || + phy->tx_fir_int == 4)) { + dev_err(dev, + "%s: Invalid: Interpolation %d in filter config", + __func__, phy->tx_fir_int); + return -EINVAL; + } + + + if (phy->tx_fir_int == 1 && phy->tx_fir_ntaps > 64) { + dev_err(dev, + "%s: Invalid: TAPS > 64 and Interpolation = 1", + __func__); + return -EINVAL; + } + } + + if (!phy->bypass_rx_fir) { + if (!(phy->rx_fir_dec == 1 || phy->rx_fir_dec == 2 || + phy->rx_fir_dec == 4)) { + dev_err(dev, + "%s: Invalid: Decimation %d in filter config", + __func__, phy->rx_fir_dec); + + return -EINVAL; + } + } + + if (!phy->filt_valid || phy->bypass_rx_fir || phy->bypass_tx_fir) { + ret = ad9361_calculate_rf_clock_chain(phy, + clk_get_rate(phy, phy->ref_clk_scale[TX_SAMPL_CLK]), + phy->rate_governor, rx, tx); + if (ret < 0) { + min = phy->rate_governor ? 1500000U : 1000000U; + dev_err(dev, + "%s: Calculating filter rates failed %"PRId32 + " using min frequency",__func__, ret); + ret = ad9361_calculate_rf_clock_chain(phy, min, + phy->rate_governor, rx, tx); + if (ret < 0) { + return ret; + } + } + valid = false; + } else { +#ifndef ALTERA_PLATFORM + memcpy(rx, phy->filt_rx_path_clks, sizeof(rx)); + memcpy(tx, phy->filt_tx_path_clks, sizeof(tx)); +#else + int32_t i; + uint32_t num; + num = sizeof(rx) / sizeof(rx[0]); + for (i = 0; i < num; i++) + rx[i] = phy->filt_rx_path_clks[i]; + num = sizeof(tx) / sizeof(rx[0]); + for (i = 0; i < num; i++) + tx[i] = phy->filt_tx_path_clks[i]; +#endif + valid = true; + + } + +#ifdef _DEBUG + dev_dbg(&phy->spi->dev, + "%s:RX %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32, + __func__, rx[BBPLL_FREQ], rx[ADC_FREQ], + rx[R2_FREQ], rx[R1_FREQ], + rx[CLKRF_FREQ], rx[RX_SAMPL_FREQ]); + + dev_dbg(&phy->spi->dev, + "%s:TX %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32" %"PRIu32, + __func__, tx[BBPLL_FREQ], tx[ADC_FREQ], + tx[R2_FREQ], tx[R1_FREQ], + tx[CLKRF_FREQ], tx[RX_SAMPL_FREQ]); +#endif + + if (!phy->bypass_tx_fir) { + max = (tx[DAC_FREQ] / tx[TX_SAMPL_FREQ]) * 16; + if (phy->tx_fir_ntaps > max) { + dev_err(dev, + "%s: Invalid: ratio DAC / TX_SAMPL * 16 > TAPS" + "(max %"PRIu32", adc %"PRIu32", tx %"PRIu32")", + __func__, max, tx[DAC_FREQ], tx[TX_SAMPL_FREQ]); + return -EINVAL; + } + } + + if (!phy->bypass_rx_fir) { + max = ((rx[ADC_FREQ] / ((rx[ADC_FREQ] == rx[R2_FREQ]) ? 1 : 2)) / + rx[RX_SAMPL_FREQ]) * 16; + if (phy->rx_fir_ntaps > max) { + dev_err(dev, + "%s: Invalid: ratio ADC/2 / RX_SAMPL * 16 > TAPS (max %"PRIu32")", + __func__, max); + return -EINVAL; + } + } + + ret = ad9361_set_trx_clock_chain(phy, rx, tx); + if (ret < 0) + return ret; + + /* See also: ad9361_set_trx_clock_chain() */ + if (!phy->pdata->dig_interface_tune_fir_disable && + phy->bypass_tx_fir && phy->bypass_rx_fir) + ad9361_dig_tune(phy, 0, RESTORE_DEFAULT); + + return ad9361_update_rf_bandwidth(phy, + valid ? phy->filt_rx_bw_Hz : phy->current_rx_bw_Hz, + valid ? phy->filt_tx_bw_Hz : phy->current_tx_bw_Hz); +} + +/* +* AD9361 Clocks +*/ + +/** +* Set the multiplier and the divider for the selected refclk_scale structure. +* @param priv The selected refclk_scale structure. +* @param mul The multiplier value. +* @param div The divider value. +* @return 0 in case of success, negative error code otherwise. +*/ +static inline int32_t ad9361_set_muldiv(struct refclk_scale *priv, uint32_t mul, + uint32_t div) +{ + priv->mult = mul; + priv->div = div; + return 0; +} + +/** + * Get the clk scaler for the selected refclk_scale structure. + * @param priv The selected refclk_scale structure. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_get_clk_scaler(struct refclk_scale *clk_priv) +{ + struct spi_desc *spi = clk_priv->spi; + uint32_t tmp, tmp1; + + switch (clk_priv->source) { + case BB_REFCLK: + tmp = ad9361_spi_read(spi, REG_CLOCK_CTRL); + tmp &= 0x3; + break; + case RX_REFCLK: + tmp = ad9361_spi_readf(spi, REG_REF_DIVIDE_CONFIG_1, + RX_REF_DIVIDER_MSB); + tmp1 = ad9361_spi_readf(spi, REG_REF_DIVIDE_CONFIG_2, + RX_REF_DIVIDER_LSB); + tmp = (tmp << 1) | tmp1; + break; + case TX_REFCLK: + tmp = ad9361_spi_readf(spi, REG_REF_DIVIDE_CONFIG_2, + TX_REF_DIVIDER(~0)); + break; + case ADC_CLK: + tmp = ad9361_spi_read(spi, REG_BBPLL); + return ad9361_set_muldiv(clk_priv, 1, 1 << (tmp & 0x7)); + case R2_CLK: + tmp = ad9361_spi_readf(spi, REG_RX_ENABLE_FILTER_CTRL, + DEC3_ENABLE_DECIMATION(~0)); + return ad9361_set_muldiv(clk_priv, 1, tmp + 1); + case R1_CLK: + tmp = ad9361_spi_readf(spi, REG_RX_ENABLE_FILTER_CTRL, RHB2_EN); + return ad9361_set_muldiv(clk_priv, 1, tmp + 1); + case CLKRF_CLK: + tmp = ad9361_spi_readf(spi, REG_RX_ENABLE_FILTER_CTRL, RHB1_EN); + return ad9361_set_muldiv(clk_priv, 1, tmp + 1); + case RX_SAMPL_CLK: + tmp = ad9361_spi_readf(spi, REG_RX_ENABLE_FILTER_CTRL, + RX_FIR_ENABLE_DECIMATION(~0)); + + if (!tmp) + tmp = 1; /* bypass filter */ + else + tmp = (1 << (tmp - 1)); + + return ad9361_set_muldiv(clk_priv, 1, tmp); + case DAC_CLK: + tmp = ad9361_spi_readf(spi, REG_BBPLL, BIT(3)); + return ad9361_set_muldiv(clk_priv, 1, tmp + 1); + case T2_CLK: + tmp = ad9361_spi_readf(spi, REG_TX_ENABLE_FILTER_CTRL, + THB3_ENABLE_INTERP(~0)); + return ad9361_set_muldiv(clk_priv, 1, tmp + 1); + case T1_CLK: + tmp = ad9361_spi_readf(spi, REG_TX_ENABLE_FILTER_CTRL, THB2_EN); + return ad9361_set_muldiv(clk_priv, 1, tmp + 1); + case CLKTF_CLK: + tmp = ad9361_spi_readf(spi, REG_TX_ENABLE_FILTER_CTRL, THB1_EN); + return ad9361_set_muldiv(clk_priv, 1, tmp + 1); + case TX_SAMPL_CLK: + tmp = ad9361_spi_readf(spi, REG_TX_ENABLE_FILTER_CTRL, + TX_FIR_ENABLE_INTERPOLATION(~0)); + + if (!tmp) + tmp = 1; /* bypass filter */ + else + tmp = (1 << (tmp - 1)); + + return ad9361_set_muldiv(clk_priv, 1, tmp); + default: + return -EINVAL; + } + + /* REFCLK Scaler */ + switch (tmp) { + case 0: + ad9361_set_muldiv(clk_priv, 1, 1); + break; + case 1: + ad9361_set_muldiv(clk_priv, 1, 2); + break; + case 2: + ad9361_set_muldiv(clk_priv, 1, 4); + break; + case 3: + ad9361_set_muldiv(clk_priv, 2, 1); + break; + default: + return -EINVAL; + + } + + return 0; +} + +/** + * Calculate the REFCLK Scaler for the selected refclk_scale structure. + * Note: REFCLK Scaler values - 00: x1; 01: x½; 10: x¼; 11: x2. + * @param clk_priv The selected refclk_scale structure. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_to_refclk_scaler(struct refclk_scale *clk_priv) +{ + /* REFCLK Scaler */ + switch (((clk_priv->mult & 0xF) << 4) | (clk_priv->div & 0xF)) { + case 0x11: + return 0; + case 0x12: + return 1; + case 0x14: + return 2; + case 0x21: + return 3; + default: + return -EINVAL; + } +}; + +/** + * Set clk scaler for the selected refclk_scale structure. + * @param clk_priv The selected refclk_scale structure. + * @param set Set true, the reference clock frequency will be scaled before + * it enters the BBPLL. + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad9361_set_clk_scaler(struct refclk_scale *clk_priv, bool set) +{ + struct spi_desc *spi = clk_priv->spi; + uint32_t tmp; + int32_t ret; + + switch (clk_priv->source) { + case BB_REFCLK: + ret = ad9361_to_refclk_scaler(clk_priv); + if (ret < 0) + return ret; + if (set) + return ad9361_spi_writef(spi, REG_CLOCK_CTRL, + REF_FREQ_SCALER(~0), ret); + break; + + case RX_REFCLK: + ret = ad9361_to_refclk_scaler(clk_priv); + if (ret < 0) + return ret; + if (set) { + tmp = ret; + ret = ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_1, + RX_REF_DIVIDER_MSB, tmp >> 1); + ret |= ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_2, + RX_REF_DIVIDER_LSB, tmp & 1); + return ret; + } + break; + case TX_REFCLK: + ret = ad9361_to_refclk_scaler(clk_priv); + if (ret < 0) + return ret; + if (set) + return ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_2, + TX_REF_DIVIDER(~0), ret); + break; + case ADC_CLK: + tmp = ilog2((uint8_t)clk_priv->div); + if (clk_priv->mult != 1 || tmp > 6 || tmp < 1) + return -EINVAL; + + if (set) + return ad9361_spi_writef(spi, REG_BBPLL, 0x7, tmp); + break; + case R2_CLK: + if (clk_priv->mult != 1 || clk_priv->div > 3 || clk_priv->div < 1) + return -EINVAL; + if (set) + return ad9361_spi_writef(spi, REG_RX_ENABLE_FILTER_CTRL, + DEC3_ENABLE_DECIMATION(~0), + clk_priv->div - 1); + break; + case R1_CLK: + if (clk_priv->mult != 1 || clk_priv->div > 2 || clk_priv->div < 1) + return -EINVAL; + if (set) + return ad9361_spi_writef(spi, REG_RX_ENABLE_FILTER_CTRL, + RHB2_EN, clk_priv->div - 1); + break; + case CLKRF_CLK: + if (clk_priv->mult != 1 || clk_priv->div > 2 || clk_priv->div < 1) + return -EINVAL; + if (set) + return ad9361_spi_writef(spi, REG_RX_ENABLE_FILTER_CTRL, + RHB1_EN, clk_priv->div - 1); + break; + case RX_SAMPL_CLK: + if (clk_priv->mult != 1 || clk_priv->div > 4 || + clk_priv->div < 1 || clk_priv->div == 3) + return -EINVAL; + + if (clk_priv->phy->bypass_rx_fir) + tmp = 0; + else + tmp = ilog2(clk_priv->div) + 1; + + if (set) + return ad9361_spi_writef(spi, REG_RX_ENABLE_FILTER_CTRL, + RX_FIR_ENABLE_DECIMATION(~0), tmp); + break; + case DAC_CLK: + if (clk_priv->mult != 1 || clk_priv->div > 2 || clk_priv->div < 1) + return -EINVAL; + if (set) + return ad9361_spi_writef(spi, REG_BBPLL, + BIT(3), clk_priv->div - 1); + break; + case T2_CLK: + if (clk_priv->mult != 1 || clk_priv->div > 3 || clk_priv->div < 1) + return -EINVAL; + if (set) + return ad9361_spi_writef(spi, REG_TX_ENABLE_FILTER_CTRL, + THB3_ENABLE_INTERP(~0), + clk_priv->div - 1); + break; + case T1_CLK: + if (clk_priv->mult != 1 || clk_priv->div > 2 || clk_priv->div < 1) + return -EINVAL; + if (set) + return ad9361_spi_writef(spi, REG_TX_ENABLE_FILTER_CTRL, + THB2_EN, clk_priv->div - 1); + break; + case CLKTF_CLK: + if (clk_priv->mult != 1 || clk_priv->div > 2 || clk_priv->div < 1) + return -EINVAL; + if (set) + return ad9361_spi_writef(spi, REG_TX_ENABLE_FILTER_CTRL, + THB1_EN, clk_priv->div - 1); + break; + case TX_SAMPL_CLK: + if (clk_priv->mult != 1 || clk_priv->div > 4 || + clk_priv->div < 1 || clk_priv->div == 3) + return -EINVAL; + + if (clk_priv->phy->bypass_tx_fir) + tmp = 0; + else + tmp = ilog2(clk_priv->div) + 1; + + if (set) + return ad9361_spi_writef(spi, REG_TX_ENABLE_FILTER_CTRL, + TX_FIR_ENABLE_INTERPOLATION(~0), tmp); + break; + default: + return -EINVAL; + } + + return 0; +} + +/** + * Recalculate the clock rate. + * @param clk_priv The refclk_scale structure. + * @param parent_rate The parent clock rate. + * @return The clock rate. + */ +uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, + uint32_t parent_rate) +{ + uint64_t rate; + + ad9361_get_clk_scaler(clk_priv); + rate = (parent_rate * clk_priv->mult) / clk_priv->div; + + return (uint32_t)rate; +} + +/** + * Calculate the closest possible clock rate that can be set. + * @param clk_priv The refclk_scale structure. + * @param rate The clock rate. + * @param prate The parent clock rate. + * @return The closest possible clock rate that can be set. + */ +int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, + uint32_t rate, + uint32_t *prate) +{ + int32_t ret; + + if (rate >= *prate) { + clk_priv->mult = DIV_ROUND_CLOSEST(rate, *prate); + clk_priv->div = 1; + + } else { + clk_priv->div = DIV_ROUND_CLOSEST(*prate, rate); + clk_priv->mult = 1; + if (!clk_priv->div) { + dev_err(&clk_priv->spi->dev, "%s: divide by zero", + __func__); + clk_priv->div = 1; + } + } + + ret = ad9361_set_clk_scaler(clk_priv, false); + if (ret < 0) + return ret; + + return (*prate / clk_priv->div) * clk_priv->mult; +} + +/** + * Set the clock rate. + * @param clk_priv The refclk_scale structure. + * @param rate The clock rate. + * @param parent_rate The parent clock rate. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, + uint32_t parent_rate) +{ + dev_dbg(&clk_priv->spi->dev, "%s: Rate %"PRIu32" Hz Parent Rate %"PRIu32" Hz", + __func__, rate, parent_rate); + + if (rate >= parent_rate) { + clk_priv->mult = DIV_ROUND_CLOSEST(rate, parent_rate); + clk_priv->div = 1; + } else { + clk_priv->div = DIV_ROUND_CLOSEST(parent_rate, rate); + clk_priv->mult = 1; + if (!clk_priv->div) { + dev_err(&clk_priv->spi->dev, "%s: divide by zero", + __func__); + clk_priv->div = 1; + } + } + + return ad9361_set_clk_scaler(clk_priv, true); +} + +/* + * BBPLL + */ +/** + * Recalculate the clock rate. + * @param clk_priv The refclk_scale structure. + * @param parent_rate The parent clock rate. + * @return The clock rate. + */ +uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, + uint32_t parent_rate) +{ + uint64_t rate; + uint32_t fract, integer; + uint8_t buf[4]; + + ad9361_spi_readm(clk_priv->spi, REG_INTEGER_BB_FREQ_WORD, &buf[0], + REG_INTEGER_BB_FREQ_WORD - REG_FRACT_BB_FREQ_WORD_1 + 1); + + fract = (buf[3] << 16) | (buf[2] << 8) | buf[1]; + integer = buf[0]; + + rate = ((uint64_t)parent_rate * fract); + do_div(&rate, BBPLL_MODULUS); + rate += (uint64_t)parent_rate * integer; + + return (uint32_t)rate; +} + +/** + * Calculate the closest possible clock rate that can be set. + * @param clk_priv The refclk_scale structure. + * @param rate The clock rate. + * @param prate The parent clock rate. + * @return The closest possible clock rate that can be set. + */ +int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate, + uint32_t *prate) +{ + uint64_t tmp; + uint32_t fract, integer; + uint64_t temp; + + if (clk_priv) { + // Unused variable - fix compiler warning + } + + if (rate > MAX_BBPLL_FREQ) + return MAX_BBPLL_FREQ; + + if (rate < MIN_BBPLL_FREQ) + return MIN_BBPLL_FREQ; + + temp = rate; + tmp = do_div(&temp, *prate); + rate = temp; + tmp = tmp * BBPLL_MODULUS + (*prate >> 1); + do_div(&tmp, *prate); + + integer = rate; + fract = tmp; + + tmp = *prate * (uint64_t)fract; + do_div(&tmp, BBPLL_MODULUS); + tmp += *prate * integer; + + return tmp; +} + +/** + * Set the clock rate. + * @param clk_priv The refclk_scale structure. + * @param rate The clock rate. + * @param parent_rate The parent clock rate. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate, + uint32_t parent_rate) +{ + struct spi_desc *spi = clk_priv->spi; + uint64_t tmp; + uint32_t fract, integer; + int32_t icp_val; + uint8_t lf_defaults[3] = { 0x35, 0x5B, 0xE8 }; + uint64_t temp; + + dev_dbg(&spi->dev, "%s: Rate %"PRIu32" Hz Parent Rate %"PRIu32" Hz", + __func__, rate, parent_rate); + + /* + * Setup Loop Filter and CP Current + * Scale is 150uA @ (1280MHz BBPLL, 40MHz REFCLK) + */ + tmp = (rate >> 7) * 150ULL; + do_div(&tmp, (parent_rate >> 7) * 32UL); + + /* 25uA/LSB, Offset 25uA */ + icp_val = DIV_ROUND_CLOSEST((uint32_t)tmp, 25U) - 1; + + icp_val = clamp(icp_val, 1, 64); + + ad9361_spi_write(spi, REG_CP_CURRENT, icp_val); + ad9361_spi_writem(spi, REG_LOOP_FILTER_3, lf_defaults, + ARRAY_SIZE(lf_defaults)); + + /* Allow calibration to occur and set cal count to 1024 for max accuracy */ + ad9361_spi_write(spi, REG_VCO_CTRL, + FREQ_CAL_ENABLE | FREQ_CAL_COUNT_LENGTH(3)); + /* Set calibration clock to REFCLK/4 for more accuracy */ + ad9361_spi_write(spi, REG_SDM_CTRL, 0x10); + + /* Calculate and set BBPLL frequency word */ + temp = rate; + tmp = do_div(&temp, parent_rate); + rate = temp; + tmp = tmp *(uint64_t)BBPLL_MODULUS + (parent_rate >> 1); + do_div(&tmp, parent_rate); + + integer = rate; + fract = tmp; + + ad9361_spi_write(spi, REG_INTEGER_BB_FREQ_WORD, integer); + ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_3, fract); + ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_2, fract >> 8); + ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_1, fract >> 16); + + ad9361_spi_write(spi, REG_SDM_CTRL_1, + INIT_BB_FO_CAL | BBPLL_RESET_BAR); /* Start BBPLL Calibration */ + ad9361_spi_write(spi, REG_SDM_CTRL_1, + BBPLL_RESET_BAR); /* Clear BBPLL start calibration bit */ + + ad9361_spi_write(spi, REG_VCO_PROGRAM_1, + 0x86); /* Increase BBPLL KV and phase margin */ + ad9361_spi_write(spi, REG_VCO_PROGRAM_2, + 0x01); /* Increase BBPLL KV and phase margin */ + ad9361_spi_write(spi, REG_VCO_PROGRAM_2, + 0x05); /* Increase BBPLL KV and phase margin */ + + return ad9361_check_cal_done(clk_priv->phy, REG_CH_1_OVERFLOW, + BBPLL_LOCK, 1); +} + +/* + * RFPLL + */ + +/** + * Calculate the RFPLL frequency. + * @param parent_rate The parent clock rate. + * @param integer The integer value. + * @param fract The fractional value. + * @param vco_div The VCO divider. + * @return The RFPLL frequency. + */ +static uint64_t ad9361_calc_rfpll_int_freq(uint64_t parent_rate, + uint64_t integer, + uint64_t fract, uint32_t vco_div) +{ + uint64_t rate; + + rate = parent_rate * fract; + do_div(&rate, RFPLL_MODULUS); + rate += parent_rate * integer; + + return rate >> (vco_div + 1); +} + +/** + * Calculate the RFPLL dividers. + * @param phy The AD9361 state structure. + * @param clk_priv The refclk_scale structure. + * @param freq The RFPLL frequency. + * @param parent_rate The parent clock rate. + * @param integer The integer value. + * @param fract The fractional value. + * @param vco_div The VCO divider. + * @param vco_freq The VCO frequency. + * @return The RFPLL frequency. + */ +static int32_t ad9361_calc_rfpll_int_divder(struct ad9361_rf_phy *phy, + struct refclk_scale *clk_priv, uint64_t freq, + uint64_t parent_rate, uint32_t *integer, + uint32_t *fract, int32_t *vco_div, uint64_t *vco_freq) +{ + uint64_t tmp; + int32_t div, ret; + + ret = ad9361_validate_rfpll(phy, clk_priv->source == TX_RFPLL_INT, freq); + if (ret) + return ret; + + div = -1; + + while (freq <= MIN_VCO_FREQ_HZ) { + freq <<= 1; + div++; + } + + *vco_div = div; + *vco_freq = freq; + tmp = do_div(&freq, parent_rate); + tmp = tmp * RFPLL_MODULUS + (parent_rate >> 1); + do_div(&tmp, parent_rate); + *integer = freq; + *fract = tmp; + + return 0; +} + +/** + * Recalculate the clock rate. + * @param clk_priv The refclk_scale structure. + * @param parent_rate The parent clock rate. + * @return The clock rate. + */ +uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, + uint32_t parent_rate) +{ + struct ad9361_rf_phy *phy = clk_priv->phy; + uint32_t fract, integer; + uint8_t buf[5]; + uint32_t reg, div_mask, vco_div, profile; + + dev_dbg(&clk_priv->spi->dev, "%s: Parent Rate %"PRIu32" Hz", + __func__, parent_rate); + + switch (clk_priv->source) { + case RX_RFPLL_INT: + reg = REG_RX_FRACT_BYTE_2; + div_mask = RX_VCO_DIVIDER(~0); + profile = phy->fastlock.current_profile[0]; + break; + case TX_RFPLL_INT: + reg = REG_TX_FRACT_BYTE_2; + div_mask = TX_VCO_DIVIDER(~0); + profile = phy->fastlock.current_profile[1]; + break; + default: + return -EINVAL; + } + + if (profile) { + bool tx = clk_priv->source == TX_RFPLL_INT; + profile = profile - 1; + + buf[0] = ad9361_fastlock_readval(phy->spi, tx, profile, 4); + buf[1] = ad9361_fastlock_readval(phy->spi, tx, profile, 3); + buf[2] = ad9361_fastlock_readval(phy->spi, tx, profile, 2); + buf[3] = ad9361_fastlock_readval(phy->spi, tx, profile, 1); + buf[4] = ad9361_fastlock_readval(phy->spi, tx, profile, 0); + vco_div = ad9361_fastlock_readval(phy->spi, tx, profile, 12) & 0xF; + + } else { + ad9361_spi_readm(clk_priv->spi, reg, &buf[0], ARRAY_SIZE(buf)); + vco_div = ad9361_spi_readf(clk_priv->spi, REG_RFPLL_DIVIDERS, div_mask); + } + + fract = (SYNTH_FRACT_WORD(buf[0]) << 16) | (buf[1] << 8) | buf[2]; + integer = (SYNTH_INTEGER_WORD(buf[3]) << 8) | buf[4]; + + return ad9361_to_clk(ad9361_calc_rfpll_int_freq(parent_rate, integer, + fract, vco_div)); +} + +/** + * Calculate the closest possible clock rate that can be set. + * @param clk_priv The refclk_scale structure. + * @param rate The clock rate. + * @param prate The parent clock rate. + * @return The closest possible clock rate that can be set. + */ +int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, + uint32_t rate, + uint32_t *prate) +{ + dev_dbg(&clk_priv->spi->dev, "%s: Rate %"PRIu32" Hz", __func__, rate); + + if (prate) { + // Unused variable - fix compiler warning + } + + if (clk_priv) { + // Unused variable - fix compiler warning + } + + if (ad9361_from_clk(rate) > MAX_CARRIER_FREQ_HZ || + ad9361_from_clk(rate) < ((clk_priv->source == TX_RFPLL_INT) ? + MIN_TX_CARRIER_FREQ_HZ : MIN_RX_CARRIER_FREQ_HZ)) + return -EINVAL; + + return rate; +} + +/** + * Set the clock rate. + * @param clk_priv The refclk_scale structure. + * @param rate The clock rate. + * @param parent_rate The parent clock rate. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, + uint32_t parent_rate) +{ + struct ad9361_rf_phy *phy = clk_priv->phy; + uint64_t vco = 0; + uint8_t buf[5]; + uint32_t reg, div_mask, lock_reg, fract = 0, integer = 0; + int32_t vco_div, ret, fixup_other; + + dev_dbg(&clk_priv->spi->dev, + "%s: %s Rate %"PRIu32" Hz Parent Rate %"PRIu32" Hz", + __func__, clk_priv->source == TX_RFPLL_INT ? "TX" : "RX", + rate, parent_rate); + + ad9361_fastlock_prepare(phy, clk_priv->source == TX_RFPLL_INT, 0, false); + + ret = ad9361_calc_rfpll_int_divder(phy, clk_priv, ad9361_from_clk(rate), + parent_rate, + &integer, &fract, &vco_div, &vco); + if (ret < 0) + return ret; + + switch (clk_priv->source) { + case RX_RFPLL_INT: + reg = REG_RX_FRACT_BYTE_2; + lock_reg = REG_RX_CP_OVERRANGE_VCO_LOCK; + div_mask = RX_VCO_DIVIDER(~0); + phy->cached_rx_rfpll_div = vco_div; + phy->current_rx_lo_freq = rate; + break; + case TX_RFPLL_INT: + reg = REG_TX_FRACT_BYTE_2; + lock_reg = REG_TX_CP_OVERRANGE_VCO_LOCK; + div_mask = TX_VCO_DIVIDER(~0); + phy->cached_tx_rfpll_div = vco_div; + phy->current_tx_lo_freq = rate; + break; + default: + return -EINVAL; + + } + + /* Option to skip VCO cal in TDD mode when moving from TX/RX to Alert */ + if (phy->pdata->tdd_skip_vco_cal) + ad9361_trx_vco_cal_control(phy, clk_priv->source == TX_RFPLL_INT, + true); + + do { + fixup_other = 0; + ad9361_rfpll_vco_init(phy, div_mask == TX_VCO_DIVIDER(~0), + vco, parent_rate); + + buf[0] = SYNTH_FRACT_WORD(fract >> 16); + buf[1] = fract >> 8; + buf[2] = fract & 0xFF; + buf[3] = SYNTH_INTEGER_WORD(integer >> 8) | + (~SYNTH_INTEGER_WORD(~0) & + ad9361_spi_read(clk_priv->spi, reg - 3)); + buf[4] = integer & 0xFF; + + ad9361_spi_writem(clk_priv->spi, reg, buf, 5); + ad9361_spi_writef(clk_priv->spi, REG_RFPLL_DIVIDERS, div_mask, vco_div); + + ret = ad9361_check_cal_done(phy, lock_reg, VCO_LOCK, 1); + + /* In FDD mode with RX LO == TX LO frequency we use TDD tables to + * reduce VCO pulling + */ + + if (((phy->pdata->fdd && !phy->pdata->fdd_independent_mode) && + (phy->current_tx_lo_freq == phy->current_rx_lo_freq) && + (phy->current_tx_use_tdd_table != phy->current_rx_use_tdd_table)) || + ((phy->pdata->fdd && !phy->pdata->fdd_independent_mode) && + (phy->current_tx_lo_freq != phy->current_rx_lo_freq) && + (phy->current_tx_use_tdd_table || phy->current_rx_use_tdd_table))) { + unsigned long _rate; + + switch (clk_priv->source) { + case RX_RFPLL_INT: + reg = REG_TX_FRACT_BYTE_2; + lock_reg = REG_TX_CP_OVERRANGE_VCO_LOCK; + div_mask = TX_VCO_DIVIDER(~0); + _rate = phy->current_tx_lo_freq; + break; + case TX_RFPLL_INT: + reg = REG_RX_FRACT_BYTE_2; + lock_reg = REG_RX_CP_OVERRANGE_VCO_LOCK; + div_mask = RX_VCO_DIVIDER(~0); + _rate = phy->current_rx_lo_freq; + break; + default: + return -EINVAL; + + } + + if (phy->current_tx_lo_freq != phy->current_rx_lo_freq) { + ad9361_calc_rfpll_int_divder(phy, clk_priv, ad9361_from_clk(_rate), + parent_rate, &integer, &fract, &vco_div, &vco); + + ad9361_fastlock_prepare(phy, clk_priv->source == RX_RFPLL_INT, 0, false); + } + + fixup_other = 1; + } + + } while (fixup_other); + + if (phy->pdata->tdd_skip_vco_cal) + ad9361_trx_vco_cal_control(phy, clk_priv->source == TX_RFPLL_INT, + false); + + return ret; +} + +/** + * Recalculate the clock rate. + * @param clk_priv The refclk_scale structure. + * @return The clock rate. + */ +uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv) +{ + struct ad9361_rf_phy *phy = clk_priv->phy; + + return phy->clks[clk_priv->source]->rate; +} + +/** + * Set the clock rate. + * @param clk_priv The refclk_scale structure. + * @param rate The clock rate. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, + uint32_t rate) +{ + struct ad9361_rf_phy *phy = clk_priv->phy; + + phy->clks[clk_priv->source]->rate = rate; + + return 0; +} + +/** + * Recalculate the clock rate. + * @param clk_priv The refclk_scale structure. + * @return The clock rate. + */ +uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv) +{ + struct ad9361_rf_phy *phy = clk_priv->phy; + uint32_t rate; + + switch (clk_priv->source) { + case RX_RFPLL: + if (phy->pdata->use_ext_rx_lo) { + if (phy->ad9361_rfpll_ext_recalc_rate) + rate = phy->ad9361_rfpll_ext_recalc_rate(clk_priv); + else + rate = ad9361_rfpll_dummy_recalc_rate(phy->ref_clk_scale[RX_RFPLL_DUMMY]); + } else { + rate = ad9361_rfpll_int_recalc_rate(phy->ref_clk_scale[RX_RFPLL_INT], + phy->clks[RX_REFCLK]->rate); + } + break; + case TX_RFPLL: + if (phy->pdata->use_ext_tx_lo) { + if (phy->ad9361_rfpll_ext_recalc_rate) + rate = phy->ad9361_rfpll_ext_recalc_rate(clk_priv); + else + rate = ad9361_rfpll_dummy_recalc_rate(phy->ref_clk_scale[TX_RFPLL_DUMMY]); + } else { + rate = ad9361_rfpll_int_recalc_rate(phy->ref_clk_scale[TX_RFPLL_INT], + phy->clks[TX_REFCLK]->rate); + } + break; + default: + rate = 0; + break; + } + + return rate; +} + +/** + * Calculate the closest possible clock rate that can be set. + * @param clk_priv The refclk_scale structure. + * @param rate The clock rate. + * @return The closest possible clock rate that can be set. + */ +int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate) +{ + struct ad9361_rf_phy *phy = clk_priv->phy; + int32_t round_rate; + + switch (clk_priv->source) { + case RX_RFPLL: + if (phy->pdata->use_ext_rx_lo) { + if (phy->ad9361_rfpll_ext_round_rate) + round_rate = phy->ad9361_rfpll_ext_round_rate(clk_priv, rate); + else + round_rate = rate; + } else { + round_rate = ad9361_rfpll_int_round_rate(phy->ref_clk_scale[RX_RFPLL_INT], rate, + &phy->clks[phy->ref_clk_scale[RX_RFPLL_INT]->parent_source]->rate); + } + break; + case TX_RFPLL: + if (phy->pdata->use_ext_tx_lo) { + if (phy->ad9361_rfpll_ext_round_rate) + round_rate = phy->ad9361_rfpll_ext_round_rate(clk_priv, rate); + else + round_rate = rate; + } else { + round_rate = ad9361_rfpll_int_round_rate(phy->ref_clk_scale[TX_RFPLL_INT], rate, + &phy->clks[phy->ref_clk_scale[TX_RFPLL_INT]->parent_source]->rate); + } + break; + default: + round_rate = 0; + break; + } + + return round_rate; +} + +/** + * Set the clock rate. + * @param clk_priv The refclk_scale structure. + * @param rate The clock rate. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate) +{ + struct ad9361_rf_phy *phy = clk_priv->phy; + int32_t ret; + + switch (clk_priv->source) { + case RX_RFPLL: + if (phy->pdata->use_ext_rx_lo) { + if (phy->ad9361_rfpll_ext_set_rate) + phy->ad9361_rfpll_ext_set_rate(clk_priv, rate); + else + ad9361_rfpll_dummy_set_rate(phy->ref_clk_scale[RX_RFPLL_DUMMY], rate); + } else { + ad9361_rfpll_int_set_rate(phy->ref_clk_scale[RX_RFPLL_INT], rate, + phy->clks[phy->ref_clk_scale[RX_RFPLL_INT]->parent_source]->rate); + } + /* Load Gain Table */ + ret = ad9361_load_gt(phy, ad9361_from_clk(rate), GT_RX1 + GT_RX2); + if (ret < 0) + return ret; + break; + case TX_RFPLL: + if (phy->pdata->use_ext_tx_lo) { + if (phy->ad9361_rfpll_ext_set_rate) + phy->ad9361_rfpll_ext_set_rate(clk_priv, rate); + else + ad9361_rfpll_dummy_set_rate(phy->ref_clk_scale[TX_RFPLL_DUMMY], rate); + } else { + ad9361_rfpll_int_set_rate(phy->ref_clk_scale[TX_RFPLL_INT], rate, + phy->clks[phy->ref_clk_scale[TX_RFPLL_INT]->parent_source]->rate); + } + /* For RX LO we typically have the tracking option enabled + * so for now do nothing here. + */ + if (phy->auto_cal_en && !phy->pdata->use_ext_tx_lo) + if ((diff_abs(phy->last_tx_quad_cal_freq, ad9361_from_clk(rate))) > + phy->cal_threshold_freq) { + ret = ad9361_do_calib_run(phy, TX_QUAD_CAL, -1); + if (ret < 0) + dev_err(&phy->spi->dev, + "%s: TX QUAD cal failed", __func__); + phy->last_tx_quad_cal_freq = ad9361_from_clk(rate); + } + break; + default: + break; + } + + return 0; +} + +/** + * Set clock mux parent. + * @param clk_priv The refclk_scale structure. + * @param index Index - Enable (1), disable (0) ext lo. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index) +{ + struct ad9361_rf_phy *phy = clk_priv->phy; + int32_t ret; + + dev_dbg(&clk_priv->spi->dev, "%s: index %d", __func__, index); + + ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); + + ret = ad9361_trx_ext_lo_control(phy, clk_priv->source == TX_RFPLL, index == 1); + if (ret >= 0) + clk_priv->mult = index; + + ad9361_ensm_restore_prev_state(phy); + + return ret; +} + +/** + * Register and initialize a new clock. + * @param phy The AD9361 state structure. + * @param name The name of the new clock. + * @param parent_name The name of the parent clock. + * @param flags The flags. + * @param source The source of the new clock. + * @param parent_source The source of the parent clock. + * @return A struct clk for the new clock or a negative error code. + */ +static struct clk *ad9361_clk_register(struct ad9361_rf_phy *phy, + const char *name, + const char *parent_name, uint32_t flags, + uint32_t source, uint32_t parent_source) +{ + struct refclk_scale *clk_priv; + struct clk *clk; + + if (name) { + // Unused variable - fix compiler warning + } + if (parent_name) { + // Unused variable - fix compiler warning + } + if (flags) { + // Unused variable - fix compiler warning + } + + clk_priv = (struct refclk_scale *)malloc(sizeof(*clk_priv)); + if (!clk_priv) { + dev_err(&phy->spi->dev, + "ad9361_clk_register: could not allocate fixed factor clk"); + return (struct clk *)ERR_PTR(-ENOMEM); + } + + /* struct refclk_scale assignments */ + clk_priv->source = (enum ad9361_clocks)source; + clk_priv->parent_source = (enum ad9361_clocks)parent_source; + clk_priv->spi = phy->spi; + clk_priv->phy = phy; + + phy->ref_clk_scale[source] = clk_priv; + + clk = (struct clk *)malloc(sizeof(*clk)); + if (!clk) { + free(clk_priv); + return (struct clk *)ERR_PTR(-ENOMEM); + } + + switch (source) { + case TX_REFCLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clk_refin->rate); + break; + case RX_REFCLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clk_refin->rate); + break; + case BB_REFCLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clk_refin->rate); + break; + case BBPLL_CLK: + clk->rate = ad9361_bbpll_recalc_rate(clk_priv, phy->clks[BB_REFCLK]->rate); + break; + case ADC_CLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clks[BBPLL_CLK]->rate); + break; + case R2_CLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clks[ADC_CLK]->rate); + break; + case R1_CLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clks[R2_CLK]->rate); + break; + case CLKRF_CLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clks[R1_CLK]->rate); + break; + case RX_SAMPL_CLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clks[CLKRF_CLK]->rate); + break; + case DAC_CLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clks[ADC_CLK]->rate); + break; + case T2_CLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clks[DAC_CLK]->rate); + break; + case T1_CLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clks[T2_CLK]->rate); + break; + case CLKTF_CLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clks[T1_CLK]->rate); + break; + case TX_SAMPL_CLK: + clk->rate = ad9361_clk_factor_recalc_rate(clk_priv, phy->clks[CLKTF_CLK]->rate); + break; + case RX_RFPLL_INT: + clk->rate = ad9361_rfpll_int_recalc_rate(clk_priv, phy->clks[RX_REFCLK]->rate); + break; + case TX_RFPLL_INT: + clk->rate = ad9361_rfpll_int_recalc_rate(clk_priv, phy->clks[TX_REFCLK]->rate); + break; + case RX_RFPLL_DUMMY: + clk->rate = phy->pdata->rx_synth_freq; + break; + case TX_RFPLL_DUMMY: + clk->rate = phy->pdata->tx_synth_freq; + break; + case RX_RFPLL: + clk->rate = ad9361_rfpll_recalc_rate(clk_priv); + break; + case TX_RFPLL: + clk->rate = ad9361_rfpll_recalc_rate(clk_priv); + } + + return clk; +} + +/** + * Register and initialize all the system clocks. + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_register_clocks(struct ad9361_rf_phy *phy) +{ + uint32_t flags = CLK_GET_RATE_NOCACHE; + + /* Scaled Reference Clocks */ + phy->clks[TX_REFCLK] = ad9361_clk_register(phy, + "tx_refclk", "ad9361_ext_refclk", + flags | CLK_IGNORE_UNUSED, + TX_REFCLK, EXT_REF_CLK); + + phy->clks[RX_REFCLK] = ad9361_clk_register(phy, + "rx_refclk", "ad9361_ext_refclk", + flags | CLK_IGNORE_UNUSED, + RX_REFCLK, EXT_REF_CLK); + + phy->clks[BB_REFCLK] = ad9361_clk_register(phy, + "bb_refclk", "ad9361_ext_refclk", + flags | CLK_IGNORE_UNUSED, + BB_REFCLK, EXT_REF_CLK); + + /* Base Band PLL Clock */ + phy->clks[BBPLL_CLK] = ad9361_clk_register(phy, + "bbpll_clk", "bb_refclk", + flags | CLK_IGNORE_UNUSED, + BBPLL_CLK, BB_REFCLK); + + phy->clks[ADC_CLK] = ad9361_clk_register(phy, + "adc_clk", "bbpll_clk", + flags | CLK_IGNORE_UNUSED, + ADC_CLK, BBPLL_CLK); + + phy->clks[R2_CLK] = ad9361_clk_register(phy, + "r2_clk", "adc_clk", + flags | CLK_IGNORE_UNUSED, + R2_CLK, ADC_CLK); + + phy->clks[R1_CLK] = ad9361_clk_register(phy, + "r1_clk", "r2_clk", + flags | CLK_IGNORE_UNUSED, + R1_CLK, R2_CLK); + + phy->clks[CLKRF_CLK] = ad9361_clk_register(phy, + "clkrf_clk", "r1_clk", + flags | CLK_IGNORE_UNUSED, + CLKRF_CLK, R1_CLK); + + phy->clks[RX_SAMPL_CLK] = ad9361_clk_register(phy, + "rx_sampl_clk", "clkrf_clk", + flags | CLK_IGNORE_UNUSED, + RX_SAMPL_CLK, CLKRF_CLK); + + + phy->clks[DAC_CLK] = ad9361_clk_register(phy, + "dac_clk", "adc_clk", + flags | CLK_IGNORE_UNUSED, + DAC_CLK, ADC_CLK); + + phy->clks[T2_CLK] = ad9361_clk_register(phy, + "t2_clk", "dac_clk", + flags | CLK_IGNORE_UNUSED, + T2_CLK, DAC_CLK); + + phy->clks[T1_CLK] = ad9361_clk_register(phy, + "t1_clk", "t2_clk", + flags | CLK_IGNORE_UNUSED, + T1_CLK, T2_CLK); + + phy->clks[CLKTF_CLK] = ad9361_clk_register(phy, + "clktf_clk", "t1_clk", + flags | CLK_IGNORE_UNUSED, + CLKTF_CLK, T1_CLK); + + phy->clks[TX_SAMPL_CLK] = ad9361_clk_register(phy, + "tx_sampl_clk", "clktf_clk", + flags | CLK_IGNORE_UNUSED, + TX_SAMPL_CLK, CLKTF_CLK); + + phy->clks[RX_RFPLL_INT] = ad9361_clk_register(phy, + "rx_rfpll", "rx_refclk", + flags | CLK_IGNORE_UNUSED, + RX_RFPLL_INT, RX_REFCLK); + + phy->clks[TX_RFPLL_INT] = ad9361_clk_register(phy, + "tx_rfpll", "tx_refclk", + flags | CLK_IGNORE_UNUSED, + TX_RFPLL_INT, TX_REFCLK); + + phy->clks[RX_RFPLL_DUMMY] = ad9361_clk_register(phy, + "rx_rfpll_dummy", NULL, + flags | CLK_IGNORE_UNUSED, + RX_RFPLL_DUMMY, 0); + + phy->clks[TX_RFPLL_DUMMY] = ad9361_clk_register(phy, + "tx_rfpll_dummy", NULL, + flags | CLK_IGNORE_UNUSED, + TX_RFPLL_DUMMY, 0); + + phy->clks[RX_RFPLL] = ad9361_clk_register(phy, + "rx_rfpll", NULL, + flags | CLK_IGNORE_UNUSED, + RX_RFPLL, 0); + + phy->clks[TX_RFPLL] = ad9361_clk_register(phy, + "tx_rfpll", NULL, + flags | CLK_IGNORE_UNUSED, + TX_RFPLL, 0); + + return 0; +} + +/** + * Unregister all the system clocks. + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_unregister_clocks(struct ad9361_rf_phy *phy) +{ + int32_t i; + + for (i = 0; i < NUM_AD9361_CLKS; i++) { + free(phy->clks[i]); + free(phy->ref_clk_scale[i]); + } + + return 0; +} + +/** + * Perform an RSSI gain step calibration. + * Note: Before running the function, provide a single tone within the channel + * bandwidth and monitor the received data. Adjust the tone amplitude until + * the received data is within a few dB of full scale but not overloading. + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy) +{ + uint32_t lna_error[4]; + uint32_t mixer_error[15]; + uint64_t lo_freq_hz; + uint8_t lo_index; + uint8_t i; + + lo_freq_hz = ad9361_from_clk(clk_get_rate(phy, + phy->ref_clk_scale[RX_RFPLL])); + if (lo_freq_hz < 1300000000ULL) + lo_index = 0; + else if (lo_freq_hz < 3300000000ULL) + lo_index = 1; + else if (lo_freq_hz < 4100000000ULL) + lo_index = 2; + else + lo_index = 3; + + /* Put the AD9361 into the Alert state. */ + ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); + + /* Program the directly-addressable register values. */ + ad9361_spi_write(phy->spi, REG_MAX_MIXER_CALIBRATION_GAIN_INDEX, + MAX_MIXER_CALIBRATION_GAIN_INDEX(0x0F)); + ad9361_spi_write(phy->spi, REG_MEASURE_DURATION, + GAIN_CAL_MEAS_DURATION(0x0E)); + ad9361_spi_write(phy->spi, REG_SETTLE_TIME, + SETTLE_TIME(0x3F)); + ad9361_spi_write(phy->spi, REG_RSSI_CONFIG, + RSSI_MODE_SELECT(0x3) | DEFAULT_RSSI_MEAS_MODE); + ad9361_spi_write(phy->spi, REG_MEASURE_DURATION_01, + MEASUREMENT_DURATION_0(0x0E)); + ad9361_spi_write(phy->spi, REG_LNA_GAIN, + gain_step_calib_reg_val[lo_index][0]); + + /* Program the LNA gain step words into the internal table. */ + ad9361_spi_write(phy->spi, REG_CONFIG, + CALIB_TABLE_SELECT(0x3) | START_CALIB_TABLE_CLOCK); + for(i = 0; i < 4; i++) { + ad9361_spi_write(phy->spi, REG_WORD_ADDRESS, i); + ad9361_spi_write(phy->spi, REG_GAIN_DIFF_WORDERROR_WRITE, + gain_step_calib_reg_val[lo_index][i+1]); + ad9361_spi_write(phy->spi, REG_CONFIG, + CALIB_TABLE_SELECT(0x3) | WRITE_LNA_GAIN_DIFF | START_CALIB_TABLE_CLOCK); + udelay(3); //Wait for data to fully write to internal table + } + + ad9361_spi_write(phy->spi, REG_CONFIG, START_CALIB_TABLE_CLOCK); + ad9361_spi_write(phy->spi, REG_CONFIG, 0x00); + + /* Run and wait until the calibration completes. */ + ad9361_run_calibration(phy, RX_GAIN_STEP_CAL); + + /* Read the LNA and Mixer error terms into nonvolatile memory. */ + ad9361_spi_write(phy->spi, REG_CONFIG, CALIB_TABLE_SELECT(0x1) | READ_SELECT); + for(i = 0; i < 4; i++) { + ad9361_spi_write(phy->spi, REG_WORD_ADDRESS, i); + lna_error[i] = ad9361_spi_read(phy->spi, REG_GAIN_ERROR_READ); + } + ad9361_spi_write(phy->spi, REG_CONFIG, CALIB_TABLE_SELECT(0x1)); + for(i = 0; i < 15; i++) { + ad9361_spi_write(phy->spi, REG_WORD_ADDRESS, i); + mixer_error[i] = ad9361_spi_read(phy->spi, REG_GAIN_ERROR_READ); + } + ad9361_spi_write(phy->spi, REG_CONFIG, 0x00); + + /* Programming gain step errors into the AD9361 in the field */ + ad9361_spi_write(phy->spi, + REG_CONFIG, CALIB_TABLE_SELECT(0x3) | START_CALIB_TABLE_CLOCK); + for(i = 0; i < 4; i++) { + ad9361_spi_write(phy->spi, REG_WORD_ADDRESS, i); + ad9361_spi_write(phy->spi, REG_GAIN_DIFF_WORDERROR_WRITE, lna_error[i]); + ad9361_spi_write(phy->spi, REG_CONFIG, + CALIB_TABLE_SELECT(0x3) | WRITE_LNA_ERROR_TABLE | START_CALIB_TABLE_CLOCK); + } + ad9361_spi_write(phy->spi, REG_CONFIG, + CALIB_TABLE_SELECT(0x3) | START_CALIB_TABLE_CLOCK); + for(i = 0; i < 15; i++) { + ad9361_spi_write(phy->spi, REG_WORD_ADDRESS, i); + ad9361_spi_write(phy->spi, REG_GAIN_DIFF_WORDERROR_WRITE, mixer_error[i]); + ad9361_spi_write(phy->spi, REG_CONFIG, + CALIB_TABLE_SELECT(0x3) | WRITE_MIXER_ERROR_TABLE | START_CALIB_TABLE_CLOCK); + } + ad9361_spi_write(phy->spi, REG_CONFIG, 0x00); + + ad9361_ensm_restore_prev_state(phy); + + return 0; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361.h new file mode 100644 index 00000000..638acdc1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361.h @@ -0,0 +1,3568 @@ +/***************************************************************************//** + * @file ad9361.h + * @brief Header file of AD9361 Driver. +******************************************************************************** + * Copyright 2014(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef IIO_FREQUENCY_AD9361_H_ +#define IIO_FREQUENCY_AD9361_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "common.h" +#include "../../../include/gpio.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#define REG_SPI_CONF 0x000 /* SPI Configuration */ +#define REG_MULTICHIP_SYNC_AND_TX_MON_CTRL 0x001 /* Multi-Chip Sync and Tx Mon Control */ +#define REG_TX_ENABLE_FILTER_CTRL 0x002 /* Tx Enable & Filter Control */ +#define REG_RX_ENABLE_FILTER_CTRL 0x003 /* Rx Enable & Filter Control */ +#define REG_INPUT_SELECT 0x004 /* Input Select */ +#define REG_RFPLL_DIVIDERS 0x005 /* RFPLL Dividers */ +#define REG_RX_CLOCK_DATA_DELAY 0x006 /* Rx Clock & Data Delay */ +#define REG_TX_CLOCK_DATA_DELAY 0x007 /* Tx Clock & Data Delay */ +#define REG_CLOCK_ENABLE 0x009 /* Clock Enable */ +#define REG_BBPLL 0x00A /* BBPLL */ +#define REG_TEMP_OFFSET 0x00B /* Offset */ +#define REG_START_TEMP_READING 0x00C /* Start Temp Reading */ +#define REG_TEMP_SENSE2 0x00D /* Temp Sense2 */ +#define REG_TEMPERATURE 0x00E /* Temperature */ +#define REG_TEMP_SENSOR_CONFIG 0x00F /* Temp Sensor Config */ +#define REG_PARALLEL_PORT_CONF_1 0x010 /* Parallel Port Configuration 1 */ +#define REG_PARALLEL_PORT_CONF_2 0x011 /* Parallel Port Configuration 2 */ +#define REG_PARALLEL_PORT_CONF_3 0x012 /* Parallel Port Configuration 3 */ +#define REG_ENSM_MODE 0x013 /* ENSM Mode */ +#define REG_ENSM_CONFIG_1 0x014 /* ENSM Config 1 */ +#define REG_ENSM_CONFIG_2 0x015 /* ENSM Config 2 */ +#define REG_CALIBRATION_CTRL 0x016 /* Calibration Control */ +#define REG_STATE 0x017 /* State */ +#define REG_AUXDAC_1_WORD 0x018 /* AuxDAC 1 Word */ +#define REG_AUXDAC_2_WORD 0x019 /* AuxDAC 2 Word */ +#define REG_AUXDAC_1_CONFIG 0x01A /* AuxDAC 1 Config */ +#define REG_AUXDAC_2_CONFIG 0x01B /* AuxDAC 2 Config */ +#define REG_AUXADC_CLOCK_DIVIDER 0x01C /* AuxADC Clock Divider */ +#define REG_AUXADC_CONFIG 0x01D /* Aux ADC Config */ +#define REG_AUXADC_WORD_MSB 0x01E /* AuxADC Word MSB */ +#define REG_AUXADC_LSB 0x01F /* AuxADC LSB */ +#define REG_AUTO_GPO 0x020 /* Auto GPO */ +#define REG_AGC_GAIN_LOCK_DELAY 0x021 /* AGC Gain Lock Delay */ +#define REG_AGC_ATTACK_DELAY 0x022 /* AGC Attack Delay */ +#define REG_AUXDAC_ENABLE_CTRL 0x023 /* AuxDAC Enable Control */ +#define REG_RX_LOAD_SYNTH_DELAY 0x024 /* RX Load Synth Delay */ +#define REG_TX_LOAD_SYNTH_DELAY 0x025 /* TX Load Synth Delay */ +#define REG_EXTERNAL_LNA_CTRL 0x026 /* External LNA control */ +#define REG_GPO_FORCE_AND_INIT 0x027 /* GPO Force and Init */ +#define REG_GPO0_RX_DELAY 0x028 /* GPO0 Rx delay */ +#define REG_GPO1_RX_DELAY 0x029 /* GPO1 Rx delay */ +#define REG_GPO2_RX_DELAY 0x02A /* GPO2 Rx delay */ +#define REG_GPO3_RX_DELAY 0x02B /* GPO3 Rx delay */ +#define REG_GPO0_TX_DELAY 0x02C /* GPO0 Tx Delay */ +#define REG_GPO1_TX_DELAY 0x02D /* GPO1 Tx Delay */ +#define REG_GPO2_TX_DELAY 0x02E /* GPO2 Tx Delay */ +#define REG_GPO3_TX_DELAY 0x02F /* GPO3 Tx Delay */ +#define REG_AUXDAC1_RX_DELAY 0x030 /* AuxDAC1 Rx Delay */ +#define REG_AUXDAC1_TX_DELAY 0x031 /* AuxDAC1 Tx Delay */ +#define REG_AUXDAC2_RX_DELAY 0x032 /* AuxDAC2 Rx Delay */ +#define REG_AUXDAC2_TX_DELAY 0x033 /* AuxDAC2 Tx Delay */ +#define REG_CTRL_OUTPUT_POINTER 0x035 /* Control Output Pointer */ +#define REG_CTRL_OUTPUT_ENABLE 0x036 /* Control Output Enable */ +#define REG_PRODUCT_ID 0x037 /* Product ID */ +#define REG_REFERENCE_CLOCK_CYCLES 0x03A /* Reference Clock Cycles */ +#define REG_DIGITAL_IO_CTRL 0x03B /* Digital I/O Control */ +#define REG_LVDS_BIAS_CTRL 0x03C /* LVDS Bias control */ +#define REG_LVDS_INVERT_CTRL1 0x03D /* LVDS Invert control1 */ +#define REG_LVDS_INVERT_CTRL2 0x03E /* LVDS Invert control2 */ +#define REG_SDM_CTRL_1 0x03F /* SDM Control 1 */ +#define REG_FRACT_BB_FREQ_WORD_1 0x041 /* Fractional BB Freq Word 1 */ +#define REG_FRACT_BB_FREQ_WORD_2 0x042 /* Fractional BB Freq Word 2 */ +#define REG_FRACT_BB_FREQ_WORD_3 0x043 /* Fractional BB Freq Word 3 */ +#define REG_INTEGER_BB_FREQ_WORD 0x044 /* Integer BB Freq Word */ +#define REG_CLOCK_CTRL 0x045 /* Clock Control */ +#define REG_CP_CURRENT 0x046 /* CP Current */ +#define REG_CP_BLEED_CURRENT 0x047 /* CP Bleed Current */ +#define REG_LOOP_FILTER_1 0x048 /* Loop Filter 1 */ +#define REG_LOOP_FILTER_2 0x049 /* Loop Filter 2 */ +#define REG_LOOP_FILTER_3 0x04A /* Loop Filter 3 */ +#define REG_VCO_CTRL 0x04B /* VCO Control */ +#define REG_VCO_PROGRAM_1 0x04C +#define REG_VCO_PROGRAM_2 0x04D +#define REG_SDM_CTRL 0x04E /* SDM Control */ +#define REG_RX_SYNTH_POWER_DOWN_OVERRIDE 0x050 /* Rx Synth Power Down Override */ +#define REG_TX_SYNTH_POWER_DOWN_OVERRIDE 0x051 /* TX Synth Power Down Override */ +#define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1 0x052 /* Rx Analog Power Down Override 1 */ +#define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2 0x053 /* Rx Analog Power Down Override 2 */ +#define REG_RX1_ADC_POWER_DOWN_OVERRIDE 0x054 /* Rx1 ADC Power Down Override */ +#define REG_RX2_ADC_POWER_DOWN_OVERRIDE 0x055 /* Rx2 ADC Power Down Override */ +#define REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1 0x056 /* Tx Analog Power Down Override 1 */ +#define REG_ANALOG_POWER_DOWN_OVERRIDE 0x057 /* Analog Power Down Override */ +#define REG_MISC_POWER_DOWN_OVERRIDE 0x058 /* Misc Power Down Override */ +#define REG_CH_1_OVERFLOW 0x05E /* CH 1 Overflow */ +#define REG_CH_2_OVERFLOW 0x05F /* CH 2 Overflow */ +#define REG_TX_FILTER_COEF_ADDR 0x060 /* TX Filter Coefficient Address */ +#define REG_TX_FILTER_COEF_WRITE_DATA_1 0x061 /* TX Filter Coefficient Write Data 1 */ +#define REG_TX_FILTER_COEF_WRITE_DATA_2 0x062 /* TX Filter Coefficient Write Data 2 */ +#define REG_TX_FILTER_COEF_READ_DATA_1 0x063 /* TX Filter Coefficient Read Data 1 */ +#define REG_TX_FILTER_COEF_READ_DATA_2 0x064 /* TX Filter Coefficient Read Data 2 */ +#define REG_TX_FILTER_CONF 0x065 /* TX Filter Configuration */ +#define REG_TX_MON_LOW_GAIN 0x067 /* Tx Mon Low Gain */ +#define REG_TX_MON_HIGH_GAIN 0x068 /* Tx Mon High Gain */ +#define REG_TX_MON_DELAY 0x069 /* Tx Mon Delay */ +#define REG_TX_LEVEL_THRESH 0x06A /* Tx Level Threshold */ +#define REG_TX_RSSI1 0x06B /* TX RSSI1 */ +#define REG_TX_RSSI2 0x06C /* TX RSSI2 */ +#define REG_TX_RSSI_LSB 0x06D /* TX RSSI LSB */ +#define REG_TPM_MODE_ENABLE 0x06E /* TPM Mode Enable */ +#define REG_TX_MON_TEMP_GAIN_COEF 0x06F /* Temp Gain Coefficient */ +#define REG_TX_MON_1_CONFIG 0x070 /* Tx Mon 1 Config */ +#define REG_TX_MON_2_CONFIG 0x071 /* Tx Mon 2 Config */ +#define REG_TX1_ATTEN_0 0x073 /* Tx1 Atten 0 */ +#define REG_TX1_ATTEN_1 0x074 /* Tx1 Atten 1 */ +#define REG_TX2_ATTEN_0 0x075 /* Tx2 Atten 0 */ +#define REG_TX2_ATTEN_1 0x076 /* Tx2 Atten 1 */ +#define REG_TX_ATTEN_OFFSET 0x077 /* Tx Atten Offset */ +#define REG_TX_ATTEN_THRESH 0x078 /* Tx Atten Threshold */ +#define REG_TX1_DIG_ATTEN 0x079 /* Tx1 Dig Attenuation */ +#define REG_TX2_DIG_ATTEN 0x07C /* Tx2 Dig Attenuation */ +#define REG_TX1_SYMBOL_ATTEN 0x07F /* TX1 Symbol Attenuation */ +#define REG_TX2_SYMBOL_ATTEN 0x080 /* TX2 Symbol Attenuation */ +#define REG_TX_SYMBOL_ATTEN_CONFIG 0x081 /* TX Symbol Atten Config */ +#define REG_TX1_OUT_1_PHASE_CORR 0x08E /* Tx1 Out 1 Phase Corr */ +#define REG_TX1_OUT_1_GAIN_CORR 0x08F /* Tx1 Out 1 Gain Corr */ +#define REG_TX2_OUT_1_PHASE_CORR 0x090 /* Tx2 Out 1 Phase Corr */ +#define REG_TX2_OUT_1_GAIN_CORR 0x091 /* Tx2 Out 1 Gain Corr */ +#define REG_TX1_OUT_1_OFFSET_I 0x092 /* Tx1 Out 1 Offset I */ +#define REG_TX1_OUT_1_OFFSET_Q 0x093 /* Tx1 Out 1 Offset Q */ +#define REG_TX2_OUT_1_OFFSET_I 0x094 /* Tx2 Out 1 Offset I */ +#define REG_TX2_OUT_1_OFFSET_Q 0x095 /* Tx2 Out 1 Offset Q */ +#define REG_TX1_OUT_2_PHASE_CORR 0x096 /* Tx1 Out 2 Phase Corr */ +#define REG_TX1_OUT_2_GAIN_CORR 0x097 /* Tx1 Out 2 Gain Corr */ +#define REG_TX2_OUT_2_PHASE_CORR 0x098 /* Tx2 Out 2 Phase Corr */ +#define REG_TX2_OUT_2_GAIN_CORR 0x099 /* Tx2 Out 2 Gain Corr */ +#define REG_TX1_OUT_2_OFFSET_I 0x09A /* Tx1 Out 2 Offset I */ +#define REG_TX1_OUT_2_OFFSET_Q 0x09B /* Tx1 Out 2 Offset Q */ +#define REG_TX2_OUT_2_OFFSET_I 0x09C /* Tx2 Out 2 Offset I */ +#define REG_TX2_OUT_2_OFFSET_Q 0x09D /* Tx2 Out 2 Offset Q */ +#define REG_TX_FORCE_BITS 0x09F /* Force Bits */ +#define REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET 0x0A0 /* Quad Cal NCO Freq & Phase Offset */ +#define REG_QUAD_CAL_CTRL 0x0A1 /* Quad Cal Control */ +#define REG_KEXP_1 0x0A2 /* Kexp 1 */ +#define REG_KEXP_2 0x0A3 /* Kexp 2 */ +#define REG_QUAD_SETTLE_COUNT 0x0A4 /* QUAD Settle count */ +#define REG_MAG_FTEST_THRESH 0x0A5 /* Mag. Ftest Thresh */ +#define REG_MAG_FTEST_THRESH_2 0x0A6 /* Mag. Ftest Thresh 2 */ +#define REG_QUAD_CAL_STATUS_TX1 0x0A7 /* Quad cal status Tx1 */ +#define REG_QUAD_CAL_STATUS_TX2 0x0A8 /* Quad cal status Tx2 */ +#define REG_QUAD_CAL_COUNT 0x0A9 /* Quad cal Count */ +#define REG_TX_QUAD_FULL_LMT_GAIN 0x0AA /* Tx Quad Full/LMT Gain */ +#define REG_SQUARER_CONFIG 0x0AB /* Squarer Config */ +#define REG_TX_QUAD_CAL_ATTEN 0x0AC /* TX Quad Cal Atten */ +#define REG_THRESH_ACCUM 0x0AD /* Thresh Accum */ +#define REG_TX_QUAD_LPF_GAIN 0x0AE /* Tx Quad LPF Gain */ +#define REG_TXDAC_VDS_I 0x0B0 /* TxDAC Vds I */ +#define REG_TXDAC_VDS_Q 0x0B1 /* TxDAC Vds Q */ +#define REG_TXDAC_GN_I 0x0B2 /* TxDAC gn I */ +#define REG_TXDAC_GN_Q 0x0B3 /* TxDAC gn Q */ +#define REG_TXBBF_OPAMP_A 0x0C0 /* TxBBF OpAmp A */ +#define REG_TXBBF_OPAMP_B 0x0C1 /* TxBBF OpAmp B */ +#define REG_TX_BBF_R1 0x0C2 /* Tx BBF R1 */ +#define REG_TX_BBF_R2 0x0C3 /* Tx BBF R2 */ +#define REG_TX_BBF_R3 0x0C4 /* Tx BBF R3 */ +#define REG_TX_BBF_R4 0x0C5 /* Tx BBF R4 */ +#define REG_TX_BBF_RP 0x0C6 /* Tx BBF RP */ +#define REG_TX_BBF_C1 0x0C7 /* Tx BBF C1 */ +#define REG_TX_BBF_C2 0x0C8 /* Tx BBF C2 */ +#define REG_TX_BBF_CP 0x0C9 /* Tx BBF Cp */ +#define REG_TX_TUNE_CTRL 0x0CA /* Tx Tune Control */ +#define REG_TX_BBF_R2B 0x0CB /* Tx BBF R2b */ +#define REG_TX_BBF_TUNE 0x0CC /* Tx BBF Tune */ +#define REG_CONFIG0 0x0D0 /* Config0 */ +#define REG_RESISTOR 0x0D1 /* Resistor */ +#define REG_CAPACITOR 0x0D2 /* Capacitor */ +#define REG_LO_CM 0x0D3 /* LO CM */ +#define REG_TX_BBF_TUNE_DIVIDER 0x0D6 /* TX BBF Tune Divider */ +#define REG_TX_BBF_TUNE_MODE 0x0D7 /* TX BBF Tune Mode */ +#define REG_RX_FILTER_COEF_ADDR 0x0F0 /* Rx Filter Coeff Addr */ +#define REG_RX_FILTER_COEF_DATA_1 0x0F1 /* Rx Filter Coeff Data 1 */ +#define REG_RX_FILTER_COEF_DATA_2 0x0F2 /* Rx Filter Coeff Data 2 */ +#define REG_RX_FILTER_COEF_READ_DATA_1 0x0F3 /* Rx Filter Coeff Read Data 1 */ +#define REG_RX_FILTER_COEF_READ_DATA_2 0x0F4 /* Rx Filter Coeff Read Data 2 */ +#define REG_RX_FILTER_CONFIG 0x0F5 /* Rx Filter Config */ +#define REG_RX_FILTER_GAIN 0x0F6 /* Rx Filter Gain */ +#define REG_AGC_CONFIG_1 0x0FA /* AGC Config1 */ +#define REG_AGC_CONFIG_2 0x0FB /* AGC config2 */ +#define REG_AGC_CONFIG_3 0x0FC /* AGC Config3 */ +#define REG_MAX_LMT_FULL_GAIN 0x0FD /* Max LMT/Full Gain */ +#define REG_PEAK_WAIT_TIME 0x0FE /* Peak Wait Time */ +#define REG_DIGITAL_GAIN 0x100 /* Digital Gain */ +#define REG_AGC_LOCK_LEVEL 0x101 /* AGC Lock Level */ +#define REG_ADC_NOISE_CORRECTION_FACTOR 0x102 /* ADC noise Correction Factor */ +#define REG_GAIN_STP_CONFIG1 0x103 /* Gain Step Config1 */ +#define REG_ADC_SMALL_OVERLOAD_THRESH 0x104 /* ADC Small Overload Threshold */ +#define REG_ADC_LARGE_OVERLOAD_THRESH 0x105 /* ADC Large Overload Threshold */ +#define REG_GAIN_STP_CONFIG_2 0x106 /* Gain Step Config 2 */ +#define REG_SMALL_LMT_OVERLOAD_THRESH 0x107 /* Small LMT Overload Threshold */ +#define REG_LARGE_LMT_OVERLOAD_THRESH 0x108 /* Large LMT Overload Threshold */ +#define REG_RX1_MANUAL_LMT_FULL_GAIN 0x109 /* Rx1 Manual LMT/Full Gain */ +#define REG_RX1_MANUAL_LPF_GAIN 0x10A /* Rx1 Manual LPF gain */ +#define REG_RX1_MANUAL_DIGITALFORCED_GAIN 0x10B /* Rx1 Manual Digital/Forced Gain */ +#define REG_RX2_MANUAL_LMT_FULL_GAIN 0x10C /* Rx2 Manual LMT/Full Gain */ +#define REG_RX2_MANUAL_LPF_GAIN 0x10D /* Rx2 Manual LPF Gain */ +#define REG_RX2_MANUAL_DIGITALFORCED_GAIN 0x10E /* Rx2 Manual Digital/Forced Gain */ +#define REG_FAST_CONFIG_1 0x110 /* Config 1 */ +#define REG_FAST_CONFIG_2_SETTLING_DELAY 0x111 /* Config 2 & Settling Delay */ +#define REG_FAST_ENERGY_LOST_THRESH 0x112 /* Energy Lost Threshold */ +#define REG_FAST_STRONGER_SIGNAL_THRESH 0x113 /* Stronger Signal Threshold */ +#define REG_FAST_LOW_POWER_THRESH 0x114 /* Low Power Threshold */ +#define REG_FAST_STRONG_SIGNAL_FREEZE 0x115 /* Strong Signal Freeze */ +#define REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN 0x116 /* Final Over Range and Opt Gain */ +#define REG_FAST_ENERGY_DETECT_COUNT 0x117 /* Energy Detect Count */ +#define REG_FAST_AGCLL_UPPER_LIMIT 0x118 /* AGCLL Upper Limit */ +#define REG_FAST_GAIN_LOCK_EXIT_COUNT 0x119 /* Gain Lock Exit Count */ +#define REG_FAST_INITIAL_LMT_GAIN_LIMIT 0x11A /* Initial LMT Gain Limit */ +#define REG_FAST_INCREMENT_TIME 0x11B /* Increment Time */ +#define REG_AGC_INNER_LOW_THRESH 0x120 /* AGC Inner Low Threshold */ +#define REG_LMT_OVERLOAD_COUNTERS 0x121 /* LMT Overload Counters */ +#define REG_ADC_OVERLOAD_COUNTERS 0x122 /* ADC Overload Counters */ +#define REG_GAIN_STP1 0x123 /* Gain Step1 */ +#define REG_GAIN_UPDATE_COUNTER1 0x124 /* Gain Update Counter1 */ +#define REG_GAIN_UPDATE_COUNTER2 0x125 /* Gain Update Counter2 */ +#define REG_DIGITAL_SAT_COUNTER 0x128 /* Digital Sat Counter */ +#define REG_OUTER_POWER_THRESHS 0x129 /* Outer Power Thresholds */ +#define REG_GAIN_STP_2 0x12A /* Gain Step 2 */ +#define REG_EXT_LNA_HIGH_GAIN 0x12C /* Ext LNA High Gain */ +#define REG_EXT_LNA_LOW_GAIN 0x12D /* Ext LNA Low Gain */ +#define REG_GAIN_TABLE_ADDRESS 0x130 /* Gain Table Address */ +#define REG_GAIN_TABLE_WRITE_DATA1 0x131 /* Gain Table Write Data1 */ +#define REG_GAIN_TABLE_WRITE_DATA2 0x132 /* Gain Table Write Data2 */ +#define REG_GAIN_TABLE_WRITE_DATA3 0x133 /* Gain Table Write Data 3 */ +#define REG_GAIN_TABLE_READ_DATA1 0x134 /* Gain Table Read Data 1 */ +#define REG_GAIN_TABLE_READ_DATA2 0x135 /* Gain Table Read Data 2 */ +#define REG_GAIN_TABLE_READ_DATA3 0x136 /* Gain Table Read Data 3 */ +#define REG_GAIN_TABLE_CONFIG 0x137 /* Gain Table Config */ +#define REG_GM_SUB_TABLE_ADDRESS 0x138 /* Gm Sub Table Address */ +#define REG_GM_SUB_TABLE_GAIN_WRITE 0x139 /* Gm Sub Table Gain Word Write */ +#define REG_GM_SUB_TABLE_BIAS_WRITE 0x13A /* Gm Sub Table Bias Word Write */ +#define REG_GM_SUB_TABLE_CTRL_WRITE 0x13B /* Gm Sub Table Control Word Write */ +#define REG_GM_SUB_TABLE_GAIN_READ 0x13C /* Gm Sub Table Gain Word Read */ +#define REG_GM_SUB_TABLE_BIAS_READ 0x13D /* Gm Sub Table Bias Word Read */ +#define REG_GM_SUB_TABLE_CTRL_READ 0x13E /* Gm Sub Table Control Word Read */ +#define REG_GM_SUB_TABLE_CONFIG 0x13F /* Gm Sub Table Config */ +#define REG_WORD_ADDRESS 0x140 /* Word Address */ +#define REG_GAIN_DIFF_WORDERROR_WRITE 0x141 /* Gain Diff Word/Error Write */ +#define REG_GAIN_ERROR_READ 0x142 /* Gain Error Read */ +#define REG_CONFIG 0x143 /* Config */ +#define REG_LNA_GAIN_DIFF_READ_BACK 0x144 /* LNA Gain Diff Read Back */ +#define REG_MAX_MIXER_CALIBRATION_GAIN_INDEX 0x145 /* Max Mixer Calibration Gain Index */ +#define REG_TEMP_GAIN_COEF 0x146 /* Temp Gain Coefficient */ +#define REG_SETTLE_TIME 0x147 /* Settle Time */ +#define REG_MEASURE_DURATION 0x148 /* Measure Duration */ +#define REG_CAL_TEMP_SENSOR_WORD 0x149 /* Cal Temp sensor word */ +#define REG_MEASURE_DURATION_01 0x150 /* Measure Duration 0&1 */ +#define REG_MEASURE_DURATION_23 0x151 /* Measure Duration 2&3 */ +#define REG_RSSI_WEIGHT_0 0x152 /* RSSI Weight 0 */ +#define REG_RSSI_WEIGHT_1 0x153 /* RSSI Weight 1 */ +#define REG_RSSI_WEIGHT_2 0x154 /* RSSI Weight 2 */ +#define REG_RSSI_WEIGHT_3 0x155 /* RSSI Weight 3 */ +#define REG_RSSI_DELAY 0x156 /* RSSI delay */ +#define REG_RSSI_WAIT_TIME 0x157 /* RSSI wait time */ +#define REG_RSSI_CONFIG 0x158 /* RSSI Config */ +#define REG_ADC_MEASURE_DURATION_01 0x159 /* ADC Measure Duration 0&1 */ +#define REG_ADC_WEIGHT_0 0x15A /* ADC Weight 0 */ +#define REG_ADC_WEIGHT_1 0x15B /* ADC Weight 1 */ +#define REG_DEC_POWER_MEASURE_DURATION_0 0x15C /* Dec Power Measure Duration 0 */ +#define REG_LNA_GAIN 0x15D /* LNA Gain */ +#define REG_CH1_ADC_POWER 0x160 /* CH1 ADC Power */ +#define REG_CH1_RX_FILTER_POWER 0x161 /* CH1 Rx filter Power */ +#define REG_CH2_ADC_POWER 0x162 /* CH2 ADC Power */ +#define REG_CH2_RX_FILTER_POWER 0x163 /* CH2 Rx filter Power */ +#define REG_RX_QUAD_CAL_LEVEL 0x168 /* Rx Quad Cal Level */ +#define REG_CALIBRATION_CONFIG_1 0x169 /* Calibration Config 1 */ +#define REG_CALIBRATION_CONFIG_2 0x16A /* Calibration config2 */ +#define REG_CALIBRATION_CONFIG_3 0x16B /* Calibration config3 */ +#define REG_CALIB_COUNT 0x16C /* Calib count */ +#define REG_SETTLE_COUNT 0x16D /* Settle count */ +#define REG_RX_QUAD_GAIN1 0x16E /* Rx Quad gain1 */ +#define REG_RX_QUAD_GAIN2 0x16F /* Rx Quad gain2 */ +#define REG_RX1_INPUT_A_PHASE_CORR 0x170 /* Rx1 Input A Phase Corr */ +#define REG_RX1_INPUT_A_GAIN_CORR 0x171 /* Rx1 Input A Gain Corr */ +#define REG_RX2_INPUT_A_PHASE_CORR 0x172 /* Rx2 Input A Phase Corr */ +#define REG_RX2_INPUT_A_GAIN_CORR 0x173 /* Rx2 Input A Gain Corr */ +#define REG_RX1_INPUT_A_Q_OFFSET 0x174 /* Rx1 Input A Q" Offset */ +#define REG_RX1_INPUT_A_OFFSETS 0x175 /* Rx1 Input A Offsets */ +#define REG_INPUT_A_OFFSETS_1 0x176 /* Input A Offsets 1 */ +#define REG_RX2_INPUT_A_OFFSETS 0x177 /* Rx2 Input A Offsets */ +#define REG_RX2_INPUT_A_I_OFFSET 0x178 /* Rx2 Input A "I" Offset */ +#define REG_RX1_INPUT_BC_PHASE_CORR 0x179 /* Rx1 Input B&C Phase Corr */ +#define REG_RX1_INPUT_BC_GAIN_CORR 0x17A /* Rx1 Input B&C Gain Corr */ +#define REG_RX2_INPUT_BC_PHASE_CORR 0x17B /* Rx2 Input B&C Phase Corr */ +#define REG_RX2_INPUT_BC_GAIN_CORR 0x17C /* Rx2 Input B&C Gain Corr */ +#define REG_RX1_INPUT_BC_Q_OFFSET 0x17D /* Rx1 Input B&C "Q" Offset */ +#define REG_RX1_INPUT_BC_OFFSETS 0x17E /* Rx1 Input B&C Offsets */ +#define REG_INPUT_BC_OFFSETS_1 0x17F /* Input B&C Offsets 1 */ +#define REG_RX2_INPUT_BC_OFFSETS 0x180 /* Rx2 Input B&C Offsets */ +#define REG_RX2_INPUT_BC_I_OFFSET 0x181 /* Rx2 Input B&C "I" Offset */ +#define REG_FORCE_BITS 0x182 /* Force Bits */ +#define REG_WAIT_COUNT 0x185 /* Wait Count */ +#define REG_RF_DC_OFFSET_COUNT 0x186 /* RF DC Offset Count */ +#define REG_RF_DC_OFFSET_CONFIG_1 0x187 /* RF DC Offset Config1 */ +#define REG_RF_DC_OFFSET_ATTEN 0x188 /* RF DC Offset Attenuation */ +#define REG_INVERT_BITS 0x189 /* Invert Bits */ +#define REG_DC_OFFSET_CONFIG2 0x18B /* DC Offset Config2 */ +#define REG_RF_CAL_GAIN_INDEX 0x18C /* RF Cal Gain Index */ +#define REG_SOI_THRESH 0x18D /* SOI Threshold */ +#define REG_BB_DC_OFFSET_SHIFT 0x190 /* BB DC Offset Shift */ +#define REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT 0x191 /* BB DC Offset Fast Settle Shift */ +#define REG_BB_FAST_SETTLE_DUR 0x192 /* BB Fast Settle Dur */ +#define REG_BB_DC_OFFSET_COUNT 0x193 /* BB DC Offset Count */ +#define REG_BB_DC_OFFSET_ATTEN 0x194 /* BB DC Offset Attenuation */ +#define REG_RX1_BB_DC_WORD_I_MSB 0x19A /* RX1 BB DC word I MSB */ +#define REG_RX1_BB_DC_WORD_I_LSB 0x19B /* RX1 BB DC word I LSB */ +#define REG_RX1_BB_DC_WORD_Q_MSB 0x19C /* RX1 BB DC word Q MSB */ +#define REG_RX1_BB_DC_WORD_Q_LSB 0x19D /* RX1 BB DC word Q LSB */ +#define REG_RX2_BB_DC_WORD_I_MSB 0x19E /* RX2 BB DC word I MSB */ +#define REG_RX2_BB_DC_WORD_I_LSB 0x19F /* RX2 BB DC word I LSB */ +#define REG_RX2_BB_DC_WORD_Q_MSB 0x1A0 /* RX2 BB DC word Q MSB */ +#define REG_RX2_BB_DC_WORD_Q_LSB 0x1A1 /* RX2 BB DC word Q LSB */ +#define REG_BB_TRACK_CORR_WORD_I_MSB 0x1A2 /* BB Track corr word I MSB */ +#define REG_BB_TRACK_CORR_WORD_I_LSB 0x1A3 /* BB Track corr word I LSB */ +#define REG_BB_TRACK_CORR_WORD_Q_MSB 0x1A4 /* BB Track corr word Q MSB */ +#define REG_BB_TRACK_CORR_WORD_Q_LSB 0x1A5 /* BB Track corr word Q LSB */ +#define REG_RX1_RSSI_SYMBOL 0x1A7 /* Rx1 RSSI Symbol */ +#define REG_RX1_RSSI_PREAMBLE 0x1A8 /* Rx1 RSSI preamble */ +#define REG_RX2_RSSI_SYMBOL 0x1A9 /* Rx2 RSSI symbol */ +#define REG_RX2_RSSI_PREAMBLE 0x1AA /* Rx2 RSSI preamble */ +#define REG_SYMBOL_LSB 0x1AB /* Symbol LSB */ +#define REG_PREAMBLE_LSB 0x1AC /* Preamble LSB */ +#define REG_RX_PATH_GAIN_MSB 0x1AD /* Rx Path Gain */ +#define REG_RX_PATH_GAIN_LSB 0x1AE /* Rx Path Gain */ +#define REG_RX_DIFF_LNA_FORCE 0x1B0 /* Rx Diff LNA Force */ +#define REG_RX_LNA_BIAS_COARSE 0x1B1 /* Rx LNA Bias Coarse */ +#define REG_RX_LNA_BIAS_FINE_0 0x1B2 /* Rx LNA Bias Fine 0 */ +#define REG_RX_LNA_BIAS_FINE_1 0x1B3 /* Rx LNA Bias Fine 1 */ +#define REG_RX_MIX_GM_CONFIG 0x1C0 /* Rx Mix Gm Config */ +#define REG_RX1_MIX_GM_FORCE 0x1C1 /* Rx1 Mix Gm Force */ +#define REG_RX1_MIX_GM_BIAS_FORCE 0x1C2 /* Rx1 Mix Gm Bias (Force) */ +#define REG_RX2_MIX_GM_FORCE 0x1C3 /* Rx2 Mix Gm Force */ +#define REG_RX2_MIX_GM_BIAS_FORCE 0x1C4 /* Rx2 Mix Gm Bias (Force) */ +#define REG_INPUT_A_MSBS 0x1C8 /* Input A MSBs */ +#define REG_INPUT_A_RX1_I 0x1C9 /* Input A RX1 I */ +#define REG_INPUT_A_RX1_Q 0x1CA /* Input A RX1 Q */ +#define REG_INPUT_A_RX2_I 0x1CB /* Input A RX2 I */ +#define REG_INPUT_A_RX2_Q 0x1CC /* Input A RX2 Q */ +#define REG_INPUTS_BC_RX1_I 0x1CD /* Inputs B&C RX1 I */ +#define REG_BAND1_RX1_Q 0x1CE /* Band1 RX1 Q */ +#define REG_INPUTS_BC_RX2_I 0x1CF /* Inputs B&C RX2 I */ +#define REG_INPUTS_BC_RX2_Q 0x1D0 /* Inputs B&C RX2 Q */ +#define REG_INPUTS_BC_MSBS 0x1D1 /* Inputs B&C MSBs */ +#define REG_FORCE_OS_DAC 0x1D2 /* Force OS DAC */ +#define REG_RX_MIX_LO_CM 0x1D5 /* Rx Mix LO CM */ +#define REG_RX_CGB_SEG_ENABLE 0x1D6 /* Rx CGB Seg Enable */ +#define REG_RX_MIX_INPUTBIAS 0x1D7 /* Rx Mix Input/Bias */ +#define REG_RX_TIA_CONFIG 0x1DB /* Rx TIA Config */ +#define REG_TIA1_C_LSB 0x1DC /* TIA1 C LSB */ +#define REG_TIA1_C_MSB 0x1DD /* TIA1 C MSB */ +#define REG_TIA2_C_LSB 0x1DE /* TIA2 C LSB */ +#define REG_TIA2_C_MSB 0x1DF /* TIA2 C MSB */ +#define REG_RX1_BBF_R1A 0x1E0 /* Rx1 BBF R1A */ +#define REG_RX2_BBF_R1A 0x1E1 /* Rx2 BBF R1A */ +#define REG_RX1_TUNE_CTRL 0x1E2 /* Rx1 Tune Control */ +#define REG_RX2_TUNE_CTRL 0x1E3 /* Rx2 Tune Control */ +#define REG_RX1_BBF_R5 0x1E4 /* Rx1 BBF R5 */ +#define REG_RX2_BBF_R5 0x1E5 /* Rx2 BBF R5 */ +#define REG_RX_BBF_R2346 0x1E6 /* Rx BBF R2346 */ +#define REG_RX_BBF_C1_MSB 0x1E7 /* Rx BBF C1 MSB */ +#define REG_RX_BBF_C1_LSB 0x1E8 /* Rx BBF C1 LSB */ +#define REG_RX_BBF_C2_MSB 0x1E9 /* Rx BBF C2 MSB */ +#define REG_RX_BBF_C2_LSB 0x1EA /* Rx BBF C2 LSB */ +#define REG_RX_BBF_C3_MSB 0x1EB /* Rx BBF C3 MSB */ +#define REG_RX_BBF_C3_LSB 0x1EC /* Rx BBF C3 LSB */ +#define REG_RX_BBF_CC1_CTR 0x1ED /* Rx BBF CC1 Ctr */ +#define REG_RX_BBF_POW_RZ_BYTE0 0x1EE /* Rx BBF Pow Rz Byte0 */ +#define REG_RX_BBF_CC2_CTR 0x1EF /* Rx BBF CC2 Ctr */ +#define REG_RX_BBF_POW_RZ_BYTE1 0x1F0 /* Rx BBF Pow Rz Byte1 */ +#define REG_RX_BBF_CC3_CTR 0x1F1 /* Rx BBF CC3 Ctr */ +#define REG_RX_BBF_R5_TUNE 0x1F2 /* Rx BBF R5 Tune */ +#define REG_RX_BBF_TUNE 0x1F3 /* Rx BBF Tune */ +#define REG_RX1_BBF_MAN_GAIN 0x1F4 /* Rx1 BBF Man Gain */ +#define REG_RX2_BBF_MAN_GAIN 0x1F5 /* Rx2 BBF Man Gain */ +#define REG_RX_BBF_TUNE_DIVIDE 0x1F8 /* RX BBF Tune Divide */ +#define REG_RX_BBF_TUNE_CONFIG 0x1F9 /* RX BBF Tune Config */ +#define REG_POLE_GAIN 0x1FA /* Pole gain */ +#define REG_RX_BBBW_MHZ 0x1FB /* Rx BBBW MHz */ +#define REG_RX_BBBW_KHZ 0x1FC /* Rx BBBW kHz */ +#define REG_FB_DAC_CLK_DELAY1 0x201 /* FB DAC Clk Delay1 */ +#define REG_FB_DAC_CLK_DELAY2 0x202 /* FB DAC Clk Delay2 */ +#define REG_FLASH_SAMPLE_CLK_DELAY_3P 0x203 /* Flash Sample Clk Delay 3p */ +#define REG_FLASH_SAMPLE_CLK_DELAY_3N 0x204 /* Flash Sample Clk Delay 3n */ +#define REG_TEST_MUX_2I 0x205 /* Test MUX 2i */ +#define REG_TEST_MUX_2Q 0x206 /* Test MUX 2q */ +#define REG_INTEGRATOR_1_RESISTANCE 0x207 /* Integrator 1 Resistance */ +#define REG_INTEGRATOR_1_CAPACITANCE 0x208 /* Integrator 1 Capacitance */ +#define REG_INTEGRATOR_23_RESISTANCE 0x209 /* Integrator 23 Resistance */ +#define REG_INTEGRATOR_2_RESISTANCE 0x20A /* Integrator 2 Resistance */ +#define REG_INTEGRATOR_2_CAPACITANCE 0x20B /* Integrator 2 Capacitance */ +#define REG_INTEGRATOR_3_RESISTANCE 0x20C /* Integrator 3 Resistance */ +#define REG_INTEGRATOR_3_CAPACITANCE 0x20D /* Integrator 3 Capacitance */ +#define REG_INTEGRATOR_AMP_CC 0x20E /* Integrator Amp Cc */ +#define REG_INT_1_FB_DAC_NMOS_CURRENT_SOURCE 0x20F /* Int 1 FB DAC NMOS Current Source */ +#define REG_INT_1_FB_DAC_NMOS_CASOADE_BIAS_CURRENT 0x210 /* Int 1 FB DAC NMOS Casoade Bias Current */ +#define REG_INT_1_FB_DAC_PMOS_CURRENT_SOURCE 0x211 /* Int 1 FB DAC PMOS Current Source */ +#define REG_INT_2_FB_DAC_NMOS_CURRENT_SOURCE 0x212 /* Int 2 FB DAC NMOS Current Source */ +#define REG_INT_2_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x213 /* Int 2 FB DAC NMOS Cascode Bias Current */ +#define REG_INT_2_FB_DAC_PMOS_CURRENT_SOURCE 0x214 /* Int 2 FB DAC PMOS Current Source */ +#define REG_INT_3_FB_DAC_NMOS_CURRENT_SOURCE 0x215 /* Int 3 FB DAC NMOS Current Source */ +#define REG_INT_3_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x216 /* Int 3 FB DAC NMOS Cascode Bias Current */ +#define REG_INT_3_FB_DAC_PMOS_CURRENT_SOURCE 0x217 /* Int 3 FB DAC PMOS Current Source */ +#define REG_FB_DAC_BIAS_CURRENT 0x218 /* FB DAC Bias Current */ +#define REG_INT_1_1ST_STAGE_CURRENT 0x219 /* Int 1 1st Stage Current */ +#define REG_INT_1_1ST_STAGE_CASCODE_CURRENT 0x21A /* Int 1 1st Stage Cascode Current */ +#define REG_INT_1_2ND_STAGE_CURRENT 0x21B /* Int 1 2nd Stage Current */ +#define REG_INTEGRATOR_2_1ST_STAGE_CURRENT 0x21C /* Integrator 2 1st Stage Current */ +#define REG_INT_2_1ST_STAGE_CASCODE_CURRENT 0x21D /* Int 2 1st Stage Cascode Current */ +#define REG_INT_2_2ND_STAGE_CURRENT 0x21E /* Int 2 2nd Stage Current */ +#define REG_INT_3_1ST_STAGE_CURRENT 0x21F /* Int 3 1st Stage Current */ +#define REG_INT_3_1ST_STAGE_CASCODE_CURRENT 0x220 /* Int 3 1st Stage Cascode Current */ +#define REG_INT_3_2ND_STAGE_CURRENT 0x221 /* Int 3 2nd Stage Current */ +#define REG_FLASH_BIAS_CURRENT 0x222 /* Flash Bias Current */ +#define REG_FLASH_LADDER_BIAS 0x223 /* Flash Ladder Bias */ +#define REG_FLASH_LADDER_CASCODE_CURRENT 0x224 /* Flash Ladder Cascode Current */ +#define REG_FLASH_LADDER_BIAS2 0x225 /* Flash Ladder Bias2 */ +#define REG_RESET 0x226 /* Reset */ +#define REG_RX_PFD_CONFIG 0x230 /* RX PFD Config */ +#define REG_RX_INTEGER_BYTE_0 0x231 /* RX Integer Byte 0 */ +#define REG_RX_INTEGER_BYTE_1 0x232 /* RX Integer Byte 1 */ +#define REG_RX_FRACT_BYTE_0 0x233 /* RX Fractional Byte 0 */ +#define REG_RX_FRACT_BYTE_1 0x234 /* RX Fractional Byte 1 */ +#define REG_RX_FRACT_BYTE_2 0x235 /* RX Fractional Byte 2 */ +#define REG_RX_FORCE_ALC 0x236 /* RX Force ALC */ +#define REG_RX_FORCE_VCO_TUNE_0 0x237 /* RX Force VCO Tune 0 */ +#define REG_RX_FORCE_VCO_TUNE_1 0x238 /* RX Force VCO Tune 1 */ +#define REG_RX_ALC_VARACTOR 0x239 /* RX ALC/Varactor */ +#define REG_RX_VCO_OUTPUT 0x23A /* RX VCO Output */ +#define REG_RX_CP_CURRENT 0x23B /* RX CP Current */ +#define REG_RX_CP_OFFSET 0x23C /* RX CP Offset */ +#define REG_RX_CP_CONFIG 0x23D /* RX CP Config */ +#define REG_RX_LOOP_FILTER_1 0x23E /* RX Loop Filter 1 */ +#define REG_RX_LOOP_FILTER_2 0x23F /* RX Loop Filter 2 */ +#define REG_RX_LOOP_FILTER_3 0x240 /* RX Loop Filter 3 */ +#define REG_RX_DITHERCP_CAL 0x241 /* RX Dither/CP Cal */ +#define REG_RX_VCO_BIAS_1 0x242 /* RX VCO Bias 1 */ +#define REG_RX_CAL_STATUS 0x244 /* RX Cal Status */ +#define REG_RX_VCO_CAL_REF 0x245 /* RX VCO Cal Ref */ +#define REG_RX_VCO_PD_OVERRIDES 0x246 /* RX VCO Pd Overrides */ +#define REG_RX_CP_OVERRANGE_VCO_LOCK 0x247 /* RX CP Over Range/VCO Lock */ +#define REG_RX_VCO_LDO 0x248 /* RX VCO LDO */ +#define REG_RX_VCO_CAL 0x249 /* RX VCO Cal */ +#define REG_RX_LOCK_DETECT_CONFIG 0x24A /* RX Lock Detect Config */ +#define REG_RX_CP_LEVEL_DETECT 0x24B /* RX CP Level Detect */ +#define REG_RX_DSM_SETUP_0 0x24C /* RX DSM Setup 0 */ +#define REG_RX_DSM_SETUP_1 0x24D /* RX DSM Setup 1 */ +#define REG_RX_CORRECTION_WORD0 0x24E /* RX Correction Word0 */ +#define REG_RX_CORRECTION_WORD1 0x24F /* RX Correction Word1 */ +#define REG_RX_VCO_VARACTOR_CTRL_0 0x250 /* RX VCO Varactor Control 0 */ +#define REG_RX_VCO_VARACTOR_CTRL_1 0x251 /* RX VCO Varactor Control 1 */ +#define REG_RX_FAST_LOCK_SETUP 0x25A /* Rx Fast Lock Setup */ +#define REG_RX_FAST_LOCK_SETUP_INIT_DELAY 0x25B /* Rx Fast Lock Setup Init Delay */ +#define REG_RX_FAST_LOCK_PROGRAM_ADDR 0x25C /* Rx Fast Lock Program Addr */ +#define REG_RX_FAST_LOCK_PROGRAM_DATA 0x25D /* Rx Fast Lock Program Data */ +#define REG_RX_FAST_LOCK_PROGRAM_READ 0x25E /* Rx Fast Lock Program Read */ +#define REG_RX_FAST_LOCK_PROGRAM_CTRL 0x25F /* Rx Fast Lock Program Control */ +#define REG_RX_LO_GEN_POWER_MODE 0x261 /* Rx LO Gen Power Mode */ +#define REG_TX_PFD_CONFIG 0x270 /* TX PFD Config */ +#define REG_TX_INTEGER_BYTE_0 0x271 /* TX Integer Byte 0 */ +#define REG_TX_INTEGER_BYTE_1 0x272 /* TX Integer Byte 1 */ +#define REG_TX_FRACT_BYTE_0 0x273 /* TX Fractional Byte 0 */ +#define REG_TX_FRACT_BYTE_1 0x274 /* TX Fractional Byte 1 */ +#define REG_TX_FRACT_BYTE_2 0x275 /* TX Fractional Byte 2 */ +#define REG_TX_FORCE_ALC 0x276 /* TX Force ALC */ +#define REG_TX_FORCE_VCO_TUNE_0 0x277 /* TX Force VCO Tune 0 */ +#define REG_TX_FORCE_VCO_TUNE_1 0x278 /* TX Force VCO Tune 1 */ +#define REG_TX_ALCVARACT_OR 0x279 /* TX ALC/Varact or */ +#define REG_TX_VCO_OUTPUT 0x27A /* TX VCO Output */ +#define REG_TX_CP_CURRENT 0x27B /* TX CP Current */ +#define REG_TX_CP_OFFSET 0x27C /* TX CP Offset */ +#define REG_TX_CP_CONFIG 0x27D /* TX CP Config */ +#define REG_TX_LOOP_FILTER_1 0x27E /* TX Loop Filter 1 */ +#define REG_TX_LOOP_FILTER_2 0x27F /* TX Loop Filter 2 */ +#define REG_TX_LOOP_FILTER_3 0x280 /* TX Loop Filter 3 */ +#define REG_TX_DITHERCP_CAL 0x281 /* TX Dither/CP Cal */ +#define REG_TX_VCO_BIAS_1 0x282 /* TX VCO Bias 1 */ +#define REG_TX_VCO_BIAS_2 0x283 /* TX VCO Bias 2 */ +#define REG_TX_CAL_STATUS 0x284 /* TX Cal Status */ +#define REG_TX_VCO_CAL_REF 0x285 /* TX VCO Cal Ref */ +#define REG_TX_VCO_PD_OVERRIDES 0x286 /* TX VCO Pd Overrides */ +#define REG_TX_CP_OVERRANGE_VCO_LOCK 0x287 /* TX CP Over Range/VCO Lock */ +#define REG_TX_VCO_LDO 0x288 /* TX VCO LDO */ +#define REG_TX_VCO_CAL 0x289 /* TX VCO Cal */ +#define REG_TX_LOCK_DETECT_CONFIG 0x28A /* TX Lock Detect Config */ +#define REG_TX_CP_LEVEL_DETECT 0x28B /* TX CP Level Detect */ +#define REG_TX_DSM_SETUP_0 0x28C /* TX DSM Setup 0 */ +#define REG_TX_DSM_SETUP_1 0x28D /* TX DSM Setup 1 */ +#define REG_TX_CORRECTION_WORD0 0x28E /* TX Correction Word0 */ +#define REG_TX_CORRECTION_WORD1 0x28F /* TX Correction Word1 */ +#define REG_TX_VCO_VARACTOR_CTRL_0 0x290 /* TX VCO Varactor Control 0 */ +#define REG_TX_VCO_VARACTOR_CTRL_1 0x291 /* TX VCO Varactor Control 1 */ +#define REG_DCXO_COARSE_TUNE 0x292 /* DCXO Coarse Tune */ +#define REG_DCXO_FINE_TUNE_HIGH 0x293 /* DCXO Fine Tune2 */ +#define REG_DCXO_FINE_TUNE_LOW 0x294 /* DCXO Fine Tune1 */ +#define REG_DCXO_CONFIG 0x295 /* DCXO Config */ +#define REG_DCXO_TEMPCO_WRITE 0x296 /* DCXO Tempco Write */ +#define REG_DCXO_TEMPCO_READ 0x297 /* DCXO Tempco Read */ +#define REG_DCXO_TEMPCO_ADDR 0x298 /* DCXO Tempco Addr */ +#define REG_DELTA_T_READ 0x299 /* Delta T Read */ +#define REG_TX_FAST_LOCK_SETUP 0x29A /* Tx Fast Lock Setup */ +#define REG_TX_FAST_LOCK_SETUP_INIT_DELAY 0x29B /* Tx Fast Lock Setup Init Delay */ +#define REG_TX_FAST_LOCK_PROGRAM_ADDR 0x29C /* Tx Fast Lock Program Addr */ +#define REG_TX_FAST_LOCK_PROGRAM_DATA 0x29D /* Tx Fast Lock Program Data */ +#define REG_TX_FAST_LOCK_PROGRAM_READ 0x29E /* Tx Fast Lock Program Read */ +#define REG_TX_FAST_LOCK_PROGRAM_CTRL 0x29F /* Tx Fast Lock Program Ctrl */ +#define REG_TX_LO_GEN_POWER_MODE 0x2A1 /* Tx LO Gen Power Mode */ +#define REG_BANDGAP_CONFIG0 0x2A6 /* Bandgap Config0 */ +#define REG_BANDGAP_CONFIG1 0x2A8 /* Bandgap Config1 */ +#define REG_REF_DIVIDE_CONFIG_1 0x2AB /* Ref Divide Config 1 */ +#define REG_REF_DIVIDE_CONFIG_2 0x2AC /* Ref Divide Config 2 */ +#define REG_GAIN_RX1 0x2B0 /* Gain Rx1 */ +#define REG_LPF_GAIN_RX1 0x2B1 /* LPF Gain Rx1 */ +#define REG_DIG_GAIN_RX1 0x2B2 /* Dig gain Rx1 */ +#define REG_FAST_ATTACK_STATE 0x2B3 /* Fast Attack State */ +#define REG_SLOW_LOOP_STATE 0x2B4 /* Slow Loop State */ +#define REG_GAIN_RX2 0x2B5 /* Gain Rx2 */ +#define REG_LPF_GAIN_RX2 0x2B6 /* LPF Gain Rx2 */ +#define REG_DIG_GAIN_RX2 0x2B7 /* Dig Gain Rx2 */ +#define REG_OVRG_SIGS_RX1 0x2B8 /* Ovrg Sigs Rx1 */ +#define REG_OVRG_SIGS_RX2 0x2B9 /* Ovrg Sigs Rx2 */ +#define REG_CTRL 0x3DF /* Control */ +#define REG_BIST_CONFIG 0x3F4 /* BIST Config */ +#define REG_OBSERVE_CONFIG 0x3F5 /* Observe Config */ +#define REG_BIST_AND_DATA_PORT_TEST_CONFIG 0x3F6 /* BIST and Data Port Test Config */ +#define REG_DAC_TEST_0 0x3FC /* DAC Test 0 */ +#define REG_DAC_TEST_1 0x3FD /* DAC Test 1 */ +#define REG_DAC_TEST_2 0x3FE /* DAC Test 2 */ + +/* +* REG_SPI_CONF +*/ +#define SOFT_RESET (1 << 7) /* Soft Reset */ +#define WIRE3_SPI (1 << 6) /* 3-Wire SPI */ +#define LSB_FIRST (1 << 5) /* LSB First */ +#define _LSB_FIRST (1 << 2) /* LSB First */ +#define _WIRE3_SPI (1 << 1) /* 3-Wire SPI */ +#define _SOFT_RESET (1 << 0) /* Soft reset */ + +/* +* REG_MULTICHIP_SYNC_AND_TX_MON_CTRL +*/ +#define TX2_MONITOR_ENABLE (1 << 6) /* Tx2 Monitor Enable */ +#define TX1_MONITOR_ENABLE (1 << 5) /* Tx1 Monitor Enable */ +#define MCS_RF_ENABLE (1 << 3) /* MCS RF Enable */ +#define MCS_BBPLL_ENABLE (1 << 2) /* MCS BBPLL enable */ +#define MCS_DIGITAL_CLK_ENABLE (1 << 1) /* MCS Digital CLK Enable */ +#define MCS_BB_ENABLE (1 << 0) /* MCS BB Enable */ + +/* +* REG_TX_ENABLE_FILTER_CTRL +*/ +#define THB2_EN (1 << 3) /* THB2 Enable */ +#define THB1_EN (1 << 2) /* THB1 Enable */ +#define TX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6) /* Tx channel Enable<1:0> */ +#define THB3_ENABLE_INTERP(x) (((x) & 0x3) << 4) /* THB3 Enable & Interp<1:0> */ +#define TX_FIR_ENABLE_INTERPOLATION(x) (((x) & 0x3) << 0) /* Tx FIR Enable & Interpolation<1:0> */ +#define TX_1 1 +#define TX_2 2 +#define TX_ENABLE 1 +#define TX_DISABLE 0 + +/* +* REG_RX_ENABLE_FILTER_CTRL +*/ +#define RHB2_EN (1 << 3) /* RHB2 Enable */ +#define RHB1_EN (1 << 2) /* RHB1 Enable */ +#define RX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6) /* Rx channel Enable<1:0> */ +#define DEC3_ENABLE_DECIMATION(x) (((x) & 0x3) << 4) /* DEC3 Enable & Decimation<1:0> */ +#define RX_FIR_ENABLE_DECIMATION(x) (((x) & 0x3) << 0) /* Rx FIR Enable & Decimation<1:0> */ +#define RX_1 1 +#define RX_2 2 +#define RX_ENABLE 1 +#define RX_DISABLE 0 + +/* +* REG_INPUT_SELECT +*/ +#define TX_OUTPUT (1 << 6) /* TX Output */ +#define RX_INPUT(x) (((x) & 0x3F) << 0) /* RX Input <5:0> */ + +/* +* REG_RFPLL_DIVIDERS +*/ +#define TX_VCO_DIVIDER(x) (((x) & 0xF) << 4) /* TX VCO Divider<3:0> */ +#define RX_VCO_DIVIDER(x) (((x) & 0xF) << 0) /* RX VCO Divider<3:0> */ + +/* +* REG_RX_CLOCK_DATA_DELAY +*/ +#define DATA_CLK_DELAY(x) (((x) & 0xF) << 4) /* DATA_CLK Delay<3:0> */ +#define RX_DATA_DELAY(x) (((x) & 0xF) << 0) /* Rx Data Delay <3:0> */ + +/* +* REG_TX_CLOCK_DATA_DELAY +*/ +#define FB_CLK_DELAY(x) (((x) & 0xF) << 4) /* FB_CLK Delay<3:0> */ +#define TX_DATA_DELAY(x) (((x) & 0xF) << 0) /* Tx Data Delay <3:0> */ + +/* +* REG_CLOCK_ENABLE +*/ +#define XO_BYPASS (1 << 4) /* XO Bypass */ +#define DIGITAL_POWER_UP (1 << 2) /* Digital Power Up */ +#define CLOCK_ENABLE_DFLT (1 << 1) /* Set to 1 */ +#define BBPLL_ENABLE (1 << 0) /* BBPLL Enable */ + +/* +* REG_BBPLL +*/ +#define CLKOUT_ENABLE (1 << 4) /* CLKOUT Enable */ +#define DAC_CLK_DIV2 (1 << 3) /* DAC Clk div2 */ +#define CLKOUT_SELECT(x) (((x) & 0x7) << 5) /* CLKOUT Select<2:0> */ +#define BBPLL_DIVIDER(x) (((x) & 0x7) << 0) /* BBPLL Divider <2:0> */ + +/* +* REG_START_TEMP_READING +*/ +#define START_TEMP_READING (1 << 0) /* Start Temp Reading */ + +/* +* REG_TEMP_SENSE2 +*/ +#define TEMP_SENSE_PERIODIC_ENABLE (1 << 0) /* Temp Sense Periodic Enable */ +#define MEASUREMENT_TIME_INTERVAL(x) (((x) & 0x7F) << 1) /* Measurement Time Interval<6:0> */ + +/* +* REG_TEMP_SENSOR_CONFIG +*/ +#define TEMP_SENSOR_DECIMATION(x) (((x) & 0x7) << 0) /* Temp Sensor Decimation<2:0> */ + +/* +* REG_PARALLEL_PORT_CONF_1 +*/ +#define PP_TX_SWAP_IQ (1 << 7) /* PP Tx Swap IQ */ +#define PP_RX_SWAP_IQ (1 << 6) /* PP Rx Swap IQ */ +#define TX_CHANNEL_SWAP (1 << 5) /* Tx Channel swap */ +#define RX_CHANNEL_SWAP (1 << 4) /* Rx Channel swap */ +#define RX_FRAME_PULSE_MODE (1 << 3) /* Rx Frame Pulse Mode */ +#define R2T2_TIMING (1 << 2) /* 2R2T Timing */ +#define INVERT_DATA_BUS (1 << 1) /* Invert data bus */ +#define INVERT_DATA_CLK (1 << 0) /* Invert DATA CLK */ + +/* +* REG_PARALLEL_PORT_CONF_2 +*/ +#define FDD_ALT_WORD_ORDER (1 << 7) /* FDD Alt Word Order */ +#define INVERT_RX1 (1 << 6) /* Invert Rx1 */ +#define INVERT_RX2 (1 << 5) /* Invert Rx2 */ +#define INVERT_TX1 (1 << 4) /* Invert Tx1 */ +#define INVERT_TX2 (1 << 3) /* Invert Tx2 */ +#define INVERT_RX_FRAME (1 << 2) /* Invert Rx Frame */ +#define DELAY_RX_DATA(x) (((x) & 0x3) << 0) /* Delay Rx Data<1:0> */ + +/* +* REG_PARALLEL_PORT_CONF_3 +*/ +#define FDD_RX_RATE_2TX_RATE (1 << 7) /* FDD Rx Rate = 2*Tx Rate */ +#define SWAP_PORTS (1 << 6) /* Swap Ports */ +#define SINGLE_DATA_RATE (1 << 5) /* Single Data Rate */ +#define LVDS_MODE (1 << 4) /* LVDS Mode */ +#define HALF_DUPLEX_MODE (1 << 3) /* Half Duplex Mode */ +#define SINGLE_PORT_MODE (1 << 2) /* Single Port Mode */ +#define FULL_PORT (1 << 1) /* Full Port */ +#define FULL_DUPLEX_SWAP_BITS (1 << 0) /* Full Duplex Swap Bits */ + +/* +* REG_ENSM_MODE +*/ +#define FDD_MODE (1 << 0) /* FDD Mode */ + +/* +* REG_ENSM_CONFIG_1 +*/ +#define ENABLE_RX_DATA_PORT_FOR_CAL (1 << 7) /* Enable Rx Data Port for Cal */ +#define FORCE_RX_ON (1 << 6) /* Force Rx On */ +#define FORCE_TX_ON (1 << 5) /* Force Tx On */ +#define ENABLE_ENSM_PIN_CTRL (1 << 4) /* Enable ENSM Pin Control */ +#define LEVEL_MODE (1 << 3) /* Level Mode */ +#define FORCE_ALERT_STATE (1 << 2) /* Force Alert State */ +#define AUTO_GAIN_LOCK (1 << 1) /* Auto Gain Lock */ +#define TO_ALERT (1 << 0) /* To Alert */ + +/* +* REG_ENSM_CONFIG_2 +*/ +#define FDD_EXTERNAL_CTRL_ENABLE (1 << 7) /* FDD External Control Enable */ +#define POWER_DOWN_RX_SYNTH (1 << 6) /* Power Down Rx Synth */ +#define POWER_DOWN_TX_SYNTH (1 << 5) /* Power Down Tx Synth */ +#define TXNRX_SPI_CTRL (1 << 4) /* TXNRX SPI Control */ +#define SYNTH_ENABLE_PIN_CTRL_MODE (1 << 3) /* Synth Enable Pin Control Mode */ +#define DUAL_SYNTH_MODE (1 << 2) /* Dual Synth Mode */ +#define RX_SYNTH_READY_MASK (1 << 1) /* Rx Synth Ready Mask */ +#define TX_SYNTH_READY_MASK (1 << 0) /* Tx Synth Ready Mask */ + +/* +* REG_CALIBRATION_CTRL +*/ +#define RX_BB_TUNE_CAL (1 << 7) /* Rx BB Tune */ +#define TX_BB_TUNE_CAL (1 << 6) /* Tx BB Tune */ +#define RX_QUAD_CAL (1 << 5) /* Rx Quad Cal */ +#define TX_QUAD_CAL (1 << 4) /* Tx Quad Cal */ +#define RX_GAIN_STEP_CAL (1 << 3) /* Rx Gain Step Cal */ +#define TXMON_CAL (1 << 2) +#define RFDC_CAL (1 << 1) /* DC Cal RF Start */ +#define BBDC_CAL (1 << 0) /* DC cal BB Start */ + + +/* +* REG_STATE +*/ +#define CALIBRATION_SEQUENCE_STATE(x) (((x) & 0xF) << 4) /* Calibration Sequence State<3:0> */ +#define ENSM_STATE(x) (((x) & 0xF) << 0) /* ENSM State<3:0> */ +#define ENSM_STATE_SLEEP_WAIT 0x0 +#define ENSM_STATE_ALERT 0x5 +#define ENSM_STATE_TX 0x6 +#define ENSM_STATE_TX_FLUSH 0x7 +#define ENSM_STATE_RX 0x8 +#define ENSM_STATE_RX_FLUSH 0x9 +#define ENSM_STATE_FDD 0xA +#define ENSM_STATE_FDD_FLUSH 0xB +#define ENSM_STATE_INVALID 0xFF +#define ENSM_STATE_SLEEP 0x80 + +/* +* REG_AUXDAC_2_WORD +*/ +#define AUXDAC_2_WORD_MSB(x) (((x) & 0x3F) << 2) /* AuxDAC 2 Word<9:2> */ +#define AUXDAC_1_WORD(x) (((x) & 0x3) << 0) /* AuxDAC 1 Word <1:0> */ + +/* +* REG_AUXDAC_1_CONFIG +*/ +#define COMP_CTRL_1 (1 << 5) /* Comp Ctrl 1 */ +#define AUXDAC1_STP_FACTOR (1 << 4) /* AuxDAC1 Step Factor */ +#define AUXDAC_1_VREF(x) (((x) & 0x3) << 2) /* AuxDAC 1 Vref<1:0> */ +#define AUXDAC_1_WORD_LSB(x) (((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */ + +/* +* REG_AUXDAC_2_CONFIG +*/ +#define COMP_CTRL_2 (1 << 5) /* Comp Ctrl 2 */ +#define AUXDAC2_STP_FACTOR (1 << 4) /* AuxDAC2 Step Factor */ +#define AUXDAC_2_VREF(x) (((x) & 0xF) << 2) /* AuxDAC 2 Vref<1:0> */ +#define AUXDAC_2_WORD_LSB(x) (((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */ + +/* +* REG_AUXADC_CLOCK_DIVIDER +*/ +#define AUXADC_CLOCK_DIVIDER(x) (((x) & 0x3F) << 0) /* AuxADC Clock Divider<5:0> */ + +/* +* REG_AUXADC_CONFIG +*/ +#define AUXADC_POWER_DOWN (1 << 0) /* AuxADC Power Down */ +#define AUX_ADC_DECIMATION(x) (((x) & 0x7) << 1) /* Aux ADC Decimation<2:0> */ + +/* +* REG_AUXADC_LSB +*/ +#define AUXADC_WORD_LSB(x) (((x) & 0xF) << 0) /* AuxADC Word LSB<3:0> */ + +/* +* REG_AUTO_GPO +*/ +#define GPO_ENABLE_AUTO_RX(x) (((x) & 0xF) << 4) /* GPO Enable Auto Rx<3:0> */ +#define GPO_ENABLE_AUTO_TX(x) (((x) & 0xF) << 0) /* GPO Enable Auto Tx<3:0> */ + +/* +* REG_AGC_ATTACK_DELAY +*/ +#define INVERT_BYPASSED_LNA_POLARITY (1 << 6) /* Invert Bypassed LNA Polarity */ +#define AGC_ATTACK_DELAY(x) (((x) & 0x3F) << 0) /* AGC Attack Delay<5:0> */ + +/* +* REG_AUXDAC_ENABLE_CTRL +*/ +#define AUXDAC_MANUAL_BAR(x) (((x) & 0x3) << 6) /* AuxDac Manual Bar<1:0> */ +#define AUXDAC_AUTO_TX_BAR(x) (((x) & 0x3) << 4) /* AuxDAC Auto Tx Bar<1:0> */ +#define AUXDAC_AUTO_RX_BAR(x) (((x) & 0x3) << 2) /* AuxDAC Auto Rx Bar<1:0> */ +#define AUXDAC_INIT_BAR(x) (((x) & 0x3) << 0) /* AuxDAC Init Bar<1:0> */ + +/* +* REG_EXTERNAL_LNA_CTRL +*/ +#define AUXDAC_MANUAL_SELECT (1 << 7) /* AuxDAC Manual Select */ +#define EXTERNAL_LNA2_CTRL (1 << 6) /* External LNA2 control */ +#define EXTERNAL_LNA1_CTRL (1 << 5) /* External LNA1 control */ +#define GPO_MANUAL_SELECT (1 << 4) /* GPO manual select */ +#define OPEN(x) (((x) & 0xF) << 0) /* Open<3:0> */ + +/* +* REG_GPO_FORCE_AND_INIT +*/ +#define GPO_MANUAL_CTRL(x) (((x) & 0xF) << 4) /* GPO Manual Control<3:0> */ +#define GPO_INIT_STATE(x) (((x) & 0xF) << 0) /* GPO Init State<3:0> */ + +/* +* REG_CTRL_OUTPUT_ENABLE +*/ +#define EN_CTRL7 (1 << 7) /* En ctrl7 */ +#define EN_CTRL6 (1 << 6) /* En ctrl6 */ +#define EN_CTRL5 (1 << 5) /* En ctrl5 */ +#define EN_CTRL4 (1 << 4) /* En ctrl4 */ +#define EN_CTRL3 (1 << 3) /* En ctrl3 */ +#define EN_CTRL2 (1 << 2) /* En ctrl2 */ +#define EN_CTRL1 (1 << 1) /* En ctrl1 */ +#define EN_CTRL0 (1 << 0) /* En ctrl0 */ + +/* +* REG_PRODUCT_ID +*/ +#define PRODUCT_ID_MASK 0xF8 +#define PRODUCT_ID_9361 0x08 +#define REV_MASK 0x07 + +/* +* REG_REFERENCE_CLOCK_CYCLES +*/ +#define REFERENCE_CLOCK_CYCLES_PER_US(x) (((x) & 0x7F) << 0) /* Reference Clock Cycles per us<6:0> */ + +/* +* REG_DIGITAL_IO_CTRL +*/ +#define CLK_OUT_DRIVE (1 << 7) /* CLK Out Drive */ +#define DATACLK_DRIVE (1 << 6) /* DATACLK drive */ +#define DATA_PORT_DRIVE (1 << 2) /* Data Port Drive */ +#define DATACLK_SLEW(x) (((x) & 0x3) << 4) /* DATACLK slew <1:0> */ +#define DATA_PORT_SLEW(x) (((x) & 0x3) << 0) /* Data Port Slew<1:0> */ + +/* +* REG_LVDS_BIAS_CTRL +*/ +#define RX_ON_CHIP_TERM (1 << 5) /* Rx On Chip Term */ +#define LVDS_BYPASS_BIAS_R (1 << 4) /* Bypass Bias R */ +#define LVDS_TX_LO_VCM (1 << 3) /* LVDS Tx LO VCM */ +#define CLK_OUT_SLEW(x) (((x) & 0x3) << 6) /* CLK Out Slew<1:0> */ +#define LVDS_BIAS(x) (((x) & 0x7) << 0) /* LVDS Bias <2:0> */ + +/* +* REG_SDM_CTRL_1 +*/ +#define INIT_BB_FO_CAL (1 << 2) /* Init BB FO CAL */ +#define BBPLL_RESET_BAR (1 << 0) /* BBPLL Reset Bar */ + +/* +* REG_CLOCK_CTRL +*/ +#define REF_FREQ_SCALER(x) (((x) & 0x3) << 0) /* Ref Frequency Scaler */ + +/* +* REG_CP_CURRENT +*/ +#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */ + +/* +* REG_CP_BLEED_CURRENT +*/ +#define MCS_REFCLK_SCALE_EN (1 << 7) /* MCS refclk Scale En */ + +/* +* REG_LOOP_FILTER_1 +*/ +#define C1_WORD(x) (((x) & 0x7) << 5) /* C1 Word<2:0> */ +#define R1_WORD(x) (((x) & 0x1F) << 0) /* R1 Word<4:0> */ + +/* +* REG_LOOP_FILTER_2 +*/ +#define R2_WORD (1 << 7) /* R2 Word<0> */ +#define C2_WORD(x) (((x) & 0x1F) << 2) /* C2 Word<4:0> */ +#define C1_WORD_LSB(x) (((x) & 0x3) << 0) /* C1 Word<4:3> */ + +/* +* REG_LOOP_FILTER_3 +*/ +#define BYPASS_C3 (1 << 7) /* Bypass C3 */ +#define BYPASS_R2 (1 << 6) /* Bypass R2 */ +#define C3_WORD(x) (((x) & 0xF) << 2) /* C3 Word<3:0> */ +#define R2_WORD_LSB(x) (((x) & 0x3) << 0) /* R2 Word<2:1> */ + +/* +* REG_VCO_CTRL +*/ +#define FREQ_CAL_ENABLE (1 << 7) /* Freq Cal Enable */ +#define FREQ_CAL_RESET (1 << 4) /* Freq Cal Reset */ +#define FREQ_CAL_COUNT_LENGTH(x) (((x) & 0x3) << 5) /* Freq Cal Count Length<1:0> */ + +/* +* REG_SDM_CTRL +*/ +#define CAL_CLOCK_DIV_4 (1 << 4) /* Cal Clock div 4 */ + +/* +* REG_RX_SYNTH_POWER_DOWN_OVERRIDE +*/ +#define RX_LO_POWER_DOWN (1 << 4) /* Rx LO Power Down */ +#define RX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3) /* Rx Synth VCO ALC Power Down */ +#define RX_SYNTH_PTAT_POWER_DOWN (1 << 2) /* Rx Synth PTAT Power Down */ +#define RX_SYNTH_VCO_POWER_DOWN (1 << 1) /* Rx Synth VCO Power Down */ +#define RX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0) /* Rx Synth VCO LDO Power Down */ + +/* +* REG_TX_SYNTH_POWER_DOWN_OVERRIDE +*/ +#define TX_LO_POWER_DOWN (1 << 4) /* Tx LO Power Down */ +#define TX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3) /* Tx Synth VCO ALC Power Down */ +#define TX_SYNTH_PTAT_POWER_DOWN (1 << 2) /* Tx Synth PTAT Power Down */ +#define TX_SYNTH_VCO_POWER_DOWN (1 << 1) /* Tx Synth VCO Power Down */ +#define TX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0) /* Tx Synth VCO LDO Power Down */ + +/* +* REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1 +*/ +#define RX_OFFSET_DAC_CGIN_POWER_DOWN(x) (((x) & 0x3) << 6) /* Rx Offset DAC CGin Power Down<1:0> */ +#define RX_LMT_OVERLOAD_POWER_DOWN(x) (((x) & 0x3) << 4) /* Rx LMT Overload Power Down<1:0> */ +#define RX_MIXER_GM_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Mixer Gm Power Down<1:0> */ +#define RX_CGB_POWER_DOWN(x) (((x) & 0x3) << 0) /* Rx CGB Power Down<1:0> */ + +/* +* REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2 +*/ +#define RX_BBF_POWER_DOWN(x) (((x) & 0x3) << 6) /* Rx BBF Power Down<1:0> */ +#define RX_TIA_POWER_DOWN(x) (((x) & 0x3) << 4) /* Rx TIA Power Down<1:0> */ +#define RX_MIXER_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Mixer Power Down<1:0> */ +#define RX_OFFSET_DAC_CGOUT_POWER_DOWN(x) (((x) & 0x3) << 0) /* Rx Offset DAC CGOut Power Down<1:0> */ + +/* +* REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1 +*/ +#define TX_SECONDARY_FILTER_POWER_DOWN(x) (((x) & 0x3) << 6) /* Tx Secondary Filter Power Down<1:0> */ +#define TX_BBF_POWER_DOWN(x) (((x) & 0x3) << 4) /* Tx BBF Power Down<1:0> */ +#define TX_DAC_POWER_DOWN(x) (((x) & 0x3) << 2) /* Tx DAC Power Down<1:0> */ +#define TX_DAC_BIAS_POWER_DOWN(x) (((x) & 0x3) << 0) /* Tx DAC Bias Power Down<1:0> */ + +/* +* REG_ANALOG_POWER_DOWN_OVERRIDE +*/ +#define RX_EXT_VCO_BUFFER_POWER_DOWN (1 << 5) /* Rx Ext VCO Buffer Power Down */ +#define TX_EXT_VCO_BUFFER_POWER_DOWN (1 << 4) /* Tx Ext VCO Buffer Power Down */ +#define TX_MONITOR_POWER_DOWN(x) (((x) & 0x3) << 2) /* Tx Monitor Power Down<1:0> */ +#define TX_UPCONVERTER_POWER_DOWN(x) (((x) & 0x3) << 0) /* Tx Upconverter Power Down<1:0> */ + +/* +* REG_MISC_POWER_DOWN_OVERRIDE +*/ +#define RX_LNA_POWER_DOWN (1 << 6) /* Rx LNA Power Down */ +#define DCXO_POWER_DOWN (1 << 1) /* DCXO Power Down */ +#define MASTER_BIAS_POWER_DOWN (1 << 0) /* Master Bias Power Down */ +#define RX_CALIBRATION_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Calibration Power Down<1:0> */ + +/* +* REG_CH_1_OVERFLOW +*/ +#define BBPLL_LOCK (1 << 7) /* BBPLL Lock */ +#define CH_1_INT3 (1 << 6) /* CH 1 INT3 */ +#define CH1_HB3 (1 << 5) /* CH1 HB3 */ +#define CH1_HB2 (1 << 4) /* CH1 HB2 */ +#define CH1_QEC (1 << 3) /* CH1 QEC */ +#define CH1_HB1 (1 << 2) /* CH1 HB1 */ +#define CH1_TFIR (1 << 1) /* CH1 TFIR */ +#define CH1_RFIR (1 << 0) /* CH1 RFIR */ + +/* +* REG_CH_2_OVERFLOW +*/ +#define CH2_INT3 (1 << 6) /* CH2 INT3 */ +#define CH2_HB3 (1 << 5) /* CH2 HB3 */ +#define CH2_HB2 (1 << 4) /* CH2 HB2 */ +#define CH2_QEC (1 << 3) /* CH2 QEC */ +#define CH2_HB1 (1 << 2) /* CH2 HB1 */ +#define CH2_TFIR (1 << 1) /* CH2 TFIR */ +#define CH2_RFIR (1 << 0) /* CH2 RFIR */ + +/* +* REG_TX_FILTER_CONF +*/ +#define TX_FIR_GAIN_6DB (1 << 0) /* Filter Gain */ +#define FIR_START_CLK (1 << 1) /* Start Tx/Rx Clock */ +#define FIR_WRITE (1 << 2) /* Write Tx/Rx */ +#define FIR_SELECT(x) (((x) & 0x3) << 3) /* Select Tx/Rx CH<1:0> */ +#define FIR_NUM_TAPS(x) (((x) & 0x7) << 5) /* Number of Taps<2:0> */ + +/* +* REG_TX_MON_LOW_GAIN +*/ +#define TX_MON_TRACK (1 << 5) /* Tx Mon Track */ +#define TX_MON_LOW_GAIN(x) (((x) & 0x1F) << 0) /* Tx Mon Low Gain<4:0> */ + +/* +* REG_TX_MON_HIGH_GAIN +*/ +#define TX_MON_HIGH_GAIN(x) (((x) & 0x1F) << 0) /* Tx Mon High Gain<4:0> */ + +/* +* REG_TX_LEVEL_THRESH +*/ +#define TX_LEVEL_THRESH(x) (((x) & 0x3F) << 2) /* Tx Level Threshold<5:0> */ +#define TX_MON_DELAY_COUNTER(x) (((x) & 0x3) << 0) /* Tx Mon Delay Counter<9:8> */ + +/* +* REG_TX_RSSI_LSB +*/ +#define TX_RSSI_2 (1 << 1) /* Tx RSSI 2<0> */ +#define TX_RSSI_1 (1 << 0) /* TX RSSI 1<0> */ + +/* +* REG_TPM_MODE_ENABLE +*/ +#define TX2_MON_ENABLE (1 << 7) /* Tx2 Monitor Enable */ +#define TX1_MON_ENABLE (1 << 5) /* Tx1 Monitor Enable */ +#define ONE_SHOT_MODE (1 << 6) /* One Shot Mode */ +#define TX_MON_DURATION(x) (((x) & 0xF) << 0) /* Tx Mon Duration<3:0> */ + +/* +* REG_TX_MON_1_CONFIG +*/ +#define TX_MON_1_LO_CM(x) (((x) & 0x3F) << 2) /* Tx Mon 1 LO CM<5:0> */ +#define TX_MON_1_GAIN(x) (((x) & 0x3) << 0) /* Tx Mon 1 Gain<1:0> */ + +/* +* REG_TX_MON_2_CONFIG +*/ +#define TX_MON_2_LO_CM(x) (((x) & 0x3F) << 2) /* Tx Mon 2 LO CM<5:0> */ +#define TX_MON_2_GAIN(x) (((x) & 0x3) << 0) /* Tx Mon 2 Gain<1:0> */ + +/* +* REG_TX1_ATTEN_1 +*/ +#define TX_1_ATTEN (1 << 0) /* Tx 1 Atten <8> */ + +/* +* REG_TX2_ATTEN_1 +*/ +#define TX_2_ATTEN (1 << 0) /* Tx 2 Atten <8> */ + +/* +* REG_TX_ATTEN_OFFSET +*/ +#define MASK_CLR_ATTEN_UPDATE (1 << 6) /* Mask Clr Atten Update */ +#define TX_ATTEN_OFFSET(x) (((x) & 0x3F) << 0) /* Tx Atten Offset<5:0> */ + +/* +* REG_TX1_DIG_ATTEN +*/ +#define SEL_TX1_TX2 (1 << 6) /* Sel Tx1 & Ttx2 */ + +/* +* REG_TX2_DIG_ATTEN +*/ +#define IMMEDIATELY_UPDATE_TPC_ATTEN (1 << 6) /* Immediately Update TPC Atten */ + +/* +* REG_TX1_SYMBOL_ATTEN +*/ +#define TX_1_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0) /* Tx 1 Symbol Attenuation<6:0> */ + +/* +* REG_TX2_SYMBOL_ATTEN +*/ +#define TX_2_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0) /* Tx 2 Symbol Attenuation<6:0> */ + +/* +* REG_TX_SYMBOL_ATTEN_CONFIG +*/ +#define USE_TX1_PIN_SYMBOL_ATTEN (1 << 3) /* Use Tx1 Pin & Symbol Atten */ +#define USE_CTRL_IN_FOR_SYMBOL_ATTEN (1 << 1) /* Use CTRL IN for symbol Atten */ +#define ENABLE_SYMBOL_ATTEN (1 << 0) /* Enable Symbol Atten */ + +/* +* REG_TX_FORCE_BITS +*/ +#define FORCE_OUT_2_TX2_OFFSET (1 << 7) /* Force Out 2 Tx2 Offset */ +#define FORCE_OUT_2_TX1_OFFSET (1 << 6) /* Force Out 2 Tx1 Offset */ +#define FORCE_OUT_2_TX2_PHASE_GAIN (1 << 5) /* Force Out 2 Tx2 Phase & Gain */ +#define FORCE_OUT_2_TX1_PHASE_GAIN (1 << 4) /* Force Out 2 Tx1 Phase & Gain */ +#define FORCE_OUT_1_TX2_OFFSET (1 << 3) /* Force Out 1 Tx2 Offset */ +#define FORCE_OUT_1_TX1_OFFSET (1 << 2) /* Force Out 1 Tx1 Offset */ +#define FORCE_OUT_1_TX2_PHASE_GAIN (1 << 1) /* Force Out 1 Tx2 Phase & Gain */ +#define FORCE_OUT_1_TX1_PHASE_GAIN (1 << 0) /* Force Out 1 Tx1 Phase & Gain */ + +/* +* REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET +*/ +#define RX_NCO_FREQ(x) (((x) & 0x3) << 5) /* Rx NCO Frequency<1:0> */ +#define RX_NCO_PHASE_OFFSET(x) (((x) & 0x1F) << 0) /* Rx NCO Phase Offset<4:0> */ + +/* +* REG_QUAD_CAL_CTRL +*/ +#define FREE_RUN_ENABLE (1 << 7) /* Free Run Enable */ +#define SETTLE_MAIN_ENABLE (1 << 6) /* Settle Main Enable */ +#define DC_OFFSET_ENABLE (1 << 5) /* DC Offset Enable */ +#define GAIN_ENABLE (1 << 4) /* Gain Enable */ +#define PHASE_ENABLE (1 << 3) /* Phase Enable */ +#define QUAD_CAL_SOFT_RESET (1 << 2) /* Quad Cal Soft Reset */ +#define M_DECIM(x) (((x) & 0x3) << 0) /* M<1:0> */ + +/* +* REG_KEXP_1 +*/ +#define KEXP_TX(x) (((x) & 0x3) << 6) /* Kexp Tx<1:0> */ +#define KEXP_TX_COMP(x) (((x) & 0x3) << 4) /* Kexp Tx_comp <1:0> */ +#define KEXP_DC_I(x) (((x) & 0x3) << 2) /* Kexp DC I <1:0> */ +#define KEXP_DC_Q(x) (((x) & 0x3) << 0) /* Kexp DC Q <1:0> */ + +/* +* REG_KEXP_2 +*/ +#define INVERT_I_DATA (1 << 5) /* Invert I data */ +#define INVERT_Q_DATA (1 << 4) /* Invert Q data */ +#define TX_NCO_FREQ(x) (((x) & 0x3) << 6) /* Tx NCO frequency<1:0> */ +#define KEXP_PHASE(x) (((x) & 0x3) << 2) /* Kexp Phase <1:0> */ +#define KEXP_AMP(x) (((x) & 0x3) << 0) /* Kexp Amp <1:0> */ + +/* +* REG_QUAD_CAL_STATUS_TX1 +*/ +#define TX1_LO_CONV (1 << 1) /* Tx1 LO Conv */ +#define TX1_SSB_CONV (1 << 0) /* Tx1 SSB Conv */ +#define TX1_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2) /* Tx1 Convergence Count<5:0> */ + +/* +* REG_QUAD_CAL_STATUS_TX2 +*/ +#define TX2_LO_CONV (1 << 1) /* Tx2 LO Conv */ +#define TX2_SSB_CONV (1 << 0) /* Tx2 SSB Conv */ +#define TX2_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2) /* Tx2 Convergence Count<5:0> */ + +/* +* REG_TX_QUAD_FULL_LMT_GAIN +*/ +#define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0) /* RX Full table/LMT table gain<6:0> */ + +/* +* REG_SQUARER_CONFIG +*/ +#define GM_STAGE_TIME_CON_OVERRIDE (1 << 5) /* Gm Stage Time Con Override */ +#define GM_STAGE_MV_HP_POLE (1 << 4) /* Gm Stage MV HP Pole */ +#define GM_STAGE_LOWER_CM (1 << 3) /* Gm Stage Lower CM */ +#define BYPASS_BIAS_R (1 << 0) /* Bypass Bias R */ +#define VBIAS_CTRL(x) (((x) & 0x3) << 1) /* Vbias Control<1:0> */ + +/* +* REG_THRESH_ACCUM +*/ +#define THRESH_ACCUMULATOR(x) (((x) & 0xF) << 0) /* Threshold Accumulator<3:0> */ + +/* +* REG_TX_QUAD_LPF_GAIN +*/ +#define RX_LPF_GAIN(x) (((x) & 0x1F) << 0) /* RX LPF gain<4:0> */ + +/* +* REG_TXDAC_VDS_I +*/ +#define TXDAC_VDS_I(x) (((x) & 0x3F) << 0) /* TxDAC Vds I<5:0> */ + +/* +* REG_TXDAC_VDS_Q +*/ +#define TXDAC_VDS_Q(x) (((x) & 0x3F) << 0) /* TxDAC Vds Q<5:0> */ + +/* +* REG_TXDAC_GN_I +*/ +#define TXDAC_GN_I(x) (((x) & 0x3F) << 0) /* txDAC_gn_I<5:0> */ + +/* +* REG_TXDAC_GN_Q +*/ +#define TXDAC_GN_Q(x) (((x) & 0x3F) << 0) /* txDAC_gn_Q<5:0> */ + +/* +* REG_TXBBF_OPAMP_A +*/ +#define OPAMPA_OUTPUT_BIAS(x) (((x) & 0x3) << 5) /* OpAmpA Output Bias<1:0> */ +#define OPAMPA_RZ(x) (((x) & 0x3) << 3) /* OpAmpA RZ<1:0> */ +#define OPAMP_A_CC(x) (((x) & 0x7) << 0) /* OpAmp A CC<2:0> */ + +/* +* REG_TXBBF_OPAMP_B +*/ +#define OPAMPB_OUTPUT_BIAS(x) (((x) & 0x3) << 5) /* OpAmpB Output Bias<1:0> */ +#define OPAMPB_RZ(x) (((x) & 0x3) << 3) /* OpAmpB RZ<1:0> */ +#define OPAMP_B_CC(x) (((x) & 0x7) << 0) /* OpAmp B CC<2:0> */ + +/* +* REG_TX_BBF_R1 +*/ +#define OVERRIDE_ENABLE (1 << 7) /* Override enable */ +#define R1(x) (((x) & 0x1F) << 0) /* R1<4:0> */ + +/* +* REG_TX_BBF_R2 +*/ +#define R2(x) (((x) & 0x1F) << 0) /* R2<4:0> */ + +/* +* REG_TX_BBF_R3 +*/ +#define R3(x) (((x) & 0x1F) << 0) /* R3<4:0> */ + +/* +* REG_TX_BBF_R4 +*/ +#define R4(x) (((x) & 0x1F) << 0) /* R4<4:0> */ + +/* +* REG_TX_BBF_RP +*/ +#define RP(x) (((x) & 0x1F) << 0) /* Rp<4:0> */ + +/* +* REG_TX_BBF_C1 +*/ +#define C1(x) (((x) & 0x3F) << 0) /* C1<5:0> */ + +/* +* REG_TX_BBF_C2 +*/ +#define C2(x) (((x) & 0x3F) << 0) /* C2<5:0> */ + +/* +* REG_TX_BBF_CP +*/ +#define CP(x) (((x) & 0x3F) << 0) /* Cp<5:0> */ + +/* +* REG_TX_TUNE_CTRL +*/ +#define PD_TUNE (1 << 2) /* PD Tune */ +#define TUNER_RESAMPLE (1 << 1) /* Tuner Resample */ +#define TUNER_RESAMPLE_PHASE (1 << 0) /* Tuner Resample Phase */ +#define TUNE_CTRL(x) (((x) & 0x3) << 5) /* Tune Control<1:0> */ + +/* +* REG_TX_BBF_R2B +*/ +#define TX_BBF_BYPASS_BIAS_R (1 << 7) /* Bypass Bias R */ +#define R2B_OVR (1 << 5) /* R2b Ovr */ +#define R2B(x) (((x) & 0x1F) << 0) /* R2b<4:0> */ + +/* +* REG_TX_BBF_TUNE +*/ +#define BBF1_COMP_I (1 << 3) /* BBF1 Comp I */ +#define BBF1_COMP_Q (1 << 2) /* BBF1 Comp Q */ +#define BBF2_COMP_I (1 << 1) /* BBF2 Comp I */ +#define BBF2_COMP_Q (1 << 0) /* BBF2 Comp Q */ + +/* +* REG_CONFIG0 +*/ +#define BIAS(x) (((x) & 0x3) << 6) /* Bias<1:0> */ +#define RGM(x) (((x) & 0x3) << 4) /* Rgm<1:0> */ +#define CC(x) (((x) & 0x3) << 2) /* Cc<1:0> */ +#define AMPBIAS(x) (((x) & 0x3) << 0) /* AmpBias<1:0> */ + +/* +* REG_RESISTOR +*/ +#define RESISTOR(x) (((x) & 0xF) << 0) /* Resistor<3:0> */ + +/* +* REG_CAPACITOR +*/ +#define CAPACITOR(x) (((x) & 0x3F) << 0) /* Capacitor<5:0> */ + +/* +* REG_LO_CM +*/ +#define LO_COMMON_MODE(x) (((x) & 0x3) << 5) /* LO Common Mode<1:0> */ + +/* +* REG_TX_BBF_TUNE_MODE +*/ +#define EVALTIME (1 << 4) /* EvalTime */ +#define TX_BBF_TUNE_DIVIDER (1 << 0) /* TX BBF Tune Divider<8> */ +#define TUNE_COMP_MASK(x) (((x) & 0x3) << 5) /* Tune Comp Mask<1:0> */ +#define TUNER_MODE(x) (((x) & 0x7) << 1) /* Tuner Mode<2:0> */ + +/* +* REG_RX_FILTER_CONFIG +*/ +#define WRITE_RX (1 << 2) /* Write Rx */ +#define START_RX_CLOCK (1 << 1) /* Start Rx Clock */ +#define NUMBER_OF_TAPS(x) (((x) & 0x7) << 5) /* Number of Taps */ +#define SELECT_RX_CH(x) (((x) & 0x3) << 3) /* Select Rx Ch<1:0> */ + +/* +* REG_RX_FILTER_GAIN +*/ +#define FILTER_GAIN(x) (((x) & 0x3) << 0) /* Filter gain<1:0> */ + +/* +* REG_AGC_CONFIG_1 +*/ +#define DEC_PWR_FOR_LOW_PWR (1 << 7) /* Dec Pwr for Low Pwr */ +#define DEC_PWR_FOR_LOCK_LEVEL (1 << 6) /* Dec Pwr for Lock Level */ +#define DEC_PWR_FOR_GAIN_LOCK_EXIT (1 << 5) /* Dec Pwr for Gain Lock Exit */ +#define SLOW_ATTACK_HYBRID_MODE (1 << 4) /* Slow Attack Hybrid Mode */ +#define RX2_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 2) /* Rx 2 Gain Control Setup<1:0> */ +#define RX1_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 0) /* Rx 1 Gain Control Setup<1:0> */ +#define RX_GAIN_CTL_MASK 0x03 +#define RX2_GAIN_CTRL_SHIFT 2 +#define RX1_GAIN_CTRL_SHIFT 0 +#define RX_GAIN_CTL_MGC 0x00 +#define RX_GAIN_CTL_AGC_FAST_ATK 0x01 +#define RX_GAIN_CTL_AGC_SLOW_ATK 0x02 +#define RX_GAIN_CTL_AGC_SLOW_ATK_HYBD 0x03 + +/* +* REG_AGC_CONFIG_2 +*/ +#define AGC_SOFT_RESET (1 << 7) /* Soft Reset */ +#define AGC_GAIN_UNLOCK_CTRL (1 << 6) /* Gain Unlock Control */ +#define AGC_USE_FULL_GAIN_TABLE (1 << 3) /* Use Full Gain Table */ +#define DIG_GAIN_EN (1 << 2) /* Enable Digital Gain */ +#define MAN_GAIN_CTRL_RX2 (1 << 1) /* Manual Gain Control Rx 2 */ +#define MAN_GAIN_CTRL_RX1 (1 << 0) /* Manual Gain Control Rx 1 */ + +/* +* REG_AGC_CONFIG_3 +*/ +#define INCDEC_LMT_GAIN (1 << 4) /* Inc/Dec LMT Gain */ +#define USE_AGC_FOR_LMTLPF_GAIN (1 << 3) /* Use AGC for LMT/LPF Gain */ +#define MANUAL_INCR_STEP_SIZE(x) (((x) & 0x7) << 5) /* Manual (CTRL_IN) Incr Gain Step Size<2:0> */ +#define ADC_OVERRANGE_SAMPLE_SIZE(x) (((x) & 0x7) << 0) /* ADC Overrange Sample Size<2:0> */ + +/* +* REG_MAX_LMT_FULL_GAIN +*/ +#define MAXIMUM_FULL_TABLELMT_TABLE_INDEX(x) (((x) & 0x7F) << 0) /* Maximum Full Table/LMT Table Index<6:0> */ + +/* +* REG_PEAK_WAIT_TIME +*/ +#define MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(x) (((x) & 0x7) << 5) /* Manual (CTRL_IN) Decr Gain Step Size<2:0> */ +#define PEAK_OVERLOAD_WAIT_TIME(x) (((x) & 0x1F) << 0) /* Peak Overload Wait Time<4:0> */ + +/* +* REG_DIGITAL_GAIN +*/ +#define DIG_GAIN_STP_SIZE(x) (((x) & 0x7) << 5) /* Dig Gain Step Size<2:0> */ +#define MAXIMUM_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Maximum Digital Gain<4:0> */ + +/* +* REG_AGC_LOCK_LEVEL +*/ +#define ENABLE_DIG_SAT_OVRG (1 << 7) /* Enable Dig Sat Ovrg */ +#define AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW(x) (((x) & 0x7F) << 0) /* AGC Lock Level (Fast)/ AGC Inner High Threshold (Slow) <6:0> */ + +/* +* REG_GAIN_STP_CONFIG1 +*/ +#define LMT_DETECTOR_SETTLING_TIME(x) (((x) & 0x7) << 5) /* LMT Detector Settling Time<2:0> */ +#define DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(x) (((x) & 0x7) << 2) /* Dec Step Size for: Large LMT Overload/ Full Table Case #3 <2:0> */ +#define ADC_NOISE_CORRECTION_FACTOR(x) (((x) & 0x3) << 0) /* ADC Noise Correction Factor<1:0> */ + +/* +* REG_GAIN_STP_CONFIG_2 +*/ +#define DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE(x) (((x) & 0x7) << 4) /* Fast Attack Only. Decrement Step Size for: Small LPF Gain Change / Full Table Case #2 <2:0> */ +#define LARGE_LPF_GAIN_STEP(x) (((x) & 0xF) << 0) /* Decrement Step Size for: Large LPF Gain Change / Full Table Case #1<3:0> */ + +/* +* REG_SMALL_LMT_OVERLOAD_THRESH +*/ +#define FORCE_PD_RESET_RX2 (1 << 7) /* Force PD Reset Rx2 */ +#define FORCE_PD_RESET_RX1 (1 << 6) /* Force PD Reset Rx1 */ +#define SMALL_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0) /* Small LMT Overload Threshold<5:0> */ + +/* +* REG_LARGE_LMT_OVERLOAD_THRESH +*/ +#define LARGE_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0) /* Large LMT Overload Threshold<5:0> */ + +/* +* REG_RX1_MANUAL_LMT_FULL_GAIN +*/ +#define POWER_MEAS_IN_STATE_5_MSB (1 << 7) /* Power Meas in State 5 <3> */ +#define RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Rx1 Manual Full table/LMT table Gain Index<6:0> */ +#define RX_FULL_TBL_IDX_MASK RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(~0) + +/* +* REG_RX1_MANUAL_LPF_GAIN +*/ +#define POWER_MEAS_IN_STATE_5(x) (((x) & 0x7) << 5) /* Power Meas in State 5<2:0> */ +#define RX1_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx1 Manual LPF Gain <4:0> */ +#define RX_LPF_IDX_MASK RX1_MANUAL_LPF_GAIN(~0) + +/* +* REG_RX1_MANUAL_DIGITALFORCED_GAIN +*/ +#define FORCE_RX1_DIGITAL_GAIN (1 << 5) /* Force Rx1 Digital Gain */ +#define RX1_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Rx1 Manual/Forced Digital Gain<4:0> */ +#define RX_DIGITAL_IDX_MASK RX1_MANUALFORCED_DIGITAL_GAIN(~0) +/* +* REG_RX2_MANUAL_LMT_FULL_GAIN +*/ +#define RX2_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Rx2 Manual Full table/ LMT table Gain Index<6:0> */ + +/* +* REG_RX2_MANUAL_LPF_GAIN +*/ +#define RX2_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx2 Manual LPF Gain<4:0> */ + +/* +* REG_RX2_MANUAL_DIGITALFORCED_GAIN +*/ +#define FORCE_RX2_DIGITAL_GAIN (1 << 5) /* Force Rx2 Digital Gain */ +#define RX2_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Rx2 Manual/Forced Digital Gain<4:0> */ + +/* +* REG_FAST_CONFIG_1 +*/ +#define ENABLE_GAIN_INC_AFTER_GAIN_LOCK (1 << 7) /* Enable Gain Inc after Gain Lock */ +#define GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH (1 << 6) /* Goto Opt Gain if Energy Lost or EN_AGC High */ +#define GOTO_SET_GAIN_IF_EN_AGC_HIGH (1 << 5) /* Goto Set Gain if EN_AGC High */ +#define GOTO_SET_GAIN_IF_EXIT_RX_STATE (1 << 4) /* Goto Set Gain if Exit Rx State */ +#define DONT_UNLOCK_GAIN_IF_ENERGY_LOST (1 << 3) /* Don't Unlock Gain if Energy Lost */ +#define GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE (1 << 2) /* Goto Optimized Gain if Exit Rx State */ +#define DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG (1 << 1) /* Don't Unlock Gain If Lg ADC or LMT Ovrg */ +#define ENABLE_INCR_GAIN (1 << 0) /* Enable Incr Gain */ + +/* +* REG_FAST_CONFIG_2_SETTLING_DELAY +*/ +#define USE_LAST_LOCK_LEVEL_FOR_SET_GAIN (1 << 7) /* Use Last Lock Level for Set Gain */ +#define ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL (1 << 6) /* Enable LMT Gain Inc for Lock Level */ +#define GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH (1 << 5) /* Goto Max Gain or Opt Gain if EN_AGC High */ +#define SETTLING_DELAY(x) (((x) & 0x1F) << 0) /* Settling Delay<4:0> */ + +/* +* REG_FAST_ENERGY_LOST_THRESH +*/ +#define POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE(x) (((x) & 0x3) << 6) /* Post Lock Level Step Size for: LPF Table/ Full Table <1:0> */ +#define ENERGY_LOST_THRESH(x) (((x) & 0x3F) << 0) /* Energy lost threshold<5:0> */ + +/* +* REG_FAST_STRONGER_SIGNAL_THRESH +*/ +#define POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(x) (((x) & 0x3) << 6) /* Post Lock Level Step for LMT Table <1:0> */ +#define STRONGER_SIGNAL_THRESH(x) (((x) & 0x3F) << 0) /* Stronger Signal Threshold<5:0> */ + +/* +* REG_FAST_LOW_POWER_THRESH +*/ +#define DONT_UNLOCK_GAIN_IF_ADC_OVRG (1 << 7) /* Don't unlock gain if ADC Ovrg */ +#define LOW_POWER_THRESH(x) (((x) & 0x7F) << 0) /* Low Power Threshold<6:0> */ + +/* +* REG_FAST_STRONG_SIGNAL_FREEZE +*/ +#define DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL (1 << 7) /* Don't unlock gain if Stronger Signal */ + +/* +* REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN +*/ +#define FINAL_OVER_RANGE_COUNT(x) (((x) & 0x7) << 5) /* Final Over Range Count<2:0> */ +#define OPTIMIZE_GAIN_OFFSET(x) (((x) & 0xF) << 0) /* Optimize Gain Offset<3:0> */ + +/* +* REG_FAST_ENERGY_DETECT_COUNT +*/ +#define INCREMENT_GAIN_STP_LPFLMT(x) (((x) & 0x7) << 5) /* Increment Gain Step (LPF/LMT)<2:0> */ +#define ENERGY_DETECT_COUNT(x) (((x) & 0x1F) << 0) /* Energy Detect count<4:0> */ + +/* +* REG_FAST_AGCLL_UPPER_LIMIT +*/ +#define AGCLL_MAX_INCREASE(x) (((x) & 0x3F) << 0) /* AGCLL Max Increase<5:0> */ + +/* +* REG_FAST_GAIN_LOCK_EXIT_COUNT +*/ +#define GAIN_LOCK_EXIT_COUNT(x) (((x) & 0x3F) << 0) /* Gain Lock Exit Count<5:0> */ + +/* +* REG_FAST_INITIAL_LMT_GAIN_LIMIT +*/ +#define INITIAL_LMT_GAIN_LIMIT(x) (((x) & 0x7F) << 0) /* Initial LMT Gain Limit<6:0> */ + +/* +* REG_AGC_INNER_LOW_THRESH +*/ +#define PREVENT_GAIN_INC (1 << 7) /* Prevent Gain Inc */ +#define AGC_INNER_LOW_THRESH(x) (((x) & 0x7F) << 0) /* AGC Inner Low Threshold<6:0> */ + +/* +* REG_LMT_OVERLOAD_COUNTERS +*/ +#define LARGE_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4) /* Large LMT Overload Exceeded Counter<3:0> */ +#define SMALL_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Small LMT Overload Exceeded Counter<3:0> */ + +/* +* REG_ADC_OVERLOAD_COUNTERS +*/ +#define LARGE_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4) /* Large ADC Overload Exceeded Counter<3:0> */ +#define SMALL_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Small ADC Overload Exceeded Counter<3:0> */ + +/* +* REG_GAIN_STP1 +*/ +#define IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD (1 << 7) /* Immed. Gain Change if Lg LMT Overload */ +#define IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD (1 << 3) /* Immed. Gain Change if Lg ADC Overload */ +#define AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 4) /* AGC Inner High Threshold Exceeded Step Size<2:0> */ +#define AGC_INNER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 0) /* AGC Inner Low Threshold Exceeded Step Size<2:0> */ + +/* +* REG_DIGITAL_SAT_COUNTER +*/ +#define DOUBLE_GAIN_COUNTER (1 << 5) /* Double Gain Counter */ +#define ENABLE_SYNC_FOR_GAIN_COUNTER (1 << 4) /* Enable Sync for Gain Counter */ +#define DIG_SATURATION_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Dig Saturation Exceeded Counter<3:0> */ + +/* +* REG_OUTER_POWER_THRESHS +*/ +#define AGC_OUTER_HIGH_THRESH(x) (((x) & 0xF) << 4) /* AGC Outer High Threshold<3:0> */ +#define AGC_OUTER_LOW_THRESH(x) (((x) & 0xF) << 0) /* AGC Outer Low Threshold<3:0> */ + +/* +* REG_GAIN_STP_2 +*/ +#define AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 4) /* AGC outer High Threshold Exceeded Step Size<3:0> */ +#define AGC_OUTER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 0) /* AGC Outer Low Threshold Exceeded Step Size<3:0> */ + +/* +* REG_EXT_LNA_HIGH_GAIN +*/ +#define EXT_LNA_HIGH_GAIN(x) (((x) & 0x3F) << 0) /* Ext LNA High Gain<5:0> */ + +/* +* REG_EXT_LNA_LOW_GAIN +*/ +#define EXT_LNA_LOW_GAIN(x) (((x) & 0x3F) << 0) /* Ext LNA Low Gain<5:0> */ + +/* +* REG_GAIN_TABLE_ADDRESS +*/ +#define GAIN_TABLE_ADDRESS(x) (((x) & 0x7F) << 0) /* Gain Table Address<6:0> */ + +/* +* REG_GAIN_TABLE_WRITE_DATA1 +*/ +#define EXT_LNA_CTRL (1 << 7) /* Ext LNA Ctrl */ +#define LNA_GAIN(x) (((x) & 0x3) << 5) /* LNA Gain <1:0> */ +#define MIXER_GM_GAIN(x) (((x) & 0x1F) << 0) /* Mixer Gm Gain <4:0> */ + +/* +* REG_GAIN_TABLE_WRITE_DATA2 +*/ +#define TIA_GAIN (1 << 5) /* TIA Gain */ +#define LPF_GAIN(x) (((x) & 0x1F) << 0) /* LPF Gain <4:0> */ + +/* +* REG_GAIN_TABLE_WRITE_DATA_3 +*/ +#define RF_DC_CAL (1 << 5) /* RF DC Cal */ +#define DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Digital Gain <4:0> */ + +/* +* REG_GAIN_TABLE_READ_DATA_1 +*/ +#define TO_LNA_GAIN(x) (((x) >> 5) & 0x3) /* LNA Gain <1:0> */ +#define TO_MIXER_GM_GAIN(x) (((x) >> 0) & 0x1F) /* Mixer Gm Gain <4:0> */ + +/* +* REG_GAIN_TABLE_READ_DATA_2 +*/ +#define TO_LPF_GAIN(x) (((x) >> 0) & 0x1F) /* LPF Gain <4:0> */ + +/* +* REG_GAIN_TABLE_READ_DATA_3 +*/ +#define TO_DIGITAL_GAIN(x) (((x) >> 0) & 0x1F) /* Digital Gain <4:0> */ + +/* +* REG_GAIN_TABLE_CONFIG +*/ +#define WRITE_GAIN_TABLE (1 << 2) /* Write Gain Table */ +#define START_GAIN_TABLE_CLOCK (1 << 1) /* Start Gain Table Clock */ +#define RECEIVER_SELECT(x) (((x) & 0x3) << 3) /* Receiver Select<1:0> */ +#define GT_RX1 1 +#define GT_RX2 2 + + +/* +* REG_GM_SUB_TABLE_GAIN_WRITE +*/ +#define GM_SUB_TABLE_GAIN_WRITE(x) (((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Write<6:0> */ + +/* +* REG_GM_SUB_TABLE_BIAS_WRITE +*/ +#define GM_SUB_TABLE_BIAS_WRITE(x) (((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Write<4:0> */ + +/* +* REG_GM_SUB_TABLE_CTRL_WRITE +*/ +#define GM_SUB_TABLE_CTRL_WRITE(x) (((x) & 0x3F) << 0) /* Gm Sub Table Control Word Write<5:0> */ + +/* +* REG_GM_SUB_TABLE_GAIN_READ +*/ +#define GM_SUB_TABLE_GAIN_READ(x) (((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Read<6:0> */ + +/* +* REG_GM_SUB_TABLE_BIAS_READ +*/ +#define GM_SUB_TABLE_BIAS_READ(x) (((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Read<4:0> */ + +/* +* REG_GM_SUB_TABLE_CTRL_READ +*/ +#define GM_SUB_TABLE_CTRL_READ(x) (((x) & 0x3F) << 0) /* Gm Sub Table Control Word Read<5:0> */ + +/* +* REG_GM_SUB_TABLE_CONFIG +*/ +#define WRITE_GM_SUB_TABLE (1 << 2) /* Write Gm Sub Table */ +#define START_GM_SUB_TABLE_CLOCK (1 << 1) /* Start Gm Sub Table Clock */ + +/* +* REG_GAIN_DIFF_WORDERROR_WRITE +*/ +#define CALIB_TABLE_GAIN_DIFFERROR_WORD(x) (((x) & 0x3F) << 0) /* Calib Table Gain Diff/Error Word<5:0> */ + +/* +* REG_GAIN_ERROR_READ +*/ +#define CALIB_TABLE_GAIN_ERROR(x) (((x) & 0x1F) << 0) /* Calib Table Gain Error<4:0> */ + +/* +* REG_CONFIG +*/ +#define READ_SELECT (1 << 4) /* Read Select */ +#define WRITE_MIXER_ERROR_TABLE (1 << 3) /* Write Mixer Error Table */ +#define WRITE_LNA_ERROR_TABLE (1 << 2) /* Write LNA Error Table */ +#define WRITE_LNA_GAIN_DIFF (1 << 1) /* Write LNA Gain Diff */ +#define START_CALIB_TABLE_CLOCK (1 << 0) /* Start Calib Table Clock */ +#define CALIB_TABLE_SELECT(x) (((x) & 0x3) << 5) /* Calib Table Select<1:0> */ + +/* +* REG_LNA_GAIN_DIFF_READ_BACK +*/ +#define LNA_CALIB_TABLE_GAIN_DIFFERENCE_WORD(x) (((x) & 0x3F) << 0) /* LNA Calib Table Gain Difference Word<5:0> */ + +/* +* REG_MAX_MIXER_CALIBRATION_GAIN_INDEX +*/ +#define MAX_MIXER_CALIBRATION_GAIN_INDEX(x) (((x) & 0x1F) << 0) /* Max Mixer Calibration Gain Index<4:0> */ + +/* +* REG_SETTLE_TIME +*/ +#define ENABLE_DIG_GAIN_CORR (1 << 7) /* Enable Dig Gain Corr */ +#define FORCE_TEMP_SENSOR_FOR_CAL (1 << 6) /* Force Temp Sensor for Cal */ +#define SETTLE_TIME(x) (((x) & 0x3F) << 0) /* Settle Time<5:0> */ + +/* +* REG_MEASURE_DURATION +*/ +#define GAIN_CAL_MEAS_DURATION(x) (((x) & 0xF) << 0) /* Gain Cal Meas Duration<3:0> */ + +/* +* REG_MEASURE_DURATION_01 +*/ +#define MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4) /* Measurement duration 1 <3:0> */ +#define MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0) /* Measurement duration 0 <3:0> */ + +/* +* REG_MEASURE_DURATION_23 +*/ +#define MEASUREMENT_DURATION_3(x) (((x) & 0xF) << 4) /* Measurement duration 3 <3:0> */ +#define MEASUREMENT_DURATION_2(x) (((x) & 0xF) << 0) /* Measurement duration 2 <3:0> */ + +/* +* REG_RSSI_CONFIG +*/ +#define START_RSSI_MEAS (1 << 5) /* Start RSSI Meas (Mode 4) */ +#define ENABLE_ADC_POWER_MEAS (1 << 1) /* Enable ADC Power Meas. */ +#define DEFAULT_RSSI_MEAS_MODE (1 << 0) /* Default RSSI Meas Mode */ +#define RFIR_FOR_RSSI_MEASUREMENT(x) (((x) & 0x3) << 6) /* RFIR for RSSI measurement<1:0> */ +#define RSSI_MODE_SELECT(x) (((x) & 0x7) << 2) /* RSSI Mode Select<2:0> */ + +/* +* REG_ADC_MEASURE_DURATION_01 +*/ +#define ADC_POWER_MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4) /* ADC Power Measurement Duration 1<3:0> */ +#define ADC_POWER_MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0) /* ADC Power Measurement Duration 0 <3:0> */ + +/* +* REG_DEC_POWER_MEASURE_DURATION_0 +*/ +#define USE_HB3_OUT_FOR_ADC_PWR_MEAS (1 << 7) /* Use HB3 Out for ADC Pwr Meas */ +#define USE_HB1_OUT_FOR_DEC_PWR_MEAS (1 << 6) /* Use HB1 Out for Dec pwr Meas */ +#define ENABLE_DEC_PWR_MEAS (1 << 5) /* Enable Dec Pwr Meas */ +#define DEFAULT_MODE_ADC_POWER (1 << 4) /* Default Mode ADC Power */ +#define DEC_POWER_MEASUREMENT_DURATION(x) (((x) & 0xF) << 0) /* Dec Power Measurement Duration <3:0> */ + +/* +* REG_LNA_GAIN +*/ +#define DB_GAIN_READBACK_CHANNEL (1 << 0) /* dB Gain Read-back Channel */ +#define MAX_LNA_GAIN(x) (((x) & 0x7F) << 1) /* Max LNA Gain<6:0> */ + +/* +* REG_RX_QUAD_CAL_LEVEL +*/ +#define RX_QUAD_CAL_LEVEL(x) (((x) & 0xF) << 0) /* Rx Quad Cal Level <3 :0> */ + +/* +* REG_CALIBRATION_CONFIG_1 +*/ +#define ENABLE_PHASE_CORR (1 << 7) /* Enable Phase Corr */ +#define ENABLE_GAIN_CORR (1 << 6) /* Enable Gain Corr */ +#define USE_SETTLE_COUNT_FOR_DC_CAL_WAIT (1 << 5) /* Use Settle Count for DC Cal Wait */ +#define FIXED_DC_CAL_WAIT_TIME (1 << 4) /* Fixed DC Cal Wait Time */ +#define FREE_RUN_MODE (1 << 3) /* Free Run Mode */ +#define ENABLE_CORR_WORD_DECIMATION (1 << 2) /* Enable Corr Word Decimation */ +#define ENABLE_TRACKING_MODE_CH2 (1 << 1) /* Enable Tracking Mode CH2 */ +#define ENABLE_TRACKING_MODE_CH1 (1 << 0) /* Enable Tracking Mode CH1 */ + +/* +* REG_CALIBRATION_CONFIG_2 +*/ +#define SOFT_RESET (1 << 7) /* Soft Reset */ +#define CALIBRATION_CONFIG2_DFLT (0x3 << 5) /* Must be 2'b11 */ +#define K_EXP_PHASE(x) (((x) & 0x1F) << 0) /* K exp Phase<4:0> */ + +/* +* REG_CALIBRATION_CONFIG_3 +*/ +#define PREVENT_POS_LOOP_GAIN (1 << 7) /* Prevent Pos Loop Gain */ +#define K_EXP_AMPLITUDE(x) (((x) & 0x1F) << 0) /* K exp Amplitude<4:0> */ + +/* +* REG_RX_QUAD_GAIN1 +*/ +#define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0) /* Rx Full table/LMT table gain<6:0> */ + +/* +* REG_RX_QUAD_GAIN2 +*/ +#define CORRECTION_WORD_DECIMATION_M(x) (((x) & 0x7) << 5) /* Correction Word Decimation M<2:0> */ +#define RX_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx LPF gain<4:0> */ + +/* +* REG_RX1_INPUT_A_OFFSETS +*/ +#define RX1_INPUT_A_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2) /* Rx1 Input A "I" DC Offset<5:0> */ +#define RX1_INPUT_A_Q_DC_OFFSET(x) (((x) & 0x3) << 0) /* Rx1 Input A "Q" DC Offset<9:8> */ + +/* +* REG_INPUT_A_OFFSETS_1 +*/ +#define RX2_INPUT_A_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4) /* Rx2 Input A "Q" DC Offset<3:0> */ +#define RX1_INPUT_A_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0) /* Rx1 Input A "I" DC Offset<9:6> */ + +/* +* REG_RX2_INPUT_A_OFFSETS +*/ +#define RX2_INPUT_A_I_DC_OFFSET(x) (((x) & 0x3) << 6) /* Rx2 Input A "I" DC Offset<1:0> */ +#define RX2_INPUT_A_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0) /* Rx2 Input A "Q" DC Offset<9:4> */ + +/* +* REG_RX1_INPUT_BC_OFFSETS +*/ +#define RX1_INPUT_BC_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2) /* Rx1 Input B&C "I" DC Offset<5:0> */ +#define RX1_INPUT_BC_Q_DC_OFFSET(x) (((x) & 0x3) << 0) /* Rx1 Input B&C "Q" DC Offset<9:8> */ + +/* +* REG_INPUT_BC_OFFSETS_1 +*/ +#define RX2_INPUT_BC_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4) /* Rx2 Input B&C "Q" DC Offset<3:0> */ +#define RX1_INPUT_BC_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0) /* Rx1 Input B&C "I" DC Offset<9:6> */ + +/* +* REG_RX2_INPUT_BC_OFFSETS +*/ +#define RX2_INPUT_BC_I_DC_OFFSET(x) (((x) & 0x3) << 6) /* Rx2 Input B&C "I" DC Offset<1:0> */ +#define RX2_INPUT_BC_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0) /* Rx2 Input B&C "Q" DC Offset<9:4> */ + +/* +* REG_FORCE_BITS +*/ +#define RX2_INPUT_BC_FORCE_OFFSET (1 << 7) /* Rx2 Input B&C Force offset */ +#define RX1_INPUT_BC_FORCE_OFFSET (1 << 6) /* Rx1 Input B&C Force offset */ +#define RX2_INPUT_BC_FORCE_PHGAIN (1 << 5) /* Rx2 Input B&C Force Ph/Gain */ +#define RX1_INPUT_BC_FORCE_PHGAIN (1 << 4) /* Rx1 Input B&C Force Ph/Gain */ +#define RX2_INPUT_A_FORCE_OFFSET (1 << 3) /* Rx2 Input A Force offset */ +#define RX1_INPUT_A_FORCE_OFFSET (1 << 2) /* Rx1 Input A Force offset */ +#define RX2_INPUT_A_FORCE_PHGAIN (1 << 1) /* Rx2 Input A Force Ph/Gain */ +#define RX1_INPUT_A_FORCE_PHGAIN (1 << 0) /* Rx1 Input A Force Ph/Gain */ + +/* +* REG_RF_DC_OFFSET_CONFIG_1 +*/ +#define DAC_FS(x) (((x) & 0x3) << 4) /* DAC FS<1:0> */ +#define RF_DC_CALIBRATION_COUNT(x) (((x) & 0xF) << 0) /* RF DC Calibration Count<3:0> */ + +/* +* REG_RF_DC_OFFSET_ATTEN +*/ +#define RF_DC_OFFSET_TABLE_UPDATE_COUNT(x) (((x) & 0x7) << 5) /* RF DC Offset Table Update Count<2:0> */ +#define RF_DC_OFFSET_ATTEN(x) (((x) & 0x1F) << 0) /* RF DC Offset Attenuation<4:0> */ + +/* +* REG_INVERT_BITS +*/ +#define INVERT_RX2_RF_DC_CGIN_WORD (1 << 7) /* Invert Rx2 RF DC CGin Word */ +#define INVERT_RX1_RF_DC_CGIN_WORD (1 << 6) /* Invert Rx1 RF DC CGin Word */ +#define INVERT_RX2_RF_DC_CGOUT_WORD (1 << 5) /* Invert Rx2 RF DC CGout Word */ +#define INVERT_RX1_RF_DC_CGOUT_WORD (1 << 4) /* Invert Rx1 RF DC CGout Word */ + +/* +* REG_DC_OFFSET_CONFIG2 +*/ +#define USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL (1 << 7) /* Use Wait Counter for RF DC Init Cal */ +#define ENABLE_FAST_SETTLE_MODE (1 << 6) /* Enable Fast Settle Mode */ +#define ENABLE_BB_DC_OFFSET_TRACKING (1 << 5) /* Enable BB DC Offset Tracking */ +#define RESET_ACC_ON_GAIN_CHANGE (1 << 4) /* Reset Acc on Gain Change */ +#define ENABLE_RF_OFFSET_TRACKING (1 << 3) /* Enable RF Offset Tracking */ +#define DC_OFFSET_UPDATE(x) (((x) & 0x7) << 0) /* DC Offset Update<2:0> */ + +/* +* REG_RF_CAL_GAIN_INDEX +*/ +#define RF_MINIMUM_CALIBRATION_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* RF Minimum Calibration Gain Index<6:0> */ + +/* +* REG_SOI_THRESH +*/ +#define RF_SOI_THRESH(x) (((x) & 0x7F) << 0) /* RF SOI Threshold<6:0> */ + +/* +* REG_BB_DC_OFFSET_SHIFT +*/ +#define INCREASE_COUNT_DURATION (1 << 7) /* Increase Count Duration */ +#define BB_TRACKING_DECIMATE(x) (((x) & 0x3) << 5) /* BB Tracking Decimate<1:0> */ +#define BB_DC_M_SHIFT(x) (((x) & 0x1F) << 0) /* BB DC M Shift<4:0> */ + +/* +* REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT +*/ +#define READ_BACK_CH_SEL (1 << 7) /* Read Back CH Sel */ +#define UPDATE_TRACKING_WORD (1 << 6) /* Update Tracking Word */ +#define FORCE_RX_NULL (1 << 5) /* Force Rx Null */ +#define BB_DC_TRACKING_FAST_SETTLE_M_SHIFT(x) (((x) & 0x1F) << 0) /* BB DC Tracking Fast Settle M Shift<4:0> */ + +/* +* REG_BB_DC_OFFSET_ATTEN +*/ +#define BB_DC_OFFSET_ATTEN(x) (((x) & 0xF) << 0) /* BB DC Offset Atten<3:0> */ + +/* +* REG_RX1_BB_DC_WORD_I_MSB +*/ +#define RX1_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word I<14:8> */ + +/* +* REG_RX1_BB_DC_WORD_Q_MSB +*/ +#define RX1_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word Q<14:8> */ + +/* +* REG_RX2_BB_DC_WORD_I_MSB +*/ +#define RX2_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word I<14:8> */ + +/* +* REG_RX2_BB_DC_WORD_Q_MSB +*/ +#define RX2_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word Q<14:8> */ + +/* +* REG_BB_TRACK_CORR_WORD_I_MSB +*/ +#define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word I<14:8> */ + +/* +* REG_BB_TRACK_CORR_WORD_Q_MSB +*/ +#define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word Q<14:8> */ + +/* +* REG_SYMBOL_LSB +*/ +#define RX2_RSSI_SYMBOL (1 << 1) /* Rx2 RSSI symbol <0> */ +#define RX1_RSSI_SYMBOL (1 << 0) /* Rx1 RSSI symbol <0> */ + +/* +* REG_PREAMBLE_LSB +*/ +#define RX2_RSSI_PREAMBLE (1 << 1) /* Rx2 RSSI preamble <0> */ +#define RX1_RSSI_PREAMBLE (1 << 0) /* Rx1 RSSI preamble <0> */ + +/* +* REG_RX1_RSSI_SYMBOL, REG_RX1_RSSI_PREAMBLE, +* REG_RX2_RSSI_SYMBOL, REG_RX2_RSSI_PREAMBLE +*/ +#define RSSI_LSB_SHIFT 1 +#define RSSI_LSB_MASK1 0x01 +#define RSSI_LSB_MASK2 0x02 + +/* +* REG_RX_PATH_GAIN_LSB +*/ +#define RX_PATH_GAIN (1 << 0) /* Rx Path Gain<0> */ + +/* +* REG_RX_DIFF_LNA_FORCE +*/ +#define FORCE_RX2_LNA_GAIN (1 << 7) /* Force Rx2 LNA Gain */ +#define RX2_LNA_BYPASS (1 << 6) /* Rx2 LNA Bypass */ +#define FORCE_RX1_LNA_GAIN (1 << 3) /* Force Rx1 LNA Gain */ +#define RX1_LNA_BYPASS (1 << 2) /* Rx1 LNA Bypass */ +#define RX2_LNA_GAIN(x) (((x) & 0x3) << 4) /* Rx2 LNA Gain<1:0> */ +#define RX1_LNA_GAIN(x) (((x) & 0x3) << 0) /* Rx1 LNA Gain<1:0> */ + +/* +* REG_RX_LNA_BIAS_COARSE +*/ +#define RX_LNA_BIAS_COARSE(x) (((x) & 0xF) << 0) /* Rx LNA Bias Coarse<3:0> */ + +/* +* REG_RX_LNA_BIAS_FINE_0 +*/ +#define RX_LNA_PCASCODE_BIAS(x) (((x) & 0x7) << 5) /* Rx LNA p-Cascode Bias<2:0> */ +#define RX_LNA_BIAS(x) (((x) & 0x1F) << 0) /* Rx LNA Bias<4:0> */ + +/* +* REG_RX_LNA_BIAS_FINE_1 +*/ +#define RX_LNA_P_CASCODE_BIAS_FINE(x) (((x) & 0x3) << 0) /* Rx LNA p- Cascode Bias Fine<4:3> */ + +/* +* REG_RX_MIX_GM_CONFIG +*/ +#define RX_MIX_GM_CM_OUT(x) (((x) & 0x7) << 5) /* Rx Mix Gm CM Out<2:0> */ +#define RX_MIX_GM_PLOAD(x) (((x) & 0x3) << 0) /* Rx Mix Gm pload <1:0> */ + +/* +* REG_RX1_MIX_GM_FORCE +*/ +#define FORCE_RX1_MIX_GM (1 << 6) /* Force Rx1 Mix Gm */ +#define RX1_MIX_GM_GAIN(x) (((x) & 0x3F) << 0) /* Rx1 Mix Gm Gain<5:0> */ + +/* +* REG_RX1_MIX_GM_BIAS_FORCE +*/ +#define RX1_MIX_GM_BIAS(x) (((x) & 0x1F) << 0) /* Rx1 Mix Gm Bias<4:0> */ + +/* +* REG_RX2_MIX_GM_FORCE +*/ +#define FORCE_RX2_MIX_GM (1 << 6) /* Force Rx2 Mix Gm */ +#define RX2_MIX_GM_GAIN(x) (((x) & 0x3F) << 0) /* Rx2 Mix Gm Gain<5:0> */ + +/* +* REG_RX2_MIX_GM_BIAS_FORCE +*/ +#define RX2_MIX_GM_BIAS(x) (((x) & 0x1F) << 0) /* Rx2 Mix Gm Bias<4:0> */ + +/* +* REG_INPUT_A_MSBS +*/ +#define INPUT_A_RX1_Q(x) (((x) & 0x3) << 6) /* Input A RX1 Q<9:8> */ +#define INPUT_A_RX1_I(x) (((x) & 0x3) << 4) /* Input A RX1 I<9:8> */ +#define INPUT_A_RX2_I(x) (((x) & 0x3) << 2) /* Input A RX2 I<9:8> */ +#define INPUT_A_RX2_Q(x) (((x) & 0x3) << 0) /* Input A RX2 Q<9:8> */ + +/* +* REG_INPUTS_BC_MSBS +*/ +#define INPUTS_BC_RX1_Q(x) (((x) & 0x3) << 6) /* Inputs B&C RX1 Q<9:8> */ +#define INPUTS_BC_RX1_I(x) (((x) & 0x3) << 4) /* Inputs B&C RX1 I<9:8> */ +#define INPUTS_BC_RX2_I(x) (((x) & 0x3) << 2) /* Inputs B&C RX2 I<9:8> */ +#define INPUTS_BC_RX2_Q(x) (((x) & 0x3) << 0) /* Inputs B&C RX2 Q<9:8> */ + +/* +* REG_FORCE_OS_DAC +*/ +#define FORCE_CGIN_DAC (1 << 2) /* Force CGin DAC */ + +/* +* REG_RX_MIX_LO_CM +*/ +#define RX_MIX_LO_CM(x) (((x) & 0x3F) << 0) /* Rx Mix LO CM<5:0> */ + +/* +* REG_RX_CGB_SEG_ENABLE +*/ +#define RX_CGB_SEG_ENABLE(x) (((x) & 0x3F) << 0) /* Rx CGB Seg Enable<5:0> */ + +/* +* REG_RX_MIX_INPUTBIAS +*/ +#define RX_CGB_INPUT_CM_SEL(x) (((x) & 0x3) << 4) /* Rx CGB Input CM Sel<1:0> */ +#define RX_CGB_BIAS(x) (((x) & 0xF) << 0) /* Rx CGB Bias<3:0> */ + +/* +* REG_RX_TIA_CONFIG +*/ +#define TIA2_OVERRIDE_C (1 << 3) /* TIA2 Override C */ +#define TIA2_OVERRIDE_R (1 << 2) /* TIA2 Override R */ +#define TIA1_OVERRIDE_C (1 << 1) /* TIA1 Override C */ +#define TIA1_OVERRIDE_R (1 << 0) /* TIA1 Override R */ +#define TIA_SEL_CC(x) (((x) & 0x7) << 5) /* TIA Sel CC<2:0> */ + +/* +* REG_TIA1_C_LSB +*/ +#define TIA1_RF(x) (((x) & 0x3) << 6) /* TIA1 RF<1:0> */ +#define TIA1_C_LSB(x) (((x) & 0x3F) << 0) /* TIA1 C LSB<5:0> */ + +/* +* REG_TIA1_C_MSB +*/ +#define TIA1_C_MSB(x) (((x) & 0x7F) << 0) /* TIA1 C MSB<6:0> */ + +/* +* REG_TIA2_C_LSB +*/ +#define TIA2_RF(x) (((x) & 0x3) << 6) /* TIA2 RF<1:0> */ +#define TIA2_C_LSB(x) (((x) & 0x3F) << 0) /* TIA2 C LSB<5:0> */ + +/* +* REG_TIA2_C_MSB +*/ +#define TIA2_C_MSB(x) (((x) & 0x7F) << 0) /* TIA2 C MSB<6:0> */ + +/* +* REG_RX1_BBF_R1A +*/ +#define FORCE_RX1_RESISTORS (1 << 7) /* Force Rx1 Resistors */ +#define RX1_BBF_R1A(x) (((x) & 0x3F) << 0) /* Rx1 BBF R1A<5:0> */ + +/* +* REG_RX2_BBF_R1A +*/ +#define FORCE_RX2_RESISTORS (1 << 7) /* Force Rx2 Resistors */ +#define RX2_BBF_R1A(x) (((x) & 0x3F) << 0) /* Rx2 BBF R1A<5:0> */ + +/* +* REG_RX1_TUNE_CTRL +*/ +#define RX1_TUNE_RESAMPLE_PHASE (1 << 2) /* Rx1 Tune Resample Phase */ +#define RX1_TUNE_RESAMPLE (1 << 1) /* Rx1 Tune Resample */ +#define RX1_PD_TUNE (1 << 0) /* Rx1 PD Tune */ + +/* +* REG_RX2_TUNE_CTRL +*/ +#define RX2_TUNE_RESAMPLE_PHASE (1 << 2) /* Rx2 Tune Resam ple Phase */ +#define RX2_TUNE_RESAMPLE (1 << 1) /* Rx2 Tune Resample */ +#define RX2_PD_TUNE (1 << 0) /* Rx2 PD Tune */ + +/* +* REG_RX_BBF_R2346 +*/ +#define TUNE_OVERRIDE (1 << 7) /* Tune Override */ +#define RX_BBF_R2346(x) (((x) & 0x7) << 0) /* Rx BBF R2346<2:0> */ + +/* +* REG_RX_BBF_C1_MSB +*/ +#define RX_BBF_C1_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C1 MSB<5:0> */ + +/* +* REG_RX_BBF_C1_LSB +*/ +#define RX_BBF_C1_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C1 LSB<6:0> */ + +/* +* REG_RX_BBF_C2_MSB +*/ +#define RX_BBF_C2_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C2 MSB<5:0> */ + +/* +* REG_RX_BBF_C2_LSB +*/ +#define RX_BBF_C2_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C2 LSB<6:0> */ + +/* +* REG_RX_BBF_C3_MSB +*/ +#define RX_BBF_C3_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C3 MSB<5:0> */ + +/* +* REG_RX_BBF_C3_LSB +*/ +#define RX_BBF_C3_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C3 LSB<6:0> */ + +/* +* REG_RX_BBF_CC1_CTR +*/ +#define RX_BBF_CC1_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC1 Ctr<6:0> */ + +/* +* REG_RX_BBF_POW_RZ_BYTE0 +*/ +#define MUST_BE_ZERO (1 << 7) /* Must be zero */ +#define RX1_BBF_POW_CTR(x) (((x) & 0x3) << 5) /* Rx1 BBF Pow Ctr<1:0> */ +#define RX_BBF_RZ1_CTR(x) (((x) & 0x3) << 3) /* Rx BBF Rz1 Ctr<1:0> */ + +/* +* REG_RX_BBF_CC2_CTR +*/ +#define RX_BBF_CC2_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC2 Ctr<6:0> */ + +/* +* REG_RX_BBF_POW_RZ_BYTE1 +*/ +#define RX_BBF_POW3_CTR(x) (((x) & 0x3) << 6) /* Rx BBF Pow3 Ctr<1:0> */ +#define RX_BBF_RZ3_CTR(x) (((x) & 0x3) << 4) /* Rx BBF RZ3 Ctr<1:0> */ +#define RX_BBF_POW2_CTR(x) (((x) & 0x3) << 2) /* Rx BBF Pow2 Ctr<1:0> */ +#define RX_BBF_RZ2_CTR(x) (((x) & 0x3) << 0) /* Rx BBF Rz2 Ctr<1:0> */ + +/* +* REG_RX_BBF_CC3_CTR +*/ +#define RX_BBF_CC3_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC3 Ctr<6:0> */ + +/* +* REG_RX_BBF_TUNE +*/ +#define RXBBF_BYPASS_BIAS_R (1 << 7) /* RxBBF Bypass Bias R */ +#define RX_BBF_R5_TUNE (1 << 4) /* Rx BBF R5 Tune */ +#define RX1_BBF_TUNE_COMP_I (1 << 3) /* Rx1 BBF Tune Comp I */ +#define RX1_BBF_TUNE_COMP_Q (1 << 2) /* Rx1 BBF Tune Comp Q */ +#define RX2_BBF_TUNE_COMP_I (1 << 1) /* Rx2 BBF Tune Comp I */ +#define RX2_BBF_TUNE_COMP_Q (1 << 0) /* Rx2 BBF Tune Comp Q */ +#define RX_BBF_TUNE_CTR(x) (((x) & 0x3) << 5) /* Rx BBF Tune Ctr<1:0> */ + +/* +* REG_RX1_BBF_MAN_GAIN +*/ +#define RX1_BBF_FORCE_GAIN (1 << 5) /* Rx1 BBF Force Gain */ +#define RX1_BBF_BQ_GAIN(x) (((x) & 0x3) << 3) /* Rx1 BBF BQ Gain<1:0> */ +#define RX1_BBF_POLE_GAIN(x) (((x) & 0x7) << 0) /* Rx1 BBF Pole Gain<2:0> */ + +/* +* REG_RX2_BBF_MAN_GAIN +*/ +#define RX2_BBF_FORCE_GAIN (1 << 5) /* Rx2 BBF Force Gain */ +#define RX2_BBF_BQ_GAIN(x) (((x) & 0x3) << 3) /* Rx2 BBF BQ Gain<1:0> */ +#define RX2_BBF_POLE_GAIN(x) (((x) & 0x7) << 0) /* Rx2 BBF Pole Gain<2:0> */ + +/* +* REG_RX_BBF_TUNE_CONFIG +*/ +#define RX_TUNE_EVALTIME (1 << 4) /* Rx Tune Evaltime */ +#define RX_BBF_TUNE_DIVIDE (1 << 0) /* RX BBF Tune Divide<8> */ +#define TUNE_COMP_MASK(x) (((x) & 0x3) << 5) /* Tune Comp Mask <1:0> */ +#define RX_TUNE_MODE(x) (((x) & 0x7) << 1) /* Rx Tune Mode<2:0> */ + +/* +* REG_POLE_GAIN +*/ +#define POLE_GAIN_TUNE(x) (((x) & 0x3) << 0) /* Pole Gain Tune<1:0> */ + +/* +* REG_RX_BBBW_MHZ +*/ +#define RX_TUNE_BBBW_MHZ(x) (((x) & 0x1F) << 0) /* Rx Tune BBBW MHz<4::0> */ + +/* +* REG_RX_BBBW_KHZ +*/ +#define RX_TUNE_BBBW_KHZ(x) (((x) & 0x7F) << 0) /* Rx Tune BBBW kHz<6:0> */ + +/* +* REG_RX_PFD_CONFIG +*/ +#define BYPASS_LD_SYNTH (1 << 0) /* Bypass Ld Synth */ + +/* +* REG_RX_INTEGER_BYTE_1 +*/ +#define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */ + +/* +* REG_RX_FRACT_BYTE_2 +*/ +#define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */ + +/* +* REG_RX_FORCE_VCO_TUNE_1 +*/ +#define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */ + +/* +* REG_RX_ALC_VARACTOR +*/ +#define INIT_ALC_VALUE(x) (((x) & 0xF) << 4) /* Init ALC Value<3:0> */ +#define VCO_VARACTOR(x) (((x) & 0xF) << 0) /* VCO Varactor<3:0> */ + +/* +* REG_RX_VCO_OUTPUT +*/ +#define PORB_VCO_LOGIC (1 << 6) /* PORb VCO Logic */ +#define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0) /* VCO Output Level<3:0> */ + +/* +* REG_RX_CP_CURRENT +*/ +#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */ + +/* +* REG_RX_CP_OFFSET +*/ +#define SYNTH_RECAL (1 << 7) /* Synth Re-Cal */ + +/* +* REG_RX_CP_CONFIG +*/ +#define HALF_VCO_CAL_CLK (1 << 7) /* Half Vco Cal Clk */ +#define CP_OFFSET_OFF (1 << 4) /* CP Offset Off */ +#define F_CPCAL (1 << 3) /* F Cpcal */ +#define CP_CAL_ENABLE (1 << 2) /* Cp Cal Enable */ + +/* +* REG_RX_LOOP_FILTER_1 +*/ +#define LOOP_FILTER_C2(x) (((x) & 0xF) << 4) /* Loop Filter C2<3:0> */ +#define LOOP_FILTER_C1(x) (((x) & 0xF) << 0) /* Loop Filter C1<3:0> */ + +/* +* REG_RX_LOOP_FILTER_2 +*/ +#define LOOP_FILTER_R1(x) (((x) & 0xF) << 4) /* Loop Filter R1<3:0> */ +#define LOOP_FILTER_C3(x) (((x) & 0xF) << 0) /* Loop Filter C3<3:0> */ + +/* +* REG_RX_LOOP_FILTER_3 +*/ +#define LOOP_FILTER_BYPASS_R3 (1 << 7) /* Loop Filter Bypass R3 */ +#define LOOP_FILTER_BYPASS_R1 (1 << 6) /* Loop Filter Bypass R1 */ +#define LOOP_FILTER_BYPASS_C2 (1 << 5) /* Loop Filter Bypass C2 */ +#define LOOP_FILTER_BYPASS_C1 (1 << 4) /* Loop Filter Bypass C1 */ +#define LOOP_FILTER_R3(x) (((x) & 0xF) << 0) /* Loop Filter R3<3:0> */ + +/* +* REG_RX_DITHERCP_CAL +*/ +#define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */ + +/* +* REG_RX_VCO_BIAS_1 +*/ +#define VCO_BIAS_TCF(x) (((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */ +#define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */ + +/* +* REG_RX_CAL_STATUS +*/ +#define CP_CAL_VALID (1 << 7) /* CP Cal Valid */ +#define CP_CAL_DONE (1 << 5) /* CP Cal Done */ +#define VCO_CAL_BUSY (1 << 4) /* VCO Cal Busy */ +#define CP_CAL_WORD(x) (((x) & 0xF) << 0) /* CP Cal Word<3:0> */ + +/* +* REG_RX_VCO_CAL_REF +*/ +#define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */ + +/* +* REG_RX_VCO_PD_OVERRIDES +*/ +#define POWER_DOWN_VARACTOR_REF (1 << 3) /* Power Down Varactor Ref */ +#define PWR_DOWN_VARACT_REF_TCF (1 << 2) /* Pwr Down Varact Ref Tcf */ +#define POWER_DOWN_CAL_TCF (1 << 1) /* Power Down Cal Tcf */ +#define POWER_DOWN_VCO_BUFFFER (1 << 0) /* Power Down VCO Bufffer */ + +/* +* REG_RX_CP_OVERRANGE_VCO_LOCK +*/ +#define CP_OVRG_HIGH (1 << 7) /* CP Ovrg High */ +#define CP_OVRG_LOW (1 << 6) /* CP Ovrg Low */ +#define VCO_LOCK (1 << 1) /* Lock */ + +/* +* REG_RX_VCO_LDO +*/ +#define VCO_LDO_BYPASS (1 << 7) /* VCO LDO Bypass */ +#define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */ +#define VCO_LDO_SEL(x) (((x) & 0x7) << 2) /* VCO LDO Sel<2:0> */ +#define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */ + +/* +* REG_RX_VCO_CAL +*/ +#define VCO_CAL_EN (1 << 7) /* VCO Cal En */ +#define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4) /* VCO Cal ALC Wait <2:0> */ +#define VCO_CAL_COUNT(x) (((x) & 0x3) << 2) /* VCO Cal Count <1:0> */ + +/* +* REG_RX_LOCK_DETECT_CONFIG +*/ +#define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2) /* Lock Detect Count<1:0> */ +#define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */ + +/* +* REG_RX_CP_LEVEL_DETECT +*/ +#define CP_LEVEL_DETECT_POWER_DOWN (1 << 6) /* CP Level Detect Power Down */ +#define CP_LEVEL_THRESH_LOW(x) (((x) & 0x7) << 3) /* CP Level Threshold Low<2:0> */ +#define CP_LEVEL_THRESH_HIGH(x) (((x) & 0x7) << 0) /* CP Level Threshold High<2:0> */ + +/* +* REG_RX_DSM_SETUP_0 +*/ +#define DSM_PROG(x) (((x) & 0xF) << 0) /* DSM Prog<3:0> */ + +/* +* REG_RX_DSM_SETUP_1 +*/ +#define SIF_CLOCK (1 << 6) /* SIF clock */ +#define SIF_RESET_BAR (1 << 5) /* SIF Reset Bar */ +#define SIF_ADDR(x) (((x) & 0x1F) << 0) /* SIF Addr<4:0> */ + +/* +* REG_RX_CORRECTION_WORD0 +*/ +#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */ +#define READ_EFFECTIVE_TUNING_WORD (1 << 5) /* Read Effective Tuning Word */ +#define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */ + +/* +* REG_RX_CORRECTION_WORD1 +*/ +#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */ +#define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */ + +/* +* REG_RX_VCO_VARACTOR_CTRL_0 +*/ +#define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */ +#define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */ + +/* +* REG_RX_VCO_VARACTOR_CTRL_1 +*/ +#define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */ + +/* +* REG_RX_FAST_LOCK_SETUP +*/ +#define RX_FAST_LOCK_LOAD_SYNTH (1 << 3) /* Rx Fast Lock Load Synth */ +#define RX_FAST_LOCK_PROFILE_INIT (1 << 2) /* Rx Fast Lock Profile Init */ +#define RX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1) /* Rx Fast Lock Profile Pin Select */ +#define RX_FAST_LOCK_MODE_ENABLE (1 << 0) /* Rx Fast Lock Mode Enable */ +#define RX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5) /* Rx Fast Lock Profile<2:0> */ + +/* +* REG_RX_FAST_LOCK_PROGRAM_ADDR +*/ +#define RX_FAST_LOCK_PROFILE_ADDR(x) (((x) & 0x7) << 4) /* Rx Fast Lock Profile<2:0> */ +#define RX_FAST_LOCK_PROFILE_WORD(x) (((x) & 0xF) << 0) /* Configuration Word <3:0> */ + + +/* +* REG_RX_FAST_LOCK_PROGRAM_CTRL +*/ +#define RX_FAST_LOCK_PROGRAM_WRITE (1 << 1) /* Rx Fast Lock Program Write */ +#define RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0) /* Rx Fast Lock Program Clock Enable */ + +#define RX_FAST_LOCK_CONFIG_WORD_NUM 16 + +/* +* REG_RX_LO_GEN_POWER_MODE +*/ +#define RX_LO_GEN_POWER_MODE(x) (((x) & 0x3) << 4) /* Power Mode<3:0> */ + +/* +* REG_TX_PFD_CONFIG +*/ +#define DIV_TEST_EN (1 << 5) /* Div Test En */ +#define PFD_CLK_EDGE (1 << 1) /* PFD Clk Edge */ +#define BYPASS_LD_SYNTH (1 << 0) /* Bypass Ld Synth */ +#define PFD_WIDTH(x) (((x) & 0x3) << 2) /* PFD Width <1:0> */ + +/* +* REG_TX_INTEGER_BYTE_1 +*/ +#define SDM_BYPASS (1 << 7) /* SDM Bypass */ +#define SDM_POWER_DOWN (1 << 6) /* SDM Power Down */ +#define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */ + +/* +* REG_TX_FRACT_BYTE_2 +*/ +#define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */ + +/* +* REG_TX_FORCE_ALC +*/ +#define FORCE_ALC_ENABLE (1 << 7) /* Force ALC Enable */ +#define FORCE_ALC_WORD(x) (((x) & 0x7F) << 0) /* Force ALC Word<6:0> */ + +/* +* REG_TX_FORCE_VCO_TUNE_1 +*/ +#define BYPASS_LOAD_DELAY (1 << 7) /* Bypass Load Delay */ +#define FORCE_VCO_TUNE_ENABLE (1 << 1) /* Force VCO Tune Enable */ +#define FORCE_VCO_TUNE (1 << 0) /* Force VCO Tune */ +#define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */ + +/* +* REG_TX_ALCVARACT_OR +*/ +#define INIT_ALC_VALUE(x) (((x) & 0xF) << 4) /* Init ALC Value<3:0> */ +#define VCO_VARACTOR(x) (((x) & 0xF) << 0) /* VCO Varactor<3:0> */ + +/* +* REG_TX_VCO_OUTPUT +*/ +#define PORB_VCO_LOGIC (1 << 6) /* PORb VCO Logic */ +#define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0) /* VCO Output Level<3:0> */ + +/* +* REG_TX_CP_CURRENT +*/ +#define TX_CP_CURRENT_DFLT (1 << 7) /* Set to 1 */ +#define VTUNE_FORCE (1 << 6) /* Vtune Force */ +#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */ + +/* +* REG_TX_CP_OFFSET +*/ +#define SYNTH_RECAL (1 << 7) /* Synth Re-Cal */ +#define CHARGE_PUMP_OFFSET(x) (((x) & 0x3F) << 0) /* Charge Pump Offset<5:0> */ + +/* +* REG_TX_CP_CONFIG +*/ +#define HALF_VCO_CAL_CLK (1 << 7) /* Half Vco Cal Clk */ +#define DITHER_MODE (1 << 6) /* Dither Mode */ +#define CP_OFFSET_OFF (1 << 4) /* Cp Offset Off */ +#define F_CPCAL (1 << 3) /* F Cpcal */ +#define CP_CAL_ENABLE (1 << 2) /* Cp Cal Enable */ +#define CP_TEST(x) (((x) & 0x3) << 0) /* Cp Test <1:0> */ + +/* +* REG_TX_LOOP_FILTER_1 +*/ +#define LOOP_FILTER_C2(x) (((x) & 0xF) << 4) /* Loop Filter C2<3:0> */ +#define LOOP_FILTER_C1(x) (((x) & 0xF) << 0) /* Loop Filter C1<3:0> */ + +/* +* REG_TX_LOOP_FILTER_2 +*/ +#define LOOP_FILTER_R1(x) (((x) & 0xF) << 4) /* Loop Filter R1<3:0> */ +#define LOOP_FILTER_C3(x) (((x) & 0xF) << 0) /* Loop Filter C3<3:0> */ + +/* +* REG_TX_LOOP_FILTER_3 +*/ +#define LOOP_FILTER_BYPASS_R3 (1 << 7) /* Loop Filter Bypass R3 */ +#define LOOP_FILTER_BYPASS_R1 (1 << 6) /* Loop Filter Bypass R1 */ +#define LOOP_FILTER_BYPASS_C2 (1 << 5) /* Loop Filter Bypass C2 */ +#define LOOP_FILTER_BYPASS_C1 (1 << 4) /* Loop Filter Bypass C1 */ +#define LOOP_FILTER_R3(x) (((x) & 0xF) << 0) /* Loop Filter R3<3:0> */ + +/* +* REG_TX_DITHERCP_CAL +*/ +#define NUMBER_SDM_DITHER_BITS(x) (((x) & 0xF) << 4) /* Number SDM Dither Bits<3:0> */ +#define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */ + +/* +* REG_TX_VCO_BIAS_1 +*/ +#define MUST_BE_ZEROS(x) (((x) & 0x3) << 5) /* Must be zeros */ +#define VCO_BIAS_TCF(x) (((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */ +#define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */ + +/* +* REG_TX_VCO_BIAS_2 +*/ +#define VCO_BYPASS_BIAS_DAC_R (1 << 7) /* VCO Bypass Bias DAC R */ +#define VCO_COMP_BYPASS_BIAS_R (1 << 4) /* VCO Comp Bypass Bias R */ +#define BYPASS_PRESCALE_R (1 << 3) /* Bypass Prescale R */ +#define LAST_ALC_ENABLE (1 << 2) /* Last ALC Enable */ +#define PRESCALE_BIAS(x) (((x) & 0x3) << 0) /* Prescale Bias <1:0> */ + +/* +* REG_TX_CAL_STATUS +*/ +#define CP_CAL_VALID (1 << 7) /* CP Cal Valid */ +#define COMP_OUT (1 << 6) /* Comp Out */ +#define CP_CAL_DONE (1 << 5) /* CP Cal Done */ +#define VCO_CAL_BUSY (1 << 4) /* VCO Cal Busy */ +#define CP_CAL_WORD(x) (((x) & 0xF) << 0) /* CP Cal Word<3:0> */ + +/* +* REG_TX_VCO_CAL_REF +*/ +#define VCO_CAL_REF_MONITOR (1 << 3) /* VCO Cal Ref Monitor */ +#define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */ + +/* +* REG_TX_VCO_PD_OVERRIDES +*/ +#define POWER_DOWN_VARACTOR_REF (1 << 3) /* Power Down Varactor Ref */ +#define POWER_DOWN_VARACT_REF_TCF (1 << 2) /* Power Down Varact Ref Tcf */ +#define POWER_DOWN_CAL_TCF (1 << 1) /* Power Down Cal Tcf */ +#define POWER_DOWN_VCO_BUFFFER (1 << 0) /* Power Down VCO Bufffer */ + +/* +* REG_TX_CP_OVERRANGE_VCO_LOCK +*/ +#define CP_OVRG_HIGH (1 << 7) /* CP Ovrg High */ +#define CP_OVRG_LOW (1 << 6) /* CP Ovrg Low */ +#define VCO_LOCK (1 << 1) /* Lock */ + +/* +* REG_TX_VCO_LDO +*/ +#define VCO_LDO_BYPASS (1 << 7) /* VCO LDO Bypass */ +#define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */ +#define VCO_LDO_VOUT_SEL(x) (((x) & 0x7) << 2) /* VCO LDO Vout Sel<2:0> */ +#define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */ + +/* +* REG_TX_VCO_CAL +*/ +#define VCO_CAL_EN (1 << 7) /* VCO Cal En */ +#define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4) /* VCO Cal ALC Wait<2:0) */ +#define VCO_CAL_COUNT(x) (((x) & 0x3) << 2) /* VCO Cal Count<1:0> */ +#define FB_CLOCK_ADV(x) (((x) & 0x3) << 0) /* FB Clock Adv<1:0> */ + +/* +* REG_TX_LOCK_DETECT_CONFIG +*/ +#define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2) /* Lock Detect Count<1:0> */ +#define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */ + +/* +* REG_TX_CP_LEVEL_DETECT +*/ +#define CP_LEVEL_DETECT_POWER_DOWN (1 << 6) /* CP Level Detect Power Down */ +#define CP_LEVEL_DETECT_THRESH_LOW(x) (((x) & 0x7) << 3) /* CP Level Detect Threshold Low<2:0> */ +#define CP_LEVEL_DETECT_THRESH_HIGH(x) (((x) & 0x7) << 0) /* CP Level Detect Threshold High<2:0> */ + +/* +* REG_TX_DSM_SETUP_0 +*/ +#define DSM_PROG(x) (((x) & 0xF) << 0) /* DSM Prog<3:0> */ + +/* +* REG_TX_DSM_SETUP_1 +*/ +#define SIF_CLOCK (1 << 6) /* SIF clock */ +#define SIF_RESET_BAR (1 << 5) /* SIF Reset Bar */ +#define SIF_ADDR(x) (((x) & 0x1F) << 0) /* SIF Addr<4:0> */ + +/* +* REG_TX_CORRECTION_WORD0 +*/ +#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */ +#define READ_EFFECTIVE_TUNING_WORD (1 << 5) /* Read Effective Tuning Word */ +#define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */ + +/* +* REG_TX_CORRECTION_WORD1 +*/ +#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */ +#define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */ + +/* +* REG_TX_VCO_VARACTOR_CTRL_0 +*/ +#define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */ +#define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */ + +/* +* REG_TX_VCO_VARACTOR_CTRL_1 +*/ +#define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */ + +/* +* REG_DCXO_COARSE_TUNE +*/ +#define DCXO_TUNE_COARSE(x) (((x) & 0x3F) << 0) /* DCXO Tune Coarse<5:0> */ + +/* +* REG_DCXO_FINE_TUNE_LOW +*/ +#define DCXO_TUNE_FINE_LOW(x) (((x) & 0x1F) << 3) /* DCXO Tune Fine<4:0> */ + +/* +* REG_DCXO_FINE_TUNE_HIGH +*/ +#define DCXO_TUNE_FINE_HIGH(x) ((x) >> 5) /* DCXO Tune Fine<12:5> */ + +/* +* REG_DCXO_CONFIG +*/ +#define MUST_BE_ZERO (1 << 7) /* Must be zero */ +#define DCXO_RTAIL(x) (((x) & 0x7) << 4) /* DCXO Rtail<2:0> */ +#define DCXO_RD(x) (((x) & 0x3) << 2) /* DCXO Rd<1:0> */ + +/* +* REG_DCXO_TEMPCO_ADDR +*/ +#define DCXO_TEMPCO_EN (1 << 7) /* DCXO Tempco En */ +#define DCXO_TEMPCO_CLK (1 << 6) /* DCXO Tempco Clk */ +#define DCXO_TEMPERATURE_COEF_ADDRESS(x) (((x) & 0x3F) << 0) /* DCXO Temperature Coefficient Address<5:0> */ + +/* +* REG_TX_FAST_LOCK_SETUP +*/ +#define TX_FAST_LOCK_LOAD_SYNTH (1 << 3) /* Tx Fast Lock Load Synth */ +#define TX_FAST_LOCK_PROFILE_INIT (1 << 2) /* Tx Fast Lock Profile Init */ +#define TX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1) /* Tx Fast Lock Profile Pin Select */ +#define TX_FAST_LOCK_MODE_ENABLE (1 << 0) /* Tx Fast Lock Mode Enable */ +#define TX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5) /* Tx Fast Lock Profile<2:0> */ + +/* +* REG_TX_FAST_LOCK_PROGRAM_CTRL +*/ +#define TX_FAST_LOCK_PROGRAM_WRITE (1 << 1) /* Tx Fast Lock Program Write */ +#define TX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0) /* Tx Fast Lock Program Clock Enable */ + +/* +* REG_TX_LO_GEN_POWER_MODE +*/ +#define TX_LO_GEN_POWER_MODE(x) (((x) & 0xF) << 4) /* Power Mode<3:0> */ + +/* +* REG_BANDGAP_CONFIG0 +*/ +#define POWER_DOWN_BANDGAP_REF (1 << 7) /* Power Down Bandgap Ref */ +#define MASTER_BIAS_FILTER_BYPASS (1 << 6) /* Master Bias Filter Bypass */ +#define MASTER_BIAS_REF_SEL (1 << 5) /* Master Bias Ref Sel */ +#define MASTER_BIAS_TRIM(x) (((x) & 0x1F) << 0) /* Master Bias Trim<4:0> */ + +/* +* REG_BANDGAP_CONFIG1 +*/ +#define VCO_LDO_FILTER_BYPASS (1 << 7) /* VCO LDO Filter Bypass */ +#define VCO_LDO_REF_SEL (1 << 6) /* VCO LDO Ref Sel */ +#define BANDGAP_REF_RESET (1 << 5) /* Bandgap Ref Reset */ +#define BANDGAP_TEMP_TRIM(x) (((x) & 0x1F) << 0) /* Bandgap Temp Trim<4:0> */ + +/* +* REG_REF_DIVIDE_CONFIG_1 +*/ +#define REF_DIVIDE_CONFIG_1_DFLT (1 << 2) /* Set to 1 */ +#define RX_REF_RESET_BAR (1 << 1) /* Rx Ref Reset Bar */ +#define RX_REF_DIVIDER_MSB (1 << 0) /* Rx Ref Divider<1> */ + +/* +* REG_REF_DIVIDE_CONFIG_2 +*/ +#define RX_REF_DIVIDER_LSB (1 << 7) /* Rx Ref Divider< 0> */ +#define TX_REF_RESET_BAR (1 << 4) /* Tx Ref Reset Bar */ +#define RX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 5) /* Rx Ref Doubler FB Delay<1:0> */ +#define TX_REF_DIVIDER(x) (((x) & 0x3) << 2) /* Tx Ref Divider<1:0> */ +#define TX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 0) /* Tx Ref Doubler FB Delay<1:0> */ + +/* +* REG_GAIN_RX1,2 +*/ +#define FULL_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Full Table Gain Index Rx1/LMT Gain Rx1<6:0> */ + +/* +* REG_LPF_GAIN_RX1,2 +*/ +#define LPF_GAIN_RX(x) (((x) & 0x1F) << 0) /* LPF gain Rx1<4:0> */ + +/* +* REG_DIG_GAIN_RX1,2 +*/ +#define DIGITAL_GAIN_RX(x) (((x) & 0x1F) << 0) /* Digital gain Rx1<4:0> */ + +/* +* REG_FAST_ATTACK_STATE +*/ +#define FAST_ATTACK_STATE_RX2(x) (((x) & 0x7) << 4) /* Fast Attack State Rx2<2:0> */ +#define FAST_ATTACK_STATE_RX1(x) (((x) & 0x7) << 0) /* Fast Attack State Rx1<2:0> */ +#define FAST_ATK_MASK 0x7 +#define RX1_FAST_ATK_SHIFT 0 +#define RX2_FAST_ATK_SHIFT 4 +#define FAST_ATK_RESET 0 +#define FAST_ATK_PEAK_DETECT 1 +#define FAST_ATK_PWR_MEASURE 2 +#define FAST_ATK_FINAL_SETTELING 3 +#define FAST_ATK_FINAL_OVER 4 +#define FAST_ATK_GAIN_LOCKED 5 + +/* +* REG_SLOW_LOOP_STATE +*/ +#define SLOW_LOOP_STATE_RX2(x) (((x) & 0x7) << 4) /* Slow Loop State Rx2<2:0> */ +#define SLOW_LOOP_STATE_RX1(x) (((x) & 0x7) << 0) /* Slow Loop State Rx1<2:0> */ + + +/* +* REG_OVRG_SIGS_RX1,2 +*/ +#define GAIN_LOCK_1 (1 << 6) /* Gain Lock 1 */ +#define LOW_POWER_1 (1 << 5) /* Low Power 1 */ +#define LARGE_LMT_OL (1 << 4) /* Large LMT OL */ +#define SMALL_LMT_OL (1 << 3) /* Small LMT OL */ +#define LARGE_ADC_OL (1 << 2) /* Large ADC OL */ +#define SMALL_ADC_OL (1 << 1) /* Small ADC OL */ +#define DIG_SAT (1 << 0) /* Dig Sat */ +/* +* REG_CTRL +*/ +#define CTRL_ENABLE (1 << 0) /* Set to 1 */ + +/* +* REG_BIST_CONFIG +*/ +#define TONE_PRBS (1 << 1) /* Tone/ PRBS */ +#define BIST_ENABLE (1 << 0) /* BIST Enable */ +#define TONE_FREQ(x) (((x) & 0x3) << 6) /* Tone Frequency<1:0> */ +#define TONE_LEVEL(x) (((x) & 0x3) << 4) /* Tone Level<1:0> */ +#define BIST_CTRL_POINT(x) (((x) & 0x3) << 2) /* BIST Control Point <1:0> */ + +/* +* REG_OBSERVE_CONFIG +*/ +#define DATA_PORT_SP_HD_LOOP_TEST_OE (1 << 7) /* Data Port SP, HD Loop Test OE */ +#define RX_MASK (1 << 6) /* Rx Mask */ +#define CHANNEL (1 << 5) /* Channel */ +#define DATA_PORT_LOOP_TEST_ENABLE (1 << 0) /* Data Port Loop Test Enable */ +#define OBSERVATION_POINT(x) (((x) & 0xF) << 1) /* Observation Point<2:0> */ + +/* +* REG_BIST_AND_DATA_PORT_TEST_CONFIG +*/ +#define BIST_MASK_CHANNEL_2_Q_DATA (1 << 5) /* BIST Mask Channel 2 Q data */ +#define BIST_MASK_CHANNEL_2_I_DATA (1 << 4) /* BIST Mask Channel 2 I data */ +#define BIST_MASK_CHANNEL_1_Q_DATA (1 << 3) /* BIST Mask Channel 1 Q data */ +#define BIST_MASK_CHANNEL_1_I_DATA (1 << 2) /* BIST Mask Channel 1 I data */ +#define DATA_PORT_HILOW (1 << 1) /* Data Port Hi/Low */ +#define USE_DATA_PORT (1 << 0) /* Use Data Port */ +#define TEMP_SENSE_VBE_TEST(x) (((x) & 0x3) << 6) /* Temp Sense Vbe Test<1:0> */ + +/* +* REG_DAC_TEST_2 +*/ +#define DAC_TEST_ENABLE (1 << 7) /* DAC Test Enable */ +#define DAC_TEST_WORD(x) (((x) & 0x7F) << 0) /* DAC test Word <22:16> */ + +/* +* SPI Comm Helpers +*/ +#define AD_READ (0 << 15) +#define AD_WRITE (1 << 15) +#define AD_CNT(x) ((((x) - 1) & 0x7) << 12) +#define AD_ADDR(x) ((x) & 0x3FF) + + +/* +* AD9361 Limits +*/ + +#define RSSI_MULTIPLIER 100 +#define RSSI_RESOLUTION ((int) (0.25 * RSSI_MULTIPLIER)) +#define RSSI_MAX_WEIGHT 255 + +#define MAX_LMT_INDEX 40 +#define MAX_LPF_GAIN 24 +#define MAX_DIG_GAIN 31 + +#define MAX_BBPLL_FREF 70007000UL /* 70 MHz + 100ppm */ +#define MIN_BBPLL_FREQ 714928500UL /* 715 MHz - 100ppm */ +#define MAX_BBPLL_FREQ 1430143000UL /* 1430 MHz + 100ppm */ +#define MAX_BBPLL_DIV 64 +#define MIN_BBPLL_DIV 2 + +/* + * The ADC minimum and maximum operating output data rates + * are 25MHz and 640MHz respectively. + * For more information see here: https://ez.analog.com/docs/DOC-12763 + */ + +#define MIN_ADC_CLK 25000000UL /* 25 MHz */ +//#define MIN_ADC_CLK (MIN_BBPLL_FREQ / MAX_BBPLL_DIV) /* 11.17MHz */ +#define MAX_ADC_CLK 640000000UL /* 640 MHz */ +#define MAX_DAC_CLK (MAX_ADC_CLK / 2) + +/* Associated with outputs of stage */ +#define MAX_RX_HB1 245760000UL +#define MAX_RX_HB2 320000000UL +#define MAX_RX_HB3 640000000UL +/* Associated with inputs of stage */ +#define MAX_TX_HB1 160000000UL +#define MAX_TX_HB2 320000000UL +#define MAX_TX_HB3 320000000UL + +#define MAX_BASEBAND_RATE 61440000UL + +#define MAX_MBYTE_SPI 8 + +#define RFPLL_MODULUS 8388593UL +#define BBPLL_MODULUS 2088960UL + +#define MAX_SYNTH_FREF 80008000UL /* 80 MHz + 100ppm */ +#define MIN_SYNTH_FREF 9999000UL /* 10 MHz - 100ppm */ +#define MIN_VCO_FREQ_HZ 6000000000ULL +#define MAX_CARRIER_FREQ_HZ 6000000000ULL +#define MIN_RX_CARRIER_FREQ_HZ 70000000ULL +#define MIN_TX_CARRIER_FREQ_HZ 46875001ULL + +#define AD9363A_MAX_CARRIER_FREQ_HZ 3800000000ULL +#define AD9363A_MIN_CARRIER_FREQ_HZ 325000000ULL + +#define MAX_TX_ATTENUATION_DB 89750 + +/* +* Driver +*/ + +enum rx_gain_table_type { + RXGAIN_FULL_TBL, + RXGAIN_SPLIT_TBL, +}; + +enum rx_gain_table_name { + TBL_200_1300_MHZ, + TBL_1300_4000_MHZ, + TBL_4000_6000_MHZ, + RXGAIN_TBLS_END, +}; + +struct gain_table_info { + uint64_t start; + uint64_t end; + uint8_t max_index; + uint8_t split_table; + int8_t *abs_gain_tbl; + uint8_t (*tab)[3]; +}; + +enum fir_dest { + FIR_TX1 = 0x01, + FIR_TX2 = 0x02, + FIR_TX1_TX2 = 0x03, + FIR_RX1 = 0x81, + FIR_RX2 = 0x82, + FIR_RX1_RX2 = 0x83, + FIR_IS_RX = 0x80, +}; + +struct rf_gain_ctrl { + uint32_t ant; + uint8_t mode; +}; + +enum rf_gain_ctrl_mode { + RF_GAIN_MGC, + RF_GAIN_FASTATTACK_AGC, + RF_GAIN_SLOWATTACK_AGC, + RF_GAIN_HYBRID_AGC +}; + +enum f_agc_target_gain_index_type { + MAX_GAIN, + SET_GAIN, + OPTIMIZED_GAIN, + NO_GAIN_CHANGE, +}; + +struct gain_control { + enum rf_gain_ctrl_mode rx1_mode; + enum rf_gain_ctrl_mode rx2_mode; + + /* Common */ + uint8_t adc_ovr_sample_size; /* 1..8 Sum x samples, AGC_CONFIG_3 */ + uint8_t adc_small_overload_thresh; /* 0..255, 0x105 */ + uint8_t adc_large_overload_thresh; /* 0..255, 0x104 */ + + uint16_t lmt_overload_high_thresh; /* 16..800 mV, 0x107 */ + uint16_t lmt_overload_low_thresh; /* 16..800 mV, 0x108 */ + uint16_t dec_pow_measuremnt_duration; /* Samples, 0x15C */ + uint8_t low_power_thresh; /* -64..0 dBFS, 0x114 */ + bool use_rx_fir_out_for_dec_pwr_meas; /* clears 0x15C:6 USE_HB1_OUT_FOR_DEC_PWR_MEAS */ + + bool dig_gain_en; /* should be turned off, since ADI GT doesn't use dig gain */ + uint8_t max_dig_gain; /* 0..31 */ + + /* MGC */ + bool mgc_rx1_ctrl_inp_en; /* Enables Pin control on RX1 default SPI ctrl */ + bool mgc_rx2_ctrl_inp_en; /* Enables Pin control on RX2 default SPI ctrl */ + + uint8_t mgc_inc_gain_step; /* 1..8 */ + uint8_t mgc_dec_gain_step; /* 1..8 */ + uint8_t mgc_split_table_ctrl_inp_gain_mode; /* 0=AGC determine this, 1=only in LPF, 2=only in LMT */ + + /* AGC */ + uint8_t agc_attack_delay_extra_margin_us; /* 0..31 us */ + + uint8_t agc_outer_thresh_high; + uint8_t agc_outer_thresh_high_dec_steps; + uint8_t agc_inner_thresh_high; + uint8_t agc_inner_thresh_high_dec_steps; + uint8_t agc_inner_thresh_low; + uint8_t agc_inner_thresh_low_inc_steps; + uint8_t agc_outer_thresh_low; + uint8_t agc_outer_thresh_low_inc_steps; + + uint8_t adc_small_overload_exceed_counter; /* 0..15, 0x122 */ + uint8_t adc_large_overload_exceed_counter; /* 0..15, 0x122 */ + uint8_t adc_large_overload_inc_steps; /* 0..15, 0x106 */ + + bool adc_lmt_small_overload_prevent_gain_inc; /* 0x120 */ + + uint8_t lmt_overload_large_exceed_counter; /* 0..15, 0x121 */ + uint8_t lmt_overload_small_exceed_counter; /* 0..15, 0x121 */ + uint8_t lmt_overload_large_inc_steps; /* 0..7, 0x121 */ + + uint8_t dig_saturation_exceed_counter; /* 0..15, 0x128 */ + uint8_t dig_gain_step_size; /* 1..8, 0x100 */ + bool sync_for_gain_counter_en; /* 0x128:4 !Hybrid */ + + uint32_t gain_update_interval_us; /* in us */ + bool immed_gain_change_if_large_adc_overload; /* 0x123:3 */ + bool immed_gain_change_if_large_lmt_overload; /* 0x123:7 */ + + /* + * Fast AGC + */ + uint32_t f_agc_dec_pow_measuremnt_duration; /* Samples, 0x15C */ + uint32_t f_agc_state_wait_time_ns; /* 0x117 0..31 RX samples -> time_ns */ + /* Fast AGC - Low Power */ + bool f_agc_allow_agc_gain_increase; /* 0x110:1 */ + uint8_t f_agc_lp_thresh_increment_time; /* 0x11B RX samples */ + uint8_t f_agc_lp_thresh_increment_steps; /* 0x117 1..8 */ + + /* Fast AGC - Lock Level */ + uint8_t f_agc_lock_level; /* NOT USED: 0x101 0..-127 dBFS same as agc_inner_thresh_high */ + bool f_agc_lock_level_lmt_gain_increase_en; /* 0x111:6 */ + uint8_t f_agc_lock_level_gain_increase_upper_limit; /* 0x118 0..63 */ + /* Fast AGC - Peak Detectors and Final Settling */ + uint8_t f_agc_lpf_final_settling_steps; /* 0x112:6 0..3 (Post Lock Level Step)*/ + uint8_t f_agc_lmt_final_settling_steps; /* 0x113:6 0..3 (Post Lock Level Step)*/ + uint8_t f_agc_final_overrange_count; /* 0x116:5 0..7 */ + /* Fast AGC - Final Power Test */ + bool f_agc_gain_increase_after_gain_lock_en; /* 0x110:7 */ + /* Fast AGC - Unlocking the Gain */ + /* 0 = MAX Gain, 1 = Set Gain, 2 = Optimized Gain */ + enum f_agc_target_gain_index_type + f_agc_gain_index_type_after_exit_rx_mode; /* 0x110:[4,2] */ + bool f_agc_use_last_lock_level_for_set_gain_en; /* 0x111:7 */ + uint8_t f_agc_optimized_gain_offset; /*0x116 0..15 steps */ + bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en; /* 0x110:~6 */ + uint8_t f_agc_rst_gla_stronger_sig_thresh_above_ll; /*0x113 0..63 dbFS */ + bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* 0x110:6 */ + bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en; /* 0x110:6 */ + uint8_t f_agc_rst_gla_engergy_lost_sig_thresh_below_ll; /* 0x112:6 */ + uint8_t f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* 0x119 0..63 RX samples */ + bool f_agc_rst_gla_large_adc_overload_en; /*0x110:~1 and 0x114:~7 */ + bool f_agc_rst_gla_large_lmt_overload_en; /*0x110:~1 */ + bool f_agc_rst_gla_en_agc_pulled_high_en; + /* 0 = Max Gain, 1 = Set Gain, 2 = Optimized Gain, 3 = No Gain Change */ + + enum f_agc_target_gain_index_type + f_agc_rst_gla_if_en_agc_pulled_high_mode; /* 0x0FB, 0x111 */ + uint8_t f_agc_power_measurement_duration_in_state5; /* 0x109, 0x10a RX samples 0..524288*/ + uint8_t f_agc_large_overload_inc_steps; /* 0x106 [D6:D4] 0..7 */ +}; + +struct auxdac_control { + uint16_t dac1_default_value; + uint16_t dac2_default_value; + + bool auxdac_manual_mode_en; + + bool dac1_in_rx_en; + bool dac1_in_tx_en; + bool dac1_in_alert_en; + + bool dac2_in_rx_en; + bool dac2_in_tx_en; + bool dac2_in_alert_en; + + uint8_t dac1_rx_delay_us; + uint8_t dac1_tx_delay_us; + uint8_t dac2_rx_delay_us; + uint8_t dac2_tx_delay_us; +}; + +enum rssi_restart_mode { + AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN, + EN_AGC_PIN_IS_PULLED_HIGH, + ENTERS_RX_MODE, + GAIN_CHANGE_OCCURS, + SPI_WRITE_TO_REGISTER, + GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH, +}; + +struct rssi_control { + enum rssi_restart_mode restart_mode; + bool rssi_unit_is_rx_samples; /* default unit is time */ + uint32_t rssi_delay; + uint32_t rssi_wait; + uint32_t rssi_duration; +}; + +struct rx_gain_info { + enum rx_gain_table_type tbl_type; + int32_t starting_gain_db; + int32_t max_gain_db; + int32_t gain_step_db; + int32_t max_idx; + int32_t idx_step_offset; +}; + +struct port_control { + uint8_t pp_conf[3]; + uint8_t rx_clk_data_delay; + uint8_t tx_clk_data_delay; + uint8_t digital_io_ctrl; + uint8_t lvds_bias_ctrl; + uint8_t lvds_invert[2]; +}; + +struct ctrl_outs_control { + uint8_t index; + uint8_t en_mask; +}; + +struct elna_control { + uint16_t gain_mdB; + uint16_t bypass_loss_mdB; + uint32_t settling_delay_ns; + bool elna_1_control_en; /* GPO0 */ + bool elna_2_control_en; /* GPO1 */ + bool elna_in_gaintable_all_index_en; +}; + +struct auxadc_control { + int8_t offset; + uint32_t temp_time_inteval_ms; + uint32_t temp_sensor_decimation; + bool periodic_temp_measuremnt; + uint32_t auxadc_clock_rate; + uint32_t auxadc_decimation; +}; + +struct gpo_control { + uint32_t gpo_manual_mode_enable_mask; + bool gpo_manual_mode_en; + bool gpo0_inactive_state_high_en; + bool gpo1_inactive_state_high_en; + bool gpo2_inactive_state_high_en; + bool gpo3_inactive_state_high_en; + bool gpo0_slave_rx_en; + bool gpo0_slave_tx_en; + bool gpo1_slave_rx_en; + bool gpo1_slave_tx_en; + bool gpo2_slave_rx_en; + bool gpo2_slave_tx_en; + bool gpo3_slave_rx_en; + bool gpo3_slave_tx_en; + uint8_t gpo0_rx_delay_us; + uint8_t gpo0_tx_delay_us; + uint8_t gpo1_rx_delay_us; + uint8_t gpo1_tx_delay_us; + uint8_t gpo2_rx_delay_us; + uint8_t gpo2_tx_delay_us; + uint8_t gpo3_rx_delay_us; + uint8_t gpo3_tx_delay_us; +}; + +struct tx_monitor_control { + bool tx_mon_track_en; + bool one_shot_mode_en; + uint32_t low_high_gain_threshold_mdB; + uint8_t low_gain_dB; + uint8_t high_gain_dB; + uint16_t tx_mon_delay; + uint16_t tx_mon_duration; + uint8_t tx1_mon_front_end_gain; + uint8_t tx2_mon_front_end_gain; + uint8_t tx1_mon_lo_cm; + uint8_t tx2_mon_lo_cm; +}; + +enum ad9361_pdata_rx_freq { + BBPLL_FREQ, + ADC_FREQ, + R2_FREQ, + R1_FREQ, + CLKRF_FREQ, + RX_SAMPL_FREQ, + NUM_RX_CLOCKS, +}; + +enum ad9361_pdata_tx_freq { + IGNORE, + DAC_FREQ, + T2_FREQ, + T1_FREQ, + CLKTF_FREQ, + TX_SAMPL_FREQ, + NUM_TX_CLOCKS, +}; + +enum ad9361_clkout { + CLKOUT_DISABLE, + BUFFERED_XTALN_DCXO, + ADC_CLK_DIV_2, + ADC_CLK_DIV_3, + ADC_CLK_DIV_4, + ADC_CLK_DIV_8, + ADC_CLK_DIV_16, +}; + +struct ad9361_phy_platform_data { + bool rx2tx2; + bool fdd; + bool fdd_independent_mode; + bool split_gt; + bool use_extclk; + bool ensm_pin_pulse_mode; + bool ensm_pin_ctrl; + bool debug_mode; + bool tdd_use_dual_synth; + bool tdd_skip_vco_cal; + bool use_ext_rx_lo; + bool use_ext_tx_lo; + bool rx1rx2_phase_inversion_en; + bool qec_tracking_slow_mode_en; + uint8_t dc_offset_update_events; + uint8_t dc_offset_attenuation_high; + uint8_t dc_offset_attenuation_low; + uint8_t rf_dc_offset_count_high; + uint8_t rf_dc_offset_count_low; + uint8_t dig_interface_tune_skipmode; + uint8_t dig_interface_tune_fir_disable; + uint8_t lo_powerdown_managed_en; + uint32_t dcxo_coarse; + uint32_t dcxo_fine; + uint32_t rf_rx_input_sel; + uint32_t rf_tx_output_sel; + uint32_t rx1tx1_mode_use_rx_num; + uint32_t rx1tx1_mode_use_tx_num; + uint32_t rx_path_clks[NUM_RX_CLOCKS]; + uint32_t tx_path_clks[NUM_TX_CLOCKS]; + uint32_t trx_synth_max_fref; + uint64_t rx_synth_freq; + uint64_t tx_synth_freq; + uint32_t rf_rx_bandwidth_Hz; + uint32_t rf_tx_bandwidth_Hz; + int32_t tx_atten; + bool update_tx_gain_via_alert; + uint32_t rx_fastlock_delay_ns; + uint32_t tx_fastlock_delay_ns; + bool trx_fastlock_pinctrl_en[2]; + + enum ad9361_clkout ad9361_clkout_mode; + + struct gain_control gain_ctrl; + struct rssi_control rssi_ctrl; + struct port_control port_ctrl; + struct ctrl_outs_control ctrl_outs_ctrl; + struct elna_control elna_ctrl; + struct auxadc_control auxadc_ctrl; + struct auxdac_control auxdac_ctrl; + struct gpo_control gpo_ctrl; + struct tx_monitor_control txmon_ctrl; +}; + +struct rf_rx_gain { + uint32_t ant; /* Antenna number to read gain */ + int32_t gain_db; /* gain value in dB */ + uint32_t fgt_lmt_index; /* Full Gain Table / LNA-MIXER-TIA gain index */ + uint32_t lmt_gain; /* LNA-MIXER-TIA gain in dB (Split GT mode only)*/ + uint32_t lpf_gain; /* Low pass filter gain in dB / index (Split GT mode only)*/ + uint32_t digital_gain; /* Digital gain in dB / index */ + /* Debug only */ + uint32_t lna_index; /* LNA Index (Split GT mode only) */ + uint32_t tia_index; /* TIA Index (Split GT mode only) */ + uint32_t mixer_index; /* MIXER Index (Split GT mode only) */ + +}; +struct rf_rssi { + uint32_t ant; /* Antenna number for which RSSI is reported */ + uint32_t symbol; /* Runtime RSSI */ + uint32_t preamble; /* Initial RSSI */ + int32_t multiplier; /* Multiplier to convert reported RSSI */ + uint8_t duration; /* Duration to be considered for measuring */ +}; + +struct SynthLUT { + uint16_t VCO_MHz; + uint8_t VCO_Output_Level; + uint8_t VCO_Varactor; + uint8_t VCO_Bias_Ref; + uint8_t VCO_Bias_Tcf; + uint8_t VCO_Cal_Offset; + uint8_t VCO_Varactor_Reference; + uint8_t Charge_Pump_Current; + uint8_t LF_C2; + uint8_t LF_C1; + uint8_t LF_R1; + uint8_t LF_C3; + uint8_t LF_R3; +}; + +enum { + LUT_FTDD_40, + LUT_FTDD_60, + LUT_FTDD_80, + LUT_FTDD_ENT, +}; + +enum ad9361_clocks { + BB_REFCLK, + RX_REFCLK, + TX_REFCLK, + BBPLL_CLK, + ADC_CLK, + R2_CLK, + R1_CLK, + CLKRF_CLK, + RX_SAMPL_CLK, + DAC_CLK, + T2_CLK, + T1_CLK, + CLKTF_CLK, + TX_SAMPL_CLK, + RX_RFPLL_INT, + TX_RFPLL_INT, + RX_RFPLL_DUMMY, + TX_RFPLL_DUMMY, + RX_RFPLL, + TX_RFPLL, + NUM_AD9361_CLKS, + EXT_REF_CLK, +}; + +struct ad9361_debugfs_entry { + struct ad9361_rf_phy *phy; + const char *propname; + void *out_value; + uint32_t val; + uint8_t size; + uint8_t cmd; +}; + +struct ad9361_fastlock_entry { +#define FASTLOOK_INIT 1 + uint8_t flags; + uint8_t alc_orig; + uint8_t alc_written; +}; + +struct ad9361_fastlock { + uint8_t save_profile; + uint8_t current_profile[2]; + struct ad9361_fastlock_entry entry[2][8]; +}; + +enum dig_tune_flags { + BE_VERBOSE = 1, + BE_MOREVERBOSE = 2, + DO_IDELAY = 4, + DO_ODELAY = 8, + SKIP_STORE_RESULT = 16, + RESTORE_DEFAULT = 32, +}; + +enum ad9361_bist_mode { + BIST_DISABLE, + BIST_INJ_TX, + BIST_INJ_RX, +}; + +enum synth_pd_ctrl { + LO_DONTCARE, + LO_OFF, + LO_ON, +}; + +enum dev_id { + ID_AD9361, + ID_AD9364, + ID_AD9363A +}; + +struct ad9361_rf_phy { + enum dev_id dev_sel; + struct spi_desc *spi; + struct gpio_desc *gpio_desc_resetb; + struct gpio_desc *gpio_desc_sync; + struct gpio_desc *gpio_desc_cal_sw1; + struct gpio_desc *gpio_desc_cal_sw2; +#ifndef AXI_ADC_NOT_PRESENT + struct axi_adc *rx_adc; + struct axi_dac *tx_dac; +#endif + struct clk *clk_refin; + struct clk *clks[NUM_AD9361_CLKS]; + struct refclk_scale *ref_clk_scale[NUM_AD9361_CLKS]; + uint32_t (*ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv); + int32_t (*ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv, + uint32_t rate); + int32_t (*ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv, + uint32_t rate); + struct ad9361_phy_platform_data *pdata; + uint8_t prev_ensm_state; + uint8_t curr_ensm_state; + uint8_t cached_rx_rfpll_div; + uint8_t cached_tx_rfpll_div; + uint8_t cached_synth_pd[2]; + int32_t tx_quad_lpf_tia_match; + uint32_t current_table; + struct gain_table_info *gt_info; + bool ensm_pin_ctl_en; + + bool auto_cal_en; + bool manual_tx_quad_cal_en; + uint64_t last_tx_quad_cal_freq; + uint32_t last_tx_quad_cal_phase; + uint64_t current_tx_lo_freq; + uint64_t current_rx_lo_freq; + bool current_tx_use_tdd_table; + bool current_rx_use_tdd_table; + uint32_t current_rx_path_clks[NUM_RX_CLOCKS]; + uint32_t current_tx_path_clks[NUM_TX_CLOCKS]; + uint32_t flags; + uint32_t cal_threshold_freq; + uint32_t current_rx_bw_Hz; + uint32_t current_tx_bw_Hz; + uint32_t rxbbf_div; + uint32_t rate_governor; + bool bypass_rx_fir; + bool bypass_tx_fir; + bool rx_eq_2tx; + bool filt_valid; + uint32_t filt_rx_path_clks[NUM_RX_CLOCKS]; + uint32_t filt_tx_path_clks[NUM_TX_CLOCKS]; + uint32_t filt_rx_bw_Hz; + uint32_t filt_tx_bw_Hz; + uint8_t tx_fir_int; + uint8_t tx_fir_ntaps; + uint8_t rx_fir_dec; + uint8_t rx_fir_ntaps; + uint8_t agc_mode[2]; + bool rfdc_track_en; + bool bbdc_track_en; + bool quad_track_en; + bool txmon_tdd_en; + uint16_t auxdac1_value; + uint16_t auxdac2_value; + uint32_t tx1_atten_cached; + uint32_t tx2_atten_cached; + struct ad9361_fastlock fastlock; + struct axiadc_converter *adc_conv; + struct axiadc_state *adc_state; + int32_t bist_loopback_mode; + int32_t bist_config; + enum ad9361_bist_mode bist_prbs_mode; + enum ad9361_bist_mode bist_tone_mode; + uint32_t bist_tone_freq_Hz; + uint32_t bist_tone_level_dB; + uint32_t bist_tone_mask; + bool bbpll_initialized; +}; + +struct refclk_scale { + struct spi_desc *spi; + struct ad9361_rf_phy *phy; + uint32_t mult; + uint32_t div; + enum ad9361_clocks source; + enum ad9361_clocks parent_source; +}; + +enum debugfs_cmd { + DBGFS_NONE, + DBGFS_INIT, + DBGFS_LOOPBACK, + DBGFS_BIST_PRBS, + DBGFS_BIST_TONE, + DBGFS_BIST_DT_ANALYSIS, + DBGFS_RXGAIN_1, + DBGFS_RXGAIN_2, +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ +int32_t ad9361_spi_readm(struct spi_desc *spi, uint32_t reg, + uint8_t *rbuf, uint32_t num); +int32_t ad9361_spi_read(struct spi_desc *spi, uint32_t reg); +int32_t ad9361_spi_write(struct spi_desc *spi, + uint32_t reg, uint32_t val); +int32_t ad9361_reset(struct ad9361_rf_phy *phy); +int32_t ad9361_register_clocks(struct ad9361_rf_phy *phy); +int32_t ad9361_unregister_clocks(struct ad9361_rf_phy *phy); +uint32_t ad9361_gt(struct ad9361_rf_phy *phy); +int32_t ad9361_init_gain_tables(struct ad9361_rf_phy *phy); +int32_t ad9361_setup(struct ad9361_rf_phy *phy); +int32_t ad9361_post_setup(struct ad9361_rf_phy *phy); +int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl); +int32_t ad9361_ensm_set_state(struct ad9361_rf_phy *phy, uint8_t ensm_state, + bool pinctrl); +int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy, + uint32_t rx_id, struct rf_rx_gain *rx_gain); +int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy, + uint32_t rx_id, struct rf_rx_gain *rx_gain); +int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, + uint32_t rf_rx_bw, uint32_t rf_tx_bw); +int32_t ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy, + uint32_t tx_sample_rate, + uint32_t rate_gov, + uint32_t *rx_path_clks, + uint32_t *tx_path_clks); +int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, + uint32_t *rx_path_clks, + uint32_t *tx_path_clks); +int32_t ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy, + uint32_t *rx_path_clks, + uint32_t *tx_path_clks); +uint32_t ad9361_to_clk(uint64_t freq); +uint64_t ad9361_from_clk(uint32_t freq); +int32_t ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi); +int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy, + struct rf_gain_ctrl *gain_ctrl); +int32_t ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy, + enum fir_dest dest, int32_t gain_dB, + uint32_t ntaps, short *coef); +int32_t ad9361_validate_enable_fir(struct ad9361_rf_phy *phy); +int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb, + bool tx1, bool tx2, bool immed); +int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num); +uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, + uint32_t parent_rate); +int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, + uint32_t rate, + uint32_t *prate); +int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, + uint32_t parent_rate); +uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, + uint32_t parent_rate); +int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate, + uint32_t *prate); +int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate, + uint32_t parent_rate); +uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, + uint32_t parent_rate); +int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, + uint32_t rate, + uint32_t *prate); +int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, + uint32_t parent_rate); +uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv); +int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, + uint32_t rate); +uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv); +int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate); +int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate); +int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index); +int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track, + bool rfdc_track, bool rxquad_track); +int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode); +void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode); +int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode); +void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy, + enum ad9361_bist_mode *mode); +int32_t ad9361_bist_tone(struct ad9361_rf_phy *phy, + enum ad9361_bist_mode mode, uint32_t freq_Hz, + uint32_t level_dB, uint32_t mask); +void ad9361_get_bist_tone(struct ad9361_rf_phy *phy, + enum ad9361_bist_mode *mode, uint32_t *freq_Hz, + uint32_t *level_dB, uint32_t *mask); +int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out, + uint32_t rx_inputs, uint32_t txb); +int32_t ad9361_mcs(struct ad9361_rf_phy *phy, int32_t step); +int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal, + int32_t arg); +int32_t ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx, + uint32_t profile); +int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx, + uint32_t profile); +int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx, + uint32_t profile, uint8_t *values); +int32_t ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx, + uint32_t profile, uint8_t *values); +void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state); +uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy); +void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state); +void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy); +int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, + uint32_t freq); +int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start); +int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable); +int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, + char *buf, int32_t buflen); +int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, + enum dig_tune_flags flags); +int32_t ad9361_en_dis_tx(struct ad9361_rf_phy *phy, uint32_t tx_if, + uint32_t enable); +int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if, + uint32_t enable); +int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx, + int32_t channel); +int32_t ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy); +int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy, + uint32_t coarse, uint32_t fine); +int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state); +uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw); +int32_t ad9361_get_temp(struct ad9361_rf_phy *phy); +int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy, + enum synth_pd_ctrl rx, + enum synth_pd_ctrl tx); +void ad9361_clear_state(struct ad9361_rf_phy *phy); +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.c new file mode 100644 index 00000000..cdb4e864 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.c @@ -0,0 +1,2157 @@ +/***************************************************************************//** + * @file ad9361_api.c + * @brief Implementation of AD9361 API Driver. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "ad9361.h" +#include "ad9361_api.h" +#include "../../../include/delay.h" +#include "../../../include/spi.h" +#include "../../../include/util.h" +#include "../../../../app_config.h" + +/******************************************************************************/ +/************************ Constants Definitions *******************************/ +/******************************************************************************/ + +extern struct gain_table_info ad9361_adi_gt_info[]; + +/** + * Initialize the AD9361 part. + * @param ad9361_phy The AD9361 device structure. + * @param init_param The structure that contains the AD9361 initial parameters. + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_init (struct ad9361_rf_phy **ad9361_phy, + AD9361_InitParam *init_param) +{ + struct ad9361_rf_phy *phy; + int32_t ret = 0; + int32_t rev = 0; + int32_t i = 0; + + phy = (struct ad9361_rf_phy *)zmalloc(sizeof(*phy)); + if (!phy) { + return -ENOMEM; + } + + phy->clk_refin = (struct clk *)zmalloc(sizeof(*phy->clk_refin)); + if (!phy->clk_refin) { + return -ENOMEM; + } + + phy->pdata = (struct ad9361_phy_platform_data *)zmalloc(sizeof(*phy->pdata)); + if (!phy->pdata) { + return -ENOMEM; + } + + /* Device selection */ + phy->dev_sel = init_param->dev_sel; + + /* Reference Clock */ + phy->clk_refin->rate = init_param->reference_clk_rate; + + /* Base Configuration */ + phy->pdata->fdd = init_param->frequency_division_duplex_mode_enable; + phy->pdata->fdd_independent_mode = + init_param->frequency_division_duplex_independent_mode_enable; + phy->pdata->rx2tx2 = init_param->two_rx_two_tx_mode_enable; + phy->pdata->rx1tx1_mode_use_rx_num = init_param->one_rx_one_tx_mode_use_rx_num; + phy->pdata->rx1tx1_mode_use_tx_num = init_param->one_rx_one_tx_mode_use_tx_num; + phy->pdata->tdd_use_dual_synth = init_param->tdd_use_dual_synth_mode_enable; + phy->pdata->tdd_skip_vco_cal = init_param->tdd_skip_vco_cal_enable; + phy->pdata->rx_fastlock_delay_ns = init_param->rx_fastlock_delay_ns; + phy->pdata->tx_fastlock_delay_ns = init_param->tx_fastlock_delay_ns; + phy->pdata->trx_fastlock_pinctrl_en[0] = + init_param->rx_fastlock_pincontrol_enable; + phy->pdata->trx_fastlock_pinctrl_en[1] = + init_param->tx_fastlock_pincontrol_enable; + if (phy->dev_sel == ID_AD9363A) { + phy->pdata->use_ext_rx_lo = false; + phy->pdata->use_ext_tx_lo = false; + } else { + phy->pdata->use_ext_rx_lo = init_param->external_rx_lo_enable; + phy->pdata->use_ext_tx_lo = init_param->external_tx_lo_enable; + } + phy->pdata->dc_offset_update_events = + init_param->dc_offset_tracking_update_event_mask; + phy->pdata->dc_offset_attenuation_high = + init_param->dc_offset_attenuation_high_range; + phy->pdata->dc_offset_attenuation_low = + init_param->dc_offset_attenuation_low_range; + phy->pdata->rf_dc_offset_count_high = init_param->dc_offset_count_high_range; + phy->pdata->rf_dc_offset_count_low = init_param->dc_offset_count_low_range; + phy->pdata->split_gt = init_param->split_gain_table_mode_enable; + phy->pdata->trx_synth_max_fref = + init_param->trx_synthesizer_target_fref_overwrite_hz; + phy->pdata->qec_tracking_slow_mode_en = + init_param->qec_tracking_slow_mode_enable; + + /* ENSM Control */ + phy->pdata->ensm_pin_pulse_mode = init_param->ensm_enable_pin_pulse_mode_enable; + phy->pdata->ensm_pin_ctrl = init_param->ensm_enable_txnrx_control_enable; + + /* LO Control */ + phy->pdata->rx_synth_freq = init_param->rx_synthesizer_frequency_hz; + phy->pdata->tx_synth_freq = init_param->tx_synthesizer_frequency_hz; + phy->pdata->lo_powerdown_managed_en = + init_param->tx_lo_powerdown_managed_enable; + + /* Rate & BW Control */ + for(i = 0; i < 6; i++) { + phy->pdata->rx_path_clks[i] = init_param->rx_path_clock_frequencies[i]; + } + for(i = 0; i < 6; i++) { + phy->pdata->tx_path_clks[i] = init_param->tx_path_clock_frequencies[i]; + } + phy->pdata->rf_rx_bandwidth_Hz = init_param->rf_rx_bandwidth_hz; + phy->pdata->rf_tx_bandwidth_Hz = init_param->rf_tx_bandwidth_hz; + + /* RF Port Control */ + phy->pdata->rf_rx_input_sel = init_param->rx_rf_port_input_select; + phy->pdata->rf_tx_output_sel = init_param->tx_rf_port_input_select; + + /* TX Attenuation Control */ + phy->pdata->tx_atten = init_param->tx_attenuation_mdB; + phy->pdata->update_tx_gain_via_alert = + init_param->update_tx_gain_in_alert_enable; + + /* Reference Clock Control */ + switch (phy->dev_sel) { + case ID_AD9363A: + phy->pdata->use_extclk = true; + break; + default: + phy->pdata->use_extclk = init_param->xo_disable_use_ext_refclk_enable; + } + phy->pdata->dcxo_coarse = init_param->dcxo_coarse_and_fine_tune[0]; + phy->pdata->dcxo_fine = init_param->dcxo_coarse_and_fine_tune[1]; + phy->pdata->ad9361_clkout_mode = (enum ad9361_clkout) + init_param->clk_output_mode_select; + + /* Gain Control */ + phy->pdata->gain_ctrl.rx1_mode = (enum rf_gain_ctrl_mode) + init_param->gc_rx1_mode; + phy->pdata->gain_ctrl.rx2_mode = (enum rf_gain_ctrl_mode) + init_param->gc_rx2_mode; + phy->pdata->gain_ctrl.adc_large_overload_thresh = + init_param->gc_adc_large_overload_thresh; + phy->pdata->gain_ctrl.adc_ovr_sample_size = init_param->gc_adc_ovr_sample_size; + phy->pdata->gain_ctrl.adc_small_overload_thresh = + init_param->gc_adc_small_overload_thresh; + phy->pdata->gain_ctrl.dec_pow_measuremnt_duration = + init_param->gc_dec_pow_measurement_duration; + phy->pdata->gain_ctrl.dig_gain_en = init_param->gc_dig_gain_enable; + phy->pdata->gain_ctrl.lmt_overload_high_thresh = + init_param->gc_lmt_overload_high_thresh; + phy->pdata->gain_ctrl.lmt_overload_low_thresh = + init_param->gc_lmt_overload_low_thresh; + phy->pdata->gain_ctrl.low_power_thresh = init_param->gc_low_power_thresh; + phy->pdata->gain_ctrl.max_dig_gain = init_param->gc_max_dig_gain; + phy->pdata->gain_ctrl.use_rx_fir_out_for_dec_pwr_meas = + init_param->gc_use_rx_fir_out_for_dec_pwr_meas_enable; + + /* Gain MGC Control */ + phy->pdata->gain_ctrl.mgc_dec_gain_step = init_param->mgc_dec_gain_step; + phy->pdata->gain_ctrl.mgc_inc_gain_step = init_param->mgc_inc_gain_step; + phy->pdata->gain_ctrl.mgc_rx1_ctrl_inp_en = init_param->mgc_rx1_ctrl_inp_enable; + phy->pdata->gain_ctrl.mgc_rx2_ctrl_inp_en = init_param->mgc_rx2_ctrl_inp_enable; + phy->pdata->gain_ctrl.mgc_split_table_ctrl_inp_gain_mode = + init_param->mgc_split_table_ctrl_inp_gain_mode; + + /* Gain AGC Control */ + phy->pdata->gain_ctrl.adc_large_overload_exceed_counter = + init_param->agc_adc_large_overload_exceed_counter; + phy->pdata->gain_ctrl.adc_large_overload_inc_steps = + init_param->agc_adc_large_overload_inc_steps; + phy->pdata->gain_ctrl.adc_lmt_small_overload_prevent_gain_inc = + init_param->agc_adc_lmt_small_overload_prevent_gain_inc_enable; + phy->pdata->gain_ctrl.adc_small_overload_exceed_counter = + init_param->agc_adc_small_overload_exceed_counter; + phy->pdata->gain_ctrl.dig_gain_step_size = init_param->agc_dig_gain_step_size; + phy->pdata->gain_ctrl.dig_saturation_exceed_counter = + init_param->agc_dig_saturation_exceed_counter; + phy->pdata->gain_ctrl.gain_update_interval_us = + init_param->agc_gain_update_interval_us; + phy->pdata->gain_ctrl.immed_gain_change_if_large_adc_overload = + init_param->agc_immed_gain_change_if_large_adc_overload_enable; + phy->pdata->gain_ctrl.immed_gain_change_if_large_lmt_overload = + init_param->agc_immed_gain_change_if_large_lmt_overload_enable; + phy->pdata->gain_ctrl.agc_inner_thresh_high = init_param->agc_inner_thresh_high; + phy->pdata->gain_ctrl.agc_inner_thresh_high_dec_steps = + init_param->agc_inner_thresh_high_dec_steps; + phy->pdata->gain_ctrl.agc_inner_thresh_low = init_param->agc_inner_thresh_low; + phy->pdata->gain_ctrl.agc_inner_thresh_low_inc_steps = + init_param->agc_inner_thresh_low_inc_steps; + phy->pdata->gain_ctrl.lmt_overload_large_exceed_counter = + init_param->agc_lmt_overload_large_exceed_counter; + phy->pdata->gain_ctrl.lmt_overload_large_inc_steps = + init_param->agc_lmt_overload_large_inc_steps; + phy->pdata->gain_ctrl.lmt_overload_small_exceed_counter = + init_param->agc_lmt_overload_small_exceed_counter; + phy->pdata->gain_ctrl.agc_outer_thresh_high = init_param->agc_outer_thresh_high; + phy->pdata->gain_ctrl.agc_outer_thresh_high_dec_steps = + init_param->agc_outer_thresh_high_dec_steps; + phy->pdata->gain_ctrl.agc_outer_thresh_low = init_param->agc_outer_thresh_low; + phy->pdata->gain_ctrl.agc_outer_thresh_low_inc_steps = + init_param->agc_outer_thresh_low_inc_steps; + phy->pdata->gain_ctrl.agc_attack_delay_extra_margin_us = + init_param->agc_attack_delay_extra_margin_us; + phy->pdata->gain_ctrl.sync_for_gain_counter_en = + init_param->agc_sync_for_gain_counter_enable; + + /* Fast AGC */ + phy->pdata->gain_ctrl.f_agc_dec_pow_measuremnt_duration = + init_param->fagc_dec_pow_measuremnt_duration; + phy->pdata->gain_ctrl.f_agc_state_wait_time_ns = + init_param->fagc_state_wait_time_ns; + /* Fast AGC - Low Power */ + phy->pdata->gain_ctrl.f_agc_allow_agc_gain_increase = + init_param->fagc_allow_agc_gain_increase; + phy->pdata->gain_ctrl.f_agc_lp_thresh_increment_time = + init_param->fagc_lp_thresh_increment_time; + phy->pdata->gain_ctrl.f_agc_lp_thresh_increment_steps = + init_param->fagc_lp_thresh_increment_steps; + /* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */ + phy->pdata->gain_ctrl.f_agc_lock_level_lmt_gain_increase_en = + init_param->fagc_lock_level_lmt_gain_increase_en; + phy->pdata->gain_ctrl.f_agc_lock_level_gain_increase_upper_limit = + init_param->fagc_lock_level_gain_increase_upper_limit; + /* Fast AGC - Peak Detectors and Final Settling */ + phy->pdata->gain_ctrl.f_agc_lpf_final_settling_steps = + init_param->fagc_lpf_final_settling_steps; + phy->pdata->gain_ctrl.f_agc_lmt_final_settling_steps = + init_param->fagc_lmt_final_settling_steps; + phy->pdata->gain_ctrl.f_agc_final_overrange_count = + init_param->fagc_final_overrange_count; + /* Fast AGC - Final Power Test */ + phy->pdata->gain_ctrl.f_agc_gain_increase_after_gain_lock_en = + init_param->fagc_gain_increase_after_gain_lock_en; + /* Fast AGC - Unlocking the Gain */ + phy->pdata->gain_ctrl.f_agc_gain_index_type_after_exit_rx_mode = + (enum f_agc_target_gain_index_type) + init_param->fagc_gain_index_type_after_exit_rx_mode; + phy->pdata->gain_ctrl.f_agc_use_last_lock_level_for_set_gain_en = + init_param->fagc_use_last_lock_level_for_set_gain_en; + phy->pdata->gain_ctrl.f_agc_rst_gla_stronger_sig_thresh_exceeded_en = + init_param->fagc_rst_gla_stronger_sig_thresh_exceeded_en; + phy->pdata->gain_ctrl.f_agc_optimized_gain_offset = + init_param->fagc_optimized_gain_offset; + phy->pdata->gain_ctrl.f_agc_rst_gla_stronger_sig_thresh_above_ll = + init_param->fagc_rst_gla_stronger_sig_thresh_above_ll; + phy->pdata->gain_ctrl.f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en = + init_param->fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en; + phy->pdata->gain_ctrl.f_agc_rst_gla_engergy_lost_goto_optim_gain_en = + init_param->fagc_rst_gla_engergy_lost_goto_optim_gain_en; + phy->pdata->gain_ctrl.f_agc_rst_gla_engergy_lost_sig_thresh_below_ll = + init_param->fagc_rst_gla_engergy_lost_sig_thresh_below_ll; + phy->pdata->gain_ctrl.f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt = + init_param->fagc_energy_lost_stronger_sig_gain_lock_exit_cnt; + phy->pdata->gain_ctrl.f_agc_rst_gla_large_adc_overload_en = + init_param->fagc_rst_gla_large_adc_overload_en; + phy->pdata->gain_ctrl.f_agc_rst_gla_large_lmt_overload_en = + init_param->fagc_rst_gla_large_lmt_overload_en; + phy->pdata->gain_ctrl.f_agc_rst_gla_en_agc_pulled_high_en = + init_param->fagc_rst_gla_en_agc_pulled_high_en; + phy->pdata->gain_ctrl.f_agc_rst_gla_if_en_agc_pulled_high_mode = + (enum f_agc_target_gain_index_type) + init_param->fagc_rst_gla_if_en_agc_pulled_high_mode; + phy->pdata->gain_ctrl.f_agc_power_measurement_duration_in_state5 = + init_param->fagc_power_measurement_duration_in_state5; + phy->pdata->gain_ctrl.f_agc_large_overload_inc_steps = + init_param->fagc_large_overload_inc_steps; + + /* RSSI Control */ + phy->pdata->rssi_ctrl.rssi_delay = init_param->rssi_delay; + phy->pdata->rssi_ctrl.rssi_duration = init_param->rssi_duration; + phy->pdata->rssi_ctrl.restart_mode = (enum rssi_restart_mode) + init_param->rssi_restart_mode; + phy->pdata->rssi_ctrl.rssi_unit_is_rx_samples = + init_param->rssi_unit_is_rx_samples_enable; + phy->pdata->rssi_ctrl.rssi_wait = init_param->rssi_wait; + + /* Aux ADC Control */ + phy->pdata->auxadc_ctrl.auxadc_decimation = init_param->aux_adc_decimation; + phy->pdata->auxadc_ctrl.auxadc_clock_rate = init_param->aux_adc_rate; + + /* AuxDAC Control */ + phy->pdata->auxdac_ctrl.auxdac_manual_mode_en = + init_param->aux_dac_manual_mode_enable; + phy->pdata->auxdac_ctrl.dac1_default_value = + init_param->aux_dac1_default_value_mV; + phy->pdata->auxdac_ctrl.dac1_in_rx_en = + init_param->aux_dac1_active_in_rx_enable; + phy->pdata->auxdac_ctrl.dac1_in_tx_en = + init_param->aux_dac1_active_in_tx_enable; + phy->pdata->auxdac_ctrl.dac1_in_alert_en = + init_param->aux_dac1_active_in_alert_enable; + phy->pdata->auxdac_ctrl.dac1_rx_delay_us = init_param->aux_dac1_rx_delay_us; + phy->pdata->auxdac_ctrl.dac1_tx_delay_us = init_param->aux_dac1_tx_delay_us; + phy->pdata->auxdac_ctrl.dac2_default_value = + init_param->aux_dac2_default_value_mV; + phy->pdata->auxdac_ctrl.dac2_in_rx_en = + init_param->aux_dac2_active_in_rx_enable; + phy->pdata->auxdac_ctrl.dac2_in_tx_en = + init_param->aux_dac2_active_in_tx_enable; + phy->pdata->auxdac_ctrl.dac2_in_alert_en = + init_param->aux_dac2_active_in_alert_enable; + phy->pdata->auxdac_ctrl.dac2_rx_delay_us = init_param->aux_dac2_rx_delay_us; + phy->pdata->auxdac_ctrl.dac2_tx_delay_us = init_param->aux_dac2_tx_delay_us; + + /* Temperature Sensor Control */ + phy->pdata->auxadc_ctrl.temp_sensor_decimation = + init_param->temp_sense_decimation; + phy->pdata->auxadc_ctrl.temp_time_inteval_ms = + init_param->temp_sense_measurement_interval_ms; + phy->pdata->auxadc_ctrl.offset = init_param->temp_sense_offset_signed; + phy->pdata->auxadc_ctrl.periodic_temp_measuremnt = + init_param->temp_sense_periodic_measurement_enable; + + /* Control Out Setup */ + phy->pdata->ctrl_outs_ctrl.en_mask = init_param->ctrl_outs_enable_mask; + phy->pdata->ctrl_outs_ctrl.index = init_param->ctrl_outs_index; + + /* External LNA Control */ + phy->pdata->elna_ctrl.settling_delay_ns = init_param->elna_settling_delay_ns; + phy->pdata->elna_ctrl.gain_mdB = init_param->elna_gain_mdB; + phy->pdata->elna_ctrl.bypass_loss_mdB = init_param->elna_bypass_loss_mdB; + phy->pdata->elna_ctrl.elna_1_control_en = + init_param->elna_rx1_gpo0_control_enable; + phy->pdata->elna_ctrl.elna_2_control_en = + init_param->elna_rx2_gpo1_control_enable; + phy->pdata->elna_ctrl.elna_in_gaintable_all_index_en = + init_param->elna_gaintable_all_index_enable; + + /* Digital Interface Control */ + phy->pdata->dig_interface_tune_skipmode = + (init_param->digital_interface_tune_skip_mode); + phy->pdata->dig_interface_tune_fir_disable = + (init_param->digital_interface_tune_fir_disable); + phy->pdata->port_ctrl.pp_conf[0] = (init_param->pp_tx_swap_enable << 7); + phy->pdata->port_ctrl.pp_conf[0] |= (init_param->pp_rx_swap_enable << 6); + phy->pdata->port_ctrl.pp_conf[0] |= (init_param->tx_channel_swap_enable << 5); + phy->pdata->port_ctrl.pp_conf[0] |= (init_param->rx_channel_swap_enable << 4); + phy->pdata->port_ctrl.pp_conf[0] |= (init_param->rx_frame_pulse_mode_enable << + 3); + phy->pdata->port_ctrl.pp_conf[0] |= (init_param->two_t_two_r_timing_enable << + 2); + phy->pdata->port_ctrl.pp_conf[0] |= (init_param->invert_data_bus_enable << 1); + phy->pdata->port_ctrl.pp_conf[0] |= (init_param->invert_data_clk_enable << 0); + phy->pdata->port_ctrl.pp_conf[1] = (init_param->fdd_alt_word_order_enable << 7); + phy->pdata->port_ctrl.pp_conf[1] |= (init_param->invert_rx_frame_enable << 2); + phy->pdata->port_ctrl.pp_conf[2] = (init_param->fdd_rx_rate_2tx_enable << 7); + phy->pdata->port_ctrl.pp_conf[2] |= (init_param->swap_ports_enable << 6); + phy->pdata->port_ctrl.pp_conf[2] |= (init_param->single_data_rate_enable << 5); + phy->pdata->port_ctrl.pp_conf[2] |= (init_param->lvds_mode_enable << 4); + phy->pdata->port_ctrl.pp_conf[2] |= (init_param->half_duplex_mode_enable << 3); + phy->pdata->port_ctrl.pp_conf[2] |= (init_param->single_port_mode_enable << 2); + phy->pdata->port_ctrl.pp_conf[2] |= (init_param->full_port_enable << 1); + phy->pdata->port_ctrl.pp_conf[2] |= (init_param->full_duplex_swap_bits_enable << + 0); + phy->pdata->port_ctrl.pp_conf[1] |= (init_param->delay_rx_data & 0x3); + phy->pdata->port_ctrl.rx_clk_data_delay = DATA_CLK_DELAY( + init_param->rx_data_clock_delay); + phy->pdata->port_ctrl.rx_clk_data_delay |= RX_DATA_DELAY( + init_param->rx_data_delay); + phy->pdata->port_ctrl.tx_clk_data_delay = FB_CLK_DELAY( + init_param->tx_fb_clock_delay); + phy->pdata->port_ctrl.tx_clk_data_delay |= TX_DATA_DELAY( + init_param->tx_data_delay); + phy->pdata->port_ctrl.lvds_bias_ctrl = ((init_param->lvds_bias_mV - 75) / 75) & + 0x7; + phy->pdata->port_ctrl.lvds_bias_ctrl |= + (init_param->lvds_rx_onchip_termination_enable << 5); + phy->pdata->rx1rx2_phase_inversion_en = init_param->rx1rx2_phase_inversion_en; + + /* GPO Control */ + phy->pdata->gpo_ctrl.gpo_manual_mode_en = + init_param->gpo_manual_mode_enable; + phy->pdata->gpo_ctrl.gpo_manual_mode_enable_mask = + init_param->gpo_manual_mode_enable_mask; + phy->pdata->gpo_ctrl.gpo0_inactive_state_high_en = + init_param->gpo0_inactive_state_high_enable; + phy->pdata->gpo_ctrl.gpo1_inactive_state_high_en = + init_param->gpo1_inactive_state_high_enable; + phy->pdata->gpo_ctrl.gpo2_inactive_state_high_en = + init_param->gpo2_inactive_state_high_enable; + phy->pdata->gpo_ctrl.gpo3_inactive_state_high_en = + init_param->gpo3_inactive_state_high_enable; + + phy->pdata->gpo_ctrl.gpo0_slave_rx_en = init_param->gpo0_slave_rx_enable; + phy->pdata->gpo_ctrl.gpo0_slave_tx_en = init_param->gpo0_slave_tx_enable; + phy->pdata->gpo_ctrl.gpo1_slave_rx_en = init_param->gpo1_slave_rx_enable; + phy->pdata->gpo_ctrl.gpo1_slave_tx_en = init_param->gpo1_slave_tx_enable; + phy->pdata->gpo_ctrl.gpo2_slave_rx_en = init_param->gpo2_slave_rx_enable; + phy->pdata->gpo_ctrl.gpo2_slave_tx_en = init_param->gpo2_slave_tx_enable; + phy->pdata->gpo_ctrl.gpo3_slave_rx_en = init_param->gpo3_slave_rx_enable; + phy->pdata->gpo_ctrl.gpo3_slave_tx_en = init_param->gpo3_slave_tx_enable; + + phy->pdata->gpo_ctrl.gpo0_rx_delay_us = init_param->gpo0_rx_delay_us; + phy->pdata->gpo_ctrl.gpo0_tx_delay_us = init_param->gpo0_tx_delay_us; + phy->pdata->gpo_ctrl.gpo1_rx_delay_us = init_param->gpo1_rx_delay_us; + phy->pdata->gpo_ctrl.gpo1_tx_delay_us = init_param->gpo1_tx_delay_us; + phy->pdata->gpo_ctrl.gpo2_rx_delay_us = init_param->gpo2_rx_delay_us; + phy->pdata->gpo_ctrl.gpo2_tx_delay_us = init_param->gpo2_tx_delay_us; + phy->pdata->gpo_ctrl.gpo3_rx_delay_us = init_param->gpo3_rx_delay_us; + phy->pdata->gpo_ctrl.gpo3_tx_delay_us = init_param->gpo3_tx_delay_us; + + /* Tx Monitor Control */ + phy->pdata->txmon_ctrl.low_high_gain_threshold_mdB = + init_param->low_high_gain_threshold_mdB; + phy->pdata->txmon_ctrl.low_gain_dB = init_param->low_gain_dB; + phy->pdata->txmon_ctrl.high_gain_dB = init_param->high_gain_dB; + phy->pdata->txmon_ctrl.tx_mon_track_en = init_param->tx_mon_track_en; + phy->pdata->txmon_ctrl.one_shot_mode_en = init_param->one_shot_mode_en; + phy->pdata->txmon_ctrl.tx_mon_delay = init_param->tx_mon_delay; + phy->pdata->txmon_ctrl.tx_mon_duration = init_param->tx_mon_duration; + phy->pdata->txmon_ctrl.tx1_mon_front_end_gain = + init_param->tx1_mon_front_end_gain; + phy->pdata->txmon_ctrl.tx2_mon_front_end_gain = + init_param->tx2_mon_front_end_gain; + phy->pdata->txmon_ctrl.tx1_mon_lo_cm = init_param->tx1_mon_lo_cm; + phy->pdata->txmon_ctrl.tx2_mon_lo_cm = init_param->tx2_mon_lo_cm; + + phy->pdata->debug_mode = true; + + gpio_get(&phy->gpio_desc_resetb, &init_param->gpio_resetb); + /* Optional: next three GPIOs are used for MCS synchronization */ + gpio_get_optional(&phy->gpio_desc_sync, &init_param->gpio_sync); + gpio_get_optional(&phy->gpio_desc_cal_sw1, &init_param->gpio_cal_sw1); + gpio_get_optional(&phy->gpio_desc_cal_sw2, &init_param->gpio_cal_sw2); + + gpio_direction_output(phy->gpio_desc_resetb, 0); + + spi_init(&phy->spi, &init_param->spi_param); + + phy->pdata->port_ctrl.digital_io_ctrl = 0; + phy->pdata->port_ctrl.lvds_invert[0] = init_param->lvds_invert1_control; + phy->pdata->port_ctrl.lvds_invert[1] = init_param->lvds_invert2_control; + + if (AD9364_DEVICE) { + phy->pdata->rx2tx2 = false; + phy->pdata->rx1tx1_mode_use_rx_num = 1; + phy->pdata->rx1tx1_mode_use_tx_num = 1; + } + + phy->rx_eq_2tx = false; + + phy->current_table = -1; + phy->bypass_tx_fir = true; + phy->bypass_rx_fir = true; + phy->rate_governor = 1; + phy->rfdc_track_en = true; + phy->bbdc_track_en = true; + phy->quad_track_en = true; + + phy->gt_info = ad9361_adi_gt_info; + + phy->bist_loopback_mode = 0; + phy->bist_config = 0; + phy->bist_prbs_mode = BIST_DISABLE; + phy->bist_tone_mode = BIST_DISABLE; + phy->bist_tone_freq_Hz = 0; + phy->bist_tone_level_dB = 0; + phy->bist_tone_mask = 0; + + ad9361_reset(phy); + + ret = ad9361_spi_read(phy->spi, REG_PRODUCT_ID); + if ((ret & PRODUCT_ID_MASK) != PRODUCT_ID_9361) { + printf("%s : Unsupported PRODUCT_ID 0x%X", __func__, (unsigned int)ret); + ret = -ENODEV; + goto out; + } + rev = ret & REV_MASK; + + phy->ad9361_rfpll_ext_recalc_rate = init_param->ad9361_rfpll_ext_recalc_rate; + phy->ad9361_rfpll_ext_round_rate = init_param->ad9361_rfpll_ext_round_rate; + phy->ad9361_rfpll_ext_set_rate = init_param->ad9361_rfpll_ext_set_rate; + + ret = ad9361_register_clocks(phy); + if (ret < 0) + goto out; + + ret = ad9361_setup(phy); + if (ret < 0) + goto out_clk; + + printf("%s : AD936x Rev %d successfully initialized\n", __func__, (int)rev); + + *ad9361_phy = phy; + + return 0; + +out_clk: + ad9361_unregister_clocks(phy); +out: + free(phy->clk_refin); + free(phy->pdata); + free(phy); + printf("%s : AD936x initialization error\n", __func__); + + return -ENODEV; +} + +/** + * Free the allocated resources. + * @param phy The AD9361 current state structure. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_remove(struct ad9361_rf_phy *phy) +{ + ad9361_unregister_clocks(phy); + spi_remove(phy->spi); + gpio_remove(phy->gpio_desc_resetb); + gpio_remove(phy->gpio_desc_sync); + gpio_remove(phy->gpio_desc_cal_sw1); + gpio_remove(phy->gpio_desc_cal_sw2); + free(phy->clk_refin); + free(phy->pdata); + free(phy); + + return 0; +} + +/** + * Set the Enable State Machine (ENSM) mode. + * @param phy The AD9361 current state structure. + * @param mode The ENSM mode. + * Accepted values: + * ENSM_MODE_TX + * ENSM_MODE_RX + * ENSM_MODE_ALERT + * ENSM_MODE_FDD + * ENSM_MODE_WAIT + * ENSM_MODE_SLEEP + * ENSM_MODE_PINCTRL + * ENSM_MODE_PINCTRL_FDD_INDEP + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_en_state_machine_mode (struct ad9361_rf_phy *phy, + uint32_t mode) +{ + int32_t ret; + uint8_t ensm_state; + bool pinctrl = false; + + phy->pdata->fdd_independent_mode = false; + + switch (mode) { + case ENSM_MODE_TX: + ensm_state = ENSM_STATE_TX; + break; + case ENSM_MODE_RX: + ensm_state = ENSM_STATE_RX; + break; + case ENSM_MODE_ALERT: + ensm_state = ENSM_STATE_ALERT; + break; + case ENSM_MODE_FDD: + ensm_state = ENSM_STATE_FDD; + break; + case ENSM_MODE_WAIT: + ensm_state = ENSM_STATE_SLEEP_WAIT; + break; + case ENSM_MODE_SLEEP: + ensm_state = ENSM_STATE_SLEEP; + break; + case ENSM_MODE_PINCTRL: + ensm_state = ENSM_STATE_SLEEP_WAIT; + pinctrl = true; + break; + case ENSM_MODE_PINCTRL_FDD_INDEP: + ensm_state = ENSM_STATE_FDD; + phy->pdata->fdd_independent_mode = true; + break; + default: + return -EINVAL; + } + + ad9361_set_ensm_mode(phy, phy->pdata->fdd, pinctrl); + ret = ad9361_ensm_set_state(phy, ensm_state, pinctrl); + + return ret; +} + +/** + * Get the Enable State Machine (ENSM) mode. + * @param phy The AD9361 current state structure. + * @param mode A variable to store the selected ENSM mode. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_en_state_machine_mode (struct ad9361_rf_phy *phy, + uint32_t *mode) +{ + uint8_t ensm_state; + bool pinctrl = false; + int32_t ret; + + ensm_state = ad9361_spi_read(phy->spi, REG_STATE); + ensm_state &= ENSM_STATE(~0); + ret = ad9361_spi_read(phy->spi, REG_ENSM_CONFIG_1); + if ((ret & ENABLE_ENSM_PIN_CTRL) == ENABLE_ENSM_PIN_CTRL) + pinctrl = true; + + switch (ensm_state) { + case ENSM_STATE_TX: + *mode = ENSM_MODE_TX; + break; + case ENSM_STATE_RX: + *mode = ENSM_MODE_RX; + break; + case ENSM_STATE_ALERT: + *mode = ENSM_MODE_ALERT; + break; + case ENSM_STATE_FDD: + if (phy->pdata->fdd_independent_mode) + *mode = ENSM_MODE_PINCTRL_FDD_INDEP; + else + *mode = ENSM_MODE_FDD; + break; + case ENSM_STATE_SLEEP_WAIT: + if (pinctrl) + *mode = ENSM_MODE_PINCTRL; + else + *mode = ENSM_MODE_WAIT; + break; + case ENSM_STATE_SLEEP: + *mode = ENSM_MODE_SLEEP; + break; + default: + return -EINVAL; + } + + return 0; +} + +/** + * Set the receive RF gain for the selected channel. + * @param phy The AD9361 current state structure. + * @param ch The desired channel number (RX1, RX2). + * Accepted values in 2x2 mode: + * RX1 (0) + * RX2 (1) + * Accepted values in 1x1 mode: + * RX1 (0) + * @param gain_db The RF gain (dB). + * Example: + * 10 (10 dB) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_rx_rf_gain (struct ad9361_rf_phy *phy, + uint8_t ch, int32_t gain_db) +{ + struct rf_rx_gain rx_gain = {0, 0, 0, 0, 0, 0, 0, 0, 0}; + int32_t ret = 0; + + rx_gain.gain_db = gain_db; + ret = ad9361_set_rx_gain(phy, + ad9361_1rx1tx_channel_map(phy, false, + ch + 1), &rx_gain); + + return ret; +} + +/** + * Get current receive RF gain for the selected channel. + * @param phy The AD9361 current state structure. + * @param ch The desired channel number (RX1, RX2). + * Accepted values in 2x2 mode: + * RX1 (0) + * RX2 (1) + * Accepted values in 1x1 mode: + * RX1 (0) + * @param gain_db A variable to store the RF gain (dB). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_rf_gain (struct ad9361_rf_phy *phy, + uint8_t ch, int32_t *gain_db) +{ + struct rf_rx_gain rx_gain = {0, 0, 0, 0, 0, 0, 0, 0, 0}; + int32_t ret = 0; + + ret = ad9361_get_rx_gain(phy, ad9361_1rx1tx_channel_map(phy, + false, ch + 1), &rx_gain); + + *gain_db = rx_gain.gain_db; + + return ret; +} + +/** + * Set the RX RF bandwidth. + * @param phy The AD9361 current state structure. + * @param bandwidth_hz The desired bandwidth (Hz). + * Example: + * 18000000 (18 MHz) + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_rx_rf_bandwidth (struct ad9361_rf_phy *phy, + uint32_t bandwidth_hz) +{ + int32_t ret = 0; + + bandwidth_hz = ad9361_validate_rf_bw(phy, bandwidth_hz); + + if (phy->current_rx_bw_Hz != bandwidth_hz) + ret = ad9361_update_rf_bandwidth(phy, bandwidth_hz, + phy->current_tx_bw_Hz); + else + ret = 0; + + return ret; +} + +/** + * Get the RX RF bandwidth. + * @param phy The AD9361 current state structure. + * @param bandwidth_hz A variable to store the bandwidth value (Hz). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_rf_bandwidth (struct ad9361_rf_phy *phy, + uint32_t *bandwidth_hz) +{ + *bandwidth_hz = phy->current_rx_bw_Hz; + + return 0; +} + +/** + * Set the RX sampling frequency. + * @param phy The AD9361 current state structure. + * @param sampling_freq_hz The desired frequency (Hz). + * Example: + * 30720000 (30.72 MHz) + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_rx_sampling_freq (struct ad9361_rf_phy *phy, + uint32_t sampling_freq_hz) +{ + int32_t ret; + uint32_t rx[6], tx[6]; + + ret = ad9361_calculate_rf_clock_chain(phy, sampling_freq_hz, + phy->rate_governor, rx, tx); + if (ret < 0) + return ret; + + ad9361_set_trx_clock_chain(phy, rx, tx); + + ret = ad9361_update_rf_bandwidth(phy, phy->current_rx_bw_Hz, + phy->current_tx_bw_Hz); + + return ret; +} + +/** + * Get current RX sampling frequency. + * @param phy The AD9361 current state structure. + * @param sampling_freq_hz A variable to store the frequency value (Hz). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_sampling_freq (struct ad9361_rf_phy *phy, + uint32_t *sampling_freq_hz) +{ + *sampling_freq_hz = (uint32_t)clk_get_rate(phy, + phy->ref_clk_scale[RX_SAMPL_CLK]); + + return 0; +} + +/** + * Set the RX LO frequency. + * @param phy The AD9361 current state structure. + * @param lo_freq_hz The desired frequency (Hz). + * Example: + * 2400000000 (2.4 GHz) + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_rx_lo_freq (struct ad9361_rf_phy *phy, + uint64_t lo_freq_hz) +{ + int32_t ret; + + ret = clk_set_rate(phy, phy->ref_clk_scale[RX_RFPLL], + ad9361_to_clk(lo_freq_hz)); + + return ret; +} + +/** + * Get current RX LO frequency. + * @param phy The AD9361 current state structure. + * @param lo_freq_hz A variable to store the frequency value (Hz). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_lo_freq (struct ad9361_rf_phy *phy, + uint64_t *lo_freq_hz) +{ + *lo_freq_hz = ad9361_from_clk(clk_get_rate(phy, + phy->ref_clk_scale[RX_RFPLL])); + + return 0; +} + +/** + * Switch between internal and external LO. + * @param phy The AD9361 state structure. + * @param int_ext The selected lo (INT_LO, EXT_LO). + * Accepted values: + * INT_LO + * EXT_LO + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_rx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext) +{ + if ((phy->dev_sel == ID_AD9363A) && (int_ext == EXT_LO)) { + printf("%s : EXT_LO is not supported by AD9363!\n", __func__); + return -1; + } + + phy->pdata->use_ext_rx_lo = int_ext; + + return ad9361_clk_mux_set_parent(phy->ref_clk_scale[RX_RFPLL], int_ext); +} + +/** + * Get the RSSI for the selected channel. + * @param phy The AD9361 current state structure. + * @param ch The desired channel (RX1, RX2). + * Accepted values in 2x2 mode: + * RX1 (0) + * RX2 (1) + * Accepted values in 1x1 mode: + * RX1 (0) + * @param rssi A variable to store the RSSI. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_rssi (struct ad9361_rf_phy *phy, + uint8_t ch, struct rf_rssi *rssi) +{ + int32_t ret; + + rssi->ant = ad9361_1rx1tx_channel_map(phy, false, ch + 1); + rssi->duration = 1; + ret = ad9361_read_rssi(phy, rssi); + + return ret; +} + +/** + * Set the gain control mode for the selected channel. + * @param phy The AD9361 current state structure. + * @param ch The desired channel (RX1, RX2). + * Accepted values in 2x2 mode: + * RX1 (0) + * RX2 (1) + * Accepted values in 1x1 mode: + * RX1 (0) + * @param gc_mode The gain control mode (manual, fast_attack, slow_attack, + * hybrid). + * Accepted values: + * RF_GAIN_MGC (manual) + * RF_GAIN_FASTATTACK_AGC (fast_attack) + * RF_GAIN_SLOWATTACK_AGC (slow_attack) + * RF_GAIN_HYBRID_AGC (hybrid) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_rx_gain_control_mode (struct ad9361_rf_phy *phy, + uint8_t ch, uint8_t gc_mode) +{ + struct rf_gain_ctrl gc = {0, 0}; + + gc.ant = ad9361_1rx1tx_channel_map(phy, false, ch + 1); + gc.mode = phy->agc_mode[ch] = gc_mode; + + ad9361_set_gain_ctrl_mode(phy, &gc); + + return 0; +} + +/** + * Get the gain control mode for the selected channel. + * @param phy The AD9361 current state structure. + * @param ch The desired channel (RX1, RX2). + * Accepted values: + * RX1 (0) + * RX2 (1) + * @param gc_mode A variable to store the gain control mode. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_gain_control_mode (struct ad9361_rf_phy *phy, + uint8_t ch, uint8_t *gc_mode) +{ + *gc_mode = phy->agc_mode[ch]; + + return 0; +} + +/** + * Set the RX FIR filter configuration. + * @param phy The AD9361 current state structure. + * @param fir_cfg FIR filter configuration. + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_rx_fir_config (struct ad9361_rf_phy *phy, + AD9361_RXFIRConfig fir_cfg) +{ + int32_t ret; + + phy->rx_fir_dec = fir_cfg.rx_dec; + ret = ad9361_load_fir_filter_coef(phy, (enum fir_dest)(fir_cfg.rx | FIR_IS_RX), + fir_cfg.rx_gain, fir_cfg.rx_coef_size, fir_cfg.rx_coef); + + return ret; +} + +/** + * Get the RX FIR filter configuration. + * @param phy The AD9361 current state structure. + * @param rx_ch The selected RX channel (RX1, RX2). + * Accepted values: + * RX1 (0) + * RX2 (1) + * @param fir_cfg FIR filter configuration output file. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_fir_config(struct ad9361_rf_phy *phy, uint8_t rx_ch, + AD9361_RXFIRConfig *fir_cfg) +{ + int32_t ret; + uint32_t fir_conf; + uint8_t index; + + rx_ch += 1; + + ret = ad9361_spi_read(phy->spi, REG_RX_FILTER_CONFIG); + if(ret < 0) + return ret; + fir_conf = ret; + + fir_cfg->rx_coef_size = (((fir_conf & FIR_NUM_TAPS(7)) >> 5) + 1) * 16; + + ret = ad9361_spi_read(phy->spi, REG_RX_FILTER_GAIN); + if(ret < 0) + return ret; + fir_cfg->rx_gain = -6 * (ret & FILTER_GAIN(3)) + 6; + fir_cfg->rx = rx_ch; + + fir_conf &= ~FIR_SELECT(3); + fir_conf |= FIR_SELECT(rx_ch) | FIR_START_CLK; + ad9361_spi_write(phy->spi, REG_RX_FILTER_CONFIG, fir_conf); + + for(index = 0; index < 128; index++) { + ad9361_spi_write(phy->spi, REG_RX_FILTER_COEF_ADDR, index); + ret = ad9361_spi_read(phy->spi, REG_RX_FILTER_COEF_READ_DATA_1); + if(ret < 0) + return ret; + fir_cfg->rx_coef[index] = ret; + ret = ad9361_spi_read(phy->spi, REG_RX_FILTER_COEF_READ_DATA_2); + if(ret < 0) + return ret; + fir_cfg->rx_coef[index] |= (ret << 8); + } + + fir_conf &= ~FIR_START_CLK; + ad9361_spi_write(phy->spi, REG_RX_FILTER_CONFIG, fir_conf); + + fir_cfg->rx_dec = phy->rx_fir_dec; + + return 0; +} + +/** + * Enable/disable the RX FIR filter. + * @param phy The AD9361 current state structure. + * @param en_dis The option (ENABLE, DISABLE). + * Accepted values: + * ENABLE (1) + * DISABLE (0) + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_rx_fir_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis) +{ + int32_t ret = 0; + + if(phy->bypass_rx_fir == !en_dis) + return ret; + + phy->bypass_rx_fir = !en_dis; + ret = ad9361_validate_enable_fir(phy); + if (ret < 0) { + phy->bypass_rx_fir = true; + } + + return ret; +} + +/** + * Get the status of the RX FIR filter. + * @param phy The AD9361 current state structure. + * @param en_dis The enable/disable status buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_fir_en_dis (struct ad9361_rf_phy *phy, + uint8_t *en_dis) +{ + *en_dis = !phy->bypass_rx_fir; + + return 0; +} + +/** + * Enable/disable the RX RFDC Tracking. + * @param phy The AD9361 current state structure. + * @param en_dis The option (ENABLE, DISABLE). + * Accepted values: + * ENABLE (1) + * DISABLE (0) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_rx_rfdc_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis) +{ + int32_t ret = 0; + + if(phy->rfdc_track_en == en_dis) + return ret; + + phy->rfdc_track_en = en_dis; + ret = ad9361_tracking_control(phy, phy->bbdc_track_en, + phy->rfdc_track_en, phy->quad_track_en); + + return ret; +} + +/** + * Get the status of the RX RFDC Tracking. + * @param phy The AD9361 current state structure. + * @param en_dis The enable/disable status buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_rfdc_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t *en_dis) +{ + *en_dis = phy->rfdc_track_en; + + return 0; +} + +/** + * Enable/disable the RX BasebandDC Tracking. + * @param phy The AD9361 current state structure. + * @param en_dis The option (ENABLE, DISABLE). + * Accepted values: + * ENABLE (1) + * DISABLE (0) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_rx_bbdc_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis) +{ + int32_t ret = 0; + + if(phy->bbdc_track_en == en_dis) + return ret; + + phy->bbdc_track_en = en_dis; + ret = ad9361_tracking_control(phy, phy->bbdc_track_en, + phy->rfdc_track_en, phy->quad_track_en); + + return ret; +} + +/** + * Get the status of the RX BasebandDC Tracking. + * @param phy The AD9361 current state structure. + * @param en_dis The enable/disable status buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_bbdc_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t *en_dis) +{ + *en_dis = phy->bbdc_track_en; + + return 0; +} + +/** + * Enable/disable the RX Quadrature Tracking. + * @param phy The AD9361 current state structure. + * @param en_dis The option (ENABLE, DISABLE). + * Accepted values: + * ENABLE (1) + * DISABLE (0) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_rx_quad_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis) +{ + int32_t ret = 0; + + if(phy->quad_track_en == en_dis) + return ret; + + phy->quad_track_en = en_dis; + ret = ad9361_tracking_control(phy, phy->bbdc_track_en, + phy->rfdc_track_en, phy->quad_track_en); + + return ret; +} + +/** + * Get the status of the RX Quadrature Tracking. + * @param phy The AD9361 current state structure. + * @param en_dis The enable/disable status buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_quad_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t *en_dis) +{ + *en_dis = phy->quad_track_en; + + return 0; +} + +/** + * Set the RX RF input port. + * @param phy The AD9361 current state structure. + * @param mode The RF port. + * Accepted values: + * A_BALANCED (0 - (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced) + * B_BALANCED (1 - (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced) + * C_BALANCED (2 - (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced) + * A_N (3 - RX1A_N and RX2A_N enabled; unbalanced) + * A_P (4 - RX1A_P and RX2A_P enabled; unbalanced) + * B_N (5 - RX1B_N and RX2B_N enabled; unbalanced) + * B_P (6 - RX1B_P and RX2B_P enabled; unbalanced) + * C_N (7 - RX1C_N and RX2C_N enabled; unbalanced) + * C_P (8 - RX1C_P and RX2C_P enabled; unbalanced) + * TX_MON1 (9 - TX_MONITOR1) + * TX_MON2 (10 - TX_MONITOR2) + * TX_MON1_2 (11 - TX_MONITOR1 & TX_MONITOR2) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_rx_rf_port_input (struct ad9361_rf_phy *phy, + uint32_t mode) +{ + int32_t ret; + + phy->pdata->rf_rx_input_sel = mode; + + ret = ad9361_rf_port_setup(phy, false, + phy->pdata->rf_rx_input_sel, + phy->pdata->rf_tx_output_sel); + + return ret; +} + +/** + * Get the selected RX RF input port. + * @param phy The AD9361 current state structure. + * @param mode The RF port. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_rf_port_input (struct ad9361_rf_phy *phy, + uint32_t *mode) +{ + *mode = phy->pdata->rf_rx_input_sel; + + return 0; +} + +/** + * Store RX fastlock profile. + * To create a profile tune the synthesizer (ad9361_set_rx_lo_freq()) and then + * call this function specifying the target profile number. + * @param phy The AD9361 state structure. + * @param profile The profile number (0 - 7). + * Accepted values: + * 0 - 7 + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_rx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile) +{ + return ad9361_fastlock_store(phy, 0, profile); +} + +/** + * Recall specified RX fastlock profile. + * When in fastlock pin select mode (init_param->rx_fastlock_pincontrol_enable), + * the function needs to be called before then the pin-control can be used. + * @param phy The AD9361 state structure. + * @param profile The profile number (0 - 7). + * Accepted values: + * 0 - 7 + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_rx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile) +{ + return ad9361_fastlock_recall(phy, 0, profile); +} + +/** + * Load RX fastlock profile. A previously saved profile can be loaded in any + * of the 8 available slots. + * @param phy The AD9361 state structure. + * @param profile The profile number (0 - 7). + * Accepted values: + * 0 - 7 + * @param values Fastlock profile program data. + * Example: + * val0,val1,val2,…,val15 + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_rx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, + uint8_t *values) +{ + return ad9361_fastlock_load(phy, 0, profile, values); +} + +/** + * Save RX fastlock profile. In order to use more than 8 Profiles, an existing + * profile can be read back and stored by the user application. + * @param phy The AD9361 state structure. + * @param profile The profile number (0 - 7). + * Accepted values: + * 0 - 7 + * @param values Fastlock profile program data. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_rx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, + uint8_t *values) +{ + return ad9361_fastlock_save(phy, 0, profile, values); +} + +/** + * Power down the RX Local Oscillator. + * @param phy The AD9361 state structure. + * @param option The option (ON, OFF). + * Accepted values: + * ON (0) + * OFF (1) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_rx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option) +{ + return ad9361_synth_lo_powerdown(phy, option ? LO_OFF : LO_ON, LO_DONTCARE); +} + +/** + * Get the RX Local Oscillator power status. + * @param phy The AD9361 state structure. + * @param option Store the option (ON, OFF). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_rx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option) +{ + *option = !(phy->cached_synth_pd[1] & RX_LO_POWER_DOWN) ? OFF : ON; + + return 0; +} + +/** + * Set the transmit attenuation for the selected channel. + * @param phy The AD9361 current state structure. + * @param ch The desired channel number (TX1, TX2). + * Accepted values in 2x2 mode: + * TX1 (0) + * TX2 (1) + * Accepted values in 1x1 mode: + * TX1 (0) + * @param attenuation_mdb The attenuation (mdB). + * Example: + * 10000 (10 dB) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_tx_attenuation (struct ad9361_rf_phy *phy, + uint8_t ch, uint32_t attenuation_mdb) +{ + int32_t ret; + int32_t channel; + + channel = ad9361_1rx1tx_channel_map(phy, true, ch); + ret = ad9361_set_tx_atten(phy, attenuation_mdb, + channel == 0, channel == 1, + !phy->pdata->update_tx_gain_via_alert); + + return ret; +} + +/** + * Get current transmit attenuation for the selected channel. + * @param phy The AD9361 current state structure. + * @param ch The desired channel number (TX1, TX2). + * Accepted values in 2x2 mode: + * TX1 (0) + * TX2 (1) + * Accepted values in 1x1 mode: + * TX1 (0) + * @param attenuation_mdb A variable to store the attenuation value (mdB). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_tx_attenuation (struct ad9361_rf_phy *phy, + uint8_t ch, uint32_t *attenuation_mdb) +{ + int32_t ret; + + ret = ad9361_get_tx_atten(phy, + ad9361_1rx1tx_channel_map(phy, true, + ch + 1)); + + if(ret < 0) + return ret; + *attenuation_mdb = ret; + + return 0; +} + +/** + * Set the TX RF bandwidth. + * @param phy The AD9361 current state structure. + * @param bandwidth_hz The desired bandwidth (Hz). + * Example: + * 18000000 (18 MHz) + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_tx_rf_bandwidth (struct ad9361_rf_phy *phy, + uint32_t bandwidth_hz) +{ + int32_t ret = 0; + + bandwidth_hz = ad9361_validate_rf_bw(phy, bandwidth_hz); + + if (phy->current_tx_bw_Hz != bandwidth_hz) + ret = ad9361_update_rf_bandwidth(phy, + phy->current_rx_bw_Hz, bandwidth_hz); + else + ret = 0; + + return ret; +} + +/** + * Get the TX RF bandwidth. + * @param phy The AD9361 current state structure. + * @param bandwidth_hz A variable to store the bandwidth value (Hz). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_tx_rf_bandwidth (struct ad9361_rf_phy *phy, + uint32_t *bandwidth_hz) +{ + *bandwidth_hz = phy->current_tx_bw_Hz; + + return 0; +} + +/** + * Set the TX sampling frequency. + * @param phy The AD9361 current state structure. + * @param sampling_freq_hz The desired frequency (Hz). + * Example: + * 30720000 (30.72 MHz) + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_tx_sampling_freq (struct ad9361_rf_phy *phy, + uint32_t sampling_freq_hz) +{ + int32_t ret; + uint32_t rx[6], tx[6]; + + ret = ad9361_calculate_rf_clock_chain(phy, sampling_freq_hz, + phy->rate_governor, rx, tx); + if (ret < 0) + return ret; + + ad9361_set_trx_clock_chain(phy, rx, tx); + + ret = ad9361_update_rf_bandwidth(phy, phy->current_rx_bw_Hz, + phy->current_tx_bw_Hz); + + return ret; +} + +/** + * Get current TX sampling frequency. + * @param phy The AD9361 current state structure. + * @param sampling_freq_hz A variable to store the frequency value (Hz). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_tx_sampling_freq (struct ad9361_rf_phy *phy, + uint32_t *sampling_freq_hz) +{ + *sampling_freq_hz = (uint32_t)clk_get_rate(phy, + phy->ref_clk_scale[TX_SAMPL_CLK]); + + return 0; +} + +/** + * Set the TX LO frequency. + * @param phy The AD9361 current state structure. + * @param lo_freq_hz The desired frequency (Hz). + * Example: + * 2400000000 (2.4 GHz) + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_tx_lo_freq (struct ad9361_rf_phy *phy, + uint64_t lo_freq_hz) +{ + int32_t ret; + + ret = clk_set_rate(phy, phy->ref_clk_scale[TX_RFPLL], + ad9361_to_clk(lo_freq_hz)); + + return ret; +} + +/** + * Get current TX LO frequency. + * @param phy The AD9361 current state structure. + * @param lo_freq_hz A variable to store the frequency value (Hz). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_tx_lo_freq (struct ad9361_rf_phy *phy, + uint64_t *lo_freq_hz) +{ + *lo_freq_hz = ad9361_from_clk(clk_get_rate(phy, + phy->ref_clk_scale[TX_RFPLL])); + + return 0; +} + +/** + * Switch between internal and external LO. + * @param phy The AD9361 state structure. + * @param int_ext The selected lo (INT_LO, EXT_LO). + * Accepted values: + * INT_LO + * EXT_LO + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_tx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext) +{ + if ((phy->dev_sel == ID_AD9363A) && (int_ext == EXT_LO)) { + printf("%s : EXT_LO is not supported by AD9363!\n", __func__); + return -1; + } + + phy->pdata->use_ext_tx_lo = int_ext; + + return ad9361_clk_mux_set_parent(phy->ref_clk_scale[TX_RFPLL], int_ext); +} + +/** + * Set the TX FIR filter configuration. + * @param phy The AD9361 current state structure. + * @param fir_cfg FIR filter configuration. + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_tx_fir_config (struct ad9361_rf_phy *phy, + AD9361_TXFIRConfig fir_cfg) +{ + int32_t ret; + + phy->tx_fir_int = fir_cfg.tx_int; + ret = ad9361_load_fir_filter_coef(phy, (enum fir_dest)fir_cfg.tx, + fir_cfg.tx_gain, fir_cfg.tx_coef_size, fir_cfg.tx_coef); + + return ret; +} + +/** + * Get the TX FIR filter configuration. + * @param phy The AD9361 current state structure. + * @param tx_ch The selected TX channel (TX1, TX2). + * Accepted values: + * TX1 (0) + * TX2 (1) + * @param fir_cfg FIR filter configuration output file. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_tx_fir_config(struct ad9361_rf_phy *phy, uint8_t tx_ch, + AD9361_TXFIRConfig *fir_cfg) +{ + int32_t ret; + uint32_t fir_conf; + uint8_t index; + + tx_ch += 1; + + ret = ad9361_spi_read(phy->spi, REG_TX_FILTER_CONF); + if(ret < 0) + return ret; + fir_conf = ret; + fir_cfg->tx_coef_size = (((fir_conf & FIR_NUM_TAPS(7)) >> 5) + 1) * 16; + fir_cfg->tx_gain = -6 * (fir_conf & TX_FIR_GAIN_6DB); + fir_cfg->tx = tx_ch; + + fir_conf &= ~FIR_SELECT(3); + fir_conf |= FIR_SELECT(tx_ch) | FIR_START_CLK; + ad9361_spi_write(phy->spi, REG_TX_FILTER_CONF, fir_conf); + + for(index = 0; index < 128; index++) { + ad9361_spi_write(phy->spi, REG_TX_FILTER_COEF_ADDR, index); + ret = ad9361_spi_read(phy->spi, REG_TX_FILTER_COEF_READ_DATA_1); + if(ret < 0) + return ret; + fir_cfg->tx_coef[index] = ret; + ret = ad9361_spi_read(phy->spi, REG_TX_FILTER_COEF_READ_DATA_2); + if(ret < 0) + return ret; + fir_cfg->tx_coef[index] |= (ret << 8); + } + + fir_conf &= ~FIR_START_CLK; + ad9361_spi_write(phy->spi, REG_TX_FILTER_CONF, fir_conf); + + fir_cfg->tx_int = phy->tx_fir_int; + + return 0; +} + +/** + * Enable/disable the TX FIR filter. + * @param phy The AD9361 current state structure. + * @param en_dis The option (ENABLE, DISABLE). + * Accepted values: + * ENABLE (1) + * DISABLE (0) + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_tx_fir_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis) +{ + int32_t ret = 0; + + if(phy->bypass_tx_fir == !en_dis) + return ret; + + phy->bypass_tx_fir = !en_dis; + ret = ad9361_validate_enable_fir(phy); + if (ret < 0) { + phy->bypass_tx_fir = true; + } + + return ret; +} + +/** + * Get the status of the TX FIR filter. + * @param phy The AD9361 current state structure. + * @param en_dis The enable/disable status buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_tx_fir_en_dis (struct ad9361_rf_phy *phy, + uint8_t *en_dis) +{ + *en_dis = !phy->bypass_tx_fir; + + return 0; +} + +/** + * Get the TX RSSI for the selected channel (TX_MON should be enabled). + * @param phy The AD9361 current state structure. + * @param ch The desired channel (TX1, TX2). + * Accepted values: + * TX1 (0) + * TX2 (1) + * @param rssi_db_x_1000 A variable to store the RSSI. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_tx_rssi (struct ad9361_rf_phy *phy, + uint8_t ch, + uint32_t *rssi_db_x_1000) +{ + uint8_t reg_val_buf[3]; + uint32_t val; + int32_t ret; + + ret = ad9361_spi_readm(phy->spi, REG_TX_RSSI_LSB, + reg_val_buf, ARRAY_SIZE(reg_val_buf)); + if (ret < 0) { + return ret; + } + + switch (ch) { + case 0: + val = (reg_val_buf[2] << 1) | (reg_val_buf[0] & TX_RSSI_1); + break; + case 1: + val = (reg_val_buf[1] << 1) | ((reg_val_buf[0] & TX_RSSI_2) >> 1); + break; + default: + return -EINVAL; + } + + val *= RSSI_RESOLUTION; + + *rssi_db_x_1000 = ((val / RSSI_MULTIPLIER) * 1000) + + (val % RSSI_MULTIPLIER); + + return 0; +} + +/** + * Set the TX RF output port. + * @param phy The AD9361 current state structure. + * @param mode The RF port. + * Accepted values: + * TXA (0) + * TXB (1) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_tx_rf_port_output (struct ad9361_rf_phy *phy, + uint32_t mode) +{ + int32_t ret; + + phy->pdata->rf_tx_output_sel = mode; + + ret = ad9361_rf_port_setup(phy, true, + phy->pdata->rf_rx_input_sel, + phy->pdata->rf_tx_output_sel); + + return ret; +} + +/** + * Get the selected TX RF output port. + * @param phy The AD9361 current state structure. + * @param mode The RF port. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_tx_rf_port_output (struct ad9361_rf_phy *phy, + uint32_t *mode) +{ + *mode = phy->pdata->rf_tx_output_sel; + + return 0; +} + +/** + * Enable/disable the auto calibration. + * @param phy The AD9361 current state structure. + * @param en_dis The option (ENABLE, DISABLE). + * Accepted values: + * ENABLE (1) + * DISABLE (0) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis) +{ + if (en_dis == 0) + phy->auto_cal_en = 0; + else + phy->auto_cal_en = 1; + + return 0; +} + +/** + * Get the status of the auto calibration flag. + * @param phy The AD9361 current state structure. + * @param en_dis The enable/disable status buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy, + uint8_t *en_dis) +{ + *en_dis = phy->auto_cal_en; + + return 0; +} + +/** + * Store TX fastlock profile. + * To create a profile tune the synthesizer (ad9361_set_tx_lo_freq()) and then + * call this function specifying the target profile number. + * @param phy The AD9361 state structure. + * @param profile The profile number (0 - 7). + * Accepted values: + * 0 - 7 + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_tx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile) +{ + return ad9361_fastlock_store(phy, 1, profile); +} + +/** + * Recall specified TX fastlock profile. + * When in fastlock pin select mode (init_param->tx_fastlock_pincontrol_enable), + * the function needs to be called before then the pin-control can be used. + * @param phy The AD9361 state structure. + * @param profile The profile number (0 - 7). + * Accepted values: + * 0 - 7 + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_tx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile) +{ + return ad9361_fastlock_recall(phy, 1, profile); +} + +/** + * Load TX fastlock profile. A previously saved profile can be loaded in any + * of the 8 available slots. + * @param phy The AD9361 state structure. + * @param profile The profile number (0 - 7). + * Accepted values: + * 0 - 7 + * @param values Fastlock profile program data. + * Example: + * val0,val1,val2,…,val15 + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_tx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, + uint8_t *values) +{ + return ad9361_fastlock_load(phy, 1, profile, values); +} + +/** + * Save TX fastlock profile. In order to use more than 8 Profiles, an existing + * profile can be read back and stored by the user application. + * @param phy The AD9361 state structure. + * @param profile The profile number (0 - 7). + * Accepted values: + * 0 - 7 + * @param values Fastlock profile program data. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_tx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, + uint8_t *values) +{ + return ad9361_fastlock_save(phy, 1, profile, values); +} + +/** + * Power down the TX Local Oscillator. + * @param phy The AD9361 state structure. + * @param option The option (ON, OFF). + * Accepted values: + * ON (0) + * OFF (1) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_tx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option) +{ + return ad9361_synth_lo_powerdown(phy, LO_DONTCARE, option ? LO_OFF : LO_ON); +} + +/** + * Get the TX Local Oscillator power status. + * @param phy The AD9361 state structure. + * @param option Store the option (ON, OFF). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_tx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option) +{ + *option = !(phy->cached_synth_pd[0] & TX_LO_POWER_DOWN) ? OFF : ON; + + return 0; +} + +/** + * Set the RX and TX path rates. + * @param phy The AD9361 state structure. + * @param rx_path_clks RX path rates buffer. + * @param tx_path_clks TX path rates buffer. + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_trx_path_clks(struct ad9361_rf_phy *phy, + uint32_t *rx_path_clks, + uint32_t *tx_path_clks) +{ + int32_t ret; + + ret = ad9361_set_trx_clock_chain(phy, rx_path_clks, tx_path_clks); + if (ret < 0) + return ret; + + ret = ad9361_update_rf_bandwidth(phy, phy->current_rx_bw_Hz, + phy->current_tx_bw_Hz); + + return ret; +} + +/** + * Get the RX and TX path rates. + * @param phy The AD9361 state structure. + * @param rx_path_clks RX path rates buffer. + * @param tx_path_clks TX path rates buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_trx_path_clks(struct ad9361_rf_phy *phy, + uint32_t *rx_path_clks, + uint32_t *tx_path_clks) +{ + return ad9361_get_trx_clock_chain(phy, rx_path_clks, tx_path_clks); +} + +/** + * Set the number of channels mode. + * @param phy The AD9361 state structure. + * Note: This function also resets the device, some additional + * configurations might be necessary + * @param no_ch_mode Number of channels mode (MODE_1x1, MODE_2x2). + * Accepted values: + * MODE_1x1 (1) + * MODE_2x2 (2) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_no_ch_mode(struct ad9361_rf_phy *phy, uint8_t no_ch_mode) +{ + switch (no_ch_mode) { + case 1: + phy->pdata->rx2tx2 = 0; + break; + case 2: + phy->pdata->rx2tx2 = 1; + break; + default: + return -EINVAL; + } + + ad9361_reset(phy); + ad9361_spi_write(phy->spi, REG_SPI_CONF, SOFT_RESET | _SOFT_RESET); + ad9361_spi_write(phy->spi, REG_SPI_CONF, 0x0); + + ad9361_clear_state(phy); + + phy->clks[TX_REFCLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[TX_REFCLK], phy->clk_refin->rate); + phy->clks[TX_REFCLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[TX_REFCLK], phy->clk_refin->rate); + phy->clks[RX_REFCLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[RX_REFCLK], phy->clk_refin->rate); + phy->clks[BB_REFCLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[BB_REFCLK], phy->clk_refin->rate); + phy->clks[BBPLL_CLK]->rate = ad9361_bbpll_recalc_rate( + phy->ref_clk_scale[BBPLL_CLK], phy->clks[BB_REFCLK]->rate); + phy->clks[ADC_CLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[ADC_CLK], phy->clks[BBPLL_CLK]->rate); + phy->clks[R2_CLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[R2_CLK], phy->clks[ADC_CLK]->rate); + phy->clks[R1_CLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[R1_CLK], phy->clks[R2_CLK]->rate); + phy->clks[CLKRF_CLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[CLKRF_CLK], phy->clks[R1_CLK]->rate); + phy->clks[RX_SAMPL_CLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[RX_SAMPL_CLK], phy->clks[CLKRF_CLK]->rate); + phy->clks[DAC_CLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[DAC_CLK], phy->clks[ADC_CLK]->rate); + phy->clks[T2_CLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[T2_CLK], phy->clks[DAC_CLK]->rate); + phy->clks[T1_CLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[T1_CLK], phy->clks[T2_CLK]->rate); + phy->clks[CLKTF_CLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[CLKTF_CLK], phy->clks[T1_CLK]->rate); + phy->clks[TX_SAMPL_CLK]->rate = ad9361_clk_factor_recalc_rate( + phy->ref_clk_scale[TX_SAMPL_CLK], phy->clks[CLKTF_CLK]->rate); + phy->clks[RX_RFPLL_INT]->rate = ad9361_rfpll_int_recalc_rate( + phy->ref_clk_scale[RX_RFPLL_INT], phy->clks[RX_REFCLK]->rate); + phy->clks[TX_RFPLL_INT]->rate = ad9361_rfpll_int_recalc_rate( + phy->ref_clk_scale[TX_RFPLL_INT], phy->clks[TX_REFCLK]->rate); + phy->clks[RX_RFPLL_DUMMY]->rate = ad9361_rfpll_dummy_recalc_rate( + phy->ref_clk_scale[RX_RFPLL_DUMMY]); + phy->clks[TX_RFPLL_DUMMY]->rate = ad9361_rfpll_dummy_recalc_rate( + phy->ref_clk_scale[TX_RFPLL_DUMMY]); + phy->clks[RX_RFPLL]->rate = ad9361_rfpll_recalc_rate( + phy->ref_clk_scale[RX_RFPLL]); + phy->clks[TX_RFPLL]->rate = ad9361_rfpll_recalc_rate( + phy->ref_clk_scale[TX_RFPLL]); + + ad9361_setup(phy); +#ifndef AXI_ADC_NOT_PRESENT + /* platform specific wrapper to call ad9361_post_setup() */ + ad9361_post_setup(phy); +#endif + + return 0; +} + +/** + * Do multi chip synchronization. + * @param phy_master The AD9361 Master state structure. + * @param phy_slave The AD9361 Slave state structure. + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_do_mcs(struct ad9361_rf_phy *phy_master, + struct ad9361_rf_phy *phy_slave) +{ + uint32_t ensm_mode; + int32_t step; + int32_t reg; + + if ((phy_master->dev_sel == ID_AD9363A) || + (phy_slave->dev_sel == ID_AD9363A)) { + printf("%s : MCS is not supported by AD9363!\n", __func__); + return -1; + } + + reg = ad9361_spi_read(phy_master->spi, REG_RX_CLOCK_DATA_DELAY); + ad9361_spi_write(phy_slave->spi, REG_RX_CLOCK_DATA_DELAY, reg); + reg = ad9361_spi_read(phy_master->spi, REG_TX_CLOCK_DATA_DELAY); + ad9361_spi_write(phy_slave->spi, REG_TX_CLOCK_DATA_DELAY, reg); + + ad9361_get_en_state_machine_mode(phy_master, &ensm_mode); + + ad9361_set_en_state_machine_mode(phy_master, ENSM_MODE_ALERT); + ad9361_set_en_state_machine_mode(phy_slave, ENSM_MODE_ALERT); + + for (step = 0; step <= 5; step++) { + ad9361_mcs(phy_slave, step); + ad9361_mcs(phy_master, step); + mdelay(100); + } + + ad9361_set_en_state_machine_mode(phy_master, ensm_mode); + ad9361_set_en_state_machine_mode(phy_slave, ensm_mode); + + return 0; +} + +/** + * Enable/disable the TRX FIR filters. + * @param phy The AD9361 current state structure. + * @param en_dis The option (ENABLE, DISABLE). + * Accepted values: + * ENABLE (1) + * DISABLE (0) + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_set_trx_fir_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis) +{ + int32_t ret = 0; + + if ((phy->bypass_rx_fir == phy->bypass_tx_fir) && + (phy->bypass_rx_fir == !en_dis)) + return ret; + + phy->bypass_rx_fir = !en_dis; + phy->bypass_tx_fir = !en_dis; + ret = ad9361_validate_enable_fir(phy); + if (ret < 0) { + phy->bypass_rx_fir = true; + phy->bypass_tx_fir = true; + } + + return ret; +} + +/** + * Set the OSR rate governor. + * @param phy The AD9361 current state structure. + * @param rate_gov OSR rate governor (highest, nominal). + * Accepted values: + * HIGHEST_OSR (0 - highest OSR) + * NOMINAL_OSR (1 - nominal) + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_set_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t rate_gov) +{ + if (rate_gov == 0) + phy->rate_governor = 0; + else + phy->rate_governor = 1; + + return 0; +} + +/** + * Get the OSR rate governor. + * @param phy The AD9361 current state structure. + * @param rate_gov Option buffer. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t *rate_gov) +{ + *rate_gov = phy->rate_governor; + + return 0; +} + +/** + * Perform the selected calibration. + * @param phy The AD9361 state structure. + * @param cal The selected calibration (TX_QUAD_CAL, RFDC_CAL). + * Accepted values: + * TX_QUAD_CAL + * RFDC_CAL + * @param arg For TX_QUAD_CAL - the optional RX phase value overwrite (set to zero). + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_do_calib(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg) +{ + return ad9361_do_calib_run(phy, cal, arg); +} + +/** + * Load and enable TRX FIR filters configurations. + * @param phy The AD9361 current state structure. + * @param rx_fir_cfg RX FIR filter configuration. + * @param tx_fir_cfg TX FIR filter configuration. + * @return 0 in case of success, negative error code otherwise. + * + * Note: This function will/may affect the data path. + */ +int32_t ad9361_trx_load_enable_fir(struct ad9361_rf_phy *phy, + AD9361_RXFIRConfig rx_fir_cfg, + AD9361_TXFIRConfig tx_fir_cfg) +{ + int32_t rtx = -1, rrx = -1; + + phy->filt_rx_bw_Hz = 0; + phy->filt_tx_bw_Hz = 0; + phy->filt_valid = false; + + if (tx_fir_cfg.tx_path_clks[TX_SAMPL_FREQ]) { + memcpy(phy->filt_tx_path_clks, tx_fir_cfg.tx_path_clks, + sizeof(phy->filt_tx_path_clks)); + rtx = 0; + } + + if (rx_fir_cfg.rx_path_clks[RX_SAMPL_FREQ]) { + memcpy(phy->filt_rx_path_clks, rx_fir_cfg.rx_path_clks, + sizeof(phy->filt_rx_path_clks)); + rrx = 0; + } + + if (tx_fir_cfg.tx_bandwidth) { + phy->filt_tx_bw_Hz = tx_fir_cfg.tx_bandwidth; + } + + if (rx_fir_cfg.rx_bandwidth) { + phy->filt_rx_bw_Hz = rx_fir_cfg.rx_bandwidth; + } + + ad9361_set_tx_fir_config(phy, tx_fir_cfg); + ad9361_set_rx_fir_config(phy, rx_fir_cfg); + + if (!(rrx | rtx)) + phy->filt_valid = true; + + ad9361_set_trx_fir_en_dis(phy, 1); + + return 0; +} + +/** + * Do DCXO coarse tuning. + * @param phy The AD9361 current state structure. + * @param coarse The DCXO coarse tuning value. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_do_dcxo_tune_coarse(struct ad9361_rf_phy *phy, + uint32_t coarse) +{ + phy->pdata->dcxo_coarse = coarse; + + return ad9361_set_dcxo_tune(phy, phy->pdata->dcxo_coarse, + phy->pdata->dcxo_fine); +} + +/** + * Do DCXO fine tuning. + * @param phy The AD9361 current state structure. + * @param fine The DCXO fine tuning value. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_do_dcxo_tune_fine(struct ad9361_rf_phy *phy, + uint32_t fine) +{ + phy->pdata->dcxo_fine = fine; + + return ad9361_set_dcxo_tune(phy, phy->pdata->dcxo_coarse, + phy->pdata->dcxo_fine); +} + +/** + * Get the temperature. + * @param phy The AD9361 current state structure. + * @param temp The temperature (degrees C * 1000). + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_get_temperature(struct ad9361_rf_phy *phy, + int32_t *temp) +{ + *temp = ad9361_get_temp(phy); + return 0; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.h new file mode 100644 index 00000000..498fb459 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.h @@ -0,0 +1,552 @@ +/***************************************************************************//** + * @file ad9361_api.h + * @brief Header file of AD9361 API Driver. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef AD9361_API_H_ +#define AD9361_API_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include "ad9361_util.h" +#include "../../../include/gpio.h" +#include "../../../include/spi.h" + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +typedef struct { + /* Device selection */ + enum dev_id dev_sel; + /* Reference Clock */ + uint32_t reference_clk_rate; + /* Base Configuration */ + uint8_t two_rx_two_tx_mode_enable; /* adi,2rx-2tx-mode-enable */ + uint8_t one_rx_one_tx_mode_use_rx_num; /* adi,1rx-1tx-mode-use-rx-num */ + uint8_t one_rx_one_tx_mode_use_tx_num; /* adi,1rx-1tx-mode-use-tx-num */ + uint8_t frequency_division_duplex_mode_enable; /* adi,frequency-division-duplex-mode-enable */ + uint8_t frequency_division_duplex_independent_mode_enable; /* adi,frequency-division-duplex-independent-mode-enable */ + uint8_t tdd_use_dual_synth_mode_enable; /* adi,tdd-use-dual-synth-mode-enable */ + uint8_t tdd_skip_vco_cal_enable; /* adi,tdd-skip-vco-cal-enable */ + uint32_t tx_fastlock_delay_ns; /* adi,tx-fastlock-delay-ns */ + uint32_t rx_fastlock_delay_ns; /* adi,rx-fastlock-delay-ns */ + uint8_t rx_fastlock_pincontrol_enable; /* adi,rx-fastlock-pincontrol-enable */ + uint8_t tx_fastlock_pincontrol_enable; /* adi,tx-fastlock-pincontrol-enable */ + uint8_t external_rx_lo_enable; /* adi,external-rx-lo-enable */ + uint8_t external_tx_lo_enable; /* adi,external-tx-lo-enable */ + uint8_t dc_offset_tracking_update_event_mask; /* adi,dc-offset-tracking-update-event-mask */ + uint8_t dc_offset_attenuation_high_range; /* adi,dc-offset-attenuation-high-range */ + uint8_t dc_offset_attenuation_low_range; /* adi,dc-offset-attenuation-low-range */ + uint8_t dc_offset_count_high_range; /* adi,dc-offset-count-high-range */ + uint8_t dc_offset_count_low_range; /* adi,dc-offset-count-low-range */ + uint8_t split_gain_table_mode_enable; /* adi,split-gain-table-mode-enable */ + uint32_t trx_synthesizer_target_fref_overwrite_hz; /* adi,trx-synthesizer-target-fref-overwrite-hz */ + uint8_t qec_tracking_slow_mode_enable; /* adi,qec-tracking-slow-mode-enable */ + /* ENSM Control */ + uint8_t ensm_enable_pin_pulse_mode_enable; /* adi,ensm-enable-pin-pulse-mode-enable */ + uint8_t ensm_enable_txnrx_control_enable; /* adi,ensm-enable-txnrx-control-enable */ + /* LO Control */ + uint64_t rx_synthesizer_frequency_hz; /* adi,rx-synthesizer-frequency-hz */ + uint64_t tx_synthesizer_frequency_hz; /* adi,tx-synthesizer-frequency-hz */ + uint8_t tx_lo_powerdown_managed_enable; /* adi,tx-lo-powerdown-managed-enable */ + /* Rate & BW Control */ + uint32_t rx_path_clock_frequencies[6]; /* adi,rx-path-clock-frequencies */ + uint32_t tx_path_clock_frequencies[6]; /* adi,tx-path-clock-frequencies */ + uint32_t rf_rx_bandwidth_hz; /* adi,rf-rx-bandwidth-hz */ + uint32_t rf_tx_bandwidth_hz; /* adi,rf-tx-bandwidth-hz */ + /* RF Port Control */ + uint32_t rx_rf_port_input_select; /* adi,rx-rf-port-input-select */ + uint32_t tx_rf_port_input_select; /* adi,tx-rf-port-input-select */ + /* TX Attenuation Control */ + int32_t tx_attenuation_mdB; /* adi,tx-attenuation-mdB */ + uint8_t update_tx_gain_in_alert_enable; /* adi,update-tx-gain-in-alert-enable */ + /* Reference Clock Control */ + uint8_t xo_disable_use_ext_refclk_enable; /* adi,xo-disable-use-ext-refclk-enable */ + uint32_t dcxo_coarse_and_fine_tune[2]; /* adi,dcxo-coarse-and-fine-tune */ + uint32_t clk_output_mode_select; /* adi,clk-output-mode-select */ + /* Gain Control */ + uint8_t gc_rx1_mode; /* adi,gc-rx1-mode */ + uint8_t gc_rx2_mode; /* adi,gc-rx2-mode */ + uint8_t gc_adc_large_overload_thresh; /* adi,gc-adc-large-overload-thresh */ + uint8_t gc_adc_ovr_sample_size; /* adi,gc-adc-ovr-sample-size */ + uint8_t gc_adc_small_overload_thresh; /* adi,gc-adc-small-overload-thresh */ + uint16_t gc_dec_pow_measurement_duration; /* adi,gc-dec-pow-measurement-duration */ + uint8_t gc_dig_gain_enable; /* adi,gc-dig-gain-enable */ + uint16_t gc_lmt_overload_high_thresh; /* adi,gc-lmt-overload-high-thresh */ + uint16_t gc_lmt_overload_low_thresh; /* adi,gc-lmt-overload-low-thresh */ + uint8_t gc_low_power_thresh; /* adi,gc-low-power-thresh */ + uint8_t gc_max_dig_gain; /* adi,gc-max-dig-gain */ + uint8_t gc_use_rx_fir_out_for_dec_pwr_meas_enable; /* adi,gc-use-rx-fir-out-for-dec-pwr-meas-enable */ + /* Gain MGC Control */ + uint8_t mgc_dec_gain_step; /* adi,mgc-dec-gain-step */ + uint8_t mgc_inc_gain_step; /* adi,mgc-inc-gain-step */ + uint8_t mgc_rx1_ctrl_inp_enable; /* adi,mgc-rx1-ctrl-inp-enable */ + uint8_t mgc_rx2_ctrl_inp_enable; /* adi,mgc-rx2-ctrl-inp-enable */ + uint8_t mgc_split_table_ctrl_inp_gain_mode; /* adi,mgc-split-table-ctrl-inp-gain-mode */ + /* Gain AGC Control */ + uint8_t agc_adc_large_overload_exceed_counter; /* adi,agc-adc-large-overload-exceed-counter */ + uint8_t agc_adc_large_overload_inc_steps; /* adi,agc-adc-large-overload-inc-steps - Name is misleading should be dec-steps*/ + uint8_t agc_adc_lmt_small_overload_prevent_gain_inc_enable; /* adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable */ + uint8_t agc_adc_small_overload_exceed_counter; /* adi,agc-adc-small-overload-exceed-counter */ + uint8_t agc_dig_gain_step_size; /* adi,agc-dig-gain-step-size */ + uint8_t agc_dig_saturation_exceed_counter; /* adi,agc-dig-saturation-exceed-counter */ + uint32_t agc_gain_update_interval_us; /* adi,agc-gain-update-interval-us */ + uint8_t agc_immed_gain_change_if_large_adc_overload_enable; /* adi,agc-immed-gain-change-if-large-adc-overload-enable */ + uint8_t agc_immed_gain_change_if_large_lmt_overload_enable; /* adi,agc-immed-gain-change-if-large-lmt-overload-enable */ + uint8_t agc_inner_thresh_high; /* adi,agc-inner-thresh-high */ + uint8_t agc_inner_thresh_high_dec_steps; /* adi,agc-inner-thresh-high-dec-steps */ + uint8_t agc_inner_thresh_low; /* adi,agc-inner-thresh-low */ + uint8_t agc_inner_thresh_low_inc_steps; /* adi,agc-inner-thresh-low-inc-steps */ + uint8_t agc_lmt_overload_large_exceed_counter; /* adi,agc-lmt-overload-large-exceed-counter */ + uint8_t agc_lmt_overload_large_inc_steps; /* adi,agc-lmt-overload-large-inc-steps */ + uint8_t agc_lmt_overload_small_exceed_counter; /* adi,agc-lmt-overload-small-exceed-counter */ + uint8_t agc_outer_thresh_high; /* adi,agc-outer-thresh-high */ + uint8_t agc_outer_thresh_high_dec_steps; /* adi,agc-outer-thresh-high-dec-steps */ + uint8_t agc_outer_thresh_low; /* adi,agc-outer-thresh-low */ + uint8_t agc_outer_thresh_low_inc_steps; /* adi,agc-outer-thresh-low-inc-steps */ + uint32_t agc_attack_delay_extra_margin_us; /* adi,agc-attack-delay-extra-margin-us */ + uint8_t agc_sync_for_gain_counter_enable; /* adi,agc-sync-for-gain-counter-enable */ + /* Fast AGC */ + uint32_t fagc_dec_pow_measuremnt_duration; /* adi,fagc-dec-pow-measurement-duration */ + uint32_t fagc_state_wait_time_ns; /* adi,fagc-state-wait-time-ns */ + /* Fast AGC - Low Power */ + uint8_t fagc_allow_agc_gain_increase; /* adi,fagc-allow-agc-gain-increase-enable */ + uint32_t fagc_lp_thresh_increment_time; /* adi,fagc-lp-thresh-increment-time */ + uint32_t fagc_lp_thresh_increment_steps; /* adi,fagc-lp-thresh-increment-steps */ + /* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */ + uint8_t fagc_lock_level_lmt_gain_increase_en; /* adi,fagc-lock-level-lmt-gain-increase-enable */ + uint32_t fagc_lock_level_gain_increase_upper_limit; /* adi,fagc-lock-level-gain-increase-upper-limit */ + /* Fast AGC - Peak Detectors and Final Settling */ + uint32_t fagc_lpf_final_settling_steps; /* adi,fagc-lpf-final-settling-steps */ + uint32_t fagc_lmt_final_settling_steps; /* adi,fagc-lmt-final-settling-steps */ + uint32_t fagc_final_overrange_count; /* adi,fagc-final-overrange-count */ + /* Fast AGC - Final Power Test */ + uint8_t fagc_gain_increase_after_gain_lock_en; /* adi,fagc-gain-increase-after-gain-lock-enable */ + /* Fast AGC - Unlocking the Gain */ + uint32_t fagc_gain_index_type_after_exit_rx_mode; /* adi,fagc-gain-index-type-after-exit-rx-mode */ + uint8_t fagc_use_last_lock_level_for_set_gain_en; /* adi,fagc-use-last-lock-level-for-set-gain-enable */ + uint8_t fagc_rst_gla_stronger_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable */ + uint32_t fagc_optimized_gain_offset; /* adi,fagc-optimized-gain-offset */ + uint32_t fagc_rst_gla_stronger_sig_thresh_above_ll; /* adi,fagc-rst-gla-stronger-sig-thresh-above-ll */ + uint8_t fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable */ + uint8_t fagc_rst_gla_engergy_lost_goto_optim_gain_en; /* adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable */ + uint32_t fagc_rst_gla_engergy_lost_sig_thresh_below_ll; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll */ + uint32_t fagc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt */ + uint8_t fagc_rst_gla_large_adc_overload_en; /* adi,fagc-rst-gla-large-adc-overload-enable */ + uint8_t fagc_rst_gla_large_lmt_overload_en; /* adi,fagc-rst-gla-large-lmt-overload-enable */ + uint8_t fagc_rst_gla_en_agc_pulled_high_en; /* adi,fagc-rst-gla-en-agc-pulled-high-enable */ + uint32_t fagc_rst_gla_if_en_agc_pulled_high_mode; /* adi,fagc-rst-gla-if-en-agc-pulled-high-mode */ + uint32_t fagc_power_measurement_duration_in_state5; /* adi,fagc-power-measurement-duration-in-state5 */ + uint32_t fagc_large_overload_inc_steps; /* adi,fagc-adc-large-overload-inc-steps - Name is misleading should be dec-steps */ + /* RSSI Control */ + uint32_t rssi_delay; /* adi,rssi-delay */ + uint32_t rssi_duration; /* adi,rssi-duration */ + uint8_t rssi_restart_mode; /* adi,rssi-restart-mode */ + uint8_t rssi_unit_is_rx_samples_enable; /* adi,rssi-unit-is-rx-samples-enable */ + uint32_t rssi_wait; /* adi,rssi-wait */ + /* Aux ADC Control */ + uint32_t aux_adc_decimation; /* adi,aux-adc-decimation */ + uint32_t aux_adc_rate; /* adi,aux-adc-rate */ + /* AuxDAC Control */ + uint8_t aux_dac_manual_mode_enable; /* adi,aux-dac-manual-mode-enable */ + uint32_t aux_dac1_default_value_mV; /* adi,aux-dac1-default-value-mV */ + uint8_t aux_dac1_active_in_rx_enable; /* adi,aux-dac1-active-in-rx-enable */ + uint8_t aux_dac1_active_in_tx_enable; /* adi,aux-dac1-active-in-tx-enable */ + uint8_t aux_dac1_active_in_alert_enable; /* adi,aux-dac1-active-in-alert-enable */ + uint32_t aux_dac1_rx_delay_us; /* adi,aux-dac1-rx-delay-us */ + uint32_t aux_dac1_tx_delay_us; /* adi,aux-dac1-tx-delay-us */ + uint32_t aux_dac2_default_value_mV; /* adi,aux-dac2-default-value-mV */ + uint8_t aux_dac2_active_in_rx_enable; /* adi,aux-dac2-active-in-rx-enable */ + uint8_t aux_dac2_active_in_tx_enable; /* adi,aux-dac2-active-in-tx-enable */ + uint8_t aux_dac2_active_in_alert_enable; /* adi,aux-dac2-active-in-alert-enable */ + uint32_t aux_dac2_rx_delay_us; /* adi,aux-dac2-rx-delay-us */ + uint32_t aux_dac2_tx_delay_us; /* adi,aux-dac2-tx-delay-us */ + /* Temperature Sensor Control */ + uint32_t temp_sense_decimation; /* adi,temp-sense-decimation */ + uint16_t temp_sense_measurement_interval_ms; /* adi,temp-sense-measurement-interval-ms */ + int8_t temp_sense_offset_signed; /* adi,temp-sense-offset-signed */ + uint8_t temp_sense_periodic_measurement_enable; /* adi,temp-sense-periodic-measurement-enable */ + /* Control Out Setup */ + uint8_t ctrl_outs_enable_mask; /* adi,ctrl-outs-enable-mask */ + uint8_t ctrl_outs_index; /* adi,ctrl-outs-index */ + /* External LNA Control */ + uint32_t elna_settling_delay_ns; /* adi,elna-settling-delay-ns */ + uint32_t elna_gain_mdB; /* adi,elna-gain-mdB */ + uint32_t elna_bypass_loss_mdB; /* adi,elna-bypass-loss-mdB */ + uint8_t elna_rx1_gpo0_control_enable; /* adi,elna-rx1-gpo0-control-enable */ + uint8_t elna_rx2_gpo1_control_enable; /* adi,elna-rx2-gpo1-control-enable */ + uint8_t elna_gaintable_all_index_enable; /* adi,elna-gaintable-all-index-enable */ + /* Digital Interface Control */ + uint8_t digital_interface_tune_skip_mode; /* adi,digital-interface-tune-skip-mode */ + uint8_t digital_interface_tune_fir_disable; /* adi,digital-interface-tune-fir-disable */ + uint8_t pp_tx_swap_enable; /* adi,pp-tx-swap-enable */ + uint8_t pp_rx_swap_enable; /* adi,pp-rx-swap-enable */ + uint8_t tx_channel_swap_enable; /* adi,tx-channel-swap-enable */ + uint8_t rx_channel_swap_enable; /* adi,rx-channel-swap-enable */ + uint8_t rx_frame_pulse_mode_enable; /* adi,rx-frame-pulse-mode-enable */ + uint8_t two_t_two_r_timing_enable; /* adi,2t2r-timing-enable */ + uint8_t invert_data_bus_enable; /* adi,invert-data-bus-enable */ + uint8_t invert_data_clk_enable; /* adi,invert-data-clk-enable */ + uint8_t fdd_alt_word_order_enable; /* adi,fdd-alt-word-order-enable */ + uint8_t invert_rx_frame_enable; /* adi,invert-rx-frame-enable */ + uint8_t fdd_rx_rate_2tx_enable; /* adi,fdd-rx-rate-2tx-enable */ + uint8_t swap_ports_enable; /* adi,swap-ports-enable */ + uint8_t single_data_rate_enable; /* adi,single-data-rate-enable */ + uint8_t lvds_mode_enable; /* adi,lvds-mode-enable */ + uint8_t half_duplex_mode_enable; /* adi,half-duplex-mode-enable */ + uint8_t single_port_mode_enable; /* adi,single-port-mode-enable */ + uint8_t full_port_enable; /* adi,full-port-enable */ + uint8_t full_duplex_swap_bits_enable; /* adi,full-duplex-swap-bits-enable */ + uint32_t delay_rx_data; /* adi,delay-rx-data */ + uint32_t rx_data_clock_delay; /* adi,rx-data-clock-delay */ + uint32_t rx_data_delay; /* adi,rx-data-delay */ + uint32_t tx_fb_clock_delay; /* adi,tx-fb-clock-delay */ + uint32_t tx_data_delay; /* adi,tx-data-delay */ + uint32_t lvds_bias_mV; /* adi,lvds-bias-mV */ + uint8_t lvds_rx_onchip_termination_enable; /* adi,lvds-rx-onchip-termination-enable */ + uint8_t rx1rx2_phase_inversion_en; /* adi,rx1-rx2-phase-inversion-enable */ + uint8_t lvds_invert1_control; /* adi,lvds-invert1-control */ + uint8_t lvds_invert2_control; /* adi,lvds-invert2-control */ + /* GPO Control */ + uint8_t gpo_manual_mode_enable; /* adi,gpo-manual-mode-enable */ + uint32_t gpo_manual_mode_enable_mask; /* adi,gpo-manual-mode-enable-mask */ + uint8_t gpo0_inactive_state_high_enable; /* adi,gpo0-inactive-state-high-enable */ + uint8_t gpo1_inactive_state_high_enable; /* adi,gpo1-inactive-state-high-enable */ + uint8_t gpo2_inactive_state_high_enable; /* adi,gpo2-inactive-state-high-enable */ + uint8_t gpo3_inactive_state_high_enable; /* adi,gpo3-inactive-state-high-enable */ + uint8_t gpo0_slave_rx_enable; /* adi,gpo0-slave-rx-enable */ + uint8_t gpo0_slave_tx_enable; /* adi,gpo0-slave-tx-enable */ + uint8_t gpo1_slave_rx_enable; /* adi,gpo1-slave-rx-enable */ + uint8_t gpo1_slave_tx_enable; /* adi,gpo1-slave-tx-enable */ + uint8_t gpo2_slave_rx_enable; /* adi,gpo2-slave-rx-enable */ + uint8_t gpo2_slave_tx_enable; /* adi,gpo2-slave-tx-enable */ + uint8_t gpo3_slave_rx_enable; /* adi,gpo3-slave-rx-enable */ + uint8_t gpo3_slave_tx_enable; /* adi,gpo3-slave-tx-enable */ + uint8_t gpo0_rx_delay_us; /* adi,gpo0-rx-delay-us */ + uint8_t gpo0_tx_delay_us; /* adi,gpo0-tx-delay-us */ + uint8_t gpo1_rx_delay_us; /* adi,gpo1-rx-delay-us */ + uint8_t gpo1_tx_delay_us; /* adi,gpo1-tx-delay-us */ + uint8_t gpo2_rx_delay_us; /* adi,gpo2-rx-delay-us */ + uint8_t gpo2_tx_delay_us; /* adi,gpo2-tx-delay-us */ + uint8_t gpo3_rx_delay_us; /* adi,gpo3-rx-delay-us */ + uint8_t gpo3_tx_delay_us; /* adi,gpo3-tx-delay-us */ + /* Tx Monitor Control */ + uint32_t low_high_gain_threshold_mdB; /* adi,txmon-low-high-thresh */ + uint32_t low_gain_dB; /* adi,txmon-low-gain */ + uint32_t high_gain_dB; /* adi,txmon-high-gain */ + uint8_t tx_mon_track_en; /* adi,txmon-dc-tracking-enable */ + uint8_t one_shot_mode_en; /* adi,txmon-one-shot-mode-enable */ + uint32_t tx_mon_delay; /* adi,txmon-delay */ + uint32_t tx_mon_duration; /* adi,txmon-duration */ + uint32_t tx1_mon_front_end_gain; /* adi,txmon-1-front-end-gain */ + uint32_t tx2_mon_front_end_gain; /* adi,txmon-2-front-end-gain */ + uint32_t tx1_mon_lo_cm; /* adi,txmon-1-lo-cm */ + uint32_t tx2_mon_lo_cm; /* adi,txmon-2-lo-cm */ + /* GPIO definitions */ + struct gpio_init_param gpio_resetb; /* reset-gpios */ + /* MCS Sync */ + struct gpio_init_param gpio_sync; /* sync-gpios */ + struct gpio_init_param gpio_cal_sw1; /* cal-sw1-gpios */ + struct gpio_init_param gpio_cal_sw2; /* cal-sw2-gpios */ + + struct spi_init_param spi_param; + + /* External LO clocks */ + uint32_t (*ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv); + int32_t (*ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv, + uint32_t rate); + int32_t (*ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv, + uint32_t rate); + +} AD9361_InitParam; + +typedef struct { + uint32_t rx; /* 1, 2, 3(both) */ + int32_t rx_gain; /* -12, -6, 0, 6 */ + uint32_t rx_dec; /* 1, 2, 4 */ + int16_t rx_coef[128]; + uint8_t rx_coef_size; + uint32_t rx_path_clks[6]; + uint32_t rx_bandwidth; +} AD9361_RXFIRConfig; + +typedef struct { + uint32_t tx; /* 1, 2, 3(both) */ + int32_t tx_gain; /* -6, 0 */ + uint32_t tx_int; /* 1, 2, 4 */ + int16_t tx_coef[128]; + uint8_t tx_coef_size; + uint32_t tx_path_clks[6]; + uint32_t tx_bandwidth; +} AD9361_TXFIRConfig; + +enum ad9361_ensm_mode { + ENSM_MODE_TX, + ENSM_MODE_RX, + ENSM_MODE_ALERT, + ENSM_MODE_FDD, + ENSM_MODE_WAIT, + ENSM_MODE_SLEEP, + ENSM_MODE_PINCTRL, + ENSM_MODE_PINCTRL_FDD_INDEP, +}; + +#define ENABLE 1 +#define DISABLE 0 + +#define RX1 0 +#define RX2 1 + +#define TX1 0 +#define TX2 1 + +#define A_BALANCED 0 +#define B_BALANCED 1 +#define C_BALANCED 2 +#define A_N 3 +#define A_P 4 +#define B_N 5 +#define B_P 6 +#define C_N 7 +#define C_P 8 +#define TX_MON1 9 +#define TX_MON2 10 +#define TX_MON1_2 11 + +#define TXA 0 +#define TXB 1 + +#define MODE_1x1 1 +#define MODE_2x2 2 + +#define HIGHEST_OSR 0 +#define NOMINAL_OSR 1 + +#define INT_LO 0 +#define EXT_LO 1 + +#define ON 0 +#define OFF 1 + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ +/* Initialize the AD9361 part. */ +int32_t ad9361_init (struct ad9361_rf_phy **ad9361_phy, + AD9361_InitParam *init_param); +/* Free the allocated resources. */ +int32_t ad9361_remove(struct ad9361_rf_phy *phy); +/* Set the Enable State Machine (ENSM) mode. */ +int32_t ad9361_set_en_state_machine_mode (struct ad9361_rf_phy *phy, + uint32_t mode); +/* Get the Enable State Machine (ENSM) mode. */ +int32_t ad9361_get_en_state_machine_mode (struct ad9361_rf_phy *phy, + uint32_t *mode); +/* Set the receive RF gain for the selected channel. */ +int32_t ad9361_set_rx_rf_gain (struct ad9361_rf_phy *phy, uint8_t ch, + int32_t gain_db); +/* Get current receive RF gain for the selected channel. */ +int32_t ad9361_get_rx_rf_gain (struct ad9361_rf_phy *phy, uint8_t ch, + int32_t *gain_db); +/* Set the RX RF bandwidth. */ +int32_t ad9361_set_rx_rf_bandwidth (struct ad9361_rf_phy *phy, + uint32_t bandwidth_hz); +/* Get the RX RF bandwidth. */ +int32_t ad9361_get_rx_rf_bandwidth (struct ad9361_rf_phy *phy, + uint32_t *bandwidth_hz); +/* Set the RX sampling frequency. */ +int32_t ad9361_set_rx_sampling_freq (struct ad9361_rf_phy *phy, + uint32_t sampling_freq_hz); +/* Get current RX sampling frequency. */ +int32_t ad9361_get_rx_sampling_freq (struct ad9361_rf_phy *phy, + uint32_t *sampling_freq_hz); +/* Set the RX LO frequency. */ +int32_t ad9361_set_rx_lo_freq (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz); +/* Get current RX LO frequency. */ +int32_t ad9361_get_rx_lo_freq (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz); +/* Switch between internal and external LO. */ +int32_t ad9361_set_rx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext); +/* Get the RSSI for the selected channel. */ +int32_t ad9361_get_rx_rssi (struct ad9361_rf_phy *phy, uint8_t ch, + struct rf_rssi *rssi); +/* Set the gain control mode for the selected channel. */ +int32_t ad9361_set_rx_gain_control_mode (struct ad9361_rf_phy *phy, uint8_t ch, + uint8_t gc_mode); +/* Get the gain control mode for the selected channel. */ +int32_t ad9361_get_rx_gain_control_mode (struct ad9361_rf_phy *phy, uint8_t ch, + uint8_t *gc_mode); +/* Set the RX FIR filter configuration. */ +int32_t ad9361_set_rx_fir_config (struct ad9361_rf_phy *phy, + AD9361_RXFIRConfig fir_cfg); +/* Get the RX FIR filter configuration. */ +int32_t ad9361_get_rx_fir_config(struct ad9361_rf_phy *phy, uint8_t rx_ch, + AD9361_RXFIRConfig *fir_cfg); +/* Enable/disable the RX FIR filter. */ +int32_t ad9361_set_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis); +/* Get the status of the RX FIR filter. */ +int32_t ad9361_get_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis); +/* Enable/disable the RX RFDC Tracking. */ +int32_t ad9361_set_rx_rfdc_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis); +/* Get the status of the RX RFDC Tracking. */ +int32_t ad9361_get_rx_rfdc_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t *en_dis); +/* Enable/disable the RX BasebandDC Tracking. */ +int32_t ad9361_set_rx_bbdc_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis); +/* Get the status of the RX BasebandDC Tracking. */ +int32_t ad9361_get_rx_bbdc_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t *en_dis); +/* Enable/disable the RX Quadrature Tracking. */ +int32_t ad9361_set_rx_quad_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis); +/* Get the status of the RX Quadrature Tracking. */ +int32_t ad9361_get_rx_quad_track_en_dis (struct ad9361_rf_phy *phy, + uint8_t *en_dis); +/* Set the RX RF input port. */ +int32_t ad9361_set_rx_rf_port_input (struct ad9361_rf_phy *phy, uint32_t mode); +/* Get the selected RX RF input port. */ +int32_t ad9361_get_rx_rf_port_input (struct ad9361_rf_phy *phy, uint32_t *mode); +/* Store RX fastlock profile. */ +int32_t ad9361_rx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile); +/* Recall RX fastlock profile. */ +int32_t ad9361_rx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile); +/* Load RX fastlock profile. */ +int32_t ad9361_rx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, + uint8_t *values); +/* Save RX fastlock profile. */ +int32_t ad9361_rx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, + uint8_t *values); +/* Power down the RX Local Oscillator. */ +int32_t ad9361_rx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option); +/* Get the RX Local Oscillator power status. */ +int32_t ad9361_get_rx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option); +/* Set the transmit attenuation for the selected channel. */ +int32_t ad9361_set_tx_attenuation (struct ad9361_rf_phy *phy, uint8_t ch, + uint32_t attenuation_mdb); +/* Get current transmit attenuation for the selected channel. */ +int32_t ad9361_get_tx_attenuation (struct ad9361_rf_phy *phy, uint8_t ch, + uint32_t *attenuation_mdb); +/* Set the TX RF bandwidth. */ +int32_t ad9361_set_tx_rf_bandwidth (struct ad9361_rf_phy *phy, + uint32_t bandwidth_hz); +/* Get the TX RF bandwidth. */ +int32_t ad9361_get_tx_rf_bandwidth (struct ad9361_rf_phy *phy, + uint32_t *bandwidth_hz); +/* Set the TX sampling frequency. */ +int32_t ad9361_set_tx_sampling_freq (struct ad9361_rf_phy *phy, + uint32_t sampling_freq_hz); +/* Get current TX sampling frequency. */ +int32_t ad9361_get_tx_sampling_freq (struct ad9361_rf_phy *phy, + uint32_t *sampling_freq_hz); +/* Set the TX LO frequency. */ +int32_t ad9361_set_tx_lo_freq (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz); +/* Get current TX LO frequency. */ +int32_t ad9361_get_tx_lo_freq (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz); +/* Switch between internal and external LO. */ +int32_t ad9361_set_tx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext); +/* Set the TX FIR filter configuration. */ +int32_t ad9361_set_tx_fir_config (struct ad9361_rf_phy *phy, + AD9361_TXFIRConfig fir_cfg); +/* Get the TX FIR filter configuration. */ +int32_t ad9361_get_tx_fir_config(struct ad9361_rf_phy *phy, uint8_t tx_ch, + AD9361_TXFIRConfig *fir_cfg); +/* Enable/disable the TX FIR filter. */ +int32_t ad9361_set_tx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis); +/* Get the status of the TX FIR filter. */ +int32_t ad9361_get_tx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis); +/* Get the TX RSSI for the selected channel. */ +int32_t ad9361_get_tx_rssi (struct ad9361_rf_phy *phy, uint8_t ch, + uint32_t *rssi_db_x_1000); +/* Set the TX RF output port. */ +int32_t ad9361_set_tx_rf_port_output (struct ad9361_rf_phy *phy, uint32_t mode); +/* Get the selected TX RF output port. */ +int32_t ad9361_get_tx_rf_port_output (struct ad9361_rf_phy *phy, + uint32_t *mode); +/* Enable/disable the auto calibration. */ +int32_t ad9361_set_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy, + uint8_t en_dis); +/* Get the status of the auto calibration flag. */ +int32_t ad9361_get_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy, + uint8_t *en_dis); +/* Store TX fastlock profile. */ +int32_t ad9361_tx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile); +/* Recall TX fastlock profile. */ +int32_t ad9361_tx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile); +/* Load TX fastlock profile. */ +int32_t ad9361_tx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, + uint8_t *values); +/* Save TX fastlock profile. */ +int32_t ad9361_tx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, + uint8_t *values); +/* Power down the TX Local Oscillator. */ +int32_t ad9361_tx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option); +/* Get the TX Local Oscillator power status. */ +int32_t ad9361_get_tx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option); +/* Set the RX and TX path rates. */ +int32_t ad9361_set_trx_path_clks(struct ad9361_rf_phy *phy, + uint32_t *rx_path_clks, uint32_t *tx_path_clks); +/* Get the RX and TX path rates. */ +int32_t ad9361_get_trx_path_clks(struct ad9361_rf_phy *phy, + uint32_t *rx_path_clks, uint32_t *tx_path_clks); +/* Set the number of channels mode. */ +int32_t ad9361_set_no_ch_mode(struct ad9361_rf_phy *phy, uint8_t no_ch_mode); +/* Do multi chip synchronization. */ +int32_t ad9361_do_mcs(struct ad9361_rf_phy *phy_master, + struct ad9361_rf_phy *phy_slave); +/* Enable/disable the TRX FIR filters. */ +int32_t ad9361_set_trx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis); +/* Set the OSR rate governor. */ +int32_t ad9361_set_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t rate_gov); +/* Get the OSR rate governor. */ +int32_t ad9361_get_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t *rate_gov); +/* Perform the selected calibration. */ +int32_t ad9361_do_calib(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg); +/* Load and enable TRX FIR filters configurations. */ +int32_t ad9361_trx_load_enable_fir(struct ad9361_rf_phy *phy, + AD9361_RXFIRConfig rx_fir_cfg, + AD9361_TXFIRConfig tx_fir_cfg); +/* Do DCXO coarse tuning. */ +int32_t ad9361_do_dcxo_tune_coarse(struct ad9361_rf_phy *phy, + uint32_t coarse); +/* Do DCXO fine tuning. */ +int32_t ad9361_do_dcxo_tune_fine(struct ad9361_rf_phy *phy, + uint32_t fine); +/* Get the temperature. */ +int32_t ad9361_get_temperature(struct ad9361_rf_phy *phy, + int32_t *temp); +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_conv.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_conv.c new file mode 100644 index 00000000..c7864670 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_conv.c @@ -0,0 +1,86 @@ + +/***************************************************************************//** + * @file ad9361_conv.c + * @brief Implementation of AD9361 Conv Driver. +******************************************************************************** + * Copyright 2014-2015(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include "ad9361.h" +#include "ad9361_util.h" +#include "../../../../app_config.h" +#include "../../../include/delay.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +/** + * HDL loopback enable/disable. + * @param phy The AD9361 state structure. + * @param enable Enable/disable option. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable) +{ + return -ENODEV; +} + +/** + * Digital tune. + * @param phy The AD9361 state structure. + * @param max_freq Maximum frequency. + * @param flags Flags: BE_VERBOSE, BE_MOREVERBOSE, DO_IDELAY, DO_ODELAY. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, + enum dig_tune_flags flags) +{ + return 0; +} + +/** +* Setup the AD9361 device. +* @param phy The AD9361 state structure. +* @return 0 in case of success, negative error code otherwise. +*/ +int32_t ad9361_post_setup(struct ad9361_rf_phy *phy) +{ + return 0; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_util.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_util.c new file mode 100644 index 00000000..a49e146b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_util.c @@ -0,0 +1,335 @@ +/***************************************************************************//** + * @file ad9361_util.c + * @brief AD9361 Implementation of Util Driver. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "ad9361_util.h" +#include "../../../include/delay.h" + +/******************************************************************************/ +/*************************** Macros Definitions *******************************/ +/******************************************************************************/ +#define BITS_PER_LONG 32 + +/***************************************************************************//** + * @brief clk_prepare_enable +*******************************************************************************/ +int32_t clk_prepare_enable(struct clk *clk) +{ + if (clk) { + // Unused variable - fix compiler warning + } + + return 0; +} + +/***************************************************************************//** + * @brief clk_get_rate +*******************************************************************************/ +uint32_t clk_get_rate(struct ad9361_rf_phy *phy, + struct refclk_scale *clk_priv) +{ + uint32_t rate = 0; + uint32_t source; + + source = clk_priv->source; + + switch (source) { + case TX_REFCLK: + case RX_REFCLK: + case BB_REFCLK: + rate = ad9361_clk_factor_recalc_rate(clk_priv, + phy->clk_refin->rate); + break; + case TX_RFPLL_INT: + case RX_RFPLL_INT: + rate = ad9361_rfpll_int_recalc_rate(clk_priv, + phy->clks[clk_priv->parent_source]->rate); + break; + case RX_RFPLL_DUMMY: + case TX_RFPLL_DUMMY: + rate = ad9361_rfpll_dummy_recalc_rate(clk_priv); + break; + case TX_RFPLL: + case RX_RFPLL: + rate = ad9361_rfpll_recalc_rate(clk_priv); + break; + case BBPLL_CLK: + rate = ad9361_bbpll_recalc_rate(clk_priv, + phy->clks[clk_priv->parent_source]->rate); + break; + case ADC_CLK: + case R2_CLK: + case R1_CLK: + case CLKRF_CLK: + case RX_SAMPL_CLK: + case DAC_CLK: + case T2_CLK: + case T1_CLK: + case CLKTF_CLK: + case TX_SAMPL_CLK: + rate = ad9361_clk_factor_recalc_rate(clk_priv, + phy->clks[clk_priv->parent_source]->rate); + break; + default: + break; + } + + return rate; +} + +/***************************************************************************//** + * @brief clk_set_rate +*******************************************************************************/ +int32_t clk_set_rate(struct ad9361_rf_phy *phy, + struct refclk_scale *clk_priv, + uint32_t rate) +{ + uint32_t source; + int32_t i; + uint32_t round_rate; + + source = clk_priv->source; + if(phy->clks[source]->rate != rate) + { + switch (source) { + case TX_REFCLK: + case RX_REFCLK: + case BB_REFCLK: + round_rate = ad9361_clk_factor_round_rate(clk_priv, rate, + &phy->clk_refin->rate); + ad9361_clk_factor_set_rate(clk_priv, round_rate, + phy->clk_refin->rate); + phy->clks[source]->rate = ad9361_clk_factor_recalc_rate(clk_priv, + phy->clk_refin->rate); + break; + case TX_RFPLL_INT: + case RX_RFPLL_INT: + round_rate = ad9361_rfpll_int_round_rate(clk_priv, rate, + &phy->clks[clk_priv->parent_source]->rate); + ad9361_rfpll_int_set_rate(clk_priv, round_rate, + phy->clks[clk_priv->parent_source]->rate); + phy->clks[source]->rate = ad9361_rfpll_int_recalc_rate(clk_priv, + phy->clks[clk_priv->parent_source]->rate); + break; + case RX_RFPLL_DUMMY: + case TX_RFPLL_DUMMY: + ad9361_rfpll_dummy_set_rate(clk_priv, rate); + break; + case TX_RFPLL: + case RX_RFPLL: + round_rate = ad9361_rfpll_round_rate(clk_priv, rate); + ad9361_rfpll_set_rate(clk_priv, round_rate); + phy->clks[source]->rate = ad9361_rfpll_recalc_rate(clk_priv); + break; + case BBPLL_CLK: + round_rate = ad9361_bbpll_round_rate(clk_priv, rate, + &phy->clks[clk_priv->parent_source]->rate); + ad9361_bbpll_set_rate(clk_priv, round_rate, + phy->clks[clk_priv->parent_source]->rate); + phy->clks[source]->rate = ad9361_bbpll_recalc_rate(clk_priv, + phy->clks[clk_priv->parent_source]->rate); + phy->bbpll_initialized = true; + break; + case ADC_CLK: + case R2_CLK: + case R1_CLK: + case CLKRF_CLK: + case RX_SAMPL_CLK: + case DAC_CLK: + case T2_CLK: + case T1_CLK: + case CLKTF_CLK: + case TX_SAMPL_CLK: + round_rate = ad9361_clk_factor_round_rate(clk_priv, rate, + &phy->clks[clk_priv->parent_source]->rate); + ad9361_clk_factor_set_rate(clk_priv, round_rate, + phy->clks[clk_priv->parent_source]->rate); + phy->clks[source]->rate = ad9361_clk_factor_recalc_rate(clk_priv, + phy->clks[clk_priv->parent_source]->rate); + break; + default: + break; + } + for(i = BB_REFCLK; i < BBPLL_CLK; i++) + { + phy->clks[i]->rate = ad9361_clk_factor_recalc_rate(phy->ref_clk_scale[i], + phy->clk_refin->rate); + } + phy->clks[BBPLL_CLK]->rate = ad9361_bbpll_recalc_rate(phy->ref_clk_scale[BBPLL_CLK], + phy->clks[phy->ref_clk_scale[BBPLL_CLK]->parent_source]->rate); + for(i = ADC_CLK; i < RX_RFPLL_INT; i++) + { + phy->clks[i]->rate = ad9361_clk_factor_recalc_rate(phy->ref_clk_scale[i], + phy->clks[phy->ref_clk_scale[i]->parent_source]->rate); + } + for(i = RX_RFPLL_INT; i < RX_RFPLL_DUMMY; i++) + { + phy->clks[i]->rate = ad9361_rfpll_int_recalc_rate(phy->ref_clk_scale[i], + phy->clks[phy->ref_clk_scale[i]->parent_source]->rate); + } + for(i = RX_RFPLL_DUMMY; i < RX_RFPLL; i++) + { + phy->clks[i]->rate = ad9361_rfpll_dummy_recalc_rate(phy->ref_clk_scale[i]); + } + for(i = RX_RFPLL; i < NUM_AD9361_CLKS; i++) + { + phy->clks[i]->rate = ad9361_rfpll_recalc_rate(phy->ref_clk_scale[i]); + } + } else { + if ((source == BBPLL_CLK) && !phy->bbpll_initialized) { + round_rate = ad9361_bbpll_round_rate(clk_priv, rate, + &phy->clks[clk_priv->parent_source]->rate); + ad9361_bbpll_set_rate(clk_priv, round_rate, + phy->clks[clk_priv->parent_source]->rate); + phy->clks[source]->rate = ad9361_bbpll_recalc_rate(clk_priv, + phy->clks[clk_priv->parent_source]->rate); + phy->bbpll_initialized = true; + } + } + + return 0; +} + +/***************************************************************************//** + * @brief int_sqrt +*******************************************************************************/ +uint32_t int_sqrt(uint32_t x) +{ + uint32_t b, m, y = 0; + + if (x <= 1) + return x; + + m = 1UL << (BITS_PER_LONG - 2); + while (m != 0) { + b = y + m; + y >>= 1; + + if (x >= b) { + x -= b; + y += m; + } + m >>= 2; + } + + return y; +} + +/***************************************************************************//** + * @brief ilog2 +*******************************************************************************/ +int32_t ilog2(int32_t x) +{ + int32_t A = !(!(x >> 16)); + int32_t count = 0; + int32_t x_copy = x; + + count = count + (A << 4); + + x_copy = (((~A + 1) & (x >> 16)) + (~(~A + 1) & x)); + + A = !(!(x_copy >> 8)); + count = count + (A << 3); + x_copy = (((~A + 1) & (x_copy >> 8)) + (~(~A + 1) & x_copy)); + + A = !(!(x_copy >> 4)); + count = count + (A << 2); + x_copy = (((~A + 1) & (x_copy >> 4)) + (~(~A + 1) & x_copy)); + + A = !(!(x_copy >> 2)); + count = count + (A << 1); + x_copy = (((~A + 1) & (x_copy >> 2)) + (~(~A + 1) & x_copy)); + + A = !(!(x_copy >> 1)); + count = count + A; + + return count; +} + +/***************************************************************************//** + * @brief find_first_bit +*******************************************************************************/ +uint32_t find_first_bit(uint32_t word) +{ + int32_t num = 0; + + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + num += 1; + return num; +} + +/***************************************************************************//** + * @brief ERR_PTR +*******************************************************************************/ +void * ERR_PTR(long error) +{ + return (void *) error; +} + +/***************************************************************************//** + * @brief zmalloc +*******************************************************************************/ +void *zmalloc(size_t size) +{ + void *ptr = malloc(size); + if (ptr) + memset(ptr, 0, size); + mdelay(1); + + return ptr; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_util.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_util.h new file mode 100644 index 00000000..18788394 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/ad9361_util.h @@ -0,0 +1,121 @@ +/***************************************************************************//** + * @file ad9361_util.h + * @brief AD9361 Header file of Util driver. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef __AD9361_UTIL_H__ +#define __AD9361_UTIL_H__ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include +#include +#include "ad9361.h" +#include "common.h" +#include "../../../../app_config.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#define CLK_IGNORE_UNUSED BIT(3) +#define CLK_GET_RATE_NOCACHE BIT(6) + +#if defined(HAVE_VERBOSE_MESSAGES) +#define dev_err(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); }) +#define dev_warn(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); }) +#if defined(HAVE_DEBUG_MESSAGES) +#define dev_dbg(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); }) +#else +#define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); }) +#endif +#define printk(format, ...) printf(format, ## __VA_ARGS__) +#else +#define dev_err(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); }) +#define dev_warn(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); }) +#define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); }) +#define printk(format, ...) ({ if (0) printf(format, ## __VA_ARGS__); }) +#endif + +struct device { +}; + +struct spi_device { + struct device dev; + uint8_t id_no; +}; + +struct axiadc_state { + struct ad9361_rf_phy *phy; + uint32_t pcore_version; +}; + +struct axiadc_chip_info { + char *name; + int32_t num_channels; +}; + +struct axiadc_converter { + struct axiadc_chip_info *chip_info; + uint32_t scratch_reg[16]; +}; + +#ifdef WIN32 +#include "basetsd.h" +typedef SSIZE_T ssize_t; +#define strsep(s, ct) 0 +#define snprintf(s, n, format, ...) 0 +#define __func__ __FUNCTION__ +#endif + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ +int32_t clk_prepare_enable(struct clk *clk); +uint32_t clk_get_rate(struct ad9361_rf_phy *phy, + struct refclk_scale *clk_priv); +int32_t clk_set_rate(struct ad9361_rf_phy *phy, + struct refclk_scale *clk_priv, + uint32_t rate); +uint32_t int_sqrt(uint32_t x); +int32_t ilog2(int32_t x); +uint32_t find_first_bit(uint32_t word); +void * ERR_PTR(long error); +void *zmalloc(size_t size); + +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/common.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/common.h new file mode 100644 index 00000000..bb922d7f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361/common.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file common.h + * @brief Header file of Common Driver. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef COMMON_H_ +#define COMMON_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "../../../include/error.h" + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +#if defined (__STDC__) && (__STDC_VERSION__ >= 199901L) +#include +#else +typedef enum { false, true } bool; +#endif + +struct clk { + const char *name; + uint32_t rate; +}; + +struct clk_hw { + struct clk *clk; +}; + +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c new file mode 100644 index 00000000..7498038c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c @@ -0,0 +1,151 @@ +/***************************************************************************//** + * @file ad9361_reg.c + * @brief Implementation of AD9680 Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include "ad9361_reg.h" + +#include +#include +#include "../../../include/error.h" + +/***************************************************************************//** + * @brief ad9361_reg_read + *******************************************************************************/ +int32_t ad9361_reg_read(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data) +{ + uint8_t tx_buf[2]; + uint8_t rx_buf[1]; + int32_t ret; + + tx_buf[0] = reg_addr >> 8; + tx_buf[1] = reg_addr & 0xFF; + + + ret = spi_write_and_read_3wire(dev->spi_desc, + tx_buf, rx_buf, 2, 1); + + *reg_data = rx_buf[0]; + + return ret; +} + +/***************************************************************************//** + * @brief ad9361_reg_write + *******************************************************************************/ +int32_t ad9361_reg_write(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t reg_data) +{ + uint8_t buf[3]; + + int32_t ret; + + buf[0] = 0x80 | reg_addr >> 8; + buf[1] = reg_addr & 0xFF; + buf[2] = reg_data; + + ret = spi_write_and_read_3wire(dev->spi_desc, + buf, NULL, 3, 0); + return ret; +} + +/***************************************************************************//** + * @brief ad9361_reg_init + *******************************************************************************/ +int32_t ad9361_reg_init(struct ad9361_reg_dev **device, + const struct ad9361_reg_init_param *init_param) +{ + int ret = SUCCESS; + struct ad9361_reg_dev *dev; + + dev = (struct ad9361_reg_dev *)malloc(sizeof(*dev)); + if (!dev) + return FAILURE; + + /* SPI */ + ret = spi_init(&dev->spi_desc, init_param->spi_init); + ret |= gpio_get(&dev->gpio_desc_resetb, init_param->gpio_resetb); + + gpio_direction_output(dev->gpio_desc_resetb, 0); + + ad9361_reg_reset(dev); + + *device = dev; + + return ret; +} + +/** + * AD9361 Device Reset + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev) +{ + if (dev->gpio_desc_resetb) { + gpio_set_value(dev->gpio_desc_resetb, 0); + mdelay(10); + gpio_set_value(dev->gpio_desc_resetb, 1); + mdelay(10); + return 0; + } + return 0; +} + +/***************************************************************************//** + * @brief Free the resources allocated by ad9361_reg_setup(). + * + * @param dev - The device structure. + * + * @return SUCCESS in case of success, negative error code otherwise. +*******************************************************************************/ +int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev) +{ + int32_t ret; + + ret = spi_remove(dev->spi_desc); + + free(dev); + + return ret; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h new file mode 100644 index 00000000..46c486b8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h @@ -0,0 +1,104 @@ +/***************************************************************************//** + * @file ad9361_reg.h + * @brief Header file of ad9361_reg Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ +#ifndef ad9361_reg_H_ +#define ad9361_reg_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "../../../include/delay.h" +#include "../../../include/spi.h" +#include "../../../include/gpio.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +struct ad9361_reg_dev { + /* SPI */ + spi_desc *spi_desc; + gpio_desc *gpio_desc_resetb; +}; + +struct ad9361_reg_init_param { + /* SPI */ + spi_init_param *spi_init; + gpio_init_param *gpio_resetb; +}; + +enum Operation_Type{ + AD9361_WRITE, + AD9361_READ, + AD9361_WAIT, + AD9361_WHEN +}; + +struct ad9361_reg_config { + int operation; + uint16_t val1; + uint16_t val2; +}; + + + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +int32_t ad9361_reg_read(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data); + +int32_t ad9361_reg_write(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t reg_data); + +int32_t ad9361_reg_init(struct ad9361_reg_dev **device, + const struct ad9361_reg_init_param *init_param); + +int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev); + +int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev); + +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/axi_io.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/axi_io.h new file mode 100644 index 00000000..92b689ab --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/axi_io.h @@ -0,0 +1,59 @@ +/***************************************************************************//** + * @file axi_io.h + * @brief Header file of AXI IO. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef AXI_IO_H_ +#define AXI_IO_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* AXI IO Read data */ +int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data); + +/* AXI IO Write data */ +int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data); + +#endif // AXI_IO_H_ diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/delay.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/delay.h new file mode 100644 index 00000000..7937a9d6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/delay.h @@ -0,0 +1,59 @@ +/***************************************************************************//** + * @file delay.h + * @brief Header file of Delay functions + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef DELAY_H_ +#define DELAY_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Generate microseconds delay. */ +void udelay(uint32_t usecs); + +/* Generate miliseconds delay. */ +void mdelay(uint32_t msecs); + +#endif // DELAY_H_ diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/error.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/error.h new file mode 100644 index 00000000..275b126d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/error.h @@ -0,0 +1,67 @@ +/***************************************************************************//** + * @file error.h + * @brief Error codes definition + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef ERROR_H_ +#define ERROR_H_ + +#include + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#ifdef SUCCESS +#undef SUCCESS +#endif +#define SUCCESS 0 +#ifdef FAILURE +#undef FAILURE +#endif +#define FAILURE -1 + +#ifndef __ELASTERROR +#define __ELASTERROR 2000 +#endif + +#define EOVERRUN (__ELASTERROR + 1) /* Circular buffer overrun */ + + +#define IS_ERR_VALUE(x) ((x) < 0) + +#endif // ERROR_H_ diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/gpio.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/gpio.h new file mode 100644 index 00000000..5c057cb4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/gpio.h @@ -0,0 +1,165 @@ +/***************************************************************************//** + * @file gpio.h + * @brief Header file of GPIO Interface + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef GPIO_H_ +#define GPIO_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define GPIO_OUT 0x01 +#define GPIO_IN 0x00 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @struct gpio_platform_ops + * @brief Structure holding gpio function pointers that point to the platform + * specific function + */ +struct gpio_platform_ops ; + +/** + * @struct gpio_init_param + * @brief Structure holding the parameters for GPIO initialization. + */ +typedef struct gpio_init_param { + /** GPIO number */ + int32_t number; + /** GPIO platform specific functions */ + const struct gpio_platform_ops *platform_ops; + /** GPIO extra parameters (device specific) */ + void *extra; +} gpio_init_param; + +/** + * @struct gpio_desc + * @brief Structure holding the GPIO descriptor. + */ +typedef struct gpio_desc { + /** GPIO number */ + int32_t number; + /** GPIO platform specific functions */ + const struct gpio_platform_ops *platform_ops; + /** GPIO extra parameters (device specific) */ + void *extra; +} gpio_desc; + +/** + * @enum gpio_values + * @brief Enum that holds the possible output states of a GPIO. + */ +enum gpio_values { + /** GPIO logic low */ + GPIO_LOW, + /** GPIO logic high */ + GPIO_HIGH, + /** GPIO high impedance */ + GPIO_HIGH_Z +}; + +/** + * @struct gpio_platform_ops + * @brief Structure holding gpio function pointers that point to the platform + * specific function + */ +struct gpio_platform_ops { + /** gpio initialization function pointer */ + int32_t (*gpio_ops_get)(struct gpio_desc **, const struct gpio_init_param *); + /** gpio optional descriptor function pointer */ + int32_t (*gpio_ops_get_optional)(struct gpio_desc **, + const struct gpio_init_param *); + /** gpio remove function pointer */ + int32_t (*gpio_ops_remove)(struct gpio_desc *); + /** gpio direction input function pointer */ + int32_t (*gpio_ops_direction_input)(struct gpio_desc *); + /** gpio direction output function pointer */ + int32_t (*gpio_ops_direction_output)(struct gpio_desc *, uint8_t); + /** gpio get direction function pointer */ + int32_t (*gpio_ops_get_direction)(struct gpio_desc *, uint8_t *); + /** gpio set value function pointer */ + int32_t (*gpio_ops_set_value)(struct gpio_desc *, uint8_t); + /** gpio get value function pointer */ + int32_t (*gpio_ops_get_value)(struct gpio_desc *, uint8_t *); +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Obtain the GPIO decriptor. */ +int32_t gpio_get(struct gpio_desc **desc, + const struct gpio_init_param *param); + +/* Obtain optional GPIO descriptor. */ +int32_t gpio_get_optional(struct gpio_desc **desc, + const struct gpio_init_param *param); + +/* Free the resources allocated by gpio_get() */ +int32_t gpio_remove(struct gpio_desc *desc); + +/* Enable the input direction of the specified GPIO. */ +int32_t gpio_direction_input(struct gpio_desc *desc); + +/* Enable the output direction of the specified GPIO. */ +int32_t gpio_direction_output(struct gpio_desc *desc, + uint8_t value); + +/* Get the direction of the specified GPIO. */ +int32_t gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction); + +/* Set the value of the specified GPIO. */ +int32_t gpio_set_value(struct gpio_desc *desc, + uint8_t value); + +/* Get the value of the specified GPIO. */ +int32_t gpio_get_value(struct gpio_desc *desc, + uint8_t *value); + +#endif // GPIO_H_ diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/irq.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/irq.h new file mode 100644 index 00000000..7db97e90 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/irq.h @@ -0,0 +1,188 @@ +/***************************************************************************//** + * @file irq.h + * @brief Header file of IRQ interface. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef IRQ_H_ +#define IRQ_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum irq_uart_event_e + * @brief Possible events for uart interrupt + */ +enum irq_uart_event_e { + /** Write operation finalized */ + IRQ_WRITE_DONE, + /** Read operation finalized */ + IRQ_READ_DONE, + /** An error occurred */ + IRQ_ERROR +}; + +enum irq_trig_level { + IRQ_LEVEL_LOW, + IRQ_LEVEL_HIGH, + IRQ_EDGE_FALLING, + IRQ_EDGE_RISING, + IRQ_EDGE_BOTH +}; + +/** + * @struct irq_platform_ops + * @brief Structure holding IRQ function pointers that point to the platform + * specific function + */ +struct irq_platform_ops ; + +/** + * @struct irq_init_param + * @brief Structure holding the initial parameters for Interrupt Request. + */ +struct irq_init_param { + /** Interrupt request controller ID. */ + uint32_t irq_ctrl_id; + /** Platform specific IRQ platform ops structure. */ + const struct irq_platform_ops *platform_ops; + /** IRQ extra parameters (device specific) */ + void *extra; +}; + +/** + * @struct irq_desc + * @brief Structure for Interrupt Request descriptor. + */ +struct irq_ctrl_desc { + /** Interrupt request controller ID. */ + uint32_t irq_ctrl_id; + /** Platform specific IRQ platform ops structure. */ + const struct irq_platform_ops *platform_ops; + /** IRQ extra parameters (device specific) */ + void *extra; +}; + +/** + * @struct callback_desc + * @brief Structure describing a callback to be registered + */ +struct callback_desc { + /** + * Callback to be called when the event an event occurs + * @param ctx - Same as \ref callback_desc.ctx + * @param event - Event that generated the callback + * @param extra - Platform specific data + */ + void (*callback)(void *ctx, uint32_t event, void *extra); + /** Parameter to be passed when the callback is called */ + void *ctx; + /** Platform specific configuration for a callback */ + void *config; +}; + +/** + * @struct irq_platform_ops + * @brief Structure holding IRQ function pointers that point to the platform + * specific function + */ +struct irq_platform_ops { + /** Initialize a interrupt controller peripheral. */ + int32_t (*init)(struct irq_ctrl_desc **desc, + const struct irq_init_param *param); + /** Register a callback to handle the irq events */ + int32_t (*register_callback)(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc); + /** Unregisters a generic IRQ handling function */ + int32_t (*unregister)(struct irq_ctrl_desc *desc, uint32_t irq_id); + /** Global interrupt enable */ + int32_t (*global_enable)(struct irq_ctrl_desc *desc); + /** Global interrupt disable */ + int32_t (*global_disable)(struct irq_ctrl_desc *desc); + /** Set interrupt trigger level. */ + int32_t (*trigger_level_set)(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig); + /** Enable specific interrupt */ + int32_t (*enable)(struct irq_ctrl_desc *desc, uint32_t irq_id); + /** Disable specific interrupt */ + int32_t (*disable)(struct irq_ctrl_desc *desc, uint32_t irq_id); + /** IRQ remove function pointer */ + int32_t (*remove)(struct irq_ctrl_desc *desc); +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Initialize a interrupt controller peripheral. */ +int32_t irq_ctrl_init(struct irq_ctrl_desc **desc, + const struct irq_init_param *param); + +/* Free the resources allocated by irq_ctrl_init(). */ +int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc); + +/* Register a callback to handle the irq events */ +int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc); + +/* Unregisters a generic IRQ handling function */ +int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id); + +/* Global interrupt enable */ +int32_t irq_global_enable(struct irq_ctrl_desc *desc); + +/* Global interrupt disable */ +int32_t irq_global_disable(struct irq_ctrl_desc *desc); + +/* Set interrupt trigger level. */ +int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig); + +/* Enable specific interrupt */ +int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id); + +/* Disable specific interrupt */ +int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id); + +#endif // IRQ_H_ diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/spi.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/spi.h new file mode 100644 index 00000000..0e9b8e0d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/spi.h @@ -0,0 +1,194 @@ +/***************************************************************************//** + * @file spi.h + * @brief Header file of SPI Interface + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef SPI_H_ +#define SPI_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define SPI_CPHA 0x01 +#define SPI_CPOL 0x02 +#define SPI_3WIRE 0x04 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum spi_mode + * @brief SPI configuration for clock phase and polarity. + */ +typedef enum spi_mode { + /** Data on rising, shift out on falling */ + SPI_MODE_0 = (0 | 0), + /** Data on falling, shift out on rising */ + SPI_MODE_1 = (0 | SPI_CPHA), + /** Data on falling, shift out on rising */ + SPI_MODE_2 = (SPI_CPOL | 0), + /** Data on rising, shift out on falling */ + SPI_MODE_3 = (SPI_CPOL | SPI_CPHA), + /** Data on rising, shift out on falling */ + SPI_MODE_4 = SPI_3WIRE +} spi_mode; + +/** + * @enum spi_bit_order + * @brief SPI configuration for bit order (MSB/LSB). + */ +typedef enum spi_bit_order { + /** Most-significant bit (MSB) first */ + SPI_BIT_ORDER_MSB_FIRST = 0, + /** Least-significant bit (LSB) first */ + SPI_BIT_ORDER_LSB_FIRST = 1, +} spi_bit_order; + +/** + * @struct spi_msg_list + * @brief List item describing a SPI transfer + */ +struct spi_msg { + /** Buffer with data to send. If NULL, 0x00 will be sent */ + uint8_t *tx_buff; + /** Buffer where to store data. If NULL, incoming data won't be saved */ + uint8_t *rx_buff; + /** Length of buffers. Must have equal size. */ + uint32_t bytes_number; + /** If set, CS will be deasserted after the transfer */ + uint8_t cs_change; +}; + +/** + * @struct spi_platform_ops + * @brief Structure holding SPI function pointers that point to the platform + * specific function + */ +struct spi_platform_ops ; + +/** + * @struct spi_init_param + * @brief Structure holding the parameters for SPI initialization + */ +typedef struct spi_init_param { + /** Device ID */ + uint32_t device_id; + /** maximum transfer speed */ + uint32_t max_speed_hz; + /** SPI chip select */ + uint8_t chip_select; + /** SPI mode */ + enum spi_mode mode; + /** SPI bit order */ + enum spi_bit_order bit_order; + const struct spi_platform_ops *platform_ops; + /** SPI extra parameters (device specific) */ + void *extra; +} spi_init_param; + +/** + * @struct spi_desc + * @brief Structure holding SPI descriptor. + */ +typedef struct spi_desc { + /** Device ID */ + uint32_t device_id; + /** maximum transfer speed */ + uint32_t max_speed_hz; + /** SPI chip select */ + uint8_t chip_select; + /** SPI mode */ + enum spi_mode mode; + /** SPI bit order */ + enum spi_bit_order bit_order; + const struct spi_platform_ops *platform_ops; + /** SPI extra parameters (device specific) */ + void *extra; +} spi_desc; + +/** + * @struct spi_platform_ops + * @brief Structure holding SPI function pointers that point to the platform + * specific function + */ +struct spi_platform_ops { + /** SPI initialization function pointer */ + int32_t (*init)(struct spi_desc **, const struct spi_init_param *); + /** SPI write/read function pointer */ + int32_t (*write_and_read)(struct spi_desc *, uint8_t *, uint16_t); + /** SPI write function pointer */ + int32_t (*write_and_read_3wire)(struct spi_desc *, uint8_t *,uint8_t *,uint16_t, uint16_t); + /** Iterate over the spi_msg array and send all messages at once */ + int32_t (*transfer)(struct spi_desc *, struct spi_msg *, uint32_t); + /** SPI remove function pointer */ + int32_t (*remove)(struct spi_desc *); +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Initialize the SPI communication peripheral. */ +int32_t spi_init(struct spi_desc **desc, + const struct spi_init_param *param); + +/* Free the resources allocated by spi_init(). */ +int32_t spi_remove(struct spi_desc *desc); + +/* Write and read data to/from SPI. */ +int32_t spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number); +int32_t spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number); + +/* Iterate over the spi_msg array and send all messages at once */ +int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len); + + +#endif // SPI_H_ diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/util.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/util.h new file mode 100644 index 00000000..4255cd96 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/include/util.h @@ -0,0 +1,165 @@ +/***************************************************************************//** + * @file util.h + * @brief Implementation of utility functions. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef UTIL_H_ +#define UTIL_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#define BIT(x) (1 << (x)) + +#define ARRAY_SIZE(x) \ + (sizeof(x) / sizeof((x)[0])) + +#define DIV_ROUND_UP(x,y) \ + (((x) + (y) - 1) / (y)) +#define DIV_ROUND_CLOSEST(x, y) \ + (((x) + (y) / 2) / (y)) +#define DIV_ROUND_CLOSEST_ULL(x, y) \ + DIV_ROUND_CLOSEST(x, y) + +#define min(x, y) \ + (((x) < (y)) ? (x) : (y)) +#define min_t(type, x, y) \ + (type)min((type)(x), (type)(y)) + +#define max(x, y) \ + (((x) > (y)) ? (x) : (y)) +#define max_t(type, x, y) \ + (type)max((type)(x), (type)(y)) + +#define clamp(val, min_val, max_val) \ + (max(min((val), (max_val)), (min_val))) +#define clamp_t(type, val, min_val, max_val) \ + (type)clamp((type)(val), (type)(min_val), (type)(max_val)) + +#define swap(x, y) \ + {typeof(x) _tmp_ = (x); (x) = (y); (y) = _tmp_;} + +#define round_up(x,y) \ + (((x)+(y)-1)/(y)) + +#define BITS_PER_LONG 32 + +#define GENMASK(h, l) ({ \ + uint32_t t = (uint32_t)(~0UL); \ + t = t << (BITS_PER_LONG - (h - l + 1)); \ + t = t >> (BITS_PER_LONG - (h + 1)); \ + t; \ +}) + +#define bswap_constant_32(x) \ + ((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | (((x) & 0x000000ff) << 24)) + +#define bswap_constant_16(x) ((((x) & (uint16_t)0xff00) >> 8) | \ + (((x) & (uint16_t)0x00ff) << 8)) + +#define bit_swap_constant_8(x) \ + ((((x) & 0x80) >> 7) | \ + (((x) & 0x40) >> 5) | \ + (((x) & 0x20) >> 3) | \ + (((x) & 0x10) >> 1) | \ + (((x) & 0x08) << 1) | \ + (((x) & 0x04) << 3) | \ + (((x) & 0x02) << 5) | \ + (((x) & 0x01) << 7)) + +#define U16_MAX ((uint16_t)~0U) +#define S16_MAX ((int16_t)(U16_MAX>>1)) + +#define DIV_U64(x, y) (x / y) + +#define UNUSED_PARAM(x) ((void)x) + +#define shift_right(x, s) ((x) < 0 ? -(-(x) >> (s)) : (x) >> (s)) + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ +/* Find first set bit in word. */ +uint32_t find_first_set_bit(uint32_t word); +/* Find last set bit in word. */ +uint32_t find_last_set_bit(uint32_t word); +/* Locate the closest element in an array. */ +uint32_t find_closest(int32_t val, + const int32_t *array, + uint32_t size); +/* Shift the value and apply the specified mask. */ +uint32_t field_prep(uint32_t mask, uint32_t val); +/* Get a field specified by a mask from a word. */ +uint32_t field_get(uint32_t mask, uint32_t word); +/* Log base 2 of the given number. */ +int32_t log_base_2(uint32_t x); +/* Find greatest common divisor of the given two numbers. */ +uint32_t greatest_common_divisor(uint32_t a, + uint32_t b); +/* Calculate best rational approximation for a given fraction. */ +void rational_best_approximation(uint32_t given_numerator, + uint32_t given_denominator, + uint32_t max_numerator, + uint32_t max_denominator, + uint32_t *best_numerator, + uint32_t *best_denominator); +/* Calculate the number of set bits. */ +uint32_t hweight8(uint32_t word); +/* Calculate the quotient and the remainder of an integer division. */ +uint64_t do_div(uint64_t* n, + uint64_t base); +/* Unsigned 64bit divide with 64bit divisor and remainder */ +uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, + uint64_t *remainder); +/* Unsigned 64bit divide with 32bit divisor with remainder */ +uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder); +int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder); +/* Unsigned 64bit divide with 32bit divisor */ +uint64_t div_u64(uint64_t dividend, uint32_t divisor); +int64_t div_s64(int64_t dividend, int32_t divisor); +/* Converts from string to int32_t */ +int32_t str_to_int32(const char *str); +/* Converts from string to uint32_t */ +uint32_t srt_to_uint32(const char *str); +#endif // UTIL_H_ + diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/util/util.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/util/util.c new file mode 100644 index 00000000..58c6a83f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/adi_noos/util/util.c @@ -0,0 +1,283 @@ +/***************************************************************************//** + * @file util.c + * @brief Implementation of utility functions. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include "errno.h" +#include "../include/util.h" + +/******************************************************************************/ +/************************** Functions Implementation **************************/ +/******************************************************************************/ + +/** + * Find first set bit in word. + */ +uint32_t find_first_set_bit(uint32_t word) +{ + uint32_t first_set_bit = 0; + + while (word) { + if (word & 0x1) + return first_set_bit; + word >>= 1; + first_set_bit ++; + } + + return 32; +} + +/** + * Find last set bit in word. + */ +uint32_t find_last_set_bit(uint32_t word) +{ + uint32_t bit = 0; + uint32_t last_set_bit = 32; + + while (word) { + if (word & 0x1) + last_set_bit = bit; + word >>= 1; + bit ++; + } + + return last_set_bit; +} + +/** + * Locate the closest element in an array. + */ +uint32_t find_closest(int32_t val, + const int32_t *array, + uint32_t size) +{ + int32_t diff = abs(array[0] - val); + uint32_t ret = 0; + uint32_t i; + + for (i = 1; i < size; i++) { + if (abs(array[i] - val) < diff) { + diff = abs(array[i] - val); + ret = i; + } + } + + return ret; +} + +/** + * Shift the value and apply the specified mask. + */ +uint32_t field_prep(uint32_t mask, uint32_t val) +{ + return (val << find_first_set_bit(mask)) & mask; +} + +/** + * Get a field specified by a mask from a word. + */ +uint32_t field_get(uint32_t mask, uint32_t word) +{ + return (word & mask) >> find_first_set_bit(mask); +} + +/** + * Log base 2 of the given number. + */ +int32_t log_base_2(uint32_t x) +{ + return find_last_set_bit(x); +} + +/** + * Find greatest common divisor of the given two numbers. + */ +uint32_t greatest_common_divisor(uint32_t a, + uint32_t b) +{ + uint32_t div; + uint32_t common_div = 1; + + if ((a == 0) || (b == 0)) + return max(a, b); + + for (div = 1; (div <= a) && (div <= b); div++) + if (!(a % div) && !(b % div)) + common_div = div; + + return common_div; +} + +/** + * Calculate best rational approximation for a given fraction. + */ +void rational_best_approximation(uint32_t given_numerator, + uint32_t given_denominator, + uint32_t max_numerator, + uint32_t max_denominator, + uint32_t *best_numerator, + uint32_t *best_denominator) +{ + uint32_t gcd; + + gcd = greatest_common_divisor(given_numerator, given_denominator); + + *best_numerator = given_numerator / gcd; + *best_denominator = given_denominator / gcd; + + if ((*best_numerator > max_numerator) || + (*best_denominator > max_denominator)) { + *best_numerator = 0; + *best_denominator = 0; + } +} + +/** + * Calculate the number of set bits. + */ +uint32_t hweight8(uint32_t word) +{ + uint32_t count = 0; + + while (word) { + if (word & 0x1) + count++; + word >>= 1; + } + + return count; +} + +/** + * Calculate the quotient and the remainder of an integer division. + */ +uint64_t do_div(uint64_t* n, + uint64_t base) +{ + uint64_t mod = 0; + + mod = *n % base; + *n = *n / base; + + return mod; +} + +/** + * Unsigned 64bit divide with 64bit divisor and remainder + */ +uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder) +{ + *remainder = dividend % divisor; + + return dividend / divisor; +} + +/** + * Unsigned 64bit divide with 32bit divisor with remainder + */ +uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) +{ + *remainder = do_div(÷nd, divisor); + + return dividend; +} + +/** + * Signed 64bit divide with 32bit divisor with remainder + */ +int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder) +{ + *remainder = dividend % divisor; + return dividend / divisor; +} + +/** + * Unsigned 64bit divide with 32bit divisor + */ +uint64_t div_u64(uint64_t dividend, uint32_t divisor) +{ + uint32_t remainder; + + return div_u64_rem(dividend, divisor, &remainder); +} + +/** + * Signed 64bit divide with 32bit divisor + */ +int64_t div_s64(int64_t dividend, int32_t divisor) +{ + int32_t remainder; + return div_s64_rem(dividend, divisor, &remainder); +} + +/** + * Converts from string to int32_t + * @param *str + * @return int32_t + */ +int32_t str_to_int32(const char *str) +{ + char *end; + int32_t value = strtol(str, &end, 0); + + if (end == str) + return -EINVAL; + else + return value; +} + +/** + * Converts from string to uint32_t + * @param *str + * @return uint32_t + */ +uint32_t srt_to_uint32(const char *str) +{ + char *end; + uint32_t value = strtoul(str, &end, 0); + + if (end == str) + return -EINVAL; + else + return value; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/app_config.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/app_config.h new file mode 100644 index 00000000..d8ec3859 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/app_config.h @@ -0,0 +1,55 @@ +/***************************************************************************//** + * @file app_config.h + * @brief Config file of AD9361/API Driver. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2015(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef CONFIG_H_ +#define CONFIG_H_ + +#define XILINX_PLATFORM +#define SPI_INTERFACE_SPI_ENGINE + +#define HAVE_SPLIT_GAIN_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ +#define HAVE_TDD_SYNTH_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ + +#define AD9361_DEVICE 1 /* set it 1 if AD9361 device is used, 0 otherwise */ +#define AD9364_DEVICE 0 /* set it 1 if AD9364 device is used, 0 otherwise */ +#define AD9363A_DEVICE 0 /* set it 1 if AD9363A device is used, 0 otherwise */ + +#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */ +//#define HAVE_DEBUG_MESSAGES /* For Debug purposes only */ + +#endif diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/ad9361_profile.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/ad9361_profile.c new file mode 100644 index 00000000..50fb0456 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/ad9361_profile.c @@ -0,0 +1,325 @@ +#include "dev_profile.h" +#include "../app_config.h" +#include "../adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.h" + +AD9361_InitParam ad9361_default_init_param = { + /* Device selection */ + ID_AD9361, // dev_sel + /* Reference Clock */ + 48000000UL, //reference_clk_rate + /* Base Configuration */ + 1, //two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable + 1, //one_rx_one_tx_mode_use_rx_num *** adi,1rx-1tx-mode-use-rx-num + 1, //one_rx_one_tx_mode_use_tx_num *** adi,1rx-1tx-mode-use-tx-num + 1, //frequency_division_duplex_mode_enable *** adi,frequency-division-duplex-mode-enable + 0, //frequency_division_duplex_independent_mode_enable *** adi,frequency-division-duplex-independent-mode-enable + 0, //tdd_use_dual_synth_mode_enable *** adi,tdd-use-dual-synth-mode-enable + 0, //tdd_skip_vco_cal_enable *** adi,tdd-skip-vco-cal-enable + 0, //tx_fastlock_delay_ns *** adi,tx-fastlock-delay-ns + 0, //rx_fastlock_delay_ns *** adi,rx-fastlock-delay-ns + 0, //rx_fastlock_pincontrol_enable *** adi,rx-fastlock-pincontrol-enable + 0, //tx_fastlock_pincontrol_enable *** adi,tx-fastlock-pincontrol-enable + 0, //external_rx_lo_enable *** adi,external-rx-lo-enable + 0, //external_tx_lo_enable *** adi,external-tx-lo-enable + 5, //dc_offset_tracking_update_event_mask *** adi,dc-offset-tracking-update-event-mask + 6, //dc_offset_attenuation_high_range *** adi,dc-offset-attenuation-high-range + 5, //dc_offset_attenuation_low_range *** adi,dc-offset-attenuation-low-range + 0x28, //dc_offset_count_high_range *** adi,dc-offset-count-high-range + 0x32, //dc_offset_count_low_range *** adi,dc-offset-count-low-range + 0, //split_gain_table_mode_enable *** adi,split-gain-table-mode-enable + MAX_SYNTH_FREF, //trx_synthesizer_target_fref_overwrite_hz *** adi,trx-synthesizer-target-fref-overwrite-hz + 0, // qec_tracking_slow_mode_enable *** adi,qec-tracking-slow-mode-enable + /* ENSM Control */ + 0, //ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable + 0, //ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable + /* LO Control */ + 4125000000UL, //rx_synthesizer_frequency_hz *** adi,rx-synthesizer-frequency-hz + 4126000000UL, //tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz + 1, //tx_lo_powerdown_managed_enable *** adi,tx-lo-powerdown-managed-enable + /* Rate & BW Control */ + {768000000, 192000000, 96000000, 48000000, 24000000, 24000000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies + {768000000, 192000000, 96000000, 48000000, 24000000, 24000000},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies + 18000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz + 18000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz + /* RF Port Control */ + 0, //rx_rf_port_input_select *** adi,rx-rf-port-input-select + 0, //tx_rf_port_input_select *** adi,tx-rf-port-input-select + /* TX Attenuation Control */ + 10000, //tx_attenuation_mdB *** adi,tx-attenuation-mdB + 0, //update_tx_gain_in_alert_enable *** adi,update-tx-gain-in-alert-enable + /* Reference Clock Control */ + 0, //xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable + {8, 5920}, //dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune + CLKOUT_DISABLE, //clk_output_mode_select *** adi,clk-output-mode-select + /* Gain Control */ + 2, //gc_rx1_mode *** adi,gc-rx1-mode + 2, //gc_rx2_mode *** adi,gc-rx2-mode + 58, //gc_adc_large_overload_thresh *** adi,gc-adc-large-overload-thresh + 4, //gc_adc_ovr_sample_size *** adi,gc-adc-ovr-sample-size + 47, //gc_adc_small_overload_thresh *** adi,gc-adc-small-overload-thresh + 8192, //gc_dec_pow_measurement_duration *** adi,gc-dec-pow-measurement-duration + 0, //gc_dig_gain_enable *** adi,gc-dig-gain-enable + 800, //gc_lmt_overload_high_thresh *** adi,gc-lmt-overload-high-thresh + 704, //gc_lmt_overload_low_thresh *** adi,gc-lmt-overload-low-thresh + 24, //gc_low_power_thresh *** adi,gc-low-power-thresh + 15, //gc_max_dig_gain *** adi,gc-max-dig-gain + 0, //gc_use_rx_fir_out_for_dec_pwr_meas_enable *** adi,gc-use-rx-fir-out-for-dec-pwr-meas-enable + /* Gain MGC Control */ + 2, //mgc_dec_gain_step *** adi,mgc-dec-gain-step + 2, //mgc_inc_gain_step *** adi,mgc-inc-gain-step + 0, //mgc_rx1_ctrl_inp_enable *** adi,mgc-rx1-ctrl-inp-enable + 0, //mgc_rx2_ctrl_inp_enable *** adi,mgc-rx2-ctrl-inp-enable + 0, //mgc_split_table_ctrl_inp_gain_mode *** adi,mgc-split-table-ctrl-inp-gain-mode + /* Gain AGC Control */ + 10, //agc_adc_large_overload_exceed_counter *** adi,agc-adc-large-overload-exceed-counter + 2, //agc_adc_large_overload_inc_steps *** adi,agc-adc-large-overload-inc-steps + 0, //agc_adc_lmt_small_overload_prevent_gain_inc_enable *** adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable + 10, //agc_adc_small_overload_exceed_counter *** adi,agc-adc-small-overload-exceed-counter + 4, //agc_dig_gain_step_size *** adi,agc-dig-gain-step-size + 3, //agc_dig_saturation_exceed_counter *** adi,agc-dig-saturation-exceed-counter + 1000, // agc_gain_update_interval_us *** adi,agc-gain-update-interval-us + 0, //agc_immed_gain_change_if_large_adc_overload_enable *** adi,agc-immed-gain-change-if-large-adc-overload-enable + 0, //agc_immed_gain_change_if_large_lmt_overload_enable *** adi,agc-immed-gain-change-if-large-lmt-overload-enable + 10, //agc_inner_thresh_high *** adi,agc-inner-thresh-high + 1, //agc_inner_thresh_high_dec_steps *** adi,agc-inner-thresh-high-dec-steps + 12, //agc_inner_thresh_low *** adi,agc-inner-thresh-low + 1, //agc_inner_thresh_low_inc_steps *** adi,agc-inner-thresh-low-inc-steps + 10, //agc_lmt_overload_large_exceed_counter *** adi,agc-lmt-overload-large-exceed-counter + 2, //agc_lmt_overload_large_inc_steps *** adi,agc-lmt-overload-large-inc-steps + 10, //agc_lmt_overload_small_exceed_counter *** adi,agc-lmt-overload-small-exceed-counter + 5, //agc_outer_thresh_high *** adi,agc-outer-thresh-high + 2, //agc_outer_thresh_high_dec_steps *** adi,agc-outer-thresh-high-dec-steps + 18, //agc_outer_thresh_low *** adi,agc-outer-thresh-low + 2, //agc_outer_thresh_low_inc_steps *** adi,agc-outer-thresh-low-inc-steps + 1, //agc_attack_delay_extra_margin_us; *** adi,agc-attack-delay-extra-margin-us + 0, //agc_sync_for_gain_counter_enable *** adi,agc-sync-for-gain-counter-enable + /* Fast AGC */ + 64, //fagc_dec_pow_measuremnt_duration *** adi,fagc-dec-pow-measurement-duration + 260, //fagc_state_wait_time_ns *** adi,fagc-state-wait-time-ns + /* Fast AGC - Low Power */ + 0, //fagc_allow_agc_gain_increase *** adi,fagc-allow-agc-gain-increase-enable + 5, //fagc_lp_thresh_increment_time *** adi,fagc-lp-thresh-increment-time + 1, //fagc_lp_thresh_increment_steps *** adi,fagc-lp-thresh-increment-steps + /* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */ + 1, //fagc_lock_level_lmt_gain_increase_en *** adi,fagc-lock-level-lmt-gain-increase-enable + 5, //fagc_lock_level_gain_increase_upper_limit *** adi,fagc-lock-level-gain-increase-upper-limit + /* Fast AGC - Peak Detectors and Final Settling */ + 1, //fagc_lpf_final_settling_steps *** adi,fagc-lpf-final-settling-steps + 1, //fagc_lmt_final_settling_steps *** adi,fagc-lmt-final-settling-steps + 3, //fagc_final_overrange_count *** adi,fagc-final-overrange-count + /* Fast AGC - Final Power Test */ + 0, //fagc_gain_increase_after_gain_lock_en *** adi,fagc-gain-increase-after-gain-lock-enable + /* Fast AGC - Unlocking the Gain */ + 0, //fagc_gain_index_type_after_exit_rx_mode *** adi,fagc-gain-index-type-after-exit-rx-mode + 1, //fagc_use_last_lock_level_for_set_gain_en *** adi,fagc-use-last-lock-level-for-set-gain-enable + 1, //fagc_rst_gla_stronger_sig_thresh_exceeded_en *** adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable + 5, //fagc_optimized_gain_offset *** adi,fagc-optimized-gain-offset + 10, //fagc_rst_gla_stronger_sig_thresh_above_ll *** adi,fagc-rst-gla-stronger-sig-thresh-above-ll + 1, //fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en *** adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable + 1, //fagc_rst_gla_engergy_lost_goto_optim_gain_en *** adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable + 10, //fagc_rst_gla_engergy_lost_sig_thresh_below_ll *** adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll + 8, //fagc_energy_lost_stronger_sig_gain_lock_exit_cnt *** adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt + 1, //fagc_rst_gla_large_adc_overload_en *** adi,fagc-rst-gla-large-adc-overload-enable + 1, //fagc_rst_gla_large_lmt_overload_en *** adi,fagc-rst-gla-large-lmt-overload-enable + 0, //fagc_rst_gla_en_agc_pulled_high_en *** adi,fagc-rst-gla-en-agc-pulled-high-enable + 0, //fagc_rst_gla_if_en_agc_pulled_high_mode *** adi,fagc-rst-gla-if-en-agc-pulled-high-mode + 64, //fagc_power_measurement_duration_in_state5 *** adi,fagc-power-measurement-duration-in-state5 + 2, //fagc_large_overload_inc_steps *** adi,fagc-adc-large-overload-inc-steps + /* RSSI Control */ + 1, //rssi_delay *** adi,rssi-delay + 1000, //rssi_duration *** adi,rssi-duration + 3, //rssi_restart_mode *** adi,rssi-restart-mode + 0, //rssi_unit_is_rx_samples_enable *** adi,rssi-unit-is-rx-samples-enable + 1, //rssi_wait *** adi,rssi-wait + /* Aux ADC Control */ + 256, //aux_adc_decimation *** adi,aux-adc-decimation + 48000000UL, //aux_adc_rate *** adi,aux-adc-rate + /* AuxDAC Control */ + 1, //aux_dac_manual_mode_enable *** adi,aux-dac-manual-mode-enable + 0, //aux_dac1_default_value_mV *** adi,aux-dac1-default-value-mV + 0, //aux_dac1_active_in_rx_enable *** adi,aux-dac1-active-in-rx-enable + 0, //aux_dac1_active_in_tx_enable *** adi,aux-dac1-active-in-tx-enable + 0, //aux_dac1_active_in_alert_enable *** adi,aux-dac1-active-in-alert-enable + 0, //aux_dac1_rx_delay_us *** adi,aux-dac1-rx-delay-us + 0, //aux_dac1_tx_delay_us *** adi,aux-dac1-tx-delay-us + 0, //aux_dac2_default_value_mV *** adi,aux-dac2-default-value-mV + 0, //aux_dac2_active_in_rx_enable *** adi,aux-dac2-active-in-rx-enable + 0, //aux_dac2_active_in_tx_enable *** adi,aux-dac2-active-in-tx-enable + 0, //aux_dac2_active_in_alert_enable *** adi,aux-dac2-active-in-alert-enable + 0, //aux_dac2_rx_delay_us *** adi,aux-dac2-rx-delay-us + 0, //aux_dac2_tx_delay_us *** adi,aux-dac2-tx-delay-us + /* Temperature Sensor Control */ + 256, //temp_sense_decimation *** adi,temp-sense-decimation + 1000, //temp_sense_measurement_interval_ms *** adi,temp-sense-measurement-interval-ms + 0xCE, //temp_sense_offset_signed *** adi,temp-sense-offset-signed + 1, //temp_sense_periodic_measurement_enable *** adi,temp-sense-periodic-measurement-enable + /* Control Out Setup */ + 0xFF, //ctrl_outs_enable_mask *** adi,ctrl-outs-enable-mask + 0, //ctrl_outs_index *** adi,ctrl-outs-index + /* External LNA Control */ + 0, //elna_settling_delay_ns *** adi,elna-settling-delay-ns + 0, //elna_gain_mdB *** adi,elna-gain-mdB + 0, //elna_bypass_loss_mdB *** adi,elna-bypass-loss-mdB + 0, //elna_rx1_gpo0_control_enable *** adi,elna-rx1-gpo0-control-enable + 0, //elna_rx2_gpo1_control_enable *** adi,elna-rx2-gpo1-control-enable + 0, //elna_gaintable_all_index_enable *** adi,elna-gaintable-all-index-enable + /* Digital Interface Control */ + 0, //digital_interface_tune_skip_mode *** adi,digital-interface-tune-skip-mode + 0, //digital_interface_tune_fir_disable *** adi,digital-interface-tune-fir-disable + 1, //pp_tx_swap_enable *** adi,pp-tx-swap-enable + 1, //pp_rx_swap_enable *** adi,pp-rx-swap-enable + 0, //tx_channel_swap_enable *** adi,tx-channel-swap-enable + 0, //rx_channel_swap_enable *** adi,rx-channel-swap-enable + 1, //rx_frame_pulse_mode_enable *** adi,rx-frame-pulse-mode-enable + 0, //two_t_two_r_timing_enable *** adi,2t2r-timing-enable + 0, //invert_data_bus_enable *** adi,invert-data-bus-enable + 0, //invert_data_clk_enable *** adi,invert-data-clk-enable + 0, //fdd_alt_word_order_enable *** adi,fdd-alt-word-order-enable + 0, //invert_rx_frame_enable *** adi,invert-rx-frame-enable + 0, //fdd_rx_rate_2tx_enable *** adi,fdd-rx-rate-2tx-enable + 0, //swap_ports_enable *** adi,swap-ports-enable + 0, //single_data_rate_enable *** adi,single-data-rate-enable + 1, //lvds_mode_enable *** adi,lvds-mode-enable + 0, //half_duplex_mode_enable *** adi,half-duplex-mode-enable + 0, //single_port_mode_enable *** adi,single-port-mode-enable + 0, //full_port_enable *** adi,full-port-enable + 0, //full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable + 0, //delay_rx_data *** adi,delay-rx-data + 0, //rx_data_clock_delay *** adi,rx-data-clock-delay + 4, //rx_data_delay *** adi,rx-data-delay + 7, //tx_fb_clock_delay *** adi,tx-fb-clock-delay + 0, //tx_data_delay *** adi,tx-data-delay + 150, //lvds_bias_mV *** adi,lvds-bias-mV + 1, //lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable + 0, //rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable + 0xFF, //lvds_invert1_control *** adi,lvds-invert1-control + 0x0F, //lvds_invert2_control *** adi,lvds-invert2-control + /* GPO Control */ + 0, //gpo_manual_mode_enable *** adi,gpo-manual-mode-enable + 0, //gpo_manual_mode_enable_mask *** adi,gpo-manual-mode-enable-mask + 0, //gpo0_inactive_state_high_enable *** adi,gpo0-inactive-state-high-enable + 0, //gpo1_inactive_state_high_enable *** adi,gpo1-inactive-state-high-enable + 0, //gpo2_inactive_state_high_enable *** adi,gpo2-inactive-state-high-enable + 0, //gpo3_inactive_state_high_enable *** adi,gpo3-inactive-state-high-enable + 0, //gpo0_slave_rx_enable *** adi,gpo0-slave-rx-enable + 0, //gpo0_slave_tx_enable *** adi,gpo0-slave-tx-enable + 0, //gpo1_slave_rx_enable *** adi,gpo1-slave-rx-enable + 0, //gpo1_slave_tx_enable *** adi,gpo1-slave-tx-enable + 0, //gpo2_slave_rx_enable *** adi,gpo2-slave-rx-enable + 0, //gpo2_slave_tx_enable *** adi,gpo2-slave-tx-enable + 0, //gpo3_slave_rx_enable *** adi,gpo3-slave-rx-enable + 0, //gpo3_slave_tx_enable *** adi,gpo3-slave-tx-enable + 0, //gpo0_rx_delay_us *** adi,gpo0-rx-delay-us + 0, //gpo0_tx_delay_us *** adi,gpo0-tx-delay-us + 0, //gpo1_rx_delay_us *** adi,gpo1-rx-delay-us + 0, //gpo1_tx_delay_us *** adi,gpo1-tx-delay-us + 0, //gpo2_rx_delay_us *** adi,gpo2-rx-delay-us + 0, //gpo2_tx_delay_us *** adi,gpo2-tx-delay-us + 0, //gpo3_rx_delay_us *** adi,gpo3-rx-delay-us + 0, //gpo3_tx_delay_us *** adi,gpo3-tx-delay-us + /* Tx Monitor Control */ + 37000, //low_high_gain_threshold_mdB *** adi,txmon-low-high-thresh + 0, //low_gain_dB *** adi,txmon-low-gain + 24, //high_gain_dB *** adi,txmon-high-gain + 0, //tx_mon_track_en *** adi,txmon-dc-tracking-enable + 0, //one_shot_mode_en *** adi,txmon-one-shot-mode-enable + 511, //tx_mon_delay *** adi,txmon-delay + 8192, //tx_mon_duration *** adi,txmon-duration + 2, //tx1_mon_front_end_gain *** adi,txmon-1-front-end-gain + 2, //tx2_mon_front_end_gain *** adi,txmon-2-front-end-gain + 48, //tx1_mon_lo_cm *** adi,txmon-1-lo-cm + 48, //tx2_mon_lo_cm *** adi,txmon-2-lo-cm + /* GPIO definitions */ + /* Reset_b */ + { + .number = AD9361_1_RESET_B, + .platform_ops = GPIO_OPS, + .extra = GPIO_PARAM + }, //gpio_resetb *** reset-gpios + /* MCS Sync */ + { + .number = -1, + .platform_ops = GPIO_OPS, + .extra = GPIO_PARAM + }, //gpio_sync *** sync-gpios + /* Cal-SW1 */ + { + .number = -1, + .platform_ops = GPIO_OPS, + .extra = GPIO_PARAM + }, //gpio_cal_sw1 *** cal-sw1-gpios + /* Cal-SW2 */ + { + .number = -1, + .platform_ops = GPIO_OPS, + .extra = GPIO_PARAM + }, //gpio_cal_sw2 *** cal-sw2-gpios + + { + .device_id = SPI_DEVICE_ID, + .mode = SPI_MODE_1, + .chip_select = SPI_CS_AD9361_1, + .platform_ops = SPI_OPS, + .extra = SPI_PARAM + }, + + /* External LO clocks */ + NULL, //(*ad9361_rfpll_ext_recalc_rate)() + NULL, //(*ad9361_rfpll_ext_round_rate)() + NULL, //(*ad9361_rfpll_ext_set_rate)() +}; + +AD9361_RXFIRConfig rx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs + 3, // rx + 0, // rx_gain + 1, // rx_dec + { + -4, -6, -37, 35, 186, 86, -284, -315, + 107, 219, -4, 271, 558, -307, -1182, -356, + 658, 157, 207, 1648, 790, -2525, -2553, 748, + 865, -476, 3737, 6560, -3583, -14731, -5278, 14819, + 14819, -5278, -14731, -3583, 6560, 3737, -476, 865, + 748, -2553, -2525, 790, 1648, 207, 157, 658, + -356, -1182, -307, 558, 271, -4, 219, 107, + -315, -284, 86, 186, 35, -37, -6, -4, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, // rx_coef[128] + 64, // rx_coef_size + {0, 0, 0, 0, 0, 0}, //rx_path_clks[6] + 0 // rx_bandwidth +}; + +AD9361_TXFIRConfig tx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs + 3, // tx + -6, // tx_gain + 1, // tx_int + { + -4, -6, -37, 35, 186, 86, -284, -315, + 107, 219, -4, 271, 558, -307, -1182, -356, + 658, 157, 207, 1648, 790, -2525, -2553, 748, + 865, -476, 3737, 6560, -3583, -14731, -5278, 14819, + 14819, -5278, -14731, -3583, 6560, 3737, -476, 865, + 748, -2553, -2525, 790, 1648, 207, 157, 658, + -356, -1182, -307, 558, 271, -4, 219, 107, + -315, -284, 86, 186, 35, -37, -6, -4, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, // tx_coef[128] + 64, // tx_coef_size + {0, 0, 0, 0, 0, 0}, // tx_path_clks[6] + 0 // tx_bandwidth +}; + diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/ad9361_reg_profile.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/ad9361_reg_profile.c new file mode 100644 index 00000000..a6707ddc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/ad9361_reg_profile.c @@ -0,0 +1,1730 @@ +#include "dev_profile.h" +#include "../app_config.h" +#include "../adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h" + +#define TIMEOUT_TH 2000 + +// ad9361-1 +static spi_init_param ad9361_1_reg_spi_init = { + .device_id = SPI_DEVICE_ID, + .max_speed_hz = SPI_ENGINE_MAX_SPEED, + .mode = SPI_MODE_1, + .chip_select = SPI_CS_AD9361_1, + .platform_ops = SPI_OPS, + .extra = SPI_PARAM +}; + +static gpio_init_param ad9361_1_reg_gpio_resetb_init = { + .number = AD9361_1_RESET_B, + .platform_ops = GPIO_OPS, + .extra = GPIO_PARAM +}; +struct ad9361_reg_init_param ad9361_1_reg_default_init_param = { + /* SPI */ + .spi_init = &ad9361_1_reg_spi_init, + .gpio_resetb = &ad9361_1_reg_gpio_resetb_init +}; + +// ad9361-2 +static spi_init_param ad9361_2_reg_spi_init = { + .device_id = SPI_DEVICE_ID, + .max_speed_hz = SPI_ENGINE_MAX_SPEED, + .mode = SPI_MODE_1, + .chip_select = SPI_CS_AD9361_2, + .platform_ops = SPI_OPS, + .extra = SPI_PARAM +}; + +static gpio_init_param ad9361_2_reg_gpio_resetb_init = { + .number = AD9361_2_RESET_B, + .platform_ops = GPIO_OPS, + .extra = GPIO_PARAM +}; +struct ad9361_reg_init_param ad9361_2_reg_default_init_param = { + /* SPI */ + .spi_init = &ad9361_2_reg_spi_init, + .gpio_resetb = &ad9361_2_reg_gpio_resetb_init +}; + +uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){ + int32_t status = 0; + uint8_t value = 0; + int32_t time_out_cnt = 0; + +//************************************************************ +// AD9361 R2 Auto Generated Initialization Script: This script was +// generated using the AD9361 Customer software Version 2.1.3 +//************************************************************ +// Profile: Custom +// REFCLK_IN: 25.000 MHz + + + status = ad9361_reg_write(dev, 0x03DF, 0x01); // Required for proper operation + status = ad9361_reg_write(dev, 0x02A6, 0x0E); // Enable Master Bias + status = ad9361_reg_write(dev, 0x02A8, 0x0E); // Set Bandgap Trim + status = ad9361_reg_write(dev, 0x02AB, 0x07); // Set RF PLL reflclk scale to REFCLK * 2 + status = ad9361_reg_write(dev, 0x02AC, 0xFF); // Set RF PLL reflclk scale to REFCLK * 2 + status = ad9361_reg_write(dev, 0x0009, 0x17); // Enable Clocks + mdelay(20) ;// waits 20 ms + +//************************************************************ +// Set BBPLL Frequency: 1152.000000 +//************************************************************ + status = ad9361_reg_write(dev, 0x0045, 0x03); // Set BBPLL reflclk scale to REFCLK * 2 + status = ad9361_reg_write(dev, 0x0046, 0x03); // Set BBPLL Loop Filter Charge Pump current + status = ad9361_reg_write(dev, 0x0048, 0xE8); // Set BBPLL Loop Filter C1, R1 + status = ad9361_reg_write(dev, 0x0049, 0x5B); // Set BBPLL Loop Filter R2, C2, C1 + status = ad9361_reg_write(dev, 0x004A, 0x35); // Set BBPLL Loop Filter C3,R2 + status = ad9361_reg_write(dev, 0x004B, 0xE0); // Allow calibration to occur and set cal count to 1024 for max accuracy + status = ad9361_reg_write(dev, 0x004E, 0x10); // Set calibration clock to REFCLK/4 for more accuracy + status = ad9361_reg_write(dev, 0x0043, 0x66); // BBPLL Freq Word (Fractional[7:0]) + status = ad9361_reg_write(dev, 0x0042, 0x46); // BBPLL Freq Word (Fractional[15:8]) + status = ad9361_reg_write(dev, 0x0041, 0x01); // BBPLL Freq Word (Fractional[23:16]) + status = ad9361_reg_write(dev, 0x0044, 0x17); // BBPLL Freq Word (Integer[7:0]) + status = ad9361_reg_write(dev, 0x003F, 0x05); // Start BBPLL Calibration + status = ad9361_reg_write(dev, 0x003F, 0x01); // Clear BBPLL start calibration bit + status = ad9361_reg_write(dev, 0x004C, 0x86); // Increase BBPLL KV and phase margin + status = ad9361_reg_write(dev, 0x004D, 0x01); // Increase BBPLL KV and phase margin + status = ad9361_reg_write(dev, 0x004D, 0x05); // Increase BBPLL KV and phase margin + + // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 276.480 us (Done when 0x05E[7]==1) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x005E, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH); + + + status = ad9361_reg_write(dev, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels + status = ad9361_reg_write(dev, 0x0003, 0xE5); // Setup Rx Digital Filters/ Channels + status = ad9361_reg_write(dev, 0x0004, 0x03); // Select Rx input pin(A,B,C)/ Tx out pin (A,B) + status = ad9361_reg_write(dev, 0x000A, 0x12); // Set BBPLL post divide rate + +//************************************************************ +// Program Rx FIR: C:\Users\josh\Desktop\Config\rx64.txt +//************************************************************ + status = ad9361_reg_write(dev, 0x00F5, 0x9A); // Enable clock to Rx FIR Filter + status = ad9361_reg_write(dev, 0x00F6, 0x02); // Write Filter Gain setting + status = ad9361_reg_write(dev, 0x00F0, 0x00); // Write FIR coefficient address + status = ad9361_reg_write(dev, 0x00F1, 0x00); // Write FIR coefficient data[7:0] + status = ad9361_reg_write(dev, 0x00F2, 0x00); // Write FIR coefficient data[15:8] + status = ad9361_reg_write(dev, 0x00F5, 0x9E); // Set Write EN to push data into FIR filter register map + status = ad9361_reg_write(dev, 0x00F4, 0x00); // Dummy Write to Read only register to delay ~1us + status = ad9361_reg_write(dev, 0x00F4, 0x00); // Dummy Write to Read only register to delay ~1us + status = ad9361_reg_write(dev, 0x00F0, 0x01); + status = ad9361_reg_write(dev, 0x00F1, 0xB6); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x02); + status = ad9361_reg_write(dev, 0x00F1, 0xA5); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x03); + status = ad9361_reg_write(dev, 0x00F1, 0xEA); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x04); + status = ad9361_reg_write(dev, 0x00F1, 0x61); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x05); + status = ad9361_reg_write(dev, 0x00F1, 0xA3); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x06); + status = ad9361_reg_write(dev, 0x00F1, 0x4D); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x07); + status = ad9361_reg_write(dev, 0x00F1, 0x77); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x08); + status = ad9361_reg_write(dev, 0x00F1, 0xD5); + status = ad9361_reg_write(dev, 0x00F2, 0xFE); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x09); + status = ad9361_reg_write(dev, 0x00F1, 0x38); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0A); + status = ad9361_reg_write(dev, 0x00F1, 0xA5); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0B); + status = ad9361_reg_write(dev, 0x00F1, 0xF8); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0C); + status = ad9361_reg_write(dev, 0x00F1, 0xAD); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0D); + status = ad9361_reg_write(dev, 0x00F1, 0x75); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0E); + status = ad9361_reg_write(dev, 0x00F1, 0xFD); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0F); + status = ad9361_reg_write(dev, 0x00F1, 0xD8); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x10); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x11); + status = ad9361_reg_write(dev, 0x00F1, 0x3A); + status = ad9361_reg_write(dev, 0x00F2, 0x04); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x12); + status = ad9361_reg_write(dev, 0x00F1, 0x6B); + status = ad9361_reg_write(dev, 0x00F2, 0x05); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x13); + status = ad9361_reg_write(dev, 0x00F1, 0x51); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x14); + status = ad9361_reg_write(dev, 0x00F1, 0x80); + status = ad9361_reg_write(dev, 0x00F2, 0xFA); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x15); + status = ad9361_reg_write(dev, 0x00F1, 0x34); + status = ad9361_reg_write(dev, 0x00F2, 0xF7); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x16); + status = ad9361_reg_write(dev, 0x00F1, 0x08); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x17); + status = ad9361_reg_write(dev, 0x00F1, 0xB2); + status = ad9361_reg_write(dev, 0x00F2, 0x06); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x18); + status = ad9361_reg_write(dev, 0x00F1, 0x1A); + status = ad9361_reg_write(dev, 0x00F2, 0x0E); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x19); + status = ad9361_reg_write(dev, 0x00F1, 0x44); + status = ad9361_reg_write(dev, 0x00F2, 0x09); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1A); + status = ad9361_reg_write(dev, 0x00F1, 0x54); + status = ad9361_reg_write(dev, 0x00F2, 0xF8); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1B); + status = ad9361_reg_write(dev, 0x00F1, 0xD1); + status = ad9361_reg_write(dev, 0x00F2, 0xE7); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1C); + status = ad9361_reg_write(dev, 0x00F1, 0xC2); + status = ad9361_reg_write(dev, 0x00F2, 0xE9); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1D); + status = ad9361_reg_write(dev, 0x00F1, 0x4F); + status = ad9361_reg_write(dev, 0x00F2, 0x08); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1E); + status = ad9361_reg_write(dev, 0x00F1, 0xB2); + status = ad9361_reg_write(dev, 0x00F2, 0x3B); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1F); + status = ad9361_reg_write(dev, 0x00F1, 0x2A); + status = ad9361_reg_write(dev, 0x00F2, 0x6C); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x20); + status = ad9361_reg_write(dev, 0x00F1, 0xFF); + status = ad9361_reg_write(dev, 0x00F2, 0x7F); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x21); + status = ad9361_reg_write(dev, 0x00F1, 0x2A); + status = ad9361_reg_write(dev, 0x00F2, 0x6C); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x22); + status = ad9361_reg_write(dev, 0x00F1, 0xB2); + status = ad9361_reg_write(dev, 0x00F2, 0x3B); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x23); + status = ad9361_reg_write(dev, 0x00F1, 0x4F); + status = ad9361_reg_write(dev, 0x00F2, 0x08); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x24); + status = ad9361_reg_write(dev, 0x00F1, 0xC2); + status = ad9361_reg_write(dev, 0x00F2, 0xE9); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x25); + status = ad9361_reg_write(dev, 0x00F1, 0xD1); + status = ad9361_reg_write(dev, 0x00F2, 0xE7); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x26); + status = ad9361_reg_write(dev, 0x00F1, 0x54); + status = ad9361_reg_write(dev, 0x00F2, 0xF8); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x27); + status = ad9361_reg_write(dev, 0x00F1, 0x44); + status = ad9361_reg_write(dev, 0x00F2, 0x09); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x28); + status = ad9361_reg_write(dev, 0x00F1, 0x1A); + status = ad9361_reg_write(dev, 0x00F2, 0x0E); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x29); + status = ad9361_reg_write(dev, 0x00F1, 0xB2); + status = ad9361_reg_write(dev, 0x00F2, 0x06); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2A); + status = ad9361_reg_write(dev, 0x00F1, 0x08); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2B); + status = ad9361_reg_write(dev, 0x00F1, 0x34); + status = ad9361_reg_write(dev, 0x00F2, 0xF7); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2C); + status = ad9361_reg_write(dev, 0x00F1, 0x80); + status = ad9361_reg_write(dev, 0x00F2, 0xFA); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2D); + status = ad9361_reg_write(dev, 0x00F1, 0x51); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2E); + status = ad9361_reg_write(dev, 0x00F1, 0x6B); + status = ad9361_reg_write(dev, 0x00F2, 0x05); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2F); + status = ad9361_reg_write(dev, 0x00F1, 0x3A); + status = ad9361_reg_write(dev, 0x00F2, 0x04); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x30); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x31); + status = ad9361_reg_write(dev, 0x00F1, 0xD8); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x32); + status = ad9361_reg_write(dev, 0x00F1, 0xFD); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x33); + status = ad9361_reg_write(dev, 0x00F1, 0x75); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x34); + status = ad9361_reg_write(dev, 0x00F1, 0xAD); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x35); + status = ad9361_reg_write(dev, 0x00F1, 0xF8); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x36); + status = ad9361_reg_write(dev, 0x00F1, 0xA5); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x37); + status = ad9361_reg_write(dev, 0x00F1, 0x38); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x38); + status = ad9361_reg_write(dev, 0x00F1, 0xD5); + status = ad9361_reg_write(dev, 0x00F2, 0xFE); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x39); + status = ad9361_reg_write(dev, 0x00F1, 0x77); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3A); + status = ad9361_reg_write(dev, 0x00F1, 0x4D); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3B); + status = ad9361_reg_write(dev, 0x00F1, 0xA3); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3C); + status = ad9361_reg_write(dev, 0x00F1, 0x61); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3D); + status = ad9361_reg_write(dev, 0x00F1, 0xEA); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3E); + status = ad9361_reg_write(dev, 0x00F1, 0xA5); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3F); + status = ad9361_reg_write(dev, 0x00F1, 0xB6); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x40); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x41); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x42); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x43); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x44); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x45); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x46); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x47); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x48); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x49); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4A); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4B); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4C); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4D); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4E); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4F); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x98); // Disable clock to Rx Filter + +//************************************************************ +// Setup the Parallel Port (Digital Data Interface) +//************************************************************ + status = ad9361_reg_write(dev, 0x0010, 0xC8); // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK + status = ad9361_reg_write(dev, 0x0011, 0x00); // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data + status = ad9361_reg_write(dev, 0x0012, 0x02); // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits + status = ad9361_reg_write(dev, 0x0006, 0x00); // PPORT Rx Delay (adjusts Tco Dataclk->Data) + status = ad9361_reg_write(dev, 0x0007, 0x0F); // PPORT TX Delay (adjusts setup/hold FBCLK->Data) + +//************************************************************ +// Setup AuxDAC +//************************************************************ + status = ad9361_reg_write(dev, 0x0018, 0x00); // AuxDAC1 Word[9:2] + status = ad9361_reg_write(dev, 0x0019, 0x00); // AuxDAC2 Word[9:2] + status = ad9361_reg_write(dev, 0x001A, 0x00); // AuxDAC1 Config and Word[1:0] + status = ad9361_reg_write(dev, 0x001B, 0x00); // AuxDAC2 Config and Word[1:0] + status = ad9361_reg_write(dev, 0x0023, 0xFF); // AuxDAC Manaul/Auto Control + status = ad9361_reg_write(dev, 0x0026, 0x00); // AuxDAC Manual Select Bit/GPO Manual Select + status = ad9361_reg_write(dev, 0x0030, 0x00); // AuxDAC1 Rx Delay + status = ad9361_reg_write(dev, 0x0031, 0x00); // AuxDAC1 Tx Delay + status = ad9361_reg_write(dev, 0x0032, 0x00); // AuxDAC2 Rx Delay + status = ad9361_reg_write(dev, 0x0033, 0x00); // AuxDAC2 Tx Delay + +//************************************************************ +// Setup AuxADC +//************************************************************ + status = ad9361_reg_write(dev, 0x000B, 0x00); // Temp Sensor Setup (Offset) + status = ad9361_reg_write(dev, 0x000C, 0x00); // Temp Sensor Setup (Temp Window) + status = ad9361_reg_write(dev, 0x000D, 0x03); // Temp Sensor Setup (Periodic Measure) + status = ad9361_reg_write(dev, 0x000F, 0x04); // Temp Sensor Setup (Decimation) + status = ad9361_reg_write(dev, 0x001C, 0x00); // AuxADC Setup (Clock Div) + status = ad9361_reg_write(dev, 0x001D, 0x01); // AuxADC Setup (Decimation/Enable) + +//************************************************************ +// Setup Control Outs +//************************************************************ + status = ad9361_reg_write(dev, 0x0035, 0x00); // Ctrl Out index + status = ad9361_reg_write(dev, 0x0036, 0xFF); // Ctrl Out [7:0] output enable + +//************************************************************ +// Setup GPO +//************************************************************ + status = ad9361_reg_write(dev, 0x003A, 0x18); // Set number of REFCLK cycles for 1us delay timer + status = ad9361_reg_write(dev, 0x0020, 0x00); // GPO Auto Enable Setup in RX and TX + status = ad9361_reg_write(dev, 0x0027, 0x00); // GPO Manual and GPO auto value in ALERT + status = ad9361_reg_write(dev, 0x0028, 0x00); // GPO_0 RX Delay + status = ad9361_reg_write(dev, 0x0029, 0x00); // GPO_1 RX Delay + status = ad9361_reg_write(dev, 0x002A, 0x00); // GPO_2 RX Delay + status = ad9361_reg_write(dev, 0x002B, 0x00); // GPO_3 RX Delay + status = ad9361_reg_write(dev, 0x002C, 0x00); // GPO_0 TX Delay + status = ad9361_reg_write(dev, 0x002D, 0x00); // GPO_1 TX Delay + status = ad9361_reg_write(dev, 0x002E, 0x00); // GPO_2 TX Delay + status = ad9361_reg_write(dev, 0x002F, 0x00); // GPO_3 TX Delay + +//************************************************************ +// Setup RF PLL non-frequency-dependent registers +//************************************************************ + status = ad9361_reg_write(dev, 0x0261, 0x00); // Set Rx LO Power mode + status = ad9361_reg_write(dev, 0x02A1, 0x00); // Set Tx LO Power mode + status = ad9361_reg_write(dev, 0x0248, 0x0B); // Enable Rx VCO LDO + status = ad9361_reg_write(dev, 0x0288, 0x0B); // Enable Tx VCO LDO + status = ad9361_reg_write(dev, 0x0246, 0x02); // Set VCO Power down TCF bits + status = ad9361_reg_write(dev, 0x0286, 0x02); // Set VCO Power down TCF bits + status = ad9361_reg_write(dev, 0x0249, 0x8E); // Set VCO cal length + status = ad9361_reg_write(dev, 0x0289, 0x8E); // Set VCO cal length + status = ad9361_reg_write(dev, 0x023B, 0x80); // Enable Rx VCO cal + status = ad9361_reg_write(dev, 0x027B, 0x80); // Enable Tx VCO cal + status = ad9361_reg_write(dev, 0x0243, 0x0D); // Set Rx prescaler bias + status = ad9361_reg_write(dev, 0x0283, 0x0D); // Set Tx prescaler bias + status = ad9361_reg_write(dev, 0x023D, 0x00); // Clear Half VCO cal clock setting + status = ad9361_reg_write(dev, 0x027D, 0x00); // Clear Half VCO cal clock setting + + status = ad9361_reg_write(dev, 0x0015, 0x0C); // Set Dual Synth mode bit + status = ad9361_reg_write(dev, 0x0014, 0x1D); // Set Force ALERT State bit + status = ad9361_reg_write(dev, 0x0013, 0x01); // Set ENSM FDD mode + mdelay(1); // waits 1 ms + + status = ad9361_reg_write(dev, 0x023D, 0x04); // Start RX CP cal + + // Wait for CP cal to complete, Max RXCP Cal time: 737.280 (us)(Done when 0x244[7]==1) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0244, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x027D, 0x04); // Start TX CP cal + + // Wait for CP cal to complete, Max TXCP Cal time: 737.280 (us)(Done when 0x284[7]==1) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0284, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x023D, 0x00); // Disable RX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT + status = ad9361_reg_write(dev, 0x027D, 0x00); // Disable TX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT +//************************************************************ +// FDD RX,TX Synth Frequency: 125.000000,4125.000000 MHz +//************************************************************ +//************************************************************ +// Setup Rx Frequency-Dependent Syntheisizer Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x023A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0239, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0242, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0238, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0245, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0251, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0250, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x023B, 0x94); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x023E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x023F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0240, 0x0A); // Set Synth Loop Filter R3 + +//************************************************************ +// Setup Tx Frequency-Dependent Syntheisizer Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + +//************************************************************ +// Write Rx and Tx Frequency Words +//************************************************************ + status = ad9361_reg_write(dev, 0x0233, 0x00); // Write Rx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0234, 0x00); // Write Rx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0235, 0x00); // Write Rx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0232, 0x00); // Write Rx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0231, 0xA0); // Write Rx Synth Integer Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0005, 0x05); // Set LO divider setting + status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x05); // Set LO divider setting + +//************************************************************ +// Program Mixer GM Sub-table +//************************************************************ + status = ad9361_reg_write(dev, 0x013F, 0x02); // Start Clock + status = ad9361_reg_write(dev, 0x0138, 0x0F); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x78); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x00); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0E); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x74); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x0D); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0D); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x70); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x15); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0C); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x6C); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x1B); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0B); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x68); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x21); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0A); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x64); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x25); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x09); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x60); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x29); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x08); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x5C); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x2C); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x07); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x58); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x2F); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x06); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x54); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x31); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x05); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x50); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x33); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x04); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x4C); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x34); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x03); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x48); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x35); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x02); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x30); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x3A); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x01); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x18); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x3D); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x00); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x00); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x3E); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x013F, 0x02); // Clear Write Bit + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x013F, 0x00); // Stop Clock + +//************************************************************ +// Program Rx Gain Tables with GainTable800MHz.csv +//************************************************************ + + status = ad9361_reg_write(dev, 0x0137, 0x1A); // Start Gain Table Clock + status = ad9361_reg_write(dev, 0x0130, 0x00); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x01); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x02); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x03); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x01); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x04); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x02); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x05); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x03); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x06); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x04); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x07); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x05); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x08); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x03); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x09); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x04); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x05); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x06); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x07); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x08); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x09); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x10); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x11); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x12); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0D); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x13); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x14); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x09); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x15); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x16); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x17); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x18); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0D); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x19); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0F); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x10); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x28); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x29); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x20); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x21); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x22); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x24); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x20); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x23); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x24); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x21); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x24); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x20); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x25); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x21); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x26); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x22); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x27); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x23); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x28); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x24); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x29); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x25); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x26); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x27); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x28); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x29); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x30); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x31); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2D); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x32); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x33); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2F); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x34); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x30); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x35); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x31); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x36); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x32); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x37); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x38); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2F); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x39); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x30); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x31); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x32); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x33); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x34); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x35); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x36); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x40); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x37); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x41); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x42); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x65); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x43); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x66); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x44); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x67); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x45); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x68); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x46); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x69); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x47); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6A); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x48); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6B); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x49); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6C); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6D); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6E); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6F); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x50); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x51); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x52); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x53); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x54); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x55); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x56); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x57); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x58); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x59); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x5A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0137, 0x1A); // Clear Write Bit + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0137, 0x00); // Stop Gain Table Clock +//************************************************************ +// Setup Rx Manual Gain Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x00FA, 0xE0); // Gain Control Mode Select + status = ad9361_reg_write(dev, 0x00FB, 0x08); // Table, Digital Gain, Man Gain Ctrl + status = ad9361_reg_write(dev, 0x00FC, 0x23); // Incr Step Size, ADC Overrange Size + status = ad9361_reg_write(dev, 0x00FD, 0x4C); // Max Full/LMT Gain Table Index + status = ad9361_reg_write(dev, 0x00FE, 0x44); // Decr Step Size, Peak Overload Time + status = ad9361_reg_write(dev, 0x0100, 0x6F); // Max Digital Gain + status = ad9361_reg_write(dev, 0x0104, 0x2F); // ADC Small Overload Threshold + status = ad9361_reg_write(dev, 0x0105, 0x3A); // ADC Large Overload Threshold + status = ad9361_reg_write(dev, 0x0107, 0x2B); // Small LMT Overload Threshold + status = ad9361_reg_write(dev, 0x0108, 0x31); // Large LMT Overload Threshold + status = ad9361_reg_write(dev, 0x0109, 0x00); // Rx1 Full/LMT Gain Index + status = ad9361_reg_write(dev, 0x010A, 0x58); // Rx1 LPF Gain Index + status = ad9361_reg_write(dev, 0x010B, 0x00); // Rx1 Digital Gain Index + status = ad9361_reg_write(dev, 0x010C, 0x00); // Rx2 Full/LMT Gain Index + status = ad9361_reg_write(dev, 0x010D, 0x18); // Rx2 LPF Gain Index + status = ad9361_reg_write(dev, 0x010E, 0x00); // Rx2 Digital Gain Index + status = ad9361_reg_write(dev, 0x0114, 0x30); // Low Power Threshold + status = ad9361_reg_write(dev, 0x011A, 0x27); // Initial LMT Gain Limit + status = ad9361_reg_write(dev, 0x0081, 0x00); // Tx Symbol Gain Control +//************************************************************ +// RX Baseband Filter Tuning (Real BW: 7.500000 MHz) 3dB Filter +// Corner @ 10.500000 MHz) +//************************************************************ + status = ad9361_reg_write(dev, 0x01FB, 0x07); // RX Freq Corner (MHz) + status = ad9361_reg_write(dev, 0x01FC, 0x40); // RX Freq Corner (Khz) + status = ad9361_reg_write(dev, 0x01F8, 0x0D); // Rx BBF Tune Divider[7:0] + status = ad9361_reg_write(dev, 0x01F9, 0x1E); // RX BBF Tune Divider[8] + + status = ad9361_reg_write(dev, 0x01D5, 0x3F); // Set Rx Mix LO CM + status = ad9361_reg_write(dev, 0x01C0, 0x03); // Set GM common mode + status = ad9361_reg_write(dev, 0x01E2, 0x02); // Enable Rx1 Filter Tuner + status = ad9361_reg_write(dev, 0x01E3, 0x02); // Enable Rx2 Filter Tuner + status = ad9361_reg_write(dev, 0x0016, 0x80); // Start RX Filter Tune + + // Wait for RX filter to tune, Max Cal Time: 6.884 us (Done when 0x016[7]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x01E2, 0x03); // Disable Rx Filter Tuner (Rx1) + status = ad9361_reg_write(dev, 0x01E3, 0x03); // Disable Rx Filter Tuner (Rx2) +//************************************************************ +// TX Baseband Filter Tuning (Real BW: 7.500000 MHz) 3dB Filter +// Corner @ 12.000000 MHz) +//************************************************************ + status = ad9361_reg_write(dev, 0x00D6, 0x0B); // TX BBF Tune Divider[7:0] + status = ad9361_reg_write(dev, 0x00D7, 0x1E); // TX BBF Tune Divider[8] + + status = ad9361_reg_write(dev, 0x00CA, 0x22); // Enable Tx Filter Tuner + status = ad9361_reg_write(dev, 0x0016, 0x40); // Start Tx Filter Tune + + // Wait for TX filter to tune, Max Cal Time: 3.390 us (Done when 0x016[6]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x40) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x00CA, 0x26); // Disable Tx Filter Tuner (Both Channels) +//************************************************************ +// RX TIA Setup: Setup values scale based on RxBBF calibration +// results. See information in Calibration Guide. +//************************************************************ + status = ad9361_reg_write(dev, 0x01DB, 0x60); // Set TIA selcc[2:0] + status = ad9361_reg_write(dev, 0x01DD, 0x00); // Set RX TIA1 C MSB[6:0] + status = ad9361_reg_write(dev, 0x01DF, 0x00); // Set RX TIA2 C MSB[6:0] + status = ad9361_reg_write(dev, 0x01DC, 0x72); // Set RX TIA1 C LSB[5:0] + status = ad9361_reg_write(dev, 0x01DE, 0x72); // Set RX TIA2 C LSB[5:0] + +//************************************************************ +// TX Secondary Filter Calibration Setup: Real Bandwidth +// 7.500000MHz, 3dB Corner @ 37.500000MHz +//************************************************************ + status = ad9361_reg_write(dev, 0x00D2, 0x1E); // TX Secondary Filter PDF Cap cal[5:0] + status = ad9361_reg_write(dev, 0x00D1, 0x0C); // TX Secondary Filter PDF Res cal[3:0] + status = ad9361_reg_write(dev, 0x00D0, 0x56); // Pdampbias + +//************************************************************ +// ADC Setup: Tune ADC Performance based on RX analog filter tune +// corner. Real Bandwidth: 6.982753 MHz, ADC Clock Frequency: +// 288.000000 MHz. The values in registers 0x200 - 0x227 need to be +// calculated using the equations in the Calibration Guide. +//************************************************************ + + status = ad9361_reg_write(dev, 0x0200, 0x00); + status = ad9361_reg_write(dev, 0x0201, 0x00); + status = ad9361_reg_write(dev, 0x0202, 0x00); + status = ad9361_reg_write(dev, 0x0203, 0x24); + status = ad9361_reg_write(dev, 0x0204, 0x24); + status = ad9361_reg_write(dev, 0x0205, 0x00); + status = ad9361_reg_write(dev, 0x0206, 0x00); + status = ad9361_reg_write(dev, 0x0207, 0x7C); + status = ad9361_reg_write(dev, 0x0208, 0x46); + status = ad9361_reg_write(dev, 0x0209, 0x3C); + status = ad9361_reg_write(dev, 0x020A, 0x4C); + status = ad9361_reg_write(dev, 0x020B, 0x2C); + status = ad9361_reg_write(dev, 0x020C, 0x4F); + status = ad9361_reg_write(dev, 0x020D, 0x2A); + status = ad9361_reg_write(dev, 0x020E, 0x00); + status = ad9361_reg_write(dev, 0x020F, 0x7F); + status = ad9361_reg_write(dev, 0x0210, 0x7F); + status = ad9361_reg_write(dev, 0x0211, 0x7F); + status = ad9361_reg_write(dev, 0x0212, 0x4A); + status = ad9361_reg_write(dev, 0x0213, 0x4A); + status = ad9361_reg_write(dev, 0x0214, 0x4A); + status = ad9361_reg_write(dev, 0x0215, 0x4D); + status = ad9361_reg_write(dev, 0x0216, 0x4D); + status = ad9361_reg_write(dev, 0x0217, 0x4D); + status = ad9361_reg_write(dev, 0x0218, 0x2E); + status = ad9361_reg_write(dev, 0x0219, 0x9C); + status = ad9361_reg_write(dev, 0x021A, 0x1F); + status = ad9361_reg_write(dev, 0x021B, 0x15); + status = ad9361_reg_write(dev, 0x021C, 0x9C); + status = ad9361_reg_write(dev, 0x021D, 0x1F); + status = ad9361_reg_write(dev, 0x021E, 0x15); + status = ad9361_reg_write(dev, 0x021F, 0x9C); + status = ad9361_reg_write(dev, 0x0220, 0x1F); + status = ad9361_reg_write(dev, 0x0221, 0x2A); + status = ad9361_reg_write(dev, 0x0222, 0x2A); + status = ad9361_reg_write(dev, 0x0223, 0x40); + status = ad9361_reg_write(dev, 0x0224, 0x40); + status = ad9361_reg_write(dev, 0x0225, 0x2C); + status = ad9361_reg_write(dev, 0x0226, 0x00); + status = ad9361_reg_write(dev, 0x0227, 0x00); +//************************************************************ +// Setup and Run BB DC and RF DC Offset Calibrations +//************************************************************ + status = ad9361_reg_write(dev, 0x0193, 0x3F); + status = ad9361_reg_write(dev, 0x0190, 0x0F); // Set BBDC tracking shift M value, only applies when BB DC tracking enabled + status = ad9361_reg_write(dev, 0x0194, 0x01); // BBDC Cal setting + status = ad9361_reg_write(dev, 0x0016, 0x01); // Start BBDC offset cal + + // BBDC Max Cal Time: 8416.667 us. Cal done when 0x016[0]==0 + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x01) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x0185, 0x20); // Set RF DC offset Wait Count + status = ad9361_reg_write(dev, 0x0186, 0x32); // Set RF DC Offset Count[7:0] + status = ad9361_reg_write(dev, 0x0187, 0x24); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x018B, 0x83); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x0188, 0x05); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x0189, 0x30); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x0016, 0x02); // Start RFDC offset cal + + // RFDC Max Cal Time: 114511.250 us + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x01) != 0x00 && time_out_cnt <= TIMEOUT_TH); + +//************************************************************ +// Tx Quadrature Calibration Settings +//************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x15); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0x00); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + // Wait for cal to complete (Done when 0x016[4]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x10) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x016A, 0x75); // Set Kexp Phase + status = ad9361_reg_write(dev, 0x016B, 0x95); // Set Kexp Amplitude & Prevent Positive Gain Bit + status = ad9361_reg_write(dev, 0x0169, 0xCF); // Enable Rx Quadrature Calibration Tracking + status = ad9361_reg_write(dev, 0x018B, 0xAD); // Enable BB and RF DC Tracking Calibrations + status = ad9361_reg_write(dev, 0x0012, 0x02); // Cals done, Set PPORT Config + status = ad9361_reg_write(dev, 0x0013, 0x01); // Set ENSM FDD/TDD bit + status = ad9361_reg_write(dev, 0x0015, 0x0C); // Set Dual Synth Mode, FDD External Control bits properly + +//************************************************************ +// Set Tx Attenuation: Tx1: 0.00 dB, Tx2: 0.00 dB +//************************************************************ + status = ad9361_reg_write(dev, 0x0073, 0x00); + status = ad9361_reg_write(dev, 0x0074, 0x00); + status = ad9361_reg_write(dev, 0x0075, 0x00); + status = ad9361_reg_write(dev, 0x0076, 0x00); +//************************************************************ +// Setup RSSI and Power Measurement Duration Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x0150, 0x0E); // RSSI Measurement Duration 0, 1 + status = ad9361_reg_write(dev, 0x0151, 0x00); // RSSI Measurement Duration 2, 3 + status = ad9361_reg_write(dev, 0x0152, 0xFF); // RSSI Weighted Multiplier 0 + status = ad9361_reg_write(dev, 0x0153, 0x00); // RSSI Weighted Multiplier 1 + status = ad9361_reg_write(dev, 0x0154, 0x00); // RSSI Weighted Multiplier 2 + status = ad9361_reg_write(dev, 0x0155, 0x00); // RSSI Weighted Multiplier 3 + status = ad9361_reg_write(dev, 0x0156, 0x00); // RSSI Delay + status = ad9361_reg_write(dev, 0x0157, 0x00); // RSSI Wait + status = ad9361_reg_write(dev, 0x0158, 0x0D); // RSSI Mode Select + status = ad9361_reg_write(dev, 0x015C, 0x67); // Power Measurement Duration + +//************************************************************ +// Enable External LO & External VCO Buffer +//************************************************************ + status |= ad9361_reg_write(dev, 0x0005, 0x07); + status |= ad9361_reg_write(dev, 0x0057, 0x1C); + + return status; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/dev_profile.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/dev_profile.h new file mode 100644 index 00000000..9c3b25c4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/dev_profile.h @@ -0,0 +1,45 @@ +#ifndef DEV_PROFILE_H_ +#define DEV_PROFILE_H_ + +#include +#include "../app_config.h" +#include "../parameters.h" +#include "../adi_noos/include/spi.h" +#include "../adi_noos/include/gpio.h" +#include "../adi_noos/include/delay.h" +#include "../adi_noos/include/irq.h" +#include "../adi_noos/include/error.h" +#include "../adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.h" +#include "../adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h" +#include "../adi_noos/drivers/frequency/hmc7044/hmc7044.h" +#include "../adi_noos/drivers/adc/ad9694/ad9694.h" + +// Platform includes +#include "../adi_noos/drivers/platform/spi_extra.h" +#include "../adi_noos/drivers/platform/gpio_extra.h" +#include "../adi_noos/drivers/platform/irq_extra.h" + +// AXI-Cores includes +#include "../adi_noos/drivers/axi_core/spi_engine/spi_engine.h" + +// Declare in mian.c +extern struct spi_engine_init_param spi_engine_param; +extern struct xil_gpio_init_param xil_gpio_param; + +#define GPIO_PARAM &xil_gpio_param +#define SPI_PARAM &spi_engine_param +#define GPIO_OPS &xil_gpio_ops +#define SPI_OPS &spi_eng_platform_ops + +extern struct hmc7044_init_param hmc7044_default_init_param; + +extern AD9361_InitParam ad9361_default_init_param; +extern AD9361_RXFIRConfig rx_fir_config; +extern AD9361_TXFIRConfig tx_fir_config; + +extern struct ad9361_reg_init_param ad9361_1_reg_default_init_param; +extern struct ad9361_reg_init_param ad9361_2_reg_default_init_param; + +uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev); + +#endif /* SRC_DEV_PROFILE_H_ */ diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/hmc7044_profile.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/hmc7044_profile.c new file mode 100644 index 00000000..1e5ffa3f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/dev_profile/hmc7044_profile.c @@ -0,0 +1,116 @@ +#include "dev_profile.h" +#include "../app_config.h" +#include "../adi_noos/drivers/frequency/hmc7044/hmc7044.h" + +// hmc7044 spi settings +static spi_init_param hmc7044_spi_init_param = { + .device_id = SPI_DEVICE_ID, + .max_speed_hz = SPI_ENGINE_MAX_SPEED, + .mode = SPI_MODE_4, + .chip_select = SPI_CS_HMC7044, + .platform_ops = SPI_OPS, + .extra = SPI_PARAM +}; + +// hmc7044 channel specifications +struct hmc7044_chan_spec hmc7044_chan_spec[4] = { + /* AD9361_XTAL */ + { + .disable = 0, + .num = 3, + .divider = 100, + .coarse_delay = 0, + .fine_delay = 0, + .high_performance_mode_dis = true, + .start_up_mode_dynamic_enable = false, + .dynamic_driver_enable = false, + .output_control0_rb4_enable = true, + .force_mute_enable = false, + .driver_mode = CML, + .driver_impedance = INTERNAL_100OHM_PER_PIN, + .out_mux_mode = CHANNEL_DIV + }, + /* FPGA_DAC_LOGIC_CLK */ + { + .disable = 0, + .num = 4, + .divider = 10, + .coarse_delay = 0, + .fine_delay = 0, + .high_performance_mode_dis = true, + .start_up_mode_dynamic_enable = false, + .dynamic_driver_enable = false, + .output_control0_rb4_enable = true, + .force_mute_enable = false, + .driver_mode = CML, + .driver_impedance = INTERNAL_100OHM_PER_PIN, + .out_mux_mode = CHANNEL_DIV + }, + /* B_AD9361_XTAL */ + { + .disable = 0, + .num = 12, + .divider = 100, + .coarse_delay = 0, + .fine_delay = 0, + .high_performance_mode_dis = false, + .start_up_mode_dynamic_enable = false, + .dynamic_driver_enable = false, + .output_control0_rb4_enable = true, + .force_mute_enable = false, + .driver_mode = CML, + .driver_impedance = INTERNAL_100OHM_PER_PIN, + .out_mux_mode = CHANNEL_DIV + }, + /* AD9361_RX_EXT_LO */ + { + .disable = 0, + .num = 13, + .divider = 10, + .coarse_delay = 0, + .fine_delay = 0, + .high_performance_mode_dis = false, + .start_up_mode_dynamic_enable = false, + .dynamic_driver_enable = false, + .output_control0_rb4_enable = true, + .force_mute_enable = false, + .driver_mode = CML, + .driver_impedance = INTERNAL_100OHM_PER_PIN, + .out_mux_mode = CHANNEL_DIV + }, +}; + +// hmc7044 default configurations +struct hmc7044_init_param hmc7044_default_init_param = { + .spi_init = &hmc7044_spi_init_param, + .clkin_freq = {0, 100000000, 0, 0}, + .vcxo_freq = 100000000, + .pll2_freq = 2500000000, + .pll1_loop_bw = 200, + .sysref_timer_div = 1536, + .in_buf_mode = { + BUFFER_DISABLE, + ENABLE_AC_COUPLE | ENABLE_INTERNAL_TERM | BUFFER_ENABLE, + BUFFER_DISABLE, + BUFFER_DISABLE, + ENABLE_AC_COUPLE | ENABLE_INTERNAL_TERM | BUFFER_ENABLE + }, + .gpi_ctrl = { + GPI_DISABLE, + GPI_DISABLE, + CHIP_SLEEP_MODE, + PULSE_GEN_REQUSET + }, + .gpo_ctrl = { + PLL1_LOCK_DETECT | GPO_CMOS_MODE, + PLL2_LOCK_DETECT | GPO_CMOS_MODE, + GPO_DISABLE, + GPO_DISABLE + }, + .num_channels = 4, + .pll1_ref_prio_ctrl = 0xE4, + .sync_pin_mode = SYNC_MULTICHIP, + .high_performance_mode_clock_dist_en = false, + .pulse_gen_mode = PULSE_ONE, + .channels = hmc7044_chan_spec +}; diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/lscript.ld b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/lscript.ld new file mode 100644 index 00000000..8066126a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/lscript.ld @@ -0,0 +1,288 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: 2019.1.3 */ +/* */ +/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : Cortex-A9 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000; + +_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024; +_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048; +_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024; +_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024; +_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000 + ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000 + ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000 + ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00 +} + +/* Specify the default entry point to the program */ + +ENTRY(_vector_table) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + KEEP (*(.vectors)) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.vfp11_veneer) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) +} > ps7_ddr_0 + +.init : { + KEEP (*(.init)) +} > ps7_ddr_0 + +.fini : { + KEEP (*(.fini)) +} > ps7_ddr_0 + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > ps7_ddr_0 + +.rodata1 : { + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > ps7_ddr_0 + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > ps7_ddr_0 + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > ps7_ddr_0 + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + __data_end = .; +} > ps7_ddr_0 + +.data1 : { + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > ps7_ddr_0 + +.got : { + *(.got) +} > ps7_ddr_0 + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > ps7_ddr_0 + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > ps7_ddr_0 + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > ps7_ddr_0 + +.eh_frame : { + *(.eh_frame) +} > ps7_ddr_0 + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > ps7_ddr_0 + +.gcc_except_table : { + *(.gcc_except_table) +} > ps7_ddr_0 + +.mmu_tbl (ALIGN(16384)) : { + __mmu_tbl_start = .; + *(.mmu_tbl) + __mmu_tbl_end = .; +} > ps7_ddr_0 + +.ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidix.*.*) + __exidx_end = .; +} > ps7_ddr_0 + +.preinit_array : { + __preinit_array_start = .; + KEEP (*(SORT(.preinit_array.*))) + KEEP (*(.preinit_array)) + __preinit_array_end = .; +} > ps7_ddr_0 + +.init_array : { + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; +} > ps7_ddr_0 + +.fini_array : { + __fini_array_start = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + __fini_array_end = .; +} > ps7_ddr_0 + +.ARM.attributes : { + __ARM.attributes_start = .; + *(.ARM.attributes) + __ARM.attributes_end = .; +} > ps7_ddr_0 + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > ps7_ddr_0 + +.sbss (NOLOAD) : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + __sbss_end = .; +} > ps7_ddr_0 + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > ps7_ddr_0 + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > ps7_ddr_0 + +.bss (NOLOAD) : { + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end = .; +} > ps7_ddr_0 + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap (NOLOAD) : { + . = ALIGN(16); + _heap = .; + HeapBase = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; + HeapLimit = .; +} > ps7_ddr_0 + +.stack (NOLOAD) : { + . = ALIGN(16); + _stack_end = .; + . += _STACK_SIZE; + . = ALIGN(16); + _stack = .; + __stack = _stack; + . = ALIGN(16); + _irq_stack_end = .; + . += _IRQ_STACK_SIZE; + . = ALIGN(16); + __irq_stack = .; + _supervisor_stack_end = .; + . += _SUPERVISOR_STACK_SIZE; + . = ALIGN(16); + __supervisor_stack = .; + _abort_stack_end = .; + . += _ABORT_STACK_SIZE; + . = ALIGN(16); + __abort_stack = .; + _fiq_stack_end = .; + . += _FIQ_STACK_SIZE; + . = ALIGN(16); + __fiq_stack = .; + _undef_stack_end = .; + . += _UNDEF_STACK_SIZE; + . = ALIGN(16); + __undef_stack = .; +} > ps7_ddr_0 + +_end = .; +} + diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/main.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/main.c new file mode 100644 index 00000000..24314f41 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/main.c @@ -0,0 +1,401 @@ +/***************************************************************************//** + * @file ad9361/src/main.c + * @brief Implementation of Main Function. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +// Platform includes +#include +#include +#include +#include "xgpiops.h" +// ADI Drivers +#include "app_config.h" +#include "dev_profile/dev_profile.h" +#include "adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.h" +#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h" +// AXI-Cores includes +#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h" +#include "adi_noos/drivers/platform/gpio_extra.h" + +/******************************************************************************/ +/************************ Variables Definitions *******************************/ +/******************************************************************************/ + +struct spi_engine_init_param spi_engine_param = { + .ref_clk_hz = SPI_ENGINE_REF_CLK, + .type = SPI_ENGINE, + .spi_engine_baseaddr = SPI_ENGINE_BASEADDR, + .cs_delay = SPI_ENGINE_CS_DELAY, + .data_width = SPI_ENGINE_DATA_WIDTH +}; + +struct xil_gpio_init_param xil_gpio_param = { + .type = GPIO_PS, + .device_id = GPIO_DEVICE_ID +}; + +struct hmc7044_dev *hmc7044_inst; +struct ad9361_reg_dev *ad9361_1_reg_inst; +struct ad9361_reg_dev *ad9361_2_reg_inst; +struct ad9361_rf_phy *ad9361_phy; +struct ad9361_rf_phy *ad9361_2_phy; + +XGpioPs Gpio; + +int Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq){ + int32_t status = 0; + uint8_t value = 0; + int32_t time_out_cnt = 0; + + switch(freq){ + case TX_FREQ_125: { + //************************************************************ + // Setup Tx Frequency-Dependent Syntheisizer Registers + //************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + + //************************************************************ + // Write Tx Frequency Words + //************************************************************ + status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting + + //************************************************************ + // Tx Quadrature Calibration Settings + //************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + break; + } + case TX_FREQ_126: { + //************************************************************ + // Setup Tx Frequency-Dependent Syntheisizer Registers + //************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + + //************************************************************ + // Write Tx Frequency Words + //************************************************************ + status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting + + //************************************************************ + // Tx Quadrature Calibration Settings + //************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + break; + } + case TX_FREQ_4125: { + //************************************************************ + // Setup Tx Frequency-Dependent Syntheisizer Registers + //************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + + //************************************************************ + // Write Rx Frequency Words + //************************************************************ + status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting + + //************************************************************ + // Tx Quadrature Calibration Settings + //************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + break; + } + + // Wait for cal to complete (Done when 0x016[4]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x10) != 0x00 && time_out_cnt <= TIMEOUT_TH); + } + + return status; +} + +/***************************************************************************//** + * @brief main +*******************************************************************************/ +int main(void) +{ + int32_t Status; + XGpioPs_Config *ConfigPtr; + ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID); + Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + /**********************************************************/ + /****************** HMC7044 Configuration *****************/ + /**********************************************************/ + Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param); + if (Status != SUCCESS) { + printf("hmc7044_init() error: %d\n", Status); + return FAILURE; + } + + /**********************************************************/ + /***************** AD9361-1 Configuration *****************/ + /**********************************************************/ + XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, GPIO_OUTPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, GPIO_OUTPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, GPIO_OUTPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, GPIO_OUTPUT); + + ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param); + XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0); + ad9361_reg_config(ad9361_1_reg_inst); + XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1); + +// Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param); +// if (Status != XST_SUCCESS){ +// return XST_FAILURE; +// }else{ +// printf("Configurate AD9361 Completely!\n"); +// } +// ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config); +// ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config); + + /**********************************************************/ + /***************** AD9361-2 Configuration *****************/ + /**********************************************************/ + XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, GPIO_OUTPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, GPIO_OUTPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, GPIO_OUTPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, GPIO_OUTPUT); + + ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param); + XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0); + ad9361_reg_config(ad9361_2_reg_inst); + XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1); + +// uint8_t rd_back; +// Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back); +// Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back); + + /**********************************************************/ + /******* AD9361 Baseband Multichip Synchronization ********/ + /**********************************************************/ + XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, GPIO_OUTPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, GPIO_OUTPUT); + + // SYNC BBPLL and DIGITAL SAMPLING CLOCKS + ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable + ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D); + ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable + ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80); + XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0); + mdelay(20); + XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin + mdelay(500); + XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0); + mdelay(2000); + ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable + ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B); + XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin + mdelay(500); + XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0); + ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits + ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08); + + XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0); + mdelay(20); + XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1); + mdelay(20); + XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0); + + /**********************************************************/ + /********* AD9361 Multichip Rx Phase Calibration **********/ + /**********************************************************/ + XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, GPIO_OUTPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, GPIO_OUTPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, GPIO_INPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, GPIO_OUTPUT); + XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, GPIO_INPUT); + + // switch to lower frequency + Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126); + XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1); + mdelay(20); + + // switch rx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30); + Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30); + + // enable dual ad9361 tx channels + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels + + // switch ad9361 tx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B) + mdelay(20); + + // begin to calibrate the 1st ad9361 + XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0); + XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1); + mdelay(1); + XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0); + + // read calibration status + int32_t time_out_cnt = 0; + do{ + mdelay(1);// Wait 1ms + time_out_cnt++; + }while(((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= TIMEOUT_TH)); + + if (time_out_cnt == TIMEOUT_TH){ + return FAILURE; + } + + // begin to calibrate the 2nd ad9361 + XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1); + mdelay(1); + XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0); + + // read calibration status + time_out_cnt = 0; + do{ + mdelay(1);// Wait 1ms + time_out_cnt++; + }while(((XGpioPs_ReadPin(&Gpio,AD9361_2_CAL_DONE) == 0) && time_out_cnt <= TIMEOUT_TH)); + + if (time_out_cnt == TIMEOUT_TH){ + return FAILURE; + } + +// // enable single ad9361 tx channels +// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels +// +// // switch ad9361 tx & rx channel +// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03); +// Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03); + + // switch to higher frequency + Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_125); + XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0); + + print("Done.\n"); + + return 0; +} diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/parameters.h b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/parameters.h new file mode 100644 index 00000000..3a9eacc3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/parameters.h @@ -0,0 +1,137 @@ +/***************************************************************************//** + * @file ad9361/src/parameters.h + * @brief Parameters Definitions. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef __PARAMETERS_H__ +#define __PARAMETERS_H__ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "app_config.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#ifdef XILINX_PLATFORM + +#define FCLK_CLK0_HZ 50000000 + +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID + +#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID +#define GPIO_OFFSET 54 +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 +#define GPIO_DISABLE 0 +#define GPIO_ENABLE 1 + +// hmc7044 +#define HMC7044_RESET GPIO_OFFSET+0 +#define HMC7044_SYNC GPIO_OFFSET+1 +#define HMC7044_GPIO_0 GPIO_OFFSET+2 +#define HMC7044_GPIO_1 GPIO_OFFSET+3 +#define HMC7044_GPIO_2 GPIO_OFFSET+4 +#define HMC7044_GPIO_3 GPIO_OFFSET+5 +// ad9361-1 +#define AD9361_1_TXNRX GPIO_OFFSET+6 +#define AD9361_1_ENABLE GPIO_OFFSET+7 +#define AD9361_1_EN_AGC GPIO_OFFSET+8 +#define AD9361_1_RESET_B GPIO_OFFSET+9 +#define AD9361_1_CTRL_OUT0 GPIO_OFFSET+10 +#define AD9361_1_CTRL_OUT1 GPIO_OFFSET+11 +#define AD9361_1_CTRL_OUT2 GPIO_OFFSET+12 +#define AD9361_1_CTRL_OUT3 GPIO_OFFSET+13 +#define AD9361_1_CTRL_OUT4 GPIO_OFFSET+14 +#define AD9361_1_CTRL_OUT5 GPIO_OFFSET+15 +#define AD9361_1_CTRL_OUT6 GPIO_OFFSET+16 +#define AD9361_1_CTRL_OUT7 GPIO_OFFSET+17 +#define AD9361_1_CTRL_IN0 GPIO_OFFSET+18 +#define AD9361_1_CTRL_IN1 GPIO_OFFSET+19 +#define AD9361_1_CTRL_IN2 GPIO_OFFSET+20 +#define AD9361_1_CTRL_IN3 GPIO_OFFSET+21 +// ad9361-2 +#define AD9361_2_TXNRX GPIO_OFFSET+22 +#define AD9361_2_ENABLE GPIO_OFFSET+23 +#define AD9361_2_EN_AGC GPIO_OFFSET+24 +#define AD9361_2_RESET_B GPIO_OFFSET+25 +#define AD9361_2_CTRL_OUT0 GPIO_OFFSET+26 +#define AD9361_2_CTRL_OUT1 GPIO_OFFSET+27 +#define AD9361_2_CTRL_OUT2 GPIO_OFFSET+28 +#define AD9361_2_CTRL_OUT3 GPIO_OFFSET+29 +#define AD9361_2_CTRL_OUT4 GPIO_OFFSET+30 +#define AD9361_2_CTRL_OUT5 GPIO_OFFSET+31 +#define AD9361_2_CTRL_OUT6 GPIO_OFFSET+32 +#define AD9361_2_CTRL_OUT7 GPIO_OFFSET+33 +#define AD9361_2_CTRL_IN0 GPIO_OFFSET+34 +#define AD9361_2_CTRL_IN1 GPIO_OFFSET+35 +#define AD9361_2_CTRL_IN2 GPIO_OFFSET+36 +#define AD9361_2_CTRL_IN3 GPIO_OFFSET+37 + +#define AD9361_SYNC GPIO_OFFSET+38 +#define AD9361_RX_FIFO_RST GPIO_OFFSET+39 +#define AD9361_1_CAL_START GPIO_OFFSET+40 +#define AD9361_2_CAL_START GPIO_OFFSET+41 +#define AD9361_RECAL GPIO_OFFSET+42 +#define AD9361_TX_SWITCH GPIO_OFFSET+43 +#define AD9361_1_CAL_DONE GPIO_OFFSET+44 +#define AD9361_2_CAL_DONE GPIO_OFFSET+45 +#define AD9361_CAL_RESULT GPIO_OFFSET+46 + +#define SPI_DEVICE_ID 0 +#define SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define SPI_ENGINE_MAX_SPEED 5000000 +#define SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR +#define SPI_ENGINE_DATA_WIDTH 8 +#define SPI_ENGINE_CS_DELAY 3 +#define SPI_CS_HMC7044 0x00 +#define SPI_CS_AD9361_1 0x01 +#define SPI_CS_AD9361_2 0x02 + +#define TIMEOUT_TH 2000 + +typedef enum +{ + TX_FREQ_125, + TX_FREQ_126, + TX_FREQ_4125 +} ad9361TxFreq; + +#endif + +#endif // __PARAMETERS_H__ diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/.cproject b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/.cproject new file mode 100644 index 00000000..1e032994 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/.cproject @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/.project b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/.project new file mode 100644 index 00000000..a018188a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/.project @@ -0,0 +1,75 @@ + + + duifei_cmos_48m_bsp + Created by SDK v2019.1 + + + + + org.eclipse.cdt.make.core.makeBuilder + + + org.eclipse.cdt.core.errorOutputParser + org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser; + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.build.arguments + + + + org.eclipse.cdt.make.core.build.command + make + + + org.eclipse.cdt.make.core.build.target.auto + all + + + org.eclipse.cdt.make.core.build.target.clean + clean + + + org.eclipse.cdt.make.core.build.target.inc + all + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.enabledIncrementalBuild + true + + + org.eclipse.cdt.make.core.environment + + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + + com.xilinx.sdk.sw.SwProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.make.core.makeNature + + diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/.sdkproject b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/.sdkproject new file mode 100644 index 00000000..7e04c35b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/.sdkproject @@ -0,0 +1,4 @@ +THIRPARTY=false +HW_PROJECT_REFERENCE=system_top_hw_platform_0 +PROCESSOR=ps7_cortexa9_0 +MSS_FILE=system.mss diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/Makefile b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/Makefile new file mode 100644 index 00000000..1e68922c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/Makefile @@ -0,0 +1,35 @@ +# Makefile generated by Xilinx. + +PROCESSOR = ps7_cortexa9_0 +LIBRARIES = ${PROCESSOR}/lib/libxil.a +BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) +SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) + +ifneq (,$(findstring win,$(RDI_PLATFORM))) + SHELL = CMD +endif + +all: libs + @echo 'Finished building libraries' + +include: $(addsuffix /make.include,$(SUBDIRS)) + +libs: $(addsuffix /make.libs,$(SUBDIRS)) + +clean: $(addsuffix /make.clean,$(SUBDIRS)) + +$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a + cp -f $< $@ + +%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) + @echo "Running Make include in $(subst /make.include,,$@)" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra" + +%/make.libs: include + @echo "Running Make libs in $(subst /make.libs,,$@)" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra" + +%/make.clean: + $(MAKE) -C $(subst /make.clean,,$@) -s clean +clean: + rm -f ${PROCESSOR}/lib/libxil.a diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/system.mss b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/system.mss new file mode 100644 index 00000000..f8c0455c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m_bsp/system.mss @@ -0,0 +1,201 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 7.0 + PARAMETER PROC_INSTANCE = ps7_cortexa9_0 + PARAMETER stdin = ps7_coresight_comp_0 + PARAMETER stdout = ps7_coresight_comp_0 +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu_cortexa9 + PARAMETER DRIVER_VER = 2.7 + PARAMETER HW_INSTANCE = ps7_cortexa9_0 +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = axi_spi_engine_axi_spi_engine +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_afi_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_afi_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_afi_2 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_afi_3 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = coresightps_dcc + PARAMETER DRIVER_VER = 1.5 + PARAMETER HW_INSTANCE = ps7_coresight_comp_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = ddrps + PARAMETER DRIVER_VER = 1.0 + PARAMETER HW_INSTANCE = ps7_ddr_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_ddrc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = devcfg + PARAMETER DRIVER_VER = 3.5 + PARAMETER HW_INSTANCE = ps7_dev_cfg_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = dmaps + PARAMETER DRIVER_VER = 2.4 + PARAMETER HW_INSTANCE = ps7_dma_ns +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = dmaps + PARAMETER DRIVER_VER = 2.4 + PARAMETER HW_INSTANCE = ps7_dma_s +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_globaltimer_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpiops + PARAMETER DRIVER_VER = 3.5 + PARAMETER HW_INSTANCE = ps7_gpio_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_gpv_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_intc_dist_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_iop_bus_config_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_l2cachec_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_ocmc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_pl310_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_pmu_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = qspips + PARAMETER DRIVER_VER = 3.6 + PARAMETER HW_INSTANCE = ps7_qspi_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_qspi_linear_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_ram_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_ram_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_scuc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = scugic + PARAMETER DRIVER_VER = 4.0 + PARAMETER HW_INSTANCE = ps7_scugic_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = scutimer + PARAMETER DRIVER_VER = 2.1 + PARAMETER HW_INSTANCE = ps7_scutimer_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = scuwdt + PARAMETER DRIVER_VER = 2.1 + PARAMETER HW_INSTANCE = ps7_scuwdt_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_slcr_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = xadcps + PARAMETER DRIVER_VER = 2.3 + PARAMETER HW_INSTANCE = ps7_xadc_0 +END + + diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf b/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf new file mode 100644 index 00000000..8304e068 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf differ diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/ADF4351_2.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/ADF4351_2.v new file mode 100644 index 00000000..051c0c2d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/ADF4351_2.v @@ -0,0 +1,188 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:51:06 06/08/2020 +// Design Name: +// Module Name: test_784TR_top +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// ??????9?byte? ?1-8?????????????????8???????????????????3?byte???5?don't care?? +// ?9byte??4bit??spi??4bit?????? +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +/*************?????????*******************/ +module adf4351_2( +input i_sysclk , +input i_arstn , +output o_cfgover , +output o_ADF4351_SCK , +output o_ADF4351_DATA , +output o_ADF4351_LE , +output o_ADF4351_CE , +output o_ADF4351_mutel , +input i_ADF4351_locked + ); + + +localparam DATA_WIDTH = 32; +localparam DATA_LENTH = 6; +localparam SYS_CLOCK = 10; +localparam LOCK_PIRED = SYS_CLOCK * 100000; +localparam rst_time = 16'h7fff;//16'h7fff +reg[7:0] cnt_word = 8'd0; +reg[5:0] cnt_bits = 6'd0; + +reg [DATA_WIDTH-1:0] cfgdata = 0; +wire [DATA_WIDTH-1:0] regdata; +reg cfgover = 1'b0 ; +reg pll_locked = 1'b0 ; +reg load_en = 1'b0 ; +reg [31:0] cnt_lock = 32'b0; +(* KEEP = "TRUE" *)reg[3:0] cfgstate = 4'b0000; +wire spiIdle; + +reg spi_sdi = 1'b0,spi_csb = 1'b1 ; +assign o_cfgover = cfgover ; +assign o_ADF4351_LE = load_en ; +assign o_ADF4351_mutel= 1'b1 ; +assign o_ADF4351_SCK = o_ADF4351_CE ? 1'b0 : i_sysclk ; +assign o_ADF4351_CE = spi_csb ; +assign o_ADF4351_DATA = spi_sdi ; +reg [DATA_WIDTH-1:0] CFGREG0 ; +assign regdata = CFGREG0 ; +reg cfg_start ; +reg [15:0] counter0 ; + +always@ (posedge i_sysclk) +if(~i_arstn) + CFGREG0 <= 32'b0; +else begin +//RFout = Fpfd*(INT + (Frac/Mod)) Fpfd = Refin*[(1+D)/(R*(1+T))] + case (cnt_word) + 8'h00: CFGREG0 <= {32'h580005}; //reg 5 + 8'h01: CFGREG0 <= {32'h85003C}; //reg 4 + 8'h02: CFGREG0 <= {32'h4B3}; //reg 3 + 8'h03: CFGREG0 <= {32'h28F42}; //reg 2 {5'b0,T,R,D,12'h,reg2} R = 1 D = 1 T = 1 + 8'h04: CFGREG0 <= {32'h8008011}; //reg 1 {3'd0,phase adjust,prescaler,phase value,Frac,reg1}mod = 25 + 8'h05: CFGREG0 <= {32'hC80000}; //reg 0 {1'b0,int,frac,reg0} int = 52 frac= 8 + default : CFGREG0 <= 32'b0; + endcase +end + + + + + +always@(negedge i_sysclk)begin + if(~i_arstn)begin + cfgdata <= 0; + cnt_word <= 8'd0; + cnt_bits <= 6'd0; + cfgover <= 1'b0; + cfgstate <= 4'd0; + spi_csb <= 1'b1; + load_en <= 1'b1; + spi_sdi <= 1'b0; + end + else begin + case(cfgstate) + 4'd0:begin + if(cfg_start)begin + cfgstate <= 4'd1; + end + else begin + spi_csb <= 1'b1; + load_en <= 1'b0; + spi_sdi <= 1'b0; + cfgover <= 1'b0; + cfgstate <= 4'd0; + end + end + 4'd1:begin + cfgdata <= regdata; + cnt_lock <= 32'd0; + cnt_bits <= 6'd0; + cfgstate <= cfgstate + 1'b1; + end + 4'd2:begin + spi_csb <= 1'b0; + load_en <= 1'b0; + spi_sdi <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + cfgstate <= cfgstate + 1'b1; + cnt_word <= cnt_word + 1'b1; + end + end + 4'd3:begin + spi_csb <= 1'b1; + load_en <= 1'b1; + spi_sdi <= 1'b0; + if(cnt_word == DATA_LENTH) + cfgstate <= cfgstate + 1'b1; + else + cfgstate <= 4'd0; + end + 4'd4:begin + cfgstate <= 4'd5; + spi_csb <= 1'b1; + load_en <= 1'b0; + spi_sdi <= 1'b0; + end + 4'd5:begin//ftw cfg + if(cnt_lock > LOCK_PIRED) + begin + pll_locked <= i_ADF4351_locked; + cnt_lock <= cnt_lock; + if( (pll_locked == 1'b0) && (cnt_lock > LOCK_PIRED)) + begin + cfgstate <= 4'd1; + cnt_word <= 8'd0; + end + else + begin + cfgstate <= 4'd5; + spi_csb <= 1'b1; + spi_sdi <= 1'b0; + cfgover <= 1'b1; + end + end + else + begin + cnt_lock <= cnt_lock + 1'b1; + end + end + default:cfgstate <= 4'd0; + endcase + end +end + + +always@(negedge i_sysclk)begin + if(~i_arstn)begin + counter0 <= 16'd0; + cfg_start <= 1'b0; + end + else begin + if(counter0 == rst_time)begin//16'h7fff + counter0 <= counter0; + cfg_start <= 1'b1; + end + else begin + counter0 <= counter0 + 1'b1; + cfg_start <= 1'b0; + end + end +end + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/FRAC1.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/FRAC1.v new file mode 100644 index 00000000..1dfe0f25 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/FRAC1.v @@ -0,0 +1,441 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:37:16 01/15/2022 +// Design Name: +// Module Name: FRAC1 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module FRAC1( +input clka, +input [15:0] addra, +output reg[24:0] douta + ); + + +reg[11:0] addr=0; + +always@(posedge clka)begin + addr<= (addra+375) % 400 ; +end + +always@(posedge clka)begin + case(addr) +0 : douta <= 0 ; +1 : douta <= 83886 ; +2 : douta <= 167772 ; +3 : douta <= 251658 ; +4 : douta <= 335544 ; +5 : douta <= 419430 ; +6 : douta <= 503316 ; +7 : douta <= 587202 ; +8 : douta <= 671088 ; +9 : douta <= 754974 ; +10 : douta <= 838860 ; +11 : douta <= 922746 ; +12 : douta <= 1006632 ; +13 : douta <= 1090519 ; +14 : douta <= 1174405 ; +15 : douta <= 1258291 ; +16 : douta <= 1342177 ; +17 : douta <= 1426063 ; +18 : douta <= 1509949 ; +19 : douta <= 1593835 ; +20 : douta <= 1677721 ; +21 : douta <= 1761607 ; +22 : douta <= 1845493 ; +23 : douta <= 1929379 ; +24 : douta <= 2013265 ; +25 : douta <= 2097152 ; +26 : douta <= 2181038 ; +27 : douta <= 2264924 ; +28 : douta <= 2348810 ; +29 : douta <= 2432696 ; +30 : douta <= 2516582 ; +31 : douta <= 2600468 ; +32 : douta <= 2684354 ; +33 : douta <= 2768240 ; +34 : douta <= 2852126 ; +35 : douta <= 2936012 ; +36 : douta <= 3019898 ; +37 : douta <= 3103784 ; +38 : douta <= 3187671 ; +39 : douta <= 3271557 ; +40 : douta <= 3355443 ; +41 : douta <= 3439329 ; +42 : douta <= 3523215 ; +43 : douta <= 3607101 ; +44 : douta <= 3690987 ; +45 : douta <= 3774873 ; +46 : douta <= 3858759 ; +47 : douta <= 3942645 ; +48 : douta <= 4026531 ; +49 : douta <= 4110417 ; +50 : douta <= 4194304 ; +51 : douta <= 4278190 ; +52 : douta <= 4362076 ; +53 : douta <= 4445962 ; +54 : douta <= 4529848 ; +55 : douta <= 4613734 ; +56 : douta <= 4697620 ; +57 : douta <= 4781506 ; +58 : douta <= 4865392 ; +59 : douta <= 4949278 ; +60 : douta <= 5033164 ; +61 : douta <= 5117050 ; +62 : douta <= 5200936 ; +63 : douta <= 5284823 ; +64 : douta <= 5368709 ; +65 : douta <= 5452595 ; +66 : douta <= 5536481 ; +67 : douta <= 5620367 ; +68 : douta <= 5704253 ; +69 : douta <= 5788139 ; +70 : douta <= 5872025 ; +71 : douta <= 5955911 ; +72 : douta <= 6039797 ; +73 : douta <= 6123683 ; +74 : douta <= 6207569 ; +75 : douta <= 6291456 ; +76 : douta <= 6375342 ; +77 : douta <= 6459228 ; +78 : douta <= 6543114 ; +79 : douta <= 6627000 ; +80 : douta <= 6710886 ; +81 : douta <= 6794772 ; +82 : douta <= 6878658 ; +83 : douta <= 6962544 ; +84 : douta <= 7046430 ; +85 : douta <= 7130316 ; +86 : douta <= 7214202 ; +87 : douta <= 7298088 ; +88 : douta <= 7381975 ; +89 : douta <= 7465861 ; +90 : douta <= 7549747 ; +91 : douta <= 7633633 ; +92 : douta <= 7717519 ; +93 : douta <= 7801405 ; +94 : douta <= 7885291 ; +95 : douta <= 7969177 ; +96 : douta <= 8053063 ; +97 : douta <= 8136949 ; +98 : douta <= 8220835 ; +99 : douta <= 8304721 ; +100 : douta <= 8388608 ; +101 : douta <= 8472494 ; +102 : douta <= 8556380 ; +103 : douta <= 8640266 ; +104 : douta <= 8724152 ; +105 : douta <= 8808038 ; +106 : douta <= 8891924 ; +107 : douta <= 8975810 ; +108 : douta <= 9059696 ; +109 : douta <= 9143582 ; +110 : douta <= 9227468 ; +111 : douta <= 9311354 ; +112 : douta <= 9395240 ; +113 : douta <= 9479127 ; +114 : douta <= 9563013 ; +115 : douta <= 9646899 ; +116 : douta <= 9730785 ; +117 : douta <= 9814671 ; +118 : douta <= 9898557 ; +119 : douta <= 9982443 ; +120 : douta <= 10066329 ; +121 : douta <= 10150215 ; +122 : douta <= 10234101 ; +123 : douta <= 10317987 ; +124 : douta <= 10401873 ; +125 : douta <= 10485760 ; +126 : douta <= 10569646 ; +127 : douta <= 10653532 ; +128 : douta <= 10737418 ; +129 : douta <= 10821304 ; +130 : douta <= 10905190 ; +131 : douta <= 10989076 ; +132 : douta <= 11072962 ; +133 : douta <= 11156848 ; +134 : douta <= 11240734 ; +135 : douta <= 11324620 ; +136 : douta <= 11408506 ; +137 : douta <= 11492392 ; +138 : douta <= 11576279 ; +139 : douta <= 11660165 ; +140 : douta <= 11744051 ; +141 : douta <= 11827937 ; +142 : douta <= 11911823 ; +143 : douta <= 11995709 ; +144 : douta <= 12079595 ; +145 : douta <= 12163481 ; +146 : douta <= 12247367 ; +147 : douta <= 12331253 ; +148 : douta <= 12415139 ; +149 : douta <= 12499025 ; +150 : douta <= 12582912 ; +151 : douta <= 12666798 ; +152 : douta <= 12750684 ; +153 : douta <= 12834570 ; +154 : douta <= 12918456 ; +155 : douta <= 13002342 ; +156 : douta <= 13086228 ; +157 : douta <= 13170114 ; +158 : douta <= 13254000 ; +159 : douta <= 13337886 ; +160 : douta <= 13421772 ; +161 : douta <= 13505658 ; +162 : douta <= 13589544 ; +163 : douta <= 13673431 ; +164 : douta <= 13757317 ; +165 : douta <= 13841203 ; +166 : douta <= 13925089 ; +167 : douta <= 14008975 ; +168 : douta <= 14092861 ; +169 : douta <= 14176747 ; +170 : douta <= 14260633 ; +171 : douta <= 14344519 ; +172 : douta <= 14428405 ; +173 : douta <= 14512291 ; +174 : douta <= 14596177 ; +175 : douta <= 14680064 ; +176 : douta <= 14763950 ; +177 : douta <= 14847836 ; +178 : douta <= 14931722 ; +179 : douta <= 15015608 ; +180 : douta <= 15099494 ; +181 : douta <= 15183380 ; +182 : douta <= 15267266 ; +183 : douta <= 15351152 ; +184 : douta <= 15435038 ; +185 : douta <= 15518924 ; +186 : douta <= 15602810 ; +187 : douta <= 15686696 ; +188 : douta <= 15770583 ; +189 : douta <= 15854469 ; +190 : douta <= 15938355 ; +191 : douta <= 16022241 ; +192 : douta <= 16106127 ; +193 : douta <= 16190013 ; +194 : douta <= 16273899 ; +195 : douta <= 16357785 ; +196 : douta <= 16441671 ; +197 : douta <= 16525557 ; +198 : douta <= 16609443 ; +199 : douta <= 16693329 ; +200 : douta <= 16777216 ; +201 : douta <= 16861102 ; +202 : douta <= 16944988 ; +203 : douta <= 17028874 ; +204 : douta <= 17112760 ; +205 : douta <= 17196646 ; +206 : douta <= 17280532 ; +207 : douta <= 17364418 ; +208 : douta <= 17448304 ; +209 : douta <= 17532190 ; +210 : douta <= 17616076 ; +211 : douta <= 17699962 ; +212 : douta <= 17783848 ; +213 : douta <= 17867735 ; +214 : douta <= 17951621 ; +215 : douta <= 18035507 ; +216 : douta <= 18119393 ; +217 : douta <= 18203279 ; +218 : douta <= 18287165 ; +219 : douta <= 18371051 ; +220 : douta <= 18454937 ; +221 : douta <= 18538823 ; +222 : douta <= 18622709 ; +223 : douta <= 18706595 ; +224 : douta <= 18790481 ; +225 : douta <= 18874368 ; +226 : douta <= 18958254 ; +227 : douta <= 19042140 ; +228 : douta <= 19126026 ; +229 : douta <= 19209912 ; +230 : douta <= 19293798 ; +231 : douta <= 19377684 ; +232 : douta <= 19461570 ; +233 : douta <= 19545456 ; +234 : douta <= 19629342 ; +235 : douta <= 19713228 ; +236 : douta <= 19797114 ; +237 : douta <= 19881000 ; +238 : douta <= 19964887 ; +239 : douta <= 20048773 ; +240 : douta <= 20132659 ; +241 : douta <= 20216545 ; +242 : douta <= 20300431 ; +243 : douta <= 20384317 ; +244 : douta <= 20468203 ; +245 : douta <= 20552089 ; +246 : douta <= 20635975 ; +247 : douta <= 20719861 ; +248 : douta <= 20803747 ; +249 : douta <= 20887633 ; +250 : douta <= 20971520 ; +251 : douta <= 21055406 ; +252 : douta <= 21139292 ; +253 : douta <= 21223178 ; +254 : douta <= 21307064 ; +255 : douta <= 21390950 ; +256 : douta <= 21474836 ; +257 : douta <= 21558722 ; +258 : douta <= 21642608 ; +259 : douta <= 21726494 ; +260 : douta <= 21810380 ; +261 : douta <= 21894266 ; +262 : douta <= 21978152 ; +263 : douta <= 22062039 ; +264 : douta <= 22145925 ; +265 : douta <= 22229811 ; +266 : douta <= 22313697 ; +267 : douta <= 22397583 ; +268 : douta <= 22481469 ; +269 : douta <= 22565355 ; +270 : douta <= 22649241 ; +271 : douta <= 22733127 ; +272 : douta <= 22817013 ; +273 : douta <= 22900899 ; +274 : douta <= 22984785 ; +275 : douta <= 23068672 ; +276 : douta <= 23152558 ; +277 : douta <= 23236444 ; +278 : douta <= 23320330 ; +279 : douta <= 23404216 ; +280 : douta <= 23488102 ; +281 : douta <= 23571988 ; +282 : douta <= 23655874 ; +283 : douta <= 23739760 ; +284 : douta <= 23823646 ; +285 : douta <= 23907532 ; +286 : douta <= 23991418 ; +287 : douta <= 24075304 ; +288 : douta <= 24159191 ; +289 : douta <= 24243077 ; +290 : douta <= 24326963 ; +291 : douta <= 24410849 ; +292 : douta <= 24494735 ; +293 : douta <= 24578621 ; +294 : douta <= 24662507 ; +295 : douta <= 24746393 ; +296 : douta <= 24830279 ; +297 : douta <= 24914165 ; +298 : douta <= 24998051 ; +299 : douta <= 25081937 ; +300 : douta <= 25165824 ; +301 : douta <= 25249710 ; +302 : douta <= 25333596 ; +303 : douta <= 25417482 ; +304 : douta <= 25501368 ; +305 : douta <= 25585254 ; +306 : douta <= 25669140 ; +307 : douta <= 25753026 ; +308 : douta <= 25836912 ; +309 : douta <= 25920798 ; +310 : douta <= 26004684 ; +311 : douta <= 26088570 ; +312 : douta <= 26172456 ; +313 : douta <= 26256343 ; +314 : douta <= 26340229 ; +315 : douta <= 26424115 ; +316 : douta <= 26508001 ; +317 : douta <= 26591887 ; +318 : douta <= 26675773 ; +319 : douta <= 26759659 ; +320 : douta <= 26843545 ; +321 : douta <= 26927431 ; +322 : douta <= 27011317 ; +323 : douta <= 27095203 ; +324 : douta <= 27179089 ; +325 : douta <= 27262976 ; +326 : douta <= 27346862 ; +327 : douta <= 27430748 ; +328 : douta <= 27514634 ; +329 : douta <= 27598520 ; +330 : douta <= 27682406 ; +331 : douta <= 27766292 ; +332 : douta <= 27850178 ; +333 : douta <= 27934064 ; +334 : douta <= 28017950 ; +335 : douta <= 28101836 ; +336 : douta <= 28185722 ; +337 : douta <= 28269608 ; +338 : douta <= 28353495 ; +339 : douta <= 28437381 ; +340 : douta <= 28521267 ; +341 : douta <= 28605153 ; +342 : douta <= 28689039 ; +343 : douta <= 28772925 ; +344 : douta <= 28856811 ; +345 : douta <= 28940697 ; +346 : douta <= 29024583 ; +347 : douta <= 29108469 ; +348 : douta <= 29192355 ; +349 : douta <= 29276241 ; +350 : douta <= 29360128 ; +351 : douta <= 29444014 ; +352 : douta <= 29527900 ; +353 : douta <= 29611786 ; +354 : douta <= 29695672 ; +355 : douta <= 29779558 ; +356 : douta <= 29863444 ; +357 : douta <= 29947330 ; +358 : douta <= 30031216 ; +359 : douta <= 30115102 ; +360 : douta <= 30198988 ; +361 : douta <= 30282874 ; +362 : douta <= 30366760 ; +363 : douta <= 30450647 ; +364 : douta <= 30534533 ; +365 : douta <= 30618419 ; +366 : douta <= 30702305 ; +367 : douta <= 30786191 ; +368 : douta <= 30870077 ; +369 : douta <= 30953963 ; +370 : douta <= 31037849 ; +371 : douta <= 31121735 ; +372 : douta <= 31205621 ; +373 : douta <= 31289507 ; +374 : douta <= 31373393 ; +375 : douta <= 31457280 ; +376 : douta <= 31541166 ; +377 : douta <= 31625052 ; +378 : douta <= 31708938 ; +379 : douta <= 31792824 ; +380 : douta <= 31876710 ; +381 : douta <= 31960596 ; +382 : douta <= 32044482 ; +383 : douta <= 32128368 ; +384 : douta <= 32212254 ; +385 : douta <= 32296140 ; +386 : douta <= 32380026 ; +387 : douta <= 32463912 ; +388 : douta <= 32547799 ; +389 : douta <= 32631685 ; +390 : douta <= 32715571 ; +391 : douta <= 32799457 ; +392 : douta <= 32883343 ; +393 : douta <= 32967229 ; +394 : douta <= 33051115 ; +395 : douta <= 33135001 ; +396 : douta <= 33218887 ; +397 : douta <= 33302773 ; +398 : douta <= 33386659 ; +399 : douta <= 33470545 ; + default : douta <= douta ; + endcase +end + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/INT_ROMb.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/INT_ROMb.v new file mode 100644 index 00000000..3cf64c92 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/INT_ROMb.v @@ -0,0 +1,3569 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:37:56 01/26/2022 +// Design Name: +// Module Name: INT_ROMb +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module INT_ROMb( +input sysclk, +input [11 : 0] addra, + +output reg[15:0] douta +); + + +always@(posedge sysclk)begin + if(addra>=0 && addra<=24) douta<=50; + else if(addra<=424 ) douta<=51; + else if(addra<=824 ) douta<=52; + else if(addra<=1224 ) douta<=53; + else if(addra<=1624 ) douta<=54; + else if(addra<=2024 ) douta<=55; + else if(addra<=2424 ) douta<=56; + else if(addra<=2824 ) douta<=57; + else if(addra<=3224 ) douta<=58; + else if(addra<=3500 ) douta<=59; + else douta<=douta; +end +/* +always@(posedge sysclk)begin + case(addra) + +0 : douta <= 50 ; +1 : douta <= 50 ; +2 : douta <= 50 ; +3 : douta <= 50 ; +4 : douta <= 50 ; +5 : douta <= 50 ; +6 : douta <= 50 ; +7 : douta <= 50 ; +8 : douta <= 50 ; +9 : douta <= 50 ; +10 : douta <= 50 ; +11 : douta <= 50 ; +12 : douta <= 50 ; +13 : douta <= 50 ; +14 : douta <= 50 ; +15 : douta <= 50 ; +16 : douta <= 50 ; +17 : douta <= 50 ; +18 : douta <= 50 ; +19 : douta <= 50 ; +20 : douta <= 50 ; +21 : douta <= 50 ; +22 : douta <= 50 ; +23 : douta <= 50 ; +24 : douta <= 50 ; +25 : douta <= 51 ; +26 : douta <= 51 ; +27 : douta <= 51 ; +28 : douta <= 51 ; +29 : douta <= 51 ; +30 : douta <= 51 ; +31 : douta <= 51 ; +32 : douta <= 51 ; +33 : douta <= 51 ; +34 : douta <= 51 ; +35 : douta <= 51 ; +36 : douta <= 51 ; +37 : douta <= 51 ; +38 : douta <= 51 ; +39 : douta <= 51 ; +40 : douta <= 51 ; +41 : douta <= 51 ; +42 : douta <= 51 ; +43 : douta <= 51 ; +44 : douta <= 51 ; +45 : douta <= 51 ; +46 : douta <= 51 ; +47 : douta <= 51 ; +48 : douta <= 51 ; +49 : douta <= 51 ; +50 : douta <= 51 ; +51 : douta <= 51 ; +52 : douta <= 51 ; +53 : douta <= 51 ; +54 : douta <= 51 ; +55 : douta <= 51 ; +56 : douta <= 51 ; +57 : douta <= 51 ; +58 : douta <= 51 ; +59 : douta <= 51 ; +60 : douta <= 51 ; +61 : douta <= 51 ; +62 : douta <= 51 ; +63 : douta <= 51 ; +64 : douta <= 51 ; +65 : douta <= 51 ; +66 : douta <= 51 ; +67 : douta <= 51 ; +68 : douta <= 51 ; +69 : douta <= 51 ; +70 : douta <= 51 ; +71 : douta <= 51 ; +72 : douta <= 51 ; +73 : douta <= 51 ; +74 : douta <= 51 ; +75 : douta <= 51 ; +76 : douta <= 51 ; +77 : douta <= 51 ; +78 : douta <= 51 ; +79 : douta <= 51 ; +80 : douta <= 51 ; +81 : douta <= 51 ; +82 : douta <= 51 ; +83 : douta <= 51 ; +84 : douta <= 51 ; +85 : douta <= 51 ; +86 : douta <= 51 ; +87 : douta <= 51 ; +88 : douta <= 51 ; +89 : douta <= 51 ; +90 : douta <= 51 ; +91 : douta <= 51 ; +92 : douta <= 51 ; +93 : douta <= 51 ; +94 : douta <= 51 ; +95 : douta <= 51 ; +96 : douta <= 51 ; +97 : douta <= 51 ; +98 : douta <= 51 ; +99 : douta <= 51 ; +100 : douta <= 51 ; +101 : douta <= 51 ; +102 : douta <= 51 ; +103 : douta <= 51 ; +104 : douta <= 51 ; +105 : douta <= 51 ; +106 : douta <= 51 ; +107 : douta <= 51 ; +108 : douta <= 51 ; +109 : douta <= 51 ; +110 : douta <= 51 ; +111 : douta <= 51 ; +112 : douta <= 51 ; +113 : douta <= 51 ; +114 : douta <= 51 ; +115 : douta <= 51 ; +116 : douta <= 51 ; +117 : douta <= 51 ; +118 : douta <= 51 ; +119 : douta <= 51 ; +120 : douta <= 51 ; +121 : douta <= 51 ; +122 : douta <= 51 ; +123 : douta <= 51 ; +124 : douta <= 51 ; +125 : douta <= 51 ; +126 : douta <= 51 ; +127 : douta <= 51 ; +128 : douta <= 51 ; +129 : douta <= 51 ; +130 : douta <= 51 ; +131 : douta <= 51 ; +132 : douta <= 51 ; +133 : douta <= 51 ; +134 : douta <= 51 ; +135 : douta <= 51 ; +136 : douta <= 51 ; +137 : douta <= 51 ; +138 : douta <= 51 ; +139 : douta <= 51 ; +140 : douta <= 51 ; +141 : douta <= 51 ; +142 : douta <= 51 ; +143 : douta <= 51 ; +144 : douta <= 51 ; +145 : douta <= 51 ; +146 : douta <= 51 ; +147 : douta <= 51 ; +148 : douta <= 51 ; +149 : douta <= 51 ; +150 : douta <= 51 ; +151 : douta <= 51 ; +152 : douta <= 51 ; +153 : douta <= 51 ; +154 : douta <= 51 ; +155 : douta <= 51 ; +156 : douta <= 51 ; +157 : douta <= 51 ; +158 : douta <= 51 ; +159 : douta <= 51 ; +160 : douta <= 51 ; +161 : douta <= 51 ; +162 : douta <= 51 ; +163 : douta <= 51 ; +164 : douta <= 51 ; +165 : douta <= 51 ; +166 : douta <= 51 ; +167 : douta <= 51 ; +168 : douta <= 51 ; +169 : douta <= 51 ; +170 : douta <= 51 ; +171 : douta <= 51 ; +172 : douta <= 51 ; +173 : douta <= 51 ; +174 : douta <= 51 ; +175 : douta <= 51 ; +176 : douta <= 51 ; +177 : douta <= 51 ; +178 : douta <= 51 ; +179 : douta <= 51 ; +180 : douta <= 51 ; +181 : douta <= 51 ; +182 : douta <= 51 ; +183 : douta <= 51 ; +184 : douta <= 51 ; +185 : douta <= 51 ; +186 : douta <= 51 ; +187 : douta <= 51 ; +188 : douta <= 51 ; +189 : douta <= 51 ; +190 : douta <= 51 ; +191 : douta <= 51 ; +192 : douta <= 51 ; +193 : douta <= 51 ; +194 : douta <= 51 ; +195 : douta <= 51 ; +196 : douta <= 51 ; +197 : douta <= 51 ; +198 : douta <= 51 ; +199 : douta <= 51 ; +200 : douta <= 51 ; +201 : douta <= 51 ; +202 : douta <= 51 ; +203 : douta <= 51 ; +204 : douta <= 51 ; +205 : douta <= 51 ; +206 : douta <= 51 ; +207 : douta <= 51 ; +208 : douta <= 51 ; +209 : douta <= 51 ; +210 : douta <= 51 ; +211 : douta <= 51 ; +212 : douta <= 51 ; +213 : douta <= 51 ; +214 : douta <= 51 ; +215 : douta <= 51 ; +216 : douta <= 51 ; +217 : douta <= 51 ; +218 : douta <= 51 ; +219 : douta <= 51 ; +220 : douta <= 51 ; +221 : douta <= 51 ; +222 : douta <= 51 ; +223 : douta <= 51 ; +224 : douta <= 51 ; +225 : douta <= 51 ; +226 : douta <= 51 ; +227 : douta <= 51 ; +228 : douta <= 51 ; +229 : douta <= 51 ; +230 : douta <= 51 ; +231 : douta <= 51 ; +232 : douta <= 51 ; +233 : douta <= 51 ; +234 : douta <= 51 ; +235 : douta <= 51 ; +236 : douta <= 51 ; +237 : douta <= 51 ; +238 : douta <= 51 ; +239 : douta <= 51 ; +240 : douta <= 51 ; +241 : douta <= 51 ; +242 : douta <= 51 ; +243 : douta <= 51 ; +244 : douta <= 51 ; +245 : douta <= 51 ; +246 : douta <= 51 ; +247 : douta <= 51 ; +248 : douta <= 51 ; +249 : douta <= 51 ; +250 : douta <= 51 ; +251 : douta <= 51 ; +252 : douta <= 51 ; +253 : douta <= 51 ; +254 : douta <= 51 ; +255 : douta <= 51 ; +256 : douta <= 51 ; +257 : douta <= 51 ; +258 : douta <= 51 ; +259 : douta <= 51 ; +260 : douta <= 51 ; +261 : douta <= 51 ; +262 : douta <= 51 ; +263 : douta <= 51 ; +264 : douta <= 51 ; +265 : douta <= 51 ; +266 : douta <= 51 ; +267 : douta <= 51 ; +268 : douta <= 51 ; +269 : douta <= 51 ; +270 : douta <= 51 ; +271 : douta <= 51 ; +272 : douta <= 51 ; +273 : douta <= 51 ; +274 : douta <= 51 ; +275 : douta <= 51 ; +276 : douta <= 51 ; +277 : douta <= 51 ; +278 : douta <= 51 ; +279 : douta <= 51 ; +280 : douta <= 51 ; +281 : douta <= 51 ; +282 : douta <= 51 ; +283 : douta <= 51 ; +284 : douta <= 51 ; +285 : douta <= 51 ; +286 : douta <= 51 ; +287 : douta <= 51 ; +288 : douta <= 51 ; +289 : douta <= 51 ; +290 : douta <= 51 ; +291 : douta <= 51 ; +292 : douta <= 51 ; +293 : douta <= 51 ; +294 : douta <= 51 ; +295 : douta <= 51 ; +296 : douta <= 51 ; +297 : douta <= 51 ; +298 : douta <= 51 ; +299 : douta <= 51 ; +300 : douta <= 51 ; +301 : douta <= 51 ; +302 : douta <= 51 ; +303 : douta <= 51 ; +304 : douta <= 51 ; +305 : douta <= 51 ; +306 : douta <= 51 ; +307 : douta <= 51 ; +308 : douta <= 51 ; +309 : douta <= 51 ; +310 : douta <= 51 ; +311 : douta <= 51 ; +312 : douta <= 51 ; +313 : douta <= 51 ; +314 : douta <= 51 ; +315 : douta <= 51 ; +316 : douta <= 51 ; +317 : douta <= 51 ; +318 : douta <= 51 ; +319 : douta <= 51 ; +320 : douta <= 51 ; +321 : douta <= 51 ; +322 : douta <= 51 ; +323 : douta <= 51 ; +324 : douta <= 51 ; +325 : douta <= 51 ; +326 : douta <= 51 ; +327 : douta <= 51 ; +328 : douta <= 51 ; +329 : douta <= 51 ; +330 : douta <= 51 ; +331 : douta <= 51 ; +332 : douta <= 51 ; +333 : douta <= 51 ; +334 : douta <= 51 ; +335 : douta <= 51 ; +336 : douta <= 51 ; +337 : douta <= 51 ; +338 : douta <= 51 ; +339 : douta <= 51 ; +340 : douta <= 51 ; +341 : douta <= 51 ; +342 : douta <= 51 ; +343 : douta <= 51 ; +344 : douta <= 51 ; +345 : douta <= 51 ; +346 : douta <= 51 ; +347 : douta <= 51 ; +348 : douta <= 51 ; +349 : douta <= 51 ; +350 : douta <= 51 ; +351 : douta <= 51 ; +352 : douta <= 51 ; +353 : douta <= 51 ; +354 : douta <= 51 ; +355 : douta <= 51 ; +356 : douta <= 51 ; +357 : douta <= 51 ; +358 : douta <= 51 ; +359 : douta <= 51 ; +360 : douta <= 51 ; +361 : douta <= 51 ; +362 : douta <= 51 ; +363 : douta <= 51 ; +364 : douta <= 51 ; +365 : douta <= 51 ; +366 : douta <= 51 ; +367 : douta <= 51 ; +368 : douta <= 51 ; +369 : douta <= 51 ; +370 : douta <= 51 ; +371 : douta <= 51 ; +372 : douta <= 51 ; +373 : douta <= 51 ; +374 : douta <= 51 ; +375 : douta <= 51 ; +376 : douta <= 51 ; +377 : douta <= 51 ; +378 : douta <= 51 ; +379 : douta <= 51 ; +380 : douta <= 51 ; +381 : douta <= 51 ; +382 : douta <= 51 ; +383 : douta <= 51 ; +384 : douta <= 51 ; +385 : douta <= 51 ; +386 : douta <= 51 ; +387 : douta <= 51 ; +388 : douta <= 51 ; +389 : douta <= 51 ; +390 : douta <= 51 ; +391 : douta <= 51 ; +392 : douta <= 51 ; +393 : douta <= 51 ; +394 : douta <= 51 ; +395 : douta <= 51 ; +396 : douta <= 51 ; +397 : douta <= 51 ; +398 : douta <= 51 ; +399 : douta <= 51 ; +400 : douta <= 51 ; +401 : douta <= 51 ; +402 : douta <= 51 ; +403 : douta <= 51 ; +404 : douta <= 51 ; +405 : douta <= 51 ; +406 : douta <= 51 ; +407 : douta <= 51 ; +408 : douta <= 51 ; +409 : douta <= 51 ; +410 : douta <= 51 ; +411 : douta <= 51 ; +412 : douta <= 51 ; +413 : douta <= 51 ; +414 : douta <= 51 ; +415 : douta <= 51 ; +416 : douta <= 51 ; +417 : douta <= 51 ; +418 : douta <= 51 ; +419 : douta <= 51 ; +420 : douta <= 51 ; +421 : douta <= 51 ; +422 : douta <= 51 ; +423 : douta <= 51 ; +424 : douta <= 51 ; +425 : douta <= 52 ; +426 : douta <= 52 ; +427 : douta <= 52 ; +428 : douta <= 52 ; +429 : douta <= 52 ; +430 : douta <= 52 ; +431 : douta <= 52 ; +432 : douta <= 52 ; +433 : douta <= 52 ; +434 : douta <= 52 ; +435 : douta <= 52 ; +436 : douta <= 52 ; +437 : douta <= 52 ; +438 : douta <= 52 ; +439 : douta <= 52 ; +440 : douta <= 52 ; +441 : douta <= 52 ; +442 : douta <= 52 ; +443 : douta <= 52 ; +444 : douta <= 52 ; +445 : douta <= 52 ; +446 : douta <= 52 ; +447 : douta <= 52 ; +448 : douta <= 52 ; +449 : douta <= 52 ; +450 : douta <= 52 ; +451 : douta <= 52 ; +452 : douta <= 52 ; +453 : douta <= 52 ; +454 : douta <= 52 ; +455 : douta <= 52 ; +456 : douta <= 52 ; +457 : douta <= 52 ; +458 : douta <= 52 ; +459 : douta <= 52 ; +460 : douta <= 52 ; +461 : douta <= 52 ; +462 : douta <= 52 ; +463 : douta <= 52 ; +464 : douta <= 52 ; +465 : douta <= 52 ; +466 : douta <= 52 ; +467 : douta <= 52 ; +468 : douta <= 52 ; +469 : douta <= 52 ; +470 : douta <= 52 ; +471 : douta <= 52 ; +472 : douta <= 52 ; +473 : douta <= 52 ; +474 : douta <= 52 ; +475 : douta <= 52 ; +476 : douta <= 52 ; +477 : douta <= 52 ; +478 : douta <= 52 ; +479 : douta <= 52 ; +480 : douta <= 52 ; +481 : douta <= 52 ; +482 : douta <= 52 ; +483 : douta <= 52 ; +484 : douta <= 52 ; +485 : douta <= 52 ; +486 : douta <= 52 ; +487 : douta <= 52 ; +488 : douta <= 52 ; +489 : douta <= 52 ; +490 : douta <= 52 ; +491 : douta <= 52 ; +492 : douta <= 52 ; +493 : douta <= 52 ; +494 : douta <= 52 ; +495 : douta <= 52 ; +496 : douta <= 52 ; +497 : douta <= 52 ; +498 : douta <= 52 ; +499 : douta <= 52 ; +500 : douta <= 52 ; +501 : douta <= 52 ; +502 : douta <= 52 ; +503 : douta <= 52 ; +504 : douta <= 52 ; +505 : douta <= 52 ; +506 : douta <= 52 ; +507 : douta <= 52 ; +508 : douta <= 52 ; +509 : douta <= 52 ; +510 : douta <= 52 ; +511 : douta <= 52 ; +512 : douta <= 52 ; +513 : douta <= 52 ; +514 : douta <= 52 ; +515 : douta <= 52 ; +516 : douta <= 52 ; +517 : douta <= 52 ; +518 : douta <= 52 ; +519 : douta <= 52 ; +520 : douta <= 52 ; +521 : douta <= 52 ; +522 : douta <= 52 ; +523 : douta <= 52 ; +524 : douta <= 52 ; +525 : douta <= 52 ; +526 : douta <= 52 ; +527 : douta <= 52 ; +528 : douta <= 52 ; +529 : douta <= 52 ; +530 : douta <= 52 ; +531 : douta <= 52 ; +532 : douta <= 52 ; +533 : douta <= 52 ; +534 : douta <= 52 ; +535 : douta <= 52 ; +536 : douta <= 52 ; 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<= 52 ; +585 : douta <= 52 ; +586 : douta <= 52 ; +587 : douta <= 52 ; +588 : douta <= 52 ; +589 : douta <= 52 ; +590 : douta <= 52 ; +591 : douta <= 52 ; +592 : douta <= 52 ; +593 : douta <= 52 ; +594 : douta <= 52 ; +595 : douta <= 52 ; +596 : douta <= 52 ; +597 : douta <= 52 ; +598 : douta <= 52 ; +599 : douta <= 52 ; +600 : douta <= 52 ; +601 : douta <= 52 ; +602 : douta <= 52 ; +603 : douta <= 52 ; +604 : douta <= 52 ; +605 : douta <= 52 ; +606 : douta <= 52 ; +607 : douta <= 52 ; +608 : douta <= 52 ; +609 : douta <= 52 ; +610 : douta <= 52 ; +611 : douta <= 52 ; +612 : douta <= 52 ; +613 : douta <= 52 ; +614 : douta <= 52 ; +615 : douta <= 52 ; +616 : douta <= 52 ; +617 : douta <= 52 ; +618 : douta <= 52 ; +619 : douta <= 52 ; +620 : douta <= 52 ; +621 : douta <= 52 ; +622 : douta <= 52 ; +623 : douta <= 52 ; +624 : douta <= 52 ; +625 : douta <= 52 ; +626 : douta <= 52 ; +627 : douta <= 52 ; +628 : douta <= 52 ; +629 : douta <= 52 ; +630 : douta <= 52 ; +631 : douta <= 52 ; +632 : douta <= 52 ; +633 : douta <= 52 ; +634 : douta <= 52 ; +635 : douta <= 52 ; +636 : douta <= 52 ; +637 : douta <= 52 ; +638 : douta <= 52 ; +639 : douta <= 52 ; +640 : douta <= 52 ; +641 : douta <= 52 ; +642 : douta <= 52 ; +643 : douta <= 52 ; +644 : douta <= 52 ; +645 : douta <= 52 ; +646 : douta <= 52 ; +647 : douta <= 52 ; +648 : douta <= 52 ; +649 : douta <= 52 ; +650 : douta <= 52 ; +651 : douta <= 52 ; +652 : douta <= 52 ; +653 : douta <= 52 ; +654 : douta <= 52 ; +655 : douta <= 52 ; +656 : douta <= 52 ; +657 : douta <= 52 ; +658 : douta <= 52 ; +659 : douta <= 52 ; +660 : douta <= 52 ; +661 : douta <= 52 ; +662 : douta <= 52 ; +663 : douta <= 52 ; +664 : douta <= 52 ; +665 : douta <= 52 ; +666 : douta <= 52 ; +667 : douta <= 52 ; +668 : douta <= 52 ; +669 : douta <= 52 ; +670 : douta <= 52 ; +671 : douta <= 52 ; +672 : douta <= 52 ; +673 : douta <= 52 ; +674 : douta <= 52 ; +675 : douta <= 52 ; +676 : douta <= 52 ; +677 : douta <= 52 ; +678 : douta <= 52 ; +679 : douta <= 52 ; +680 : douta <= 52 ; +681 : douta <= 52 ; +682 : douta <= 52 ; +683 : douta <= 52 ; +684 : douta <= 52 ; +685 : douta <= 52 ; +686 : douta <= 52 ; +687 : douta <= 52 ; +688 : douta <= 52 ; +689 : douta <= 52 ; +690 : douta <= 52 ; +691 : douta <= 52 ; +692 : douta <= 52 ; +693 : douta <= 52 ; +694 : douta <= 52 ; +695 : douta <= 52 ; +696 : douta <= 52 ; +697 : douta <= 52 ; +698 : douta <= 52 ; +699 : douta <= 52 ; +700 : douta <= 52 ; +701 : douta <= 52 ; +702 : douta <= 52 ; +703 : douta <= 52 ; +704 : douta <= 52 ; +705 : douta <= 52 ; +706 : douta <= 52 ; +707 : douta <= 52 ; +708 : douta <= 52 ; +709 : douta <= 52 ; +710 : douta <= 52 ; +711 : douta <= 52 ; +712 : douta <= 52 ; +713 : douta <= 52 ; +714 : douta <= 52 ; +715 : douta <= 52 ; +716 : douta <= 52 ; +717 : douta <= 52 ; +718 : douta <= 52 ; +719 : douta <= 52 ; +720 : douta <= 52 ; +721 : douta <= 52 ; +722 : douta <= 52 ; +723 : douta <= 52 ; +724 : douta <= 52 ; +725 : douta <= 52 ; +726 : douta <= 52 ; +727 : douta <= 52 ; +728 : douta <= 52 ; +729 : douta <= 52 ; +730 : douta <= 52 ; +731 : douta <= 52 ; +732 : douta <= 52 ; +733 : douta <= 52 ; +734 : douta <= 52 ; +735 : douta <= 52 ; +736 : douta <= 52 ; +737 : douta <= 52 ; +738 : douta <= 52 ; +739 : douta <= 52 ; +740 : douta <= 52 ; +741 : douta <= 52 ; +742 : douta <= 52 ; +743 : douta <= 52 ; +744 : douta <= 52 ; +745 : douta <= 52 ; +746 : douta <= 52 ; +747 : douta <= 52 ; +748 : douta <= 52 ; +749 : douta <= 52 ; +750 : douta <= 52 ; +751 : douta <= 52 ; +752 : douta <= 52 ; +753 : douta <= 52 ; +754 : douta <= 52 ; +755 : douta <= 52 ; +756 : douta <= 52 ; +757 : douta <= 52 ; +758 : douta <= 52 ; +759 : douta <= 52 ; +760 : douta <= 52 ; +761 : douta <= 52 ; +762 : douta <= 52 ; +763 : douta <= 52 ; +764 : douta <= 52 ; +765 : douta <= 52 ; +766 : douta <= 52 ; +767 : douta <= 52 ; +768 : douta <= 52 ; +769 : douta <= 52 ; +770 : douta <= 52 ; +771 : douta <= 52 ; +772 : douta <= 52 ; +773 : douta <= 52 ; +774 : douta <= 52 ; +775 : douta <= 52 ; +776 : douta <= 52 ; +777 : douta <= 52 ; +778 : douta <= 52 ; +779 : douta <= 52 ; +780 : douta <= 52 ; +781 : douta <= 52 ; +782 : douta <= 52 ; +783 : douta <= 52 ; +784 : douta <= 52 ; +785 : douta <= 52 ; +786 : douta <= 52 ; +787 : douta <= 52 ; +788 : douta <= 52 ; +789 : douta <= 52 ; +790 : douta <= 52 ; +791 : douta <= 52 ; +792 : douta <= 52 ; +793 : douta <= 52 ; +794 : douta <= 52 ; +795 : douta <= 52 ; +796 : douta <= 52 ; +797 : douta <= 52 ; +798 : douta <= 52 ; +799 : douta <= 52 ; +800 : douta <= 52 ; +801 : douta <= 52 ; +802 : douta <= 52 ; +803 : douta <= 52 ; +804 : douta <= 52 ; +805 : douta <= 52 ; +806 : douta <= 52 ; +807 : douta <= 52 ; +808 : douta <= 52 ; +809 : douta <= 52 ; +810 : douta <= 52 ; +811 : douta <= 52 ; +812 : douta <= 52 ; +813 : douta <= 52 ; +814 : douta <= 52 ; +815 : douta <= 52 ; +816 : douta <= 52 ; +817 : douta <= 52 ; +818 : douta <= 52 ; +819 : douta <= 52 ; +820 : douta <= 52 ; +821 : douta <= 52 ; +822 : douta <= 52 ; +823 : douta <= 52 ; +824 : douta <= 52 ; +825 : douta <= 53 ; +826 : douta <= 53 ; +827 : douta <= 53 ; +828 : douta <= 53 ; +829 : douta <= 53 ; +830 : douta <= 53 ; +831 : douta <= 53 ; +832 : douta <= 53 ; +833 : douta <= 53 ; +834 : douta <= 53 ; +835 : douta <= 53 ; +836 : douta <= 53 ; +837 : douta <= 53 ; +838 : douta <= 53 ; +839 : douta <= 53 ; +840 : douta <= 53 ; +841 : douta <= 53 ; +842 : douta <= 53 ; +843 : douta <= 53 ; +844 : douta <= 53 ; +845 : douta <= 53 ; +846 : douta <= 53 ; +847 : douta <= 53 ; +848 : douta <= 53 ; +849 : douta <= 53 ; +850 : douta <= 53 ; +851 : douta <= 53 ; +852 : douta <= 53 ; +853 : douta <= 53 ; +854 : douta <= 53 ; +855 : douta <= 53 ; +856 : douta <= 53 ; +857 : douta <= 53 ; +858 : douta <= 53 ; +859 : douta <= 53 ; +860 : douta <= 53 ; +861 : douta <= 53 ; +862 : douta <= 53 ; +863 : douta <= 53 ; +864 : douta <= 53 ; +865 : douta <= 53 ; +866 : douta <= 53 ; +867 : douta <= 53 ; +868 : douta <= 53 ; +869 : douta <= 53 ; +870 : douta <= 53 ; +871 : douta <= 53 ; +872 : douta <= 53 ; +873 : douta <= 53 ; +874 : douta <= 53 ; +875 : douta <= 53 ; +876 : douta <= 53 ; +877 : douta <= 53 ; +878 : douta <= 53 ; +879 : douta <= 53 ; +880 : douta <= 53 ; +881 : douta <= 53 ; +882 : douta <= 53 ; +883 : douta <= 53 ; +884 : douta <= 53 ; +885 : douta <= 53 ; +886 : douta <= 53 ; +887 : douta <= 53 ; +888 : douta <= 53 ; +889 : douta <= 53 ; +890 : douta <= 53 ; +891 : douta <= 53 ; +892 : douta <= 53 ; +893 : douta <= 53 ; +894 : douta <= 53 ; +895 : douta <= 53 ; +896 : douta <= 53 ; +897 : douta <= 53 ; +898 : douta <= 53 ; +899 : douta <= 53 ; +900 : douta <= 53 ; +901 : douta <= 53 ; +902 : douta <= 53 ; +903 : douta <= 53 ; +904 : douta <= 53 ; +905 : douta <= 53 ; +906 : douta <= 53 ; +907 : douta <= 53 ; +908 : douta <= 53 ; +909 : douta <= 53 ; +910 : douta <= 53 ; +911 : douta <= 53 ; +912 : douta <= 53 ; +913 : douta <= 53 ; +914 : douta <= 53 ; +915 : douta <= 53 ; +916 : douta <= 53 ; +917 : douta <= 53 ; +918 : douta <= 53 ; +919 : douta <= 53 ; +920 : douta <= 53 ; +921 : douta <= 53 ; +922 : douta <= 53 ; +923 : douta <= 53 ; +924 : douta <= 53 ; +925 : douta <= 53 ; +926 : douta <= 53 ; +927 : douta <= 53 ; +928 : douta <= 53 ; +929 : douta <= 53 ; +930 : douta <= 53 ; +931 : douta <= 53 ; +932 : douta <= 53 ; +933 : douta <= 53 ; +934 : douta <= 53 ; +935 : douta <= 53 ; +936 : douta <= 53 ; +937 : douta <= 53 ; +938 : douta <= 53 ; +939 : douta <= 53 ; +940 : douta <= 53 ; +941 : douta <= 53 ; +942 : douta <= 53 ; +943 : douta <= 53 ; +944 : douta <= 53 ; +945 : douta <= 53 ; +946 : douta <= 53 ; +947 : douta <= 53 ; +948 : douta <= 53 ; +949 : douta <= 53 ; +950 : douta <= 53 ; +951 : douta <= 53 ; +952 : douta <= 53 ; +953 : douta <= 53 ; +954 : douta <= 53 ; +955 : douta <= 53 ; +956 : douta <= 53 ; +957 : douta <= 53 ; +958 : douta <= 53 ; +959 : douta <= 53 ; +960 : douta <= 53 ; +961 : douta <= 53 ; +962 : douta <= 53 ; +963 : douta <= 53 ; +964 : douta <= 53 ; +965 : douta <= 53 ; +966 : douta <= 53 ; +967 : douta <= 53 ; +968 : douta <= 53 ; +969 : douta <= 53 ; +970 : douta <= 53 ; +971 : douta <= 53 ; +972 : douta <= 53 ; +973 : douta <= 53 ; +974 : douta <= 53 ; +975 : douta <= 53 ; +976 : douta <= 53 ; +977 : douta <= 53 ; +978 : douta <= 53 ; +979 : douta <= 53 ; +980 : douta <= 53 ; +981 : douta <= 53 ; +982 : douta <= 53 ; +983 : douta <= 53 ; +984 : douta <= 53 ; +985 : douta <= 53 ; +986 : douta <= 53 ; +987 : douta <= 53 ; +988 : douta <= 53 ; +989 : douta <= 53 ; +990 : douta <= 53 ; +991 : douta <= 53 ; +992 : douta <= 53 ; +993 : douta <= 53 ; +994 : douta <= 53 ; +995 : douta <= 53 ; +996 : douta <= 53 ; +997 : douta <= 53 ; +998 : douta <= 53 ; +999 : douta <= 53 ; +1000 : douta <= 53 ; +1001 : douta <= 53 ; +1002 : douta <= 53 ; +1003 : douta <= 53 ; +1004 : douta <= 53 ; +1005 : douta <= 53 ; +1006 : douta <= 53 ; +1007 : douta <= 53 ; +1008 : douta <= 53 ; +1009 : douta <= 53 ; +1010 : douta <= 53 ; +1011 : douta <= 53 ; +1012 : douta <= 53 ; +1013 : douta <= 53 ; +1014 : douta <= 53 ; +1015 : douta <= 53 ; +1016 : douta <= 53 ; +1017 : douta <= 53 ; +1018 : douta <= 53 ; +1019 : douta <= 53 ; +1020 : douta <= 53 ; +1021 : douta <= 53 ; +1022 : douta <= 53 ; +1023 : douta <= 53 ; +1024 : douta <= 53 ; +1025 : douta <= 53 ; +1026 : douta <= 53 ; +1027 : douta <= 53 ; +1028 : douta <= 53 ; +1029 : douta <= 53 ; +1030 : douta <= 53 ; +1031 : douta <= 53 ; +1032 : douta <= 53 ; +1033 : douta <= 53 ; +1034 : douta <= 53 ; +1035 : douta <= 53 ; +1036 : douta <= 53 ; +1037 : douta <= 53 ; +1038 : douta <= 53 ; +1039 : douta <= 53 ; +1040 : douta <= 53 ; +1041 : douta <= 53 ; +1042 : douta <= 53 ; +1043 : douta <= 53 ; +1044 : douta <= 53 ; +1045 : douta <= 53 ; +1046 : douta <= 53 ; +1047 : douta <= 53 ; +1048 : douta <= 53 ; +1049 : douta <= 53 ; +1050 : douta <= 53 ; +1051 : douta <= 53 ; +1052 : douta <= 53 ; +1053 : douta <= 53 ; +1054 : douta <= 53 ; +1055 : douta <= 53 ; +1056 : douta <= 53 ; +1057 : douta <= 53 ; +1058 : douta <= 53 ; +1059 : douta <= 53 ; +1060 : douta <= 53 ; +1061 : douta <= 53 ; +1062 : douta <= 53 ; +1063 : douta <= 53 ; +1064 : douta <= 53 ; +1065 : douta <= 53 ; +1066 : douta <= 53 ; +1067 : douta <= 53 ; +1068 : douta <= 53 ; +1069 : douta <= 53 ; +1070 : douta <= 53 ; +1071 : douta <= 53 ; +1072 : douta <= 53 ; +1073 : douta <= 53 ; +1074 : douta <= 53 ; +1075 : douta <= 53 ; +1076 : douta <= 53 ; +1077 : douta <= 53 ; +1078 : douta <= 53 ; +1079 : douta <= 53 ; +1080 : douta <= 53 ; +1081 : douta <= 53 ; +1082 : douta <= 53 ; +1083 : douta <= 53 ; +1084 : douta <= 53 ; +1085 : douta <= 53 ; +1086 : douta <= 53 ; +1087 : douta <= 53 ; +1088 : douta <= 53 ; +1089 : douta <= 53 ; +1090 : douta <= 53 ; +1091 : douta <= 53 ; +1092 : douta <= 53 ; +1093 : douta <= 53 ; +1094 : douta <= 53 ; +1095 : douta <= 53 ; +1096 : douta <= 53 ; +1097 : douta <= 53 ; +1098 : douta <= 53 ; +1099 : douta <= 53 ; +1100 : douta <= 53 ; +1101 : douta <= 53 ; +1102 : douta <= 53 ; +1103 : douta <= 53 ; +1104 : douta <= 53 ; +1105 : douta <= 53 ; +1106 : douta <= 53 ; +1107 : douta <= 53 ; +1108 : douta <= 53 ; +1109 : douta <= 53 ; +1110 : douta <= 53 ; +1111 : douta <= 53 ; +1112 : douta <= 53 ; +1113 : douta <= 53 ; +1114 : douta <= 53 ; +1115 : douta <= 53 ; +1116 : douta <= 53 ; +1117 : douta <= 53 ; +1118 : douta <= 53 ; +1119 : douta <= 53 ; +1120 : douta <= 53 ; +1121 : douta <= 53 ; +1122 : douta <= 53 ; +1123 : douta <= 53 ; +1124 : douta <= 53 ; +1125 : douta <= 53 ; +1126 : douta <= 53 ; +1127 : douta <= 53 ; +1128 : douta <= 53 ; +1129 : douta <= 53 ; +1130 : douta <= 53 ; +1131 : douta <= 53 ; +1132 : douta <= 53 ; +1133 : douta <= 53 ; +1134 : douta <= 53 ; +1135 : douta <= 53 ; +1136 : douta <= 53 ; +1137 : douta <= 53 ; +1138 : douta <= 53 ; +1139 : douta <= 53 ; +1140 : douta <= 53 ; +1141 : douta <= 53 ; +1142 : douta <= 53 ; +1143 : douta <= 53 ; +1144 : douta <= 53 ; +1145 : douta <= 53 ; +1146 : douta <= 53 ; +1147 : douta <= 53 ; +1148 : douta <= 53 ; +1149 : douta <= 53 ; +1150 : douta <= 53 ; +1151 : douta <= 53 ; +1152 : douta <= 53 ; +1153 : douta <= 53 ; +1154 : douta <= 53 ; +1155 : douta <= 53 ; +1156 : douta <= 53 ; +1157 : douta <= 53 ; +1158 : douta <= 53 ; +1159 : douta <= 53 ; +1160 : douta <= 53 ; +1161 : douta <= 53 ; +1162 : douta <= 53 ; +1163 : douta <= 53 ; +1164 : douta <= 53 ; +1165 : douta <= 53 ; +1166 : douta <= 53 ; +1167 : douta <= 53 ; +1168 : douta <= 53 ; +1169 : douta <= 53 ; +1170 : douta <= 53 ; +1171 : douta <= 53 ; +1172 : douta <= 53 ; +1173 : douta <= 53 ; +1174 : douta <= 53 ; +1175 : douta <= 53 ; +1176 : douta <= 53 ; +1177 : douta <= 53 ; +1178 : douta <= 53 ; +1179 : douta <= 53 ; +1180 : douta <= 53 ; +1181 : douta <= 53 ; +1182 : douta <= 53 ; +1183 : douta <= 53 ; +1184 : douta <= 53 ; +1185 : douta <= 53 ; +1186 : douta <= 53 ; +1187 : douta <= 53 ; +1188 : douta <= 53 ; +1189 : douta <= 53 ; +1190 : douta <= 53 ; +1191 : douta <= 53 ; +1192 : douta <= 53 ; +1193 : douta <= 53 ; +1194 : douta <= 53 ; +1195 : douta <= 53 ; +1196 : douta <= 53 ; +1197 : douta <= 53 ; +1198 : douta <= 53 ; +1199 : douta <= 53 ; +1200 : douta <= 53 ; +1201 : douta <= 53 ; +1202 : douta <= 53 ; +1203 : douta <= 53 ; +1204 : douta <= 53 ; +1205 : douta <= 53 ; +1206 : douta <= 53 ; +1207 : douta <= 53 ; +1208 : douta <= 53 ; +1209 : douta <= 53 ; +1210 : douta <= 53 ; +1211 : douta <= 53 ; +1212 : douta <= 53 ; +1213 : douta <= 53 ; +1214 : douta <= 53 ; +1215 : douta <= 53 ; +1216 : douta <= 53 ; +1217 : douta <= 53 ; +1218 : douta <= 53 ; +1219 : douta <= 53 ; +1220 : douta <= 53 ; +1221 : douta <= 53 ; +1222 : douta <= 53 ; +1223 : douta <= 53 ; +1224 : douta <= 53 ; +1225 : douta <= 54 ; +1226 : douta <= 54 ; +1227 : douta <= 54 ; +1228 : douta <= 54 ; +1229 : douta <= 54 ; +1230 : douta <= 54 ; +1231 : douta <= 54 ; +1232 : douta <= 54 ; +1233 : douta <= 54 ; +1234 : douta <= 54 ; +1235 : douta <= 54 ; +1236 : douta <= 54 ; +1237 : douta <= 54 ; +1238 : douta <= 54 ; +1239 : douta <= 54 ; +1240 : douta <= 54 ; +1241 : douta <= 54 ; +1242 : douta <= 54 ; +1243 : douta <= 54 ; +1244 : douta <= 54 ; +1245 : douta <= 54 ; +1246 : douta <= 54 ; +1247 : douta <= 54 ; +1248 : douta <= 54 ; +1249 : douta <= 54 ; +1250 : douta <= 54 ; +1251 : douta <= 54 ; +1252 : douta <= 54 ; +1253 : douta <= 54 ; +1254 : douta <= 54 ; +1255 : douta <= 54 ; +1256 : douta <= 54 ; +1257 : douta <= 54 ; +1258 : douta <= 54 ; +1259 : douta <= 54 ; +1260 : douta <= 54 ; +1261 : douta <= 54 ; +1262 : douta <= 54 ; +1263 : douta <= 54 ; +1264 : douta <= 54 ; +1265 : douta <= 54 ; +1266 : douta <= 54 ; +1267 : douta <= 54 ; +1268 : douta <= 54 ; +1269 : douta <= 54 ; +1270 : douta <= 54 ; +1271 : douta <= 54 ; +1272 : douta <= 54 ; +1273 : douta <= 54 ; +1274 : douta <= 54 ; +1275 : douta <= 54 ; +1276 : douta <= 54 ; +1277 : douta <= 54 ; +1278 : douta <= 54 ; +1279 : douta <= 54 ; +1280 : douta <= 54 ; +1281 : douta <= 54 ; +1282 : douta <= 54 ; +1283 : douta <= 54 ; +1284 : douta <= 54 ; +1285 : douta <= 54 ; +1286 : douta <= 54 ; +1287 : douta <= 54 ; +1288 : douta <= 54 ; +1289 : douta <= 54 ; +1290 : douta <= 54 ; +1291 : douta <= 54 ; +1292 : douta <= 54 ; +1293 : douta <= 54 ; +1294 : douta <= 54 ; +1295 : douta <= 54 ; +1296 : douta <= 54 ; +1297 : douta <= 54 ; +1298 : douta <= 54 ; +1299 : douta <= 54 ; +1300 : douta <= 54 ; +1301 : douta <= 54 ; +1302 : douta <= 54 ; +1303 : douta <= 54 ; +1304 : douta <= 54 ; +1305 : douta <= 54 ; +1306 : douta <= 54 ; +1307 : douta <= 54 ; +1308 : douta <= 54 ; +1309 : douta <= 54 ; +1310 : douta <= 54 ; +1311 : douta <= 54 ; +1312 : douta <= 54 ; +1313 : douta <= 54 ; +1314 : douta <= 54 ; +1315 : douta <= 54 ; +1316 : douta <= 54 ; +1317 : douta <= 54 ; +1318 : douta <= 54 ; +1319 : douta <= 54 ; +1320 : douta <= 54 ; +1321 : douta <= 54 ; +1322 : douta <= 54 ; +1323 : douta <= 54 ; +1324 : douta <= 54 ; +1325 : douta <= 54 ; +1326 : douta <= 54 ; +1327 : douta <= 54 ; +1328 : douta <= 54 ; +1329 : douta <= 54 ; +1330 : douta <= 54 ; +1331 : douta <= 54 ; +1332 : douta <= 54 ; +1333 : douta <= 54 ; +1334 : douta <= 54 ; +1335 : douta <= 54 ; +1336 : douta <= 54 ; +1337 : douta <= 54 ; +1338 : douta <= 54 ; +1339 : douta <= 54 ; +1340 : douta <= 54 ; +1341 : douta <= 54 ; +1342 : douta <= 54 ; +1343 : douta <= 54 ; +1344 : douta <= 54 ; +1345 : douta <= 54 ; +1346 : douta <= 54 ; +1347 : douta <= 54 ; +1348 : douta <= 54 ; +1349 : douta <= 54 ; +1350 : douta <= 54 ; +1351 : douta <= 54 ; +1352 : douta <= 54 ; +1353 : douta <= 54 ; +1354 : douta <= 54 ; +1355 : douta <= 54 ; +1356 : douta <= 54 ; +1357 : douta <= 54 ; +1358 : douta <= 54 ; +1359 : douta <= 54 ; +1360 : douta <= 54 ; +1361 : douta <= 54 ; +1362 : douta <= 54 ; +1363 : douta <= 54 ; +1364 : douta <= 54 ; +1365 : douta <= 54 ; +1366 : douta <= 54 ; +1367 : douta <= 54 ; +1368 : douta <= 54 ; +1369 : douta <= 54 ; +1370 : douta <= 54 ; +1371 : douta <= 54 ; +1372 : douta <= 54 ; +1373 : douta <= 54 ; +1374 : douta <= 54 ; +1375 : douta <= 54 ; +1376 : douta <= 54 ; +1377 : douta <= 54 ; +1378 : douta <= 54 ; +1379 : douta <= 54 ; +1380 : douta <= 54 ; +1381 : douta <= 54 ; +1382 : douta <= 54 ; +1383 : douta <= 54 ; +1384 : douta <= 54 ; +1385 : douta <= 54 ; +1386 : douta <= 54 ; +1387 : douta <= 54 ; +1388 : douta <= 54 ; +1389 : douta <= 54 ; +1390 : douta <= 54 ; +1391 : douta <= 54 ; +1392 : douta <= 54 ; +1393 : douta <= 54 ; +1394 : douta <= 54 ; +1395 : douta <= 54 ; +1396 : douta <= 54 ; +1397 : douta <= 54 ; +1398 : douta <= 54 ; +1399 : douta <= 54 ; +1400 : douta <= 54 ; +1401 : douta <= 54 ; +1402 : douta <= 54 ; +1403 : douta <= 54 ; +1404 : douta <= 54 ; +1405 : douta <= 54 ; +1406 : douta <= 54 ; +1407 : douta <= 54 ; +1408 : douta <= 54 ; +1409 : douta <= 54 ; +1410 : douta <= 54 ; +1411 : douta <= 54 ; +1412 : douta <= 54 ; +1413 : douta <= 54 ; +1414 : douta <= 54 ; +1415 : douta <= 54 ; +1416 : douta <= 54 ; +1417 : douta <= 54 ; +1418 : douta <= 54 ; +1419 : douta <= 54 ; +1420 : douta <= 54 ; +1421 : douta <= 54 ; +1422 : douta <= 54 ; +1423 : douta <= 54 ; +1424 : douta <= 54 ; +1425 : douta <= 54 ; +1426 : douta <= 54 ; +1427 : douta <= 54 ; +1428 : douta <= 54 ; +1429 : douta <= 54 ; +1430 : douta <= 54 ; +1431 : douta <= 54 ; +1432 : douta <= 54 ; +1433 : douta <= 54 ; +1434 : douta <= 54 ; +1435 : douta <= 54 ; +1436 : douta <= 54 ; +1437 : douta <= 54 ; +1438 : douta <= 54 ; +1439 : douta <= 54 ; +1440 : douta <= 54 ; +1441 : douta <= 54 ; +1442 : douta <= 54 ; +1443 : douta <= 54 ; +1444 : douta <= 54 ; +1445 : douta <= 54 ; +1446 : douta <= 54 ; +1447 : douta <= 54 ; +1448 : douta <= 54 ; +1449 : douta <= 54 ; +1450 : douta <= 54 ; +1451 : douta <= 54 ; +1452 : douta <= 54 ; +1453 : douta <= 54 ; +1454 : douta <= 54 ; +1455 : douta <= 54 ; +1456 : douta <= 54 ; +1457 : douta <= 54 ; +1458 : douta <= 54 ; +1459 : douta <= 54 ; +1460 : douta <= 54 ; +1461 : douta <= 54 ; +1462 : douta <= 54 ; +1463 : douta <= 54 ; +1464 : douta <= 54 ; +1465 : douta <= 54 ; +1466 : douta <= 54 ; +1467 : douta <= 54 ; +1468 : douta <= 54 ; +1469 : douta <= 54 ; +1470 : douta <= 54 ; +1471 : douta <= 54 ; +1472 : douta <= 54 ; +1473 : douta <= 54 ; +1474 : douta <= 54 ; +1475 : douta <= 54 ; +1476 : douta <= 54 ; +1477 : douta <= 54 ; +1478 : douta <= 54 ; +1479 : douta <= 54 ; +1480 : douta <= 54 ; +1481 : douta <= 54 ; +1482 : douta <= 54 ; +1483 : douta <= 54 ; +1484 : douta <= 54 ; +1485 : douta <= 54 ; +1486 : douta <= 54 ; +1487 : douta <= 54 ; +1488 : douta <= 54 ; +1489 : douta <= 54 ; +1490 : douta <= 54 ; +1491 : douta <= 54 ; +1492 : douta <= 54 ; +1493 : douta <= 54 ; +1494 : douta <= 54 ; +1495 : douta <= 54 ; +1496 : douta <= 54 ; +1497 : douta <= 54 ; +1498 : douta <= 54 ; +1499 : douta <= 54 ; +1500 : douta <= 54 ; +1501 : douta <= 54 ; +1502 : douta <= 54 ; +1503 : douta <= 54 ; +1504 : douta <= 54 ; +1505 : douta <= 54 ; +1506 : douta <= 54 ; +1507 : douta <= 54 ; +1508 : douta <= 54 ; +1509 : douta <= 54 ; +1510 : douta <= 54 ; +1511 : douta <= 54 ; +1512 : douta <= 54 ; +1513 : douta <= 54 ; +1514 : douta <= 54 ; +1515 : douta <= 54 ; +1516 : douta <= 54 ; +1517 : douta <= 54 ; +1518 : douta <= 54 ; +1519 : douta <= 54 ; +1520 : douta <= 54 ; +1521 : douta <= 54 ; +1522 : douta <= 54 ; +1523 : douta <= 54 ; +1524 : douta <= 54 ; +1525 : douta <= 54 ; +1526 : douta <= 54 ; +1527 : douta <= 54 ; +1528 : douta <= 54 ; +1529 : douta <= 54 ; +1530 : douta <= 54 ; +1531 : douta <= 54 ; +1532 : douta <= 54 ; +1533 : douta <= 54 ; +1534 : douta <= 54 ; +1535 : douta <= 54 ; +1536 : douta <= 54 ; +1537 : douta <= 54 ; +1538 : douta <= 54 ; +1539 : douta <= 54 ; +1540 : douta <= 54 ; +1541 : douta <= 54 ; +1542 : douta <= 54 ; +1543 : douta <= 54 ; +1544 : douta <= 54 ; +1545 : douta <= 54 ; +1546 : douta <= 54 ; +1547 : douta <= 54 ; +1548 : douta <= 54 ; +1549 : douta <= 54 ; +1550 : douta <= 54 ; +1551 : douta <= 54 ; +1552 : douta <= 54 ; +1553 : douta <= 54 ; +1554 : douta <= 54 ; +1555 : douta <= 54 ; +1556 : douta <= 54 ; +1557 : douta <= 54 ; +1558 : douta <= 54 ; +1559 : douta <= 54 ; +1560 : douta <= 54 ; +1561 : douta <= 54 ; +1562 : douta <= 54 ; +1563 : douta <= 54 ; +1564 : douta <= 54 ; +1565 : douta <= 54 ; +1566 : douta <= 54 ; +1567 : douta <= 54 ; +1568 : douta <= 54 ; +1569 : douta <= 54 ; +1570 : douta <= 54 ; +1571 : douta <= 54 ; +1572 : douta <= 54 ; +1573 : douta <= 54 ; +1574 : douta <= 54 ; +1575 : douta <= 54 ; +1576 : douta <= 54 ; +1577 : douta <= 54 ; +1578 : douta <= 54 ; +1579 : douta <= 54 ; +1580 : douta <= 54 ; +1581 : douta <= 54 ; +1582 : douta <= 54 ; +1583 : douta <= 54 ; +1584 : douta <= 54 ; +1585 : douta <= 54 ; +1586 : douta <= 54 ; +1587 : douta <= 54 ; +1588 : douta <= 54 ; +1589 : douta <= 54 ; +1590 : douta <= 54 ; +1591 : douta <= 54 ; +1592 : douta <= 54 ; +1593 : douta <= 54 ; +1594 : douta <= 54 ; +1595 : douta <= 54 ; +1596 : douta <= 54 ; +1597 : douta <= 54 ; +1598 : douta <= 54 ; +1599 : douta <= 54 ; +1600 : douta <= 54 ; +1601 : douta <= 54 ; +1602 : douta <= 54 ; +1603 : douta <= 54 ; +1604 : douta <= 54 ; +1605 : douta <= 54 ; +1606 : douta <= 54 ; +1607 : douta <= 54 ; +1608 : douta <= 54 ; +1609 : douta <= 54 ; +1610 : douta <= 54 ; +1611 : douta <= 54 ; +1612 : douta <= 54 ; +1613 : douta <= 54 ; +1614 : douta <= 54 ; +1615 : douta <= 54 ; +1616 : douta <= 54 ; +1617 : douta <= 54 ; +1618 : douta <= 54 ; +1619 : douta <= 54 ; +1620 : douta <= 54 ; +1621 : douta <= 54 ; +1622 : douta <= 54 ; +1623 : douta <= 54 ; +1624 : douta <= 54 ; +1625 : douta <= 55 ; +1626 : douta <= 55 ; +1627 : douta <= 55 ; +1628 : douta <= 55 ; +1629 : douta <= 55 ; +1630 : douta <= 55 ; +1631 : douta <= 55 ; +1632 : douta <= 55 ; +1633 : douta <= 55 ; +1634 : douta <= 55 ; +1635 : douta <= 55 ; +1636 : douta <= 55 ; +1637 : douta <= 55 ; +1638 : douta <= 55 ; +1639 : douta <= 55 ; +1640 : douta <= 55 ; +1641 : douta <= 55 ; +1642 : douta <= 55 ; +1643 : douta <= 55 ; +1644 : douta <= 55 ; +1645 : douta <= 55 ; +1646 : douta <= 55 ; +1647 : douta <= 55 ; +1648 : douta <= 55 ; +1649 : douta <= 55 ; +1650 : douta <= 55 ; +1651 : douta <= 55 ; +1652 : douta <= 55 ; +1653 : douta <= 55 ; +1654 : douta <= 55 ; +1655 : douta <= 55 ; +1656 : douta <= 55 ; +1657 : douta <= 55 ; +1658 : douta <= 55 ; +1659 : douta <= 55 ; +1660 : douta <= 55 ; +1661 : douta <= 55 ; +1662 : douta <= 55 ; +1663 : douta <= 55 ; +1664 : douta <= 55 ; +1665 : douta <= 55 ; +1666 : douta <= 55 ; +1667 : douta <= 55 ; +1668 : douta <= 55 ; +1669 : douta <= 55 ; +1670 : douta <= 55 ; +1671 : douta <= 55 ; +1672 : douta <= 55 ; +1673 : douta <= 55 ; +1674 : douta <= 55 ; +1675 : douta <= 55 ; +1676 : douta <= 55 ; +1677 : douta <= 55 ; +1678 : douta <= 55 ; +1679 : douta <= 55 ; +1680 : douta <= 55 ; +1681 : douta <= 55 ; +1682 : douta <= 55 ; +1683 : douta <= 55 ; +1684 : douta <= 55 ; +1685 : douta <= 55 ; +1686 : douta <= 55 ; +1687 : douta <= 55 ; +1688 : douta <= 55 ; +1689 : douta <= 55 ; +1690 : douta <= 55 ; +1691 : douta <= 55 ; +1692 : douta <= 55 ; +1693 : douta <= 55 ; +1694 : douta <= 55 ; +1695 : douta <= 55 ; +1696 : douta <= 55 ; +1697 : douta <= 55 ; +1698 : douta <= 55 ; +1699 : douta <= 55 ; +1700 : douta <= 55 ; +1701 : douta <= 55 ; +1702 : douta <= 55 ; +1703 : douta <= 55 ; +1704 : douta <= 55 ; +1705 : douta <= 55 ; +1706 : douta <= 55 ; +1707 : douta <= 55 ; +1708 : douta <= 55 ; +1709 : douta <= 55 ; +1710 : douta <= 55 ; +1711 : douta <= 55 ; +1712 : douta <= 55 ; +1713 : douta <= 55 ; +1714 : douta <= 55 ; +1715 : douta <= 55 ; +1716 : douta <= 55 ; +1717 : douta <= 55 ; +1718 : douta <= 55 ; +1719 : douta <= 55 ; +1720 : douta <= 55 ; +1721 : douta <= 55 ; +1722 : douta <= 55 ; +1723 : douta <= 55 ; +1724 : douta <= 55 ; +1725 : douta <= 55 ; +1726 : douta <= 55 ; +1727 : douta <= 55 ; +1728 : douta <= 55 ; +1729 : douta <= 55 ; +1730 : douta <= 55 ; +1731 : douta <= 55 ; +1732 : douta <= 55 ; +1733 : douta <= 55 ; +1734 : douta <= 55 ; +1735 : douta <= 55 ; +1736 : douta <= 55 ; +1737 : douta <= 55 ; +1738 : douta <= 55 ; +1739 : douta <= 55 ; +1740 : douta <= 55 ; +1741 : douta <= 55 ; +1742 : douta <= 55 ; +1743 : douta <= 55 ; +1744 : douta <= 55 ; +1745 : douta <= 55 ; +1746 : douta <= 55 ; +1747 : douta <= 55 ; +1748 : douta <= 55 ; +1749 : douta <= 55 ; +1750 : douta <= 55 ; +1751 : douta <= 55 ; +1752 : douta <= 55 ; +1753 : douta <= 55 ; +1754 : douta <= 55 ; +1755 : douta <= 55 ; +1756 : douta <= 55 ; +1757 : douta <= 55 ; +1758 : douta <= 55 ; +1759 : douta <= 55 ; +1760 : douta <= 55 ; +1761 : douta <= 55 ; +1762 : douta <= 55 ; +1763 : douta <= 55 ; +1764 : douta <= 55 ; +1765 : douta <= 55 ; +1766 : douta <= 55 ; +1767 : douta <= 55 ; +1768 : douta <= 55 ; +1769 : douta <= 55 ; +1770 : douta <= 55 ; +1771 : douta <= 55 ; +1772 : douta <= 55 ; +1773 : douta <= 55 ; +1774 : douta <= 55 ; +1775 : douta <= 55 ; +1776 : douta <= 55 ; +1777 : douta <= 55 ; +1778 : douta <= 55 ; +1779 : douta <= 55 ; +1780 : douta <= 55 ; +1781 : douta <= 55 ; +1782 : douta <= 55 ; +1783 : douta <= 55 ; +1784 : douta <= 55 ; +1785 : douta <= 55 ; +1786 : douta <= 55 ; +1787 : douta <= 55 ; +1788 : douta <= 55 ; +1789 : douta <= 55 ; +1790 : douta <= 55 ; +1791 : douta <= 55 ; +1792 : douta <= 55 ; +1793 : douta <= 55 ; +1794 : douta <= 55 ; +1795 : douta <= 55 ; +1796 : douta <= 55 ; +1797 : douta <= 55 ; +1798 : douta <= 55 ; +1799 : douta <= 55 ; +1800 : douta <= 55 ; +1801 : douta <= 55 ; +1802 : douta <= 55 ; +1803 : douta <= 55 ; +1804 : douta <= 55 ; +1805 : douta <= 55 ; +1806 : douta <= 55 ; +1807 : douta <= 55 ; +1808 : douta <= 55 ; +1809 : douta <= 55 ; +1810 : douta <= 55 ; +1811 : douta <= 55 ; +1812 : douta <= 55 ; +1813 : douta <= 55 ; +1814 : douta <= 55 ; +1815 : douta <= 55 ; +1816 : douta <= 55 ; +1817 : douta <= 55 ; +1818 : douta <= 55 ; +1819 : douta <= 55 ; +1820 : douta <= 55 ; +1821 : douta <= 55 ; +1822 : douta <= 55 ; +1823 : douta <= 55 ; +1824 : douta <= 55 ; +1825 : douta <= 55 ; +1826 : douta <= 55 ; +1827 : douta <= 55 ; +1828 : douta <= 55 ; +1829 : douta <= 55 ; +1830 : douta <= 55 ; +1831 : douta <= 55 ; +1832 : douta <= 55 ; +1833 : douta <= 55 ; +1834 : douta <= 55 ; +1835 : douta <= 55 ; +1836 : douta <= 55 ; +1837 : douta <= 55 ; +1838 : douta <= 55 ; +1839 : douta <= 55 ; +1840 : douta <= 55 ; +1841 : douta <= 55 ; +1842 : douta <= 55 ; +1843 : douta <= 55 ; +1844 : douta <= 55 ; +1845 : douta <= 55 ; +1846 : douta <= 55 ; +1847 : douta <= 55 ; +1848 : douta <= 55 ; +1849 : douta <= 55 ; +1850 : douta <= 55 ; +1851 : douta <= 55 ; +1852 : douta <= 55 ; +1853 : douta <= 55 ; +1854 : douta <= 55 ; +1855 : douta <= 55 ; +1856 : douta <= 55 ; +1857 : douta <= 55 ; +1858 : douta <= 55 ; +1859 : douta <= 55 ; +1860 : douta <= 55 ; +1861 : douta <= 55 ; +1862 : douta <= 55 ; +1863 : douta <= 55 ; +1864 : douta <= 55 ; +1865 : douta <= 55 ; +1866 : douta <= 55 ; +1867 : douta <= 55 ; +1868 : douta <= 55 ; +1869 : douta <= 55 ; +1870 : douta <= 55 ; +1871 : douta <= 55 ; +1872 : douta <= 55 ; +1873 : douta <= 55 ; +1874 : douta <= 55 ; +1875 : douta <= 55 ; +1876 : douta <= 55 ; +1877 : douta <= 55 ; +1878 : douta <= 55 ; +1879 : douta <= 55 ; +1880 : douta <= 55 ; +1881 : douta <= 55 ; +1882 : douta <= 55 ; +1883 : douta <= 55 ; +1884 : douta <= 55 ; +1885 : douta <= 55 ; +1886 : douta <= 55 ; +1887 : douta <= 55 ; +1888 : douta <= 55 ; +1889 : douta <= 55 ; +1890 : douta <= 55 ; +1891 : douta <= 55 ; +1892 : douta <= 55 ; +1893 : douta <= 55 ; +1894 : douta <= 55 ; +1895 : douta <= 55 ; +1896 : douta <= 55 ; +1897 : douta <= 55 ; +1898 : douta <= 55 ; +1899 : douta <= 55 ; +1900 : douta <= 55 ; +1901 : douta <= 55 ; +1902 : douta <= 55 ; +1903 : douta <= 55 ; +1904 : douta <= 55 ; +1905 : douta <= 55 ; +1906 : douta <= 55 ; +1907 : douta <= 55 ; +1908 : douta <= 55 ; +1909 : douta <= 55 ; +1910 : douta <= 55 ; +1911 : douta <= 55 ; +1912 : douta <= 55 ; +1913 : douta <= 55 ; +1914 : douta <= 55 ; +1915 : douta <= 55 ; +1916 : douta <= 55 ; +1917 : douta <= 55 ; +1918 : douta <= 55 ; +1919 : douta <= 55 ; +1920 : douta <= 55 ; +1921 : douta <= 55 ; +1922 : douta <= 55 ; +1923 : douta <= 55 ; +1924 : douta <= 55 ; +1925 : douta <= 55 ; +1926 : douta <= 55 ; +1927 : douta <= 55 ; +1928 : douta <= 55 ; +1929 : douta <= 55 ; +1930 : douta <= 55 ; +1931 : douta <= 55 ; +1932 : douta <= 55 ; +1933 : douta <= 55 ; +1934 : douta <= 55 ; +1935 : douta <= 55 ; +1936 : douta <= 55 ; +1937 : douta <= 55 ; +1938 : douta <= 55 ; +1939 : douta <= 55 ; +1940 : douta <= 55 ; +1941 : douta <= 55 ; +1942 : douta <= 55 ; +1943 : douta <= 55 ; +1944 : douta <= 55 ; +1945 : douta <= 55 ; +1946 : douta <= 55 ; +1947 : douta <= 55 ; +1948 : douta <= 55 ; +1949 : douta <= 55 ; +1950 : douta <= 55 ; +1951 : douta <= 55 ; +1952 : douta <= 55 ; +1953 : douta <= 55 ; +1954 : douta <= 55 ; +1955 : douta <= 55 ; +1956 : douta <= 55 ; +1957 : douta <= 55 ; +1958 : douta <= 55 ; +1959 : douta <= 55 ; +1960 : douta <= 55 ; +1961 : douta <= 55 ; +1962 : douta <= 55 ; +1963 : douta <= 55 ; +1964 : douta <= 55 ; +1965 : douta <= 55 ; +1966 : douta <= 55 ; +1967 : douta <= 55 ; +1968 : douta <= 55 ; +1969 : douta <= 55 ; +1970 : douta <= 55 ; +1971 : douta <= 55 ; +1972 : douta <= 55 ; +1973 : douta <= 55 ; +1974 : douta <= 55 ; +1975 : douta <= 55 ; +1976 : douta <= 55 ; +1977 : douta <= 55 ; +1978 : douta <= 55 ; +1979 : douta <= 55 ; +1980 : douta <= 55 ; +1981 : douta <= 55 ; +1982 : douta <= 55 ; +1983 : douta <= 55 ; +1984 : douta <= 55 ; +1985 : douta <= 55 ; +1986 : douta <= 55 ; +1987 : douta <= 55 ; +1988 : douta <= 55 ; +1989 : douta <= 55 ; +1990 : douta <= 55 ; +1991 : douta <= 55 ; +1992 : douta <= 55 ; +1993 : douta <= 55 ; +1994 : douta <= 55 ; +1995 : douta <= 55 ; +1996 : douta <= 55 ; +1997 : douta <= 55 ; +1998 : douta <= 55 ; +1999 : douta <= 55 ; +2000 : douta <= 55 ; +2001 : douta <= 55 ; +2002 : douta <= 55 ; +2003 : douta <= 55 ; +2004 : douta <= 55 ; +2005 : douta <= 55 ; +2006 : douta <= 55 ; +2007 : douta <= 55 ; +2008 : douta <= 55 ; +2009 : douta <= 55 ; +2010 : douta <= 55 ; +2011 : douta <= 55 ; +2012 : douta <= 55 ; +2013 : douta <= 55 ; +2014 : douta <= 55 ; +2015 : douta <= 55 ; +2016 : douta <= 55 ; +2017 : douta <= 55 ; +2018 : douta <= 55 ; +2019 : douta <= 55 ; +2020 : douta <= 55 ; +2021 : douta <= 55 ; +2022 : douta <= 55 ; +2023 : douta <= 55 ; +2024 : douta <= 55 ; +2025 : douta <= 56 ; +2026 : douta <= 56 ; +2027 : douta <= 56 ; +2028 : douta <= 56 ; +2029 : douta <= 56 ; +2030 : douta <= 56 ; +2031 : douta <= 56 ; +2032 : douta <= 56 ; +2033 : douta <= 56 ; +2034 : douta <= 56 ; +2035 : douta <= 56 ; +2036 : douta <= 56 ; +2037 : douta <= 56 ; +2038 : douta <= 56 ; +2039 : douta <= 56 ; +2040 : douta <= 56 ; +2041 : douta <= 56 ; +2042 : douta <= 56 ; +2043 : douta <= 56 ; +2044 : douta <= 56 ; +2045 : douta <= 56 ; +2046 : douta <= 56 ; +2047 : douta <= 56 ; +2048 : douta <= 56 ; +2049 : douta <= 56 ; +2050 : douta <= 56 ; +2051 : douta <= 56 ; +2052 : douta <= 56 ; +2053 : douta <= 56 ; +2054 : douta <= 56 ; +2055 : douta <= 56 ; +2056 : douta <= 56 ; +2057 : douta <= 56 ; +2058 : douta <= 56 ; +2059 : douta <= 56 ; +2060 : douta <= 56 ; +2061 : douta <= 56 ; +2062 : douta <= 56 ; +2063 : douta <= 56 ; +2064 : douta <= 56 ; +2065 : douta <= 56 ; +2066 : douta <= 56 ; +2067 : douta <= 56 ; +2068 : douta <= 56 ; +2069 : douta <= 56 ; +2070 : douta <= 56 ; +2071 : douta <= 56 ; +2072 : douta <= 56 ; +2073 : douta <= 56 ; +2074 : douta <= 56 ; +2075 : douta <= 56 ; +2076 : douta <= 56 ; +2077 : douta <= 56 ; +2078 : douta <= 56 ; +2079 : douta <= 56 ; +2080 : douta <= 56 ; +2081 : douta <= 56 ; +2082 : douta <= 56 ; +2083 : douta <= 56 ; +2084 : douta <= 56 ; +2085 : douta <= 56 ; +2086 : douta <= 56 ; +2087 : douta <= 56 ; +2088 : douta <= 56 ; +2089 : douta <= 56 ; +2090 : douta <= 56 ; +2091 : douta <= 56 ; +2092 : douta <= 56 ; +2093 : douta <= 56 ; +2094 : douta <= 56 ; +2095 : douta <= 56 ; +2096 : douta <= 56 ; +2097 : douta <= 56 ; +2098 : douta <= 56 ; +2099 : douta <= 56 ; +2100 : douta <= 56 ; +2101 : douta <= 56 ; +2102 : douta <= 56 ; +2103 : douta <= 56 ; +2104 : douta <= 56 ; +2105 : douta <= 56 ; +2106 : douta <= 56 ; +2107 : douta <= 56 ; +2108 : douta <= 56 ; +2109 : douta <= 56 ; +2110 : douta <= 56 ; +2111 : douta <= 56 ; +2112 : douta <= 56 ; +2113 : douta <= 56 ; +2114 : douta <= 56 ; +2115 : douta <= 56 ; +2116 : douta <= 56 ; +2117 : douta <= 56 ; +2118 : douta <= 56 ; +2119 : douta <= 56 ; +2120 : douta <= 56 ; +2121 : douta <= 56 ; +2122 : douta <= 56 ; +2123 : douta <= 56 ; +2124 : douta <= 56 ; +2125 : douta <= 56 ; +2126 : douta <= 56 ; +2127 : douta <= 56 ; +2128 : douta <= 56 ; +2129 : douta <= 56 ; +2130 : douta <= 56 ; +2131 : douta <= 56 ; +2132 : douta <= 56 ; +2133 : douta <= 56 ; +2134 : douta <= 56 ; +2135 : douta <= 56 ; +2136 : douta <= 56 ; +2137 : douta <= 56 ; +2138 : douta <= 56 ; +2139 : douta <= 56 ; +2140 : douta <= 56 ; +2141 : douta <= 56 ; +2142 : douta <= 56 ; +2143 : douta <= 56 ; +2144 : douta <= 56 ; +2145 : douta <= 56 ; +2146 : douta <= 56 ; +2147 : douta <= 56 ; +2148 : douta <= 56 ; +2149 : douta <= 56 ; +2150 : douta <= 56 ; +2151 : douta <= 56 ; +2152 : douta <= 56 ; +2153 : douta <= 56 ; +2154 : douta <= 56 ; +2155 : douta <= 56 ; +2156 : douta <= 56 ; +2157 : douta <= 56 ; +2158 : douta <= 56 ; +2159 : douta <= 56 ; +2160 : douta <= 56 ; +2161 : douta <= 56 ; +2162 : douta <= 56 ; +2163 : douta <= 56 ; +2164 : douta <= 56 ; +2165 : douta <= 56 ; +2166 : douta <= 56 ; +2167 : douta <= 56 ; +2168 : douta <= 56 ; +2169 : douta <= 56 ; +2170 : douta <= 56 ; +2171 : douta <= 56 ; +2172 : douta <= 56 ; +2173 : douta <= 56 ; +2174 : douta <= 56 ; +2175 : douta <= 56 ; +2176 : douta <= 56 ; +2177 : douta <= 56 ; +2178 : douta <= 56 ; +2179 : douta <= 56 ; +2180 : douta <= 56 ; +2181 : douta <= 56 ; +2182 : douta <= 56 ; +2183 : douta <= 56 ; +2184 : douta <= 56 ; +2185 : douta <= 56 ; +2186 : douta <= 56 ; +2187 : douta <= 56 ; +2188 : douta <= 56 ; +2189 : douta <= 56 ; +2190 : douta <= 56 ; +2191 : douta <= 56 ; +2192 : douta <= 56 ; +2193 : douta <= 56 ; +2194 : douta <= 56 ; +2195 : douta <= 56 ; +2196 : douta <= 56 ; +2197 : douta <= 56 ; +2198 : douta <= 56 ; +2199 : douta <= 56 ; +2200 : douta <= 56 ; +2201 : douta <= 56 ; +2202 : douta <= 56 ; +2203 : douta <= 56 ; +2204 : douta <= 56 ; +2205 : douta <= 56 ; +2206 : douta <= 56 ; +2207 : douta <= 56 ; +2208 : douta <= 56 ; +2209 : douta <= 56 ; +2210 : douta <= 56 ; +2211 : douta <= 56 ; +2212 : douta <= 56 ; +2213 : douta <= 56 ; +2214 : douta <= 56 ; +2215 : douta <= 56 ; +2216 : douta <= 56 ; +2217 : douta <= 56 ; +2218 : douta <= 56 ; +2219 : douta <= 56 ; +2220 : douta <= 56 ; +2221 : douta <= 56 ; +2222 : douta <= 56 ; +2223 : douta <= 56 ; +2224 : douta <= 56 ; +2225 : douta <= 56 ; +2226 : douta <= 56 ; +2227 : douta <= 56 ; +2228 : douta <= 56 ; +2229 : douta <= 56 ; +2230 : douta <= 56 ; +2231 : douta <= 56 ; +2232 : douta <= 56 ; +2233 : douta <= 56 ; +2234 : douta <= 56 ; +2235 : douta <= 56 ; +2236 : douta <= 56 ; +2237 : douta <= 56 ; +2238 : douta <= 56 ; +2239 : douta <= 56 ; +2240 : douta <= 56 ; +2241 : douta <= 56 ; +2242 : douta <= 56 ; +2243 : douta <= 56 ; +2244 : douta <= 56 ; +2245 : douta <= 56 ; +2246 : douta <= 56 ; +2247 : douta <= 56 ; +2248 : douta <= 56 ; +2249 : douta <= 56 ; +2250 : douta <= 56 ; +2251 : douta <= 56 ; +2252 : douta <= 56 ; +2253 : douta <= 56 ; +2254 : douta <= 56 ; +2255 : douta <= 56 ; +2256 : douta <= 56 ; +2257 : douta <= 56 ; +2258 : douta <= 56 ; +2259 : douta <= 56 ; +2260 : douta <= 56 ; +2261 : douta <= 56 ; +2262 : douta <= 56 ; +2263 : douta <= 56 ; +2264 : douta <= 56 ; +2265 : douta <= 56 ; +2266 : douta <= 56 ; +2267 : douta <= 56 ; +2268 : douta <= 56 ; +2269 : douta <= 56 ; +2270 : douta <= 56 ; +2271 : douta <= 56 ; +2272 : douta <= 56 ; +2273 : douta <= 56 ; +2274 : douta <= 56 ; +2275 : douta <= 56 ; +2276 : douta <= 56 ; +2277 : douta <= 56 ; +2278 : douta <= 56 ; +2279 : douta <= 56 ; +2280 : douta <= 56 ; +2281 : douta <= 56 ; +2282 : douta <= 56 ; +2283 : douta <= 56 ; +2284 : douta <= 56 ; +2285 : douta <= 56 ; +2286 : douta <= 56 ; +2287 : douta <= 56 ; +2288 : douta <= 56 ; +2289 : douta <= 56 ; +2290 : douta <= 56 ; +2291 : douta <= 56 ; +2292 : douta <= 56 ; +2293 : douta <= 56 ; +2294 : douta <= 56 ; +2295 : douta <= 56 ; +2296 : douta <= 56 ; +2297 : douta <= 56 ; +2298 : douta <= 56 ; +2299 : douta <= 56 ; +2300 : douta <= 56 ; +2301 : douta <= 56 ; +2302 : douta <= 56 ; +2303 : douta <= 56 ; +2304 : douta <= 56 ; +2305 : douta <= 56 ; +2306 : douta <= 56 ; +2307 : douta <= 56 ; +2308 : douta <= 56 ; +2309 : douta <= 56 ; +2310 : douta <= 56 ; +2311 : douta <= 56 ; +2312 : douta <= 56 ; +2313 : douta <= 56 ; +2314 : douta <= 56 ; +2315 : douta <= 56 ; +2316 : douta <= 56 ; +2317 : douta <= 56 ; +2318 : douta <= 56 ; +2319 : douta <= 56 ; +2320 : douta <= 56 ; +2321 : douta <= 56 ; +2322 : douta <= 56 ; +2323 : douta <= 56 ; +2324 : douta <= 56 ; +2325 : douta <= 56 ; +2326 : douta <= 56 ; +2327 : douta <= 56 ; +2328 : douta <= 56 ; +2329 : douta <= 56 ; +2330 : douta <= 56 ; +2331 : douta <= 56 ; +2332 : douta <= 56 ; +2333 : douta <= 56 ; +2334 : douta <= 56 ; +2335 : douta <= 56 ; +2336 : douta <= 56 ; +2337 : douta <= 56 ; +2338 : douta <= 56 ; +2339 : douta <= 56 ; +2340 : douta <= 56 ; +2341 : douta <= 56 ; +2342 : douta <= 56 ; +2343 : douta <= 56 ; +2344 : douta <= 56 ; +2345 : douta <= 56 ; +2346 : douta <= 56 ; +2347 : douta <= 56 ; +2348 : douta <= 56 ; +2349 : douta <= 56 ; +2350 : douta <= 56 ; +2351 : douta <= 56 ; +2352 : douta <= 56 ; +2353 : douta <= 56 ; +2354 : douta <= 56 ; +2355 : douta <= 56 ; +2356 : douta <= 56 ; +2357 : douta <= 56 ; +2358 : douta <= 56 ; +2359 : douta <= 56 ; +2360 : douta <= 56 ; +2361 : douta <= 56 ; +2362 : douta <= 56 ; +2363 : douta <= 56 ; +2364 : douta <= 56 ; +2365 : douta <= 56 ; +2366 : douta <= 56 ; +2367 : douta <= 56 ; +2368 : douta <= 56 ; +2369 : douta <= 56 ; +2370 : douta <= 56 ; +2371 : douta <= 56 ; +2372 : douta <= 56 ; +2373 : douta <= 56 ; +2374 : douta <= 56 ; +2375 : douta <= 56 ; +2376 : douta <= 56 ; +2377 : douta <= 56 ; +2378 : douta <= 56 ; +2379 : douta <= 56 ; +2380 : douta <= 56 ; +2381 : douta <= 56 ; +2382 : douta <= 56 ; +2383 : douta <= 56 ; +2384 : douta <= 56 ; +2385 : douta <= 56 ; +2386 : douta <= 56 ; +2387 : douta <= 56 ; +2388 : douta <= 56 ; +2389 : douta <= 56 ; +2390 : douta <= 56 ; +2391 : douta <= 56 ; +2392 : douta <= 56 ; +2393 : douta <= 56 ; +2394 : douta <= 56 ; +2395 : douta <= 56 ; +2396 : douta <= 56 ; +2397 : douta <= 56 ; +2398 : douta <= 56 ; +2399 : douta <= 56 ; +2400 : douta <= 56 ; +2401 : douta <= 56 ; +2402 : douta <= 56 ; +2403 : douta <= 56 ; +2404 : douta <= 56 ; +2405 : douta <= 56 ; +2406 : douta <= 56 ; +2407 : douta <= 56 ; +2408 : douta <= 56 ; +2409 : douta <= 56 ; +2410 : douta <= 56 ; +2411 : douta <= 56 ; +2412 : douta <= 56 ; +2413 : douta <= 56 ; +2414 : douta <= 56 ; +2415 : douta <= 56 ; +2416 : douta <= 56 ; +2417 : douta <= 56 ; +2418 : douta <= 56 ; +2419 : douta <= 56 ; +2420 : douta <= 56 ; +2421 : douta <= 56 ; +2422 : douta <= 56 ; +2423 : douta <= 56 ; +2424 : douta <= 56 ; +2425 : douta <= 57 ; +2426 : douta <= 57 ; +2427 : douta <= 57 ; +2428 : douta <= 57 ; +2429 : douta <= 57 ; +2430 : douta <= 57 ; +2431 : douta <= 57 ; +2432 : douta <= 57 ; +2433 : douta <= 57 ; +2434 : douta <= 57 ; +2435 : douta <= 57 ; +2436 : douta <= 57 ; +2437 : douta <= 57 ; +2438 : douta <= 57 ; +2439 : douta <= 57 ; +2440 : douta <= 57 ; +2441 : douta <= 57 ; +2442 : douta <= 57 ; +2443 : douta <= 57 ; +2444 : douta <= 57 ; +2445 : douta <= 57 ; +2446 : douta <= 57 ; +2447 : douta <= 57 ; +2448 : douta <= 57 ; +2449 : douta <= 57 ; +2450 : douta <= 57 ; +2451 : douta <= 57 ; +2452 : douta <= 57 ; +2453 : douta <= 57 ; +2454 : douta <= 57 ; +2455 : douta <= 57 ; +2456 : douta <= 57 ; +2457 : douta <= 57 ; +2458 : douta <= 57 ; +2459 : douta <= 57 ; +2460 : douta <= 57 ; +2461 : douta <= 57 ; +2462 : douta <= 57 ; +2463 : douta <= 57 ; +2464 : douta <= 57 ; +2465 : douta <= 57 ; +2466 : douta <= 57 ; +2467 : douta <= 57 ; +2468 : douta <= 57 ; +2469 : douta <= 57 ; +2470 : douta <= 57 ; +2471 : douta <= 57 ; +2472 : douta <= 57 ; +2473 : douta <= 57 ; +2474 : douta <= 57 ; +2475 : douta <= 57 ; +2476 : douta <= 57 ; +2477 : douta <= 57 ; +2478 : douta <= 57 ; +2479 : douta <= 57 ; +2480 : douta <= 57 ; +2481 : douta <= 57 ; +2482 : douta <= 57 ; +2483 : douta <= 57 ; +2484 : douta <= 57 ; +2485 : douta <= 57 ; +2486 : douta <= 57 ; +2487 : douta <= 57 ; +2488 : douta <= 57 ; +2489 : douta <= 57 ; +2490 : douta <= 57 ; +2491 : douta <= 57 ; +2492 : douta <= 57 ; +2493 : douta <= 57 ; +2494 : douta <= 57 ; +2495 : douta <= 57 ; +2496 : douta <= 57 ; +2497 : douta <= 57 ; +2498 : douta <= 57 ; +2499 : douta <= 57 ; +2500 : douta <= 57 ; +2501 : douta <= 57 ; +2502 : douta <= 57 ; +2503 : douta <= 57 ; +2504 : douta <= 57 ; +2505 : douta <= 57 ; +2506 : douta <= 57 ; +2507 : douta <= 57 ; +2508 : douta <= 57 ; +2509 : douta <= 57 ; +2510 : douta <= 57 ; +2511 : douta <= 57 ; +2512 : douta <= 57 ; +2513 : douta <= 57 ; +2514 : douta <= 57 ; +2515 : douta <= 57 ; +2516 : douta <= 57 ; +2517 : douta <= 57 ; +2518 : douta <= 57 ; +2519 : douta <= 57 ; +2520 : douta <= 57 ; +2521 : douta <= 57 ; +2522 : douta <= 57 ; +2523 : douta <= 57 ; +2524 : douta <= 57 ; +2525 : douta <= 57 ; +2526 : douta <= 57 ; +2527 : douta <= 57 ; +2528 : douta <= 57 ; +2529 : douta <= 57 ; +2530 : douta <= 57 ; +2531 : douta <= 57 ; +2532 : douta <= 57 ; +2533 : douta <= 57 ; +2534 : douta <= 57 ; +2535 : douta <= 57 ; +2536 : douta <= 57 ; +2537 : douta <= 57 ; +2538 : douta <= 57 ; +2539 : douta <= 57 ; +2540 : douta <= 57 ; +2541 : douta <= 57 ; +2542 : douta <= 57 ; +2543 : douta <= 57 ; +2544 : douta <= 57 ; +2545 : douta <= 57 ; +2546 : douta <= 57 ; +2547 : douta <= 57 ; +2548 : douta <= 57 ; +2549 : douta <= 57 ; +2550 : douta <= 57 ; +2551 : douta <= 57 ; +2552 : douta <= 57 ; +2553 : douta <= 57 ; +2554 : douta <= 57 ; +2555 : douta <= 57 ; +2556 : douta <= 57 ; +2557 : douta <= 57 ; +2558 : douta <= 57 ; +2559 : douta <= 57 ; +2560 : douta <= 57 ; +2561 : douta <= 57 ; +2562 : douta <= 57 ; +2563 : douta <= 57 ; +2564 : douta <= 57 ; +2565 : douta <= 57 ; +2566 : douta <= 57 ; +2567 : douta <= 57 ; +2568 : douta <= 57 ; +2569 : douta <= 57 ; +2570 : douta <= 57 ; +2571 : douta <= 57 ; +2572 : douta <= 57 ; +2573 : douta <= 57 ; +2574 : douta <= 57 ; +2575 : douta <= 57 ; +2576 : douta <= 57 ; +2577 : douta <= 57 ; +2578 : douta <= 57 ; +2579 : douta <= 57 ; +2580 : douta <= 57 ; +2581 : douta <= 57 ; +2582 : douta <= 57 ; +2583 : douta <= 57 ; +2584 : douta <= 57 ; +2585 : douta <= 57 ; +2586 : douta <= 57 ; +2587 : douta <= 57 ; +2588 : douta <= 57 ; +2589 : douta <= 57 ; +2590 : douta <= 57 ; +2591 : douta <= 57 ; +2592 : douta <= 57 ; +2593 : douta <= 57 ; +2594 : douta <= 57 ; +2595 : douta <= 57 ; +2596 : douta <= 57 ; +2597 : douta <= 57 ; +2598 : douta <= 57 ; +2599 : douta <= 57 ; +2600 : douta <= 57 ; +2601 : douta <= 57 ; +2602 : douta <= 57 ; +2603 : douta <= 57 ; +2604 : douta <= 57 ; +2605 : douta <= 57 ; +2606 : douta <= 57 ; +2607 : douta <= 57 ; +2608 : douta <= 57 ; +2609 : douta <= 57 ; +2610 : douta <= 57 ; +2611 : douta <= 57 ; +2612 : douta <= 57 ; +2613 : douta <= 57 ; +2614 : douta <= 57 ; +2615 : douta <= 57 ; +2616 : douta <= 57 ; +2617 : douta <= 57 ; +2618 : douta <= 57 ; +2619 : douta <= 57 ; +2620 : douta <= 57 ; +2621 : douta <= 57 ; +2622 : douta <= 57 ; +2623 : douta <= 57 ; +2624 : douta <= 57 ; +2625 : douta <= 57 ; +2626 : douta <= 57 ; +2627 : douta <= 57 ; +2628 : douta <= 57 ; +2629 : douta <= 57 ; +2630 : douta <= 57 ; +2631 : douta <= 57 ; +2632 : douta <= 57 ; +2633 : douta <= 57 ; +2634 : douta <= 57 ; +2635 : douta <= 57 ; +2636 : douta <= 57 ; +2637 : douta <= 57 ; +2638 : douta <= 57 ; +2639 : douta <= 57 ; +2640 : douta <= 57 ; +2641 : douta <= 57 ; +2642 : douta <= 57 ; +2643 : douta <= 57 ; +2644 : douta <= 57 ; +2645 : douta <= 57 ; +2646 : douta <= 57 ; +2647 : douta <= 57 ; +2648 : douta <= 57 ; +2649 : douta <= 57 ; +2650 : douta <= 57 ; +2651 : douta <= 57 ; +2652 : douta <= 57 ; +2653 : douta <= 57 ; +2654 : douta <= 57 ; +2655 : douta <= 57 ; +2656 : douta <= 57 ; +2657 : douta <= 57 ; +2658 : douta <= 57 ; +2659 : douta <= 57 ; +2660 : douta <= 57 ; +2661 : douta <= 57 ; +2662 : douta <= 57 ; +2663 : douta <= 57 ; +2664 : douta <= 57 ; +2665 : douta <= 57 ; +2666 : douta <= 57 ; +2667 : douta <= 57 ; +2668 : douta <= 57 ; +2669 : douta <= 57 ; +2670 : douta <= 57 ; +2671 : douta <= 57 ; +2672 : douta <= 57 ; +2673 : douta <= 57 ; +2674 : douta <= 57 ; +2675 : douta <= 57 ; +2676 : douta <= 57 ; +2677 : douta <= 57 ; +2678 : douta <= 57 ; +2679 : douta <= 57 ; +2680 : douta <= 57 ; +2681 : douta <= 57 ; +2682 : douta <= 57 ; +2683 : douta <= 57 ; +2684 : douta <= 57 ; +2685 : douta <= 57 ; +2686 : douta <= 57 ; +2687 : douta <= 57 ; +2688 : douta <= 57 ; +2689 : douta <= 57 ; +2690 : douta <= 57 ; +2691 : douta <= 57 ; +2692 : douta <= 57 ; +2693 : douta <= 57 ; +2694 : douta <= 57 ; +2695 : douta <= 57 ; +2696 : douta <= 57 ; +2697 : douta <= 57 ; +2698 : douta <= 57 ; +2699 : douta <= 57 ; +2700 : douta <= 57 ; +2701 : douta <= 57 ; +2702 : douta <= 57 ; +2703 : douta <= 57 ; +2704 : douta <= 57 ; +2705 : douta <= 57 ; +2706 : douta <= 57 ; +2707 : douta <= 57 ; +2708 : douta <= 57 ; +2709 : douta <= 57 ; +2710 : douta <= 57 ; +2711 : douta <= 57 ; +2712 : douta <= 57 ; +2713 : douta <= 57 ; +2714 : douta <= 57 ; +2715 : douta <= 57 ; +2716 : douta <= 57 ; +2717 : douta <= 57 ; +2718 : douta <= 57 ; +2719 : douta <= 57 ; +2720 : douta <= 57 ; +2721 : douta <= 57 ; +2722 : douta <= 57 ; +2723 : douta <= 57 ; +2724 : douta <= 57 ; +2725 : douta <= 57 ; +2726 : douta <= 57 ; +2727 : douta <= 57 ; +2728 : douta <= 57 ; +2729 : douta <= 57 ; +2730 : douta <= 57 ; +2731 : douta <= 57 ; +2732 : douta <= 57 ; +2733 : douta <= 57 ; +2734 : douta <= 57 ; +2735 : douta <= 57 ; +2736 : douta <= 57 ; +2737 : douta <= 57 ; +2738 : douta <= 57 ; +2739 : douta <= 57 ; +2740 : douta <= 57 ; +2741 : douta <= 57 ; +2742 : douta <= 57 ; +2743 : douta <= 57 ; +2744 : douta <= 57 ; +2745 : douta <= 57 ; +2746 : douta <= 57 ; +2747 : douta <= 57 ; +2748 : douta <= 57 ; +2749 : douta <= 57 ; +2750 : douta <= 57 ; +2751 : douta <= 57 ; +2752 : douta <= 57 ; +2753 : douta <= 57 ; +2754 : douta <= 57 ; +2755 : douta <= 57 ; +2756 : douta <= 57 ; +2757 : douta <= 57 ; +2758 : douta <= 57 ; +2759 : douta <= 57 ; +2760 : douta <= 57 ; +2761 : douta <= 57 ; +2762 : douta <= 57 ; +2763 : douta <= 57 ; +2764 : douta <= 57 ; +2765 : douta <= 57 ; +2766 : douta <= 57 ; +2767 : douta <= 57 ; +2768 : douta <= 57 ; +2769 : douta <= 57 ; +2770 : douta <= 57 ; +2771 : douta <= 57 ; +2772 : douta <= 57 ; +2773 : douta <= 57 ; +2774 : douta <= 57 ; +2775 : douta <= 57 ; +2776 : douta <= 57 ; +2777 : douta <= 57 ; +2778 : douta <= 57 ; +2779 : douta <= 57 ; +2780 : douta <= 57 ; +2781 : douta <= 57 ; +2782 : douta <= 57 ; +2783 : douta <= 57 ; +2784 : douta <= 57 ; +2785 : douta <= 57 ; +2786 : douta <= 57 ; +2787 : douta <= 57 ; +2788 : douta <= 57 ; +2789 : douta <= 57 ; +2790 : douta <= 57 ; +2791 : douta <= 57 ; +2792 : douta <= 57 ; +2793 : douta <= 57 ; +2794 : douta <= 57 ; +2795 : douta <= 57 ; +2796 : douta <= 57 ; +2797 : douta <= 57 ; +2798 : douta <= 57 ; +2799 : douta <= 57 ; +2800 : douta <= 57 ; +2801 : douta <= 57 ; +2802 : douta <= 57 ; +2803 : douta <= 57 ; +2804 : douta <= 57 ; +2805 : douta <= 57 ; +2806 : douta <= 57 ; +2807 : douta <= 57 ; +2808 : douta <= 57 ; +2809 : douta <= 57 ; +2810 : douta <= 57 ; +2811 : douta <= 57 ; +2812 : douta <= 57 ; +2813 : douta <= 57 ; +2814 : douta <= 57 ; +2815 : douta <= 57 ; +2816 : douta <= 57 ; +2817 : douta <= 57 ; +2818 : douta <= 57 ; +2819 : douta <= 57 ; +2820 : douta <= 57 ; +2821 : douta <= 57 ; +2822 : douta <= 57 ; +2823 : douta <= 57 ; +2824 : douta <= 57 ; +2825 : douta <= 58 ; +2826 : douta <= 58 ; +2827 : douta <= 58 ; +2828 : douta <= 58 ; +2829 : douta <= 58 ; +2830 : douta <= 58 ; +2831 : douta <= 58 ; +2832 : douta <= 58 ; +2833 : douta <= 58 ; +2834 : douta <= 58 ; +2835 : douta <= 58 ; +2836 : douta <= 58 ; +2837 : douta <= 58 ; +2838 : douta <= 58 ; +2839 : douta <= 58 ; +2840 : douta <= 58 ; +2841 : douta <= 58 ; +2842 : douta <= 58 ; +2843 : douta <= 58 ; +2844 : douta <= 58 ; +2845 : douta <= 58 ; +2846 : douta <= 58 ; +2847 : douta <= 58 ; +2848 : douta <= 58 ; +2849 : douta <= 58 ; +2850 : douta <= 58 ; +2851 : douta <= 58 ; +2852 : douta <= 58 ; +2853 : douta <= 58 ; +2854 : douta <= 58 ; +2855 : douta <= 58 ; +2856 : douta <= 58 ; +2857 : douta <= 58 ; +2858 : douta <= 58 ; +2859 : douta <= 58 ; +2860 : douta <= 58 ; +2861 : douta <= 58 ; +2862 : douta <= 58 ; +2863 : douta <= 58 ; +2864 : douta <= 58 ; +2865 : douta <= 58 ; +2866 : douta <= 58 ; +2867 : douta <= 58 ; +2868 : douta <= 58 ; +2869 : douta <= 58 ; +2870 : douta <= 58 ; +2871 : douta <= 58 ; +2872 : douta <= 58 ; +2873 : douta <= 58 ; +2874 : douta <= 58 ; +2875 : douta <= 58 ; +2876 : douta <= 58 ; +2877 : douta <= 58 ; +2878 : douta <= 58 ; +2879 : douta <= 58 ; +2880 : douta <= 58 ; +2881 : douta <= 58 ; +2882 : douta <= 58 ; +2883 : douta <= 58 ; +2884 : douta <= 58 ; +2885 : douta <= 58 ; +2886 : douta <= 58 ; +2887 : douta <= 58 ; +2888 : douta <= 58 ; +2889 : douta <= 58 ; +2890 : douta <= 58 ; +2891 : douta <= 58 ; +2892 : douta <= 58 ; +2893 : douta <= 58 ; +2894 : douta <= 58 ; +2895 : douta <= 58 ; +2896 : douta <= 58 ; +2897 : douta <= 58 ; +2898 : douta <= 58 ; +2899 : douta <= 58 ; +2900 : douta <= 58 ; +2901 : douta <= 58 ; +2902 : douta <= 58 ; +2903 : douta <= 58 ; +2904 : douta <= 58 ; +2905 : douta <= 58 ; +2906 : douta <= 58 ; +2907 : douta <= 58 ; +2908 : douta <= 58 ; +2909 : douta <= 58 ; +2910 : douta <= 58 ; +2911 : douta <= 58 ; +2912 : douta <= 58 ; +2913 : douta <= 58 ; +2914 : douta <= 58 ; +2915 : douta <= 58 ; +2916 : douta <= 58 ; +2917 : douta <= 58 ; +2918 : douta <= 58 ; +2919 : douta <= 58 ; +2920 : douta <= 58 ; +2921 : douta <= 58 ; +2922 : douta <= 58 ; +2923 : douta <= 58 ; +2924 : douta <= 58 ; +2925 : douta <= 58 ; +2926 : douta <= 58 ; +2927 : douta <= 58 ; +2928 : douta <= 58 ; +2929 : douta <= 58 ; +2930 : douta <= 58 ; +2931 : douta <= 58 ; +2932 : douta <= 58 ; +2933 : douta <= 58 ; +2934 : douta <= 58 ; +2935 : douta <= 58 ; +2936 : douta <= 58 ; +2937 : douta <= 58 ; +2938 : douta <= 58 ; +2939 : douta <= 58 ; +2940 : douta <= 58 ; +2941 : douta <= 58 ; +2942 : douta <= 58 ; +2943 : douta <= 58 ; +2944 : douta <= 58 ; +2945 : douta <= 58 ; +2946 : douta <= 58 ; +2947 : douta <= 58 ; +2948 : douta <= 58 ; +2949 : douta <= 58 ; +2950 : douta <= 58 ; +2951 : douta <= 58 ; +2952 : douta <= 58 ; +2953 : douta <= 58 ; +2954 : douta <= 58 ; +2955 : douta <= 58 ; +2956 : douta <= 58 ; +2957 : douta <= 58 ; +2958 : douta <= 58 ; +2959 : douta <= 58 ; +2960 : douta <= 58 ; +2961 : douta <= 58 ; +2962 : douta <= 58 ; +2963 : douta <= 58 ; +2964 : douta <= 58 ; +2965 : douta <= 58 ; +2966 : douta <= 58 ; +2967 : douta <= 58 ; +2968 : douta <= 58 ; +2969 : douta <= 58 ; +2970 : douta <= 58 ; +2971 : douta <= 58 ; +2972 : douta <= 58 ; +2973 : douta <= 58 ; +2974 : douta <= 58 ; +2975 : douta <= 58 ; +2976 : douta <= 58 ; +2977 : douta <= 58 ; +2978 : douta <= 58 ; +2979 : douta <= 58 ; +2980 : douta <= 58 ; +2981 : douta <= 58 ; +2982 : douta <= 58 ; +2983 : douta <= 58 ; +2984 : douta <= 58 ; +2985 : douta <= 58 ; +2986 : douta <= 58 ; +2987 : douta <= 58 ; +2988 : douta <= 58 ; +2989 : douta <= 58 ; +2990 : douta <= 58 ; +2991 : douta <= 58 ; +2992 : douta <= 58 ; +2993 : douta <= 58 ; +2994 : douta <= 58 ; +2995 : douta <= 58 ; +2996 : douta <= 58 ; +2997 : douta <= 58 ; +2998 : douta <= 58 ; +2999 : douta <= 58 ; +3000 : douta <= 58 ; +3001 : douta <= 58 ; +3002 : douta <= 58 ; +3003 : douta <= 58 ; +3004 : douta <= 58 ; +3005 : douta <= 58 ; +3006 : douta <= 58 ; +3007 : douta <= 58 ; +3008 : douta <= 58 ; +3009 : douta <= 58 ; +3010 : douta <= 58 ; +3011 : douta <= 58 ; +3012 : douta <= 58 ; +3013 : douta <= 58 ; +3014 : douta <= 58 ; +3015 : douta <= 58 ; +3016 : douta <= 58 ; +3017 : douta <= 58 ; +3018 : douta <= 58 ; +3019 : douta <= 58 ; +3020 : douta <= 58 ; +3021 : douta <= 58 ; +3022 : douta <= 58 ; +3023 : douta <= 58 ; +3024 : douta <= 58 ; +3025 : douta <= 58 ; +3026 : douta <= 58 ; +3027 : douta <= 58 ; +3028 : douta <= 58 ; +3029 : douta <= 58 ; +3030 : douta <= 58 ; +3031 : douta <= 58 ; +3032 : douta <= 58 ; +3033 : douta <= 58 ; +3034 : douta <= 58 ; +3035 : douta <= 58 ; +3036 : douta <= 58 ; +3037 : douta <= 58 ; +3038 : douta <= 58 ; +3039 : douta <= 58 ; +3040 : douta <= 58 ; +3041 : douta <= 58 ; +3042 : douta <= 58 ; +3043 : douta <= 58 ; +3044 : douta <= 58 ; +3045 : douta <= 58 ; +3046 : douta <= 58 ; +3047 : douta <= 58 ; +3048 : douta <= 58 ; +3049 : douta <= 58 ; +3050 : douta <= 58 ; +3051 : douta <= 58 ; +3052 : douta <= 58 ; +3053 : douta <= 58 ; +3054 : douta <= 58 ; +3055 : douta <= 58 ; +3056 : douta <= 58 ; +3057 : douta <= 58 ; +3058 : douta <= 58 ; +3059 : douta <= 58 ; +3060 : douta <= 58 ; +3061 : douta <= 58 ; +3062 : douta <= 58 ; +3063 : douta <= 58 ; +3064 : douta <= 58 ; +3065 : douta <= 58 ; +3066 : douta <= 58 ; +3067 : douta <= 58 ; +3068 : douta <= 58 ; +3069 : douta <= 58 ; +3070 : douta <= 58 ; +3071 : douta <= 58 ; +3072 : douta <= 58 ; +3073 : douta <= 58 ; +3074 : douta <= 58 ; +3075 : douta <= 58 ; +3076 : douta <= 58 ; +3077 : douta <= 58 ; +3078 : douta <= 58 ; +3079 : douta <= 58 ; +3080 : douta <= 58 ; +3081 : douta <= 58 ; +3082 : douta <= 58 ; +3083 : douta <= 58 ; +3084 : douta <= 58 ; +3085 : douta <= 58 ; +3086 : douta <= 58 ; +3087 : douta <= 58 ; +3088 : douta <= 58 ; +3089 : douta <= 58 ; +3090 : douta <= 58 ; +3091 : douta <= 58 ; +3092 : douta <= 58 ; +3093 : douta <= 58 ; +3094 : douta <= 58 ; +3095 : douta <= 58 ; +3096 : douta <= 58 ; +3097 : douta <= 58 ; +3098 : douta <= 58 ; +3099 : douta <= 58 ; +3100 : douta <= 58 ; +3101 : douta <= 58 ; +3102 : douta <= 58 ; +3103 : douta <= 58 ; +3104 : douta <= 58 ; +3105 : douta <= 58 ; +3106 : douta <= 58 ; +3107 : douta <= 58 ; +3108 : douta <= 58 ; +3109 : douta <= 58 ; +3110 : douta <= 58 ; +3111 : douta <= 58 ; +3112 : douta <= 58 ; +3113 : douta <= 58 ; +3114 : douta <= 58 ; +3115 : douta <= 58 ; +3116 : douta <= 58 ; +3117 : douta <= 58 ; +3118 : douta <= 58 ; +3119 : douta <= 58 ; +3120 : douta <= 58 ; +3121 : douta <= 58 ; +3122 : douta <= 58 ; +3123 : douta <= 58 ; +3124 : douta <= 58 ; +3125 : douta <= 58 ; +3126 : douta <= 58 ; +3127 : douta <= 58 ; +3128 : douta <= 58 ; +3129 : douta <= 58 ; +3130 : douta <= 58 ; +3131 : douta <= 58 ; +3132 : douta <= 58 ; +3133 : douta <= 58 ; +3134 : douta <= 58 ; +3135 : douta <= 58 ; +3136 : douta <= 58 ; +3137 : douta <= 58 ; +3138 : douta <= 58 ; +3139 : douta <= 58 ; +3140 : douta <= 58 ; +3141 : douta <= 58 ; +3142 : douta <= 58 ; +3143 : douta <= 58 ; +3144 : douta <= 58 ; +3145 : douta <= 58 ; +3146 : douta <= 58 ; +3147 : douta <= 58 ; +3148 : douta <= 58 ; +3149 : douta <= 58 ; +3150 : douta <= 58 ; +3151 : douta <= 58 ; +3152 : douta <= 58 ; +3153 : douta <= 58 ; +3154 : douta <= 58 ; +3155 : douta <= 58 ; +3156 : douta <= 58 ; +3157 : douta <= 58 ; +3158 : douta <= 58 ; +3159 : douta <= 58 ; +3160 : douta <= 58 ; +3161 : douta <= 58 ; +3162 : douta <= 58 ; +3163 : douta <= 58 ; +3164 : douta <= 58 ; +3165 : douta <= 58 ; +3166 : douta <= 58 ; +3167 : douta <= 58 ; +3168 : douta <= 58 ; +3169 : douta <= 58 ; +3170 : douta <= 58 ; +3171 : douta <= 58 ; +3172 : douta <= 58 ; +3173 : douta <= 58 ; +3174 : douta <= 58 ; +3175 : douta <= 58 ; +3176 : douta <= 58 ; +3177 : douta <= 58 ; +3178 : douta <= 58 ; +3179 : douta <= 58 ; +3180 : douta <= 58 ; +3181 : douta <= 58 ; +3182 : douta <= 58 ; +3183 : douta <= 58 ; +3184 : douta <= 58 ; +3185 : douta <= 58 ; +3186 : douta <= 58 ; +3187 : douta <= 58 ; +3188 : douta <= 58 ; +3189 : douta <= 58 ; +3190 : douta <= 58 ; +3191 : douta <= 58 ; +3192 : douta <= 58 ; +3193 : douta <= 58 ; +3194 : douta <= 58 ; +3195 : douta <= 58 ; +3196 : douta <= 58 ; +3197 : douta <= 58 ; +3198 : douta <= 58 ; +3199 : douta <= 58 ; +3200 : douta <= 58 ; +3201 : douta <= 58 ; +3202 : douta <= 58 ; +3203 : douta <= 58 ; +3204 : douta <= 58 ; +3205 : douta <= 58 ; +3206 : douta <= 58 ; +3207 : douta <= 58 ; +3208 : douta <= 58 ; +3209 : douta <= 58 ; +3210 : douta <= 58 ; +3211 : douta <= 58 ; +3212 : douta <= 58 ; +3213 : douta <= 58 ; +3214 : douta <= 58 ; +3215 : douta <= 58 ; +3216 : douta <= 58 ; +3217 : douta <= 58 ; +3218 : douta <= 58 ; +3219 : douta <= 58 ; +3220 : douta <= 58 ; +3221 : douta <= 58 ; +3222 : douta <= 58 ; +3223 : douta <= 58 ; +3224 : douta <= 58 ; +3225 : douta <= 59 ; +3226 : douta <= 59 ; +3227 : douta <= 59 ; +3228 : douta <= 59 ; +3229 : douta <= 59 ; +3230 : douta <= 59 ; +3231 : douta <= 59 ; +3232 : douta <= 59 ; +3233 : douta <= 59 ; +3234 : douta <= 59 ; +3235 : douta <= 59 ; +3236 : douta <= 59 ; +3237 : douta <= 59 ; +3238 : douta <= 59 ; +3239 : douta <= 59 ; +3240 : douta <= 59 ; +3241 : douta <= 59 ; +3242 : douta <= 59 ; +3243 : douta <= 59 ; +3244 : douta <= 59 ; +3245 : douta <= 59 ; +3246 : douta <= 59 ; +3247 : douta <= 59 ; +3248 : douta <= 59 ; +3249 : douta <= 59 ; +3250 : douta <= 59 ; +3251 : douta <= 59 ; +3252 : douta <= 59 ; +3253 : douta <= 59 ; +3254 : douta <= 59 ; +3255 : douta <= 59 ; +3256 : douta <= 59 ; +3257 : douta <= 59 ; +3258 : douta <= 59 ; +3259 : douta <= 59 ; +3260 : douta <= 59 ; +3261 : douta <= 59 ; +3262 : douta <= 59 ; +3263 : douta <= 59 ; +3264 : douta <= 59 ; +3265 : douta <= 59 ; +3266 : douta <= 59 ; +3267 : douta <= 59 ; +3268 : douta <= 59 ; +3269 : douta <= 59 ; +3270 : douta <= 59 ; +3271 : douta <= 59 ; +3272 : douta <= 59 ; +3273 : douta <= 59 ; +3274 : douta <= 59 ; +3275 : douta <= 59 ; +3276 : douta <= 59 ; +3277 : douta <= 59 ; +3278 : douta <= 59 ; +3279 : douta <= 59 ; +3280 : douta <= 59 ; +3281 : douta <= 59 ; +3282 : douta <= 59 ; +3283 : douta <= 59 ; +3284 : douta <= 59 ; +3285 : douta <= 59 ; +3286 : douta <= 59 ; +3287 : douta <= 59 ; +3288 : douta <= 59 ; +3289 : douta <= 59 ; +3290 : douta <= 59 ; +3291 : douta <= 59 ; +3292 : douta <= 59 ; +3293 : douta <= 59 ; +3294 : douta <= 59 ; +3295 : douta <= 59 ; +3296 : douta <= 59 ; +3297 : douta <= 59 ; +3298 : douta <= 59 ; +3299 : douta <= 59 ; +3300 : douta <= 59 ; +3301 : douta <= 59 ; +3302 : douta <= 59 ; +3303 : douta <= 59 ; +3304 : douta <= 59 ; +3305 : douta <= 59 ; +3306 : douta <= 59 ; +3307 : douta <= 59 ; +3308 : douta <= 59 ; +3309 : douta <= 59 ; +3310 : douta <= 59 ; +3311 : douta <= 59 ; +3312 : douta <= 59 ; +3313 : douta <= 59 ; +3314 : douta <= 59 ; +3315 : douta <= 59 ; +3316 : douta <= 59 ; +3317 : douta <= 59 ; +3318 : douta <= 59 ; +3319 : douta <= 59 ; +3320 : douta <= 59 ; +3321 : douta <= 59 ; +3322 : douta <= 59 ; +3323 : douta <= 59 ; +3324 : douta <= 59 ; +3325 : douta <= 59 ; +3326 : douta <= 59 ; +3327 : douta <= 59 ; +3328 : douta <= 59 ; +3329 : douta <= 59 ; +3330 : douta <= 59 ; +3331 : douta <= 59 ; +3332 : douta <= 59 ; +3333 : douta <= 59 ; +3334 : douta <= 59 ; +3335 : douta <= 59 ; +3336 : douta <= 59 ; +3337 : douta <= 59 ; +3338 : douta <= 59 ; +3339 : douta <= 59 ; +3340 : douta <= 59 ; +3341 : douta <= 59 ; +3342 : douta <= 59 ; +3343 : douta <= 59 ; +3344 : douta <= 59 ; +3345 : douta <= 59 ; +3346 : douta <= 59 ; +3347 : douta <= 59 ; +3348 : douta <= 59 ; +3349 : douta <= 59 ; +3350 : douta <= 59 ; +3351 : douta <= 59 ; +3352 : douta <= 59 ; +3353 : douta <= 59 ; +3354 : douta <= 59 ; +3355 : douta <= 59 ; +3356 : douta <= 59 ; +3357 : douta <= 59 ; +3358 : douta <= 59 ; +3359 : douta <= 59 ; +3360 : douta <= 59 ; +3361 : douta <= 59 ; +3362 : douta <= 59 ; +3363 : douta <= 59 ; +3364 : douta <= 59 ; +3365 : douta <= 59 ; +3366 : douta <= 59 ; +3367 : douta <= 59 ; +3368 : douta <= 59 ; +3369 : douta <= 59 ; +3370 : douta <= 59 ; +3371 : douta <= 59 ; +3372 : douta <= 59 ; +3373 : douta <= 59 ; +3374 : douta <= 59 ; +3375 : douta <= 59 ; +3376 : douta <= 59 ; +3377 : douta <= 59 ; +3378 : douta <= 59 ; +3379 : douta <= 59 ; +3380 : douta <= 59 ; +3381 : douta <= 59 ; +3382 : douta <= 59 ; +3383 : douta <= 59 ; +3384 : douta <= 59 ; +3385 : douta <= 59 ; +3386 : douta <= 59 ; +3387 : douta <= 59 ; +3388 : douta <= 59 ; +3389 : douta <= 59 ; +3390 : douta <= 59 ; +3391 : douta <= 59 ; +3392 : douta <= 59 ; +3393 : douta <= 59 ; +3394 : douta <= 59 ; +3395 : douta <= 59 ; +3396 : douta <= 59 ; +3397 : douta <= 59 ; +3398 : douta <= 59 ; +3399 : douta <= 59 ; +3400 : douta <= 59 ; +3401 : douta <= 59 ; +3402 : douta <= 59 ; +3403 : douta <= 59 ; +3404 : douta <= 59 ; +3405 : douta <= 59 ; +3406 : douta <= 59 ; +3407 : douta <= 59 ; +3408 : douta <= 59 ; +3409 : douta <= 59 ; +3410 : douta <= 59 ; +3411 : douta <= 59 ; +3412 : douta <= 59 ; +3413 : douta <= 59 ; +3414 : douta <= 59 ; +3415 : douta <= 59 ; +3416 : douta <= 59 ; +3417 : douta <= 59 ; +3418 : douta <= 59 ; +3419 : douta <= 59 ; +3420 : douta <= 59 ; +3421 : douta <= 59 ; +3422 : douta <= 59 ; +3423 : douta <= 59 ; +3424 : douta <= 59 ; +3425 : douta <= 59 ; +3426 : douta <= 59 ; +3427 : douta <= 59 ; +3428 : douta <= 59 ; +3429 : douta <= 59 ; +3430 : douta <= 59 ; +3431 : douta <= 59 ; +3432 : douta <= 59 ; +3433 : douta <= 59 ; +3434 : douta <= 59 ; +3435 : douta <= 59 ; +3436 : douta <= 59 ; +3437 : douta <= 59 ; +3438 : douta <= 59 ; +3439 : douta <= 59 ; +3440 : douta <= 59 ; +3441 : douta <= 59 ; +3442 : douta <= 59 ; +3443 : douta <= 59 ; +3444 : douta <= 59 ; +3445 : douta <= 59 ; +3446 : douta <= 59 ; +3447 : douta <= 59 ; +3448 : douta <= 59 ; +3449 : douta <= 59 ; +3450 : douta <= 59 ; +3451 : douta <= 59 ; +3452 : douta <= 59 ; +3453 : douta <= 59 ; +3454 : douta <= 59 ; +3455 : douta <= 59 ; +3456 : douta <= 59 ; +3457 : douta <= 59 ; +3458 : douta <= 59 ; +3459 : douta <= 59 ; +3460 : douta <= 59 ; +3461 : douta <= 59 ; +3462 : douta <= 59 ; +3463 : douta <= 59 ; +3464 : douta <= 59 ; +3465 : douta <= 59 ; +3466 : douta <= 59 ; +3467 : douta <= 59 ; +3468 : douta <= 59 ; +3469 : douta <= 59 ; +3470 : douta <= 59 ; +3471 : douta <= 59 ; +3472 : douta <= 59 ; +3473 : douta <= 59 ; +3474 : douta <= 59 ; +3475 : douta <= 59 ; +3476 : douta <= 59 ; +3477 : douta <= 59 ; +3478 : douta <= 59 ; +3479 : douta <= 59 ; +3480 : douta <= 59 ; +3481 : douta <= 59 ; +3482 : douta <= 59 ; +3483 : douta <= 59 ; +3484 : douta <= 59 ; +3485 : douta <= 59 ; +3486 : douta <= 59 ; +3487 : douta <= 59 ; +3488 : douta <= 59 ; +3489 : douta <= 59 ; +3490 : douta <= 59 ; +3491 : douta <= 59 ; +3492 : douta <= 59 ; +3493 : douta <= 59 ; +3494 : douta <= 59 ; +3495 : douta <= 59 ; +3496 : douta <= 59 ; +3497 : douta <= 59 ; +3498 : douta <= 59 ; +3499 : douta <= 59 ; +3500 : douta <= 59 ; + + + +default:douta <= 59 ; +endcase + + +end + +*/ + + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_1.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_1.v new file mode 100644 index 00000000..a52fc093 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_1.v @@ -0,0 +1,348 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:05:24 04/08/2022 +// Design Name: +// Module Name: R_CAL +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module R_CAL_1( +input i_clk , +input i_rstn , +input signed[7:0] i_temp , +input [15:0] fre_mode , +output reg[3:0] R_CAL + + ); + +//接收通道1 +always@(posedge i_clk,negedge i_rstn)begin //1dB 步进 + if(!i_rstn) + R_CAL<='d0; + else if(i_temp>=8'sd70)begin//高温校准接收通道1 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 6 ; //20495 ~ 20534 + 4 : R_CAL<= 6 ; //20535 ~ 20574 + 5 : R_CAL<= 6 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 6 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + + else if(i_temp>=8'sd0)begin//常温校准接收通道1 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 6 ; //20495 ~ 20534 + 4 : R_CAL<= 6 ; //20535 ~ 20574 + 5 : R_CAL<= 6 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 6 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + else begin//低温校准接收通道1 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 6 ; //20495 ~ 20534 + 4 : R_CAL<= 6 ; //20535 ~ 20574 + 5 : R_CAL<= 6 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 6 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_2.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_2.v new file mode 100644 index 00000000..4e9cfcca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_2.v @@ -0,0 +1,349 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:05:24 04/08/2022 +// Design Name: +// Module Name: R_CAL +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module R_CAL_2( +input i_clk , +input i_rstn , +input signed[7:0] i_temp , +input [15:0] fre_mode , +output reg[3:0] R_CAL + + ); + + +//接收通道2 +always@(posedge i_clk,negedge i_rstn)begin //1dB 步进 + if(!i_rstn) + R_CAL<='d0; + else if(i_temp>=8'sd70)begin//高温校准接收通道2 + case(fre_mode) + 0 : R_CAL<= 6 ; //20375 ~ 20414 + 1 : R_CAL<= 6 ; //20415 ~ 20454 + 2 : R_CAL<= 6 ; //20455 ~ 20494 + 3 : R_CAL<= 5 ; //20495 ~ 20534 + 4 : R_CAL<= 5 ; //20535 ~ 20574 + 5 : R_CAL<= 5 ; //20575 ~ 20614 + 6 : R_CAL<= 5 ; //20615 ~ 20654 + 7 : R_CAL<= 5 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 5 ; //20775 ~ 20814 + 11: R_CAL<= 5 ; //20815 ~ 20854 + 12: R_CAL<= 5 ; //20855 ~ 20894 + 13: R_CAL<= 5 ; //20895 ~ 20934 + 14: R_CAL<= 5 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 6 ; //21135 ~ 21174 + 20: R_CAL<= 6 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 7 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 7 ; //22775 ~ 22814 + 61: R_CAL<= 7 ; //22815 ~ 22854 + 62: R_CAL<= 7 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 7 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 5 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 5 ; //23615 ~ 23654 + 82: R_CAL<= 5 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 5 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + + else if(i_temp>=8'sd0)begin//常温校准接收通道2 + case(fre_mode) + 0 : R_CAL<= 6 ; //20375 ~ 20414 + 1 : R_CAL<= 6 ; //20415 ~ 20454 + 2 : R_CAL<= 6 ; //20455 ~ 20494 + 3 : R_CAL<= 5 ; //20495 ~ 20534 + 4 : R_CAL<= 5 ; //20535 ~ 20574 + 5 : R_CAL<= 5 ; //20575 ~ 20614 + 6 : R_CAL<= 5 ; //20615 ~ 20654 + 7 : R_CAL<= 5 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 5 ; //20775 ~ 20814 + 11: R_CAL<= 5 ; //20815 ~ 20854 + 12: R_CAL<= 5 ; //20855 ~ 20894 + 13: R_CAL<= 5 ; //20895 ~ 20934 + 14: R_CAL<= 5 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 6 ; //21135 ~ 21174 + 20: R_CAL<= 6 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 7 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 7 ; //22775 ~ 22814 + 61: R_CAL<= 7 ; //22815 ~ 22854 + 62: R_CAL<= 7 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 7 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 5 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 5 ; //23615 ~ 23654 + 82: R_CAL<= 5 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 5 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + else begin//低温校准接收通道2 + case(fre_mode) + 0 : R_CAL<= 6 ; //20375 ~ 20414 + 1 : R_CAL<= 6 ; //20415 ~ 20454 + 2 : R_CAL<= 6 ; //20455 ~ 20494 + 3 : R_CAL<= 5 ; //20495 ~ 20534 + 4 : R_CAL<= 5 ; //20535 ~ 20574 + 5 : R_CAL<= 5 ; //20575 ~ 20614 + 6 : R_CAL<= 5 ; //20615 ~ 20654 + 7 : R_CAL<= 5 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 5 ; //20775 ~ 20814 + 11: R_CAL<= 5 ; //20815 ~ 20854 + 12: R_CAL<= 5 ; //20855 ~ 20894 + 13: R_CAL<= 5 ; //20895 ~ 20934 + 14: R_CAL<= 5 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 6 ; //21135 ~ 21174 + 20: R_CAL<= 6 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 7 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 7 ; //22775 ~ 22814 + 61: R_CAL<= 7 ; //22815 ~ 22854 + 62: R_CAL<= 7 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 7 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 5 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 5 ; //23615 ~ 23654 + 82: R_CAL<= 5 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 5 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_3.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_3.v new file mode 100644 index 00000000..ec51530b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_3.v @@ -0,0 +1,348 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:05:24 04/08/2022 +// Design Name: +// Module Name: R_CAL +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module R_CAL_3( +input i_clk , +input i_rstn , +input signed[7:0] i_temp , +input [15:0] fre_mode , +output reg[3:0] R_CAL + + ); + +//接收通道3 +always@(posedge i_clk,negedge i_rstn)begin //1dB 步进 + if(!i_rstn) + R_CAL<='d0; + else if(i_temp>=8'sd70)begin//高温校准接收通道3 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 6 ; //20695 ~ 20734 + 9 : R_CAL<= 6 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 8 ; //21175 ~ 21214 + 21: R_CAL<= 8 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 9 ; //21415 ~ 21454 + 27: R_CAL<= 9 ; //21455 ~ 21494 + 28: R_CAL<= 9 ; //21495 ~ 21534 + 29: R_CAL<= 9 ; //21535 ~ 21574 + 30: R_CAL<= 9 ; //21575 ~ 21614 + 31: R_CAL<= 9 ; //21615 ~ 21654 + 32: R_CAL<= 9 ; //21655 ~ 21694 + 33: R_CAL<= 9 ; //21695 ~ 21734 + 34: R_CAL<= 9 ; //21735 ~ 21774 + 35: R_CAL<= 9 ; //21775 ~ 21814 + 36: R_CAL<= 9 ; //21815 ~ 21854 + 37: R_CAL<= 9 ; //21855 ~ 21894 + 38: R_CAL<= 9 ; //21895 ~ 21934 + 39: R_CAL<= 9 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 8 ; //22055 ~ 22094 + 43: R_CAL<= 8 ; //22095 ~ 22134 + 44: R_CAL<= 8 ; //22135 ~ 22174 + 45: R_CAL<= 8 ; //22175 ~ 22214 + 46: R_CAL<= 8 ; //22215 ~ 22254 + 47: R_CAL<= 8 ; //22255 ~ 22294 + 48: R_CAL<= 8 ; //22295 ~ 22334 + 49: R_CAL<= 8 ; //22335 ~ 22374 + 50: R_CAL<= 8 ; //22375 ~ 22414 + 51: R_CAL<= 8 ; //22415 ~ 22454 + 52: R_CAL<= 8 ; //22455 ~ 22494 + 53: R_CAL<= 8 ; //22495 ~ 22534 + 54: R_CAL<= 8 ; //22535 ~ 22574 + 55: R_CAL<= 8 ; //22575 ~ 22614 + 56: R_CAL<= 8 ; //22615 ~ 22654 + 57: R_CAL<= 8 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 9 ; //22895 ~ 22934 + 64: R_CAL<= 9 ; //22935 ~ 22974 + 65: R_CAL<= 9 ; //22975 ~ 23014 + 66: R_CAL<= 9 ; //23015 ~ 23054 + 67: R_CAL<= 9 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 8 ; //23175 ~ 23214 + 71: R_CAL<= 8 ; //23215 ~ 23254 + 72: R_CAL<= 8 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 7 ; //23415 ~ 23454 + 77: R_CAL<= 7 ; //23455 ~ 23494 + 78: R_CAL<= 7 ; //23495 ~ 23534 + 79: R_CAL<= 7 ; //23535 ~ 23574 + 80: R_CAL<= 7 ; //23575 ~ 23614 + 81: R_CAL<= 7 ; //23615 ~ 23654 + 82: R_CAL<= 7 ; //23655 ~ 23694 + 83: R_CAL<= 7 ; //23695 ~ 23734 + 84: R_CAL<= 7 ; //23735 ~ 23774 + 85: R_CAL<= 7 ; //23775 ~ 23814 + 86: R_CAL<= 7 ; //23815 ~ 23854 + 87: R_CAL<= 7 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + + else if(i_temp>=8'sd0)begin//常温校准接收通道3 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 6 ; //20695 ~ 20734 + 9 : R_CAL<= 6 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 8 ; //21175 ~ 21214 + 21: R_CAL<= 8 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 9 ; //21415 ~ 21454 + 27: R_CAL<= 9 ; //21455 ~ 21494 + 28: R_CAL<= 9 ; //21495 ~ 21534 + 29: R_CAL<= 9 ; //21535 ~ 21574 + 30: R_CAL<= 9 ; //21575 ~ 21614 + 31: R_CAL<= 9 ; //21615 ~ 21654 + 32: R_CAL<= 9 ; //21655 ~ 21694 + 33: R_CAL<= 9 ; //21695 ~ 21734 + 34: R_CAL<= 9 ; //21735 ~ 21774 + 35: R_CAL<= 9 ; //21775 ~ 21814 + 36: R_CAL<= 9 ; //21815 ~ 21854 + 37: R_CAL<= 9 ; //21855 ~ 21894 + 38: R_CAL<= 9 ; //21895 ~ 21934 + 39: R_CAL<= 9 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 8 ; //22055 ~ 22094 + 43: R_CAL<= 8 ; //22095 ~ 22134 + 44: R_CAL<= 8 ; //22135 ~ 22174 + 45: R_CAL<= 8 ; //22175 ~ 22214 + 46: R_CAL<= 8 ; //22215 ~ 22254 + 47: R_CAL<= 8 ; //22255 ~ 22294 + 48: R_CAL<= 8 ; //22295 ~ 22334 + 49: R_CAL<= 8 ; //22335 ~ 22374 + 50: R_CAL<= 8 ; //22375 ~ 22414 + 51: R_CAL<= 8 ; //22415 ~ 22454 + 52: R_CAL<= 8 ; //22455 ~ 22494 + 53: R_CAL<= 8 ; //22495 ~ 22534 + 54: R_CAL<= 8 ; //22535 ~ 22574 + 55: R_CAL<= 8 ; //22575 ~ 22614 + 56: R_CAL<= 8 ; //22615 ~ 22654 + 57: R_CAL<= 8 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 9 ; //22895 ~ 22934 + 64: R_CAL<= 9 ; //22935 ~ 22974 + 65: R_CAL<= 9 ; //22975 ~ 23014 + 66: R_CAL<= 9 ; //23015 ~ 23054 + 67: R_CAL<= 9 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 8 ; //23175 ~ 23214 + 71: R_CAL<= 8 ; //23215 ~ 23254 + 72: R_CAL<= 8 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 7 ; //23415 ~ 23454 + 77: R_CAL<= 7 ; //23455 ~ 23494 + 78: R_CAL<= 7 ; //23495 ~ 23534 + 79: R_CAL<= 7 ; //23535 ~ 23574 + 80: R_CAL<= 7 ; //23575 ~ 23614 + 81: R_CAL<= 7 ; //23615 ~ 23654 + 82: R_CAL<= 7 ; //23655 ~ 23694 + 83: R_CAL<= 7 ; //23695 ~ 23734 + 84: R_CAL<= 7 ; //23735 ~ 23774 + 85: R_CAL<= 7 ; //23775 ~ 23814 + 86: R_CAL<= 7 ; //23815 ~ 23854 + 87: R_CAL<= 7 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + else begin//低温校准接收通道3 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 6 ; //20695 ~ 20734 + 9 : R_CAL<= 6 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 8 ; //21175 ~ 21214 + 21: R_CAL<= 8 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 9 ; //21415 ~ 21454 + 27: R_CAL<= 9 ; //21455 ~ 21494 + 28: R_CAL<= 9 ; //21495 ~ 21534 + 29: R_CAL<= 9 ; //21535 ~ 21574 + 30: R_CAL<= 9 ; //21575 ~ 21614 + 31: R_CAL<= 9 ; //21615 ~ 21654 + 32: R_CAL<= 9 ; //21655 ~ 21694 + 33: R_CAL<= 9 ; //21695 ~ 21734 + 34: R_CAL<= 9 ; //21735 ~ 21774 + 35: R_CAL<= 9 ; //21775 ~ 21814 + 36: R_CAL<= 9 ; //21815 ~ 21854 + 37: R_CAL<= 9 ; //21855 ~ 21894 + 38: R_CAL<= 9 ; //21895 ~ 21934 + 39: R_CAL<= 9 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 8 ; //22055 ~ 22094 + 43: R_CAL<= 8 ; //22095 ~ 22134 + 44: R_CAL<= 8 ; //22135 ~ 22174 + 45: R_CAL<= 8 ; //22175 ~ 22214 + 46: R_CAL<= 8 ; //22215 ~ 22254 + 47: R_CAL<= 8 ; //22255 ~ 22294 + 48: R_CAL<= 8 ; //22295 ~ 22334 + 49: R_CAL<= 8 ; //22335 ~ 22374 + 50: R_CAL<= 8 ; //22375 ~ 22414 + 51: R_CAL<= 8 ; //22415 ~ 22454 + 52: R_CAL<= 8 ; //22455 ~ 22494 + 53: R_CAL<= 8 ; //22495 ~ 22534 + 54: R_CAL<= 8 ; //22535 ~ 22574 + 55: R_CAL<= 8 ; //22575 ~ 22614 + 56: R_CAL<= 8 ; //22615 ~ 22654 + 57: R_CAL<= 8 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 9 ; //22895 ~ 22934 + 64: R_CAL<= 9 ; //22935 ~ 22974 + 65: R_CAL<= 9 ; //22975 ~ 23014 + 66: R_CAL<= 9 ; //23015 ~ 23054 + 67: R_CAL<= 9 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 8 ; //23175 ~ 23214 + 71: R_CAL<= 8 ; //23215 ~ 23254 + 72: R_CAL<= 8 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 7 ; //23415 ~ 23454 + 77: R_CAL<= 7 ; //23455 ~ 23494 + 78: R_CAL<= 7 ; //23495 ~ 23534 + 79: R_CAL<= 7 ; //23535 ~ 23574 + 80: R_CAL<= 7 ; //23575 ~ 23614 + 81: R_CAL<= 7 ; //23615 ~ 23654 + 82: R_CAL<= 7 ; //23655 ~ 23694 + 83: R_CAL<= 7 ; //23695 ~ 23734 + 84: R_CAL<= 7 ; //23735 ~ 23774 + 85: R_CAL<= 7 ; //23775 ~ 23814 + 86: R_CAL<= 7 ; //23815 ~ 23854 + 87: R_CAL<= 7 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_4.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_4.v new file mode 100644 index 00000000..eaa7f3f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/R_CAL_4.v @@ -0,0 +1,349 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:05:24 04/08/2022 +// Design Name: +// Module Name: R_CAL +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module R_CAL_4( +input i_clk , +input i_rstn , +input signed[7:0] i_temp , +input [15:0] fre_mode , +output reg[3:0] R_CAL + + ); + + +//接收通道4 +always@(posedge i_clk,negedge i_rstn)begin //1dB 步进 + if(!i_rstn) + R_CAL<='d0; + else if(i_temp>=8'sd70)begin//高温校准接收通道4 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 7 ; //20615 ~ 20654 + 7 : R_CAL<= 7 ; //20655 ~ 20694 + 8 : R_CAL<= 7 ; //20695 ~ 20734 + 9 : R_CAL<= 7 ; //20735 ~ 20774 + 10: R_CAL<= 7 ; //20775 ~ 20814 + 11: R_CAL<= 7 ; //20815 ~ 20854 + 12: R_CAL<= 7 ; //20855 ~ 20894 + 13: R_CAL<= 7 ; //20895 ~ 20934 + 14: R_CAL<= 7 ; //20935 ~ 20974 + 15: R_CAL<= 7 ; //20975 ~ 21014 + 16: R_CAL<= 7 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 8 ; //21895 ~ 21934 + 39: R_CAL<= 8 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 6 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + + else if(i_temp>=8'sd0)begin//常温校准接收通道4 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 7 ; //20615 ~ 20654 + 7 : R_CAL<= 7 ; //20655 ~ 20694 + 8 : R_CAL<= 7 ; //20695 ~ 20734 + 9 : R_CAL<= 7 ; //20735 ~ 20774 + 10: R_CAL<= 7 ; //20775 ~ 20814 + 11: R_CAL<= 7 ; //20815 ~ 20854 + 12: R_CAL<= 7 ; //20855 ~ 20894 + 13: R_CAL<= 7 ; //20895 ~ 20934 + 14: R_CAL<= 7 ; //20935 ~ 20974 + 15: R_CAL<= 7 ; //20975 ~ 21014 + 16: R_CAL<= 7 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 8 ; //21895 ~ 21934 + 39: R_CAL<= 8 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 6 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + else begin//低温校准接收通道4 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 7 ; //20615 ~ 20654 + 7 : R_CAL<= 7 ; //20655 ~ 20694 + 8 : R_CAL<= 7 ; //20695 ~ 20734 + 9 : R_CAL<= 7 ; //20735 ~ 20774 + 10: R_CAL<= 7 ; //20775 ~ 20814 + 11: R_CAL<= 7 ; //20815 ~ 20854 + 12: R_CAL<= 7 ; //20855 ~ 20894 + 13: R_CAL<= 7 ; //20895 ~ 20934 + 14: R_CAL<= 7 ; //20935 ~ 20974 + 15: R_CAL<= 7 ; //20975 ~ 21014 + 16: R_CAL<= 7 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 8 ; //21895 ~ 21934 + 39: R_CAL<= 8 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 6 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/Sisyif.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/Sisyif.v new file mode 100644 index 00000000..264a7dba --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/Sisyif.v @@ -0,0 +1,301 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: Chengdu Tiger +// Engineer: Tangxy +// +// Create Date: 14:14:49 09/06/2021 +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Sisyif( +input clk_40m , +input clk_20m , +input rst_n , +//调零至信处接口 +input SPI_CLK_F ,//SPI控制，时钟暂定50MHz，用来发送跳频频点、发射MGC值、接收MGC值 +input SPI_SYN_F ,//片选 +input SPI_MOSI_F , +output SPI_MISO_F , +input TP_EN_F ,//跳频使能控制(上升沿更新) +input TR_MGC_F ,//接收发射MGC使能控制(上升沿更新) +input CAL_F ,//校准MGC使能(上升沿更新) +input PRF ,//高发低收，默认接收 + +//信处至射频接口 +output standby ,//高开低待机，默认待机 +output SW_PLL ,//乒乓频率源选择0：频率源A —— 1：频率源B +output T ,//发射电源控制 +output R ,//接收电源控制 +output SW_BPF ,//开关滤波器选择 +output SCLK1 ,//锁相环A控制 +output SDIO1 ,// +output CS1 ,// +input LD1 ,// +output SCLK2 ,//锁相环B控制 +output SDIO2 ,// +output CS2 ,// +input LD2 ,// +output SCLK3 ,//点频源控制 +output SDIO3 ,// +output CS3 ,// +input LD3 ,// +output TMGC_16db ,//发射通道MGC控制,高电平衰减 +output TMGC_8db ,// +output TMGC_4db ,// +output TMGC_2db ,// +output TMGC_1db ,// +output RMGC_16db ,//四个接收通道MGC控制，同时控制，高电平衰减 +output RMGC_8db ,// +output RMGC_4db ,// +output RMGC_2db ,// +output RMGC_1db ,// +output ENABLE ,//SPI控制四个接收通道增益校准 +output SC ,// +output SD ,// +output END_SYN ,// +input SDOUT ,// +inout DQ_WD ,//温度传感器 +output SW_RX //接收监测控制 + +); + +wire vio_rstn ; +wire [9:0] SYNC_OUT ; +wire [35:0] CONTROL0 ; +wire [35:0] CONTROL1 ; +wire [150:0] TRIG0 ; + +wire[15:0] temp_data ;//LSB =0.625 C +wire[7:0] temp ;//LSB =1°C +wire[11:0] hop_fre_code; +wire adf4371_hop1 ; +wire adf4371_hop2 ; +wire [15:0] fre_code ; +wire [7:0] tx_mgc ; +wire [7:0] rx1_mgc ; +wire [7:0] rx2_mgc ; +wire [7:0] rx3_mgc ; +wire [7:0] rx4_mgc ; +wire [3:0] cal1_mgc ; +wire [3:0] cal2_mgc ; +wire [3:0] cal3_mgc ; +wire [3:0] cal4_mgc ; +wire [7:0] tx_cal_mgc ; +wire [3:0] model ; +wire [3:0] rf_en ; +wire [31:0] frame_count; +wire [3:0] ceshi_model; +wire [15:0] current_fre_code ; +wire [15:0] cal_fre_code ; +wire [7:0] R_MGC_1 ; + +wire SW_C1; +wire SW; +wire SW2; +wire SW3; + +wire [3:0] R_CAL1; +wire [3:0] R_CAL2; +wire [3:0] R_CAL3; +wire [3:0] R_CAL4; +wire [4:0] T_CAL ; + +assign temp = temp_data[11:4] ; +assign RMGC_16db = R_MGC_1[4] ; +assign RMGC_8db = R_MGC_1[3] ; +assign RMGC_4db = R_MGC_1[2] ; +assign RMGC_2db = R_MGC_1[1] ; +assign RMGC_1db = R_MGC_1[0] ; +assign standby = rf_en == 4'b0 ; +assign T = PRF ; +assign R = ~PRF ; +assign SW_BPF = SW_C1 ; +assign SW_PLL = SW ; +assign SW_RX = rx2_mgc == 8'b0 ? 1'b0 :1'b1 ; + + +spi_slave u_spi_slave ( + .i_sys_clk(clk_40m), + .i_sys_rst_n(rst_n), + .i_spi_sck(SPI_CLK_F), + .i_spi_cs(SPI_SYN_F), + .i_spi_sdi(SPI_MOSI_F), + .o_frame_count(frame_count), + .o_fre_code(fre_code), + .o_tx_mgc(tx_mgc), + .o_model(model), + .o_rf_en(rf_en), + .o_cal1_mgc(cal1_mgc), + .o_cal2_mgc(cal2_mgc), + .o_cal3_mgc(cal3_mgc), + .o_cal4_mgc(cal4_mgc), + .o_tx_cal_mgc(tx_cal_mgc), + .o_rx1_mgc(rx1_mgc), + .o_rx2_mgc(rx2_mgc), + .o_rx3_mgc(rx3_mgc), + .o_rx4_mgc(rx4_mgc), + .o_ceshi_model(ceshi_model) + ); + +spi_master u_spi_master ( +.i_sys_rst_n (rst_n) , +.i_clk (clk_40m) , +//.debug_clk (clk_80m) , +.i_spi_sck (SPI_CLK_F) , +.i_spi_cs (SPI_SYN_F) , +.o_spi_sdo (SPI_MISO_F) , +.i_spi_sdi (SPI_MOSI_F) , +.i_LD_LO3 (LD3) , +.i_LD1 (LD1) , +.i_LD2 (LD2) , +.i_cal1_mgc (R_CAL4) , +.i_cal2_mgc (R_CAL3) , +.i_cal3_mgc (R_CAL2) , +.i_cal4_mgc (R_CAL1) , +.i_temp (temp ) , +.i_frame_count (frame_count) + ); + +mgc_ctrl u_mgc_ctrl( + .i_sys_clk (clk_40m ), + .i_rst_n (rst_n ), + .i_TR_SW_F (PRF ), + .i_TP_EN_F (TP_EN_F ), + .i_T_MGC_EN_F (TR_MGC_F ), + .i_R_MGC_EN_F (TR_MGC_F ), + .i_CAL_F (CAL_F ), + .i_fre_code (fre_code ), + .i_tx_mgc (tx_mgc ), + .i_rx1_mgc (rx1_mgc ), + .i_rx2_mgc (rx2_mgc ), + .i_rx3_mgc (rx3_mgc ), + .i_rx4_mgc (rx4_mgc ), + .i_ceshi_module (ceshi_model ), + .o_current_fre_code (current_fre_code ), + .o_cal_fre_code (cal_fre_code ), + .o_hop_fre_code (hop_fre_code ), //0(20.375GHz)~3500(23.875GHz) + .o_adf4371_hop1 (adf4371_hop1 ), //high active + .o_adf4371_hop2 (adf4371_hop2 ), + .o_SW (SW ), + .o_SW2 (SW2 ), + .o_SW3 (SW3 ), + .o_SW_C1 (SW_C1 ), + .o_T_MGC_1dB (TMGC_1db ), + .o_T_MGC_2dB (TMGC_2db ), + .o_T_MGC_4dB (TMGC_4db ), + .o_T_MGC_8dB (TMGC_8db ), + .o_T_MGC_16dB (TMGC_16db ), + .o_R_MGC_1 (R_MGC_1 ) + //.o_R_MGC_2 (R_MGC_2 ), + //.o_R_MGC_3 (R_MGC_3 ), + //.o_R_MGC_4 (R_MGC_4 ) +); + +wire cfgover; +adf4371_a u_adf4371_a ( + .sysclk (clk_40m ), + .arstn (rst_n&vio_rstn ), + .cs (CS1 ), + .mux_out (LD1 ), + .sclk (SCLK1 ), + .sdio (SDIO1 ), + .rf_en (rf_en ), + .SW_PLL (SW_PLL ), + .CAL_F (CAL_F ), + .o_cfgover (cfgover ), + .ceshi_model(ceshi_model ), + .adf4371_hop(adf4371_hop1), + .fre_code (hop_fre_code) + ); + +adf4371_b u_adf4371_b ( + .sysclk (clk_40m ), + .arstn (rst_n&vio_rstn), + .cs (CS2 ), + .mux_out (LD2 ), + .sclk (SCLK2 ), + .sdio (SDIO2 ), + .rf_en (rf_en ), + .SW_PLL (SW_PLL ), + .CAL_F (CAL_F ), + .i_cfgover (cfgover ), + .ceshi_model(ceshi_model ), + .adf4371_hop(adf4371_hop2), + .fre_code (hop_fre_code) + ); + +fre_caliatt u_fre_caliatt ( + .i_clk (clk_40m ), + .i_rstn (rst_n ), + .ENABLE (ENABLE ), + .SC (SC ), + .SD (SD ), + .END_SYN (END_SYN ), + .SDOUT (SDOUT ), + .CAL_F (CAL_F ), + .i_temp (temp ), + .i_fre_mode (current_fre_code ), + .i_cal_fre_code (cal_fre_code ), + // .SYNC_OUT (SYNC_OUT ), + .SW (SW ), + .cal1_mgc (cal1_mgc ), + .cal2_mgc (cal2_mgc ), + .cal3_mgc (cal3_mgc ), + .cal4_mgc (cal4_mgc ), + .tx_cal_mgc (tx_cal_mgc ), + .tx_mgc (tx_mgc ), + .i_ceshi_module (ceshi_model ), + .R_CAL1 (R_CAL1 ), + .R_CAL2 (R_CAL2 ), + .R_CAL3 (R_CAL3 ), + .R_CAL4 (R_CAL4 ), + .T_CAL (T_CAL ) + ); + + +adf4351_2 u_adf4351 ( + .i_sysclk(clk_20m), + .i_arstn(rst_n), + .o_ADF4351_SCK(SCLK3), + .o_ADF4351_DATA(SDIO3), + .o_ADF4351_LE(CS3), + .i_ADF4351_locked(LD3) + ); + + + ds18b20_temp u_temp ( + .clk(clk_40m), + .rstn(rst_n), + .dq(DQ_WD), + .temp_data(temp_data) + ); + + + + + + +assign vio_rstn = 1'b1; + + + + + + + + + + + + endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/T_CAL.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/T_CAL.v new file mode 100644 index 00000000..ed19257a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/T_CAL.v @@ -0,0 +1,631 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:05:24 04/08/2022 +// Design Name: +// Module Name: T_CAL_ +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module T_CAL( +input i_clk , +input i_rstn , +input SW , +input signed[7:0] i_temp , +input [31:0] hop_fre_mode , +output reg[4:0] T_CAL_ + + ); + + + +//发射通道 +always@(posedge i_clk,negedge i_rstn)begin//1dB 步进 + if(!i_rstn) + T_CAL_<='d0; + else if(SW==1'b1)//B环校准值 + begin + if(i_temp>=8'sd70)//B环高温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; + end + + else if(i_temp>=8'sd0)//B环常温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; + end + + else //B环低温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; + end + end + else //A环校准值 + begin + if(i_temp>=8'sd70)//A环高温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; + end + + else if(i_temp>=8'sd0)//A环常温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; //20375 ~ 20414 + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; //20415 ~ 20454 + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; //20455 ~ 20494 + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; //20495 ~ 20534 + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; //20535 ~ 20574 + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; //20575 ~ 20614 + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; //20615 ~ 20654 + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; //20655 ~ 20694 + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; //20695 ~ 20734 + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; //20735 ~ 20774 + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; //20775 ~ 20814 + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; //20815 ~ 20854 + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; //20855 ~ 20894 + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; //20895 ~ 20934 + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; //20935 ~ 20974 + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; //20975 ~ 21014 + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; //21015 ~ 21054 + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; //21055 ~ 21094 + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; //21095 ~ 21134 + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; //21135 ~ 21174 + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; //21175 ~ 21214 + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; //21215 ~ 21254 + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; //21255 ~ 21294 + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; //21295 ~ 21334 + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; //21335 ~ 21374 + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; //21375 ~ 21414 + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; //21415 ~ 21454 + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; //21455 ~ 21494 + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; //21495 ~ 21534 + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; //21535 ~ 21574 + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; //21575 ~ 21614 + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; //21615 ~ 21654 + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; //21655 ~ 21694 + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; //21695 ~ 21734 + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; //21735 ~ 21774 + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; //21775 ~ 21814 + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; //21815 ~ 21854 + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; //21855 ~ 21875 + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21874 ~ 21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; //21895 ~ 21934 + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; //21935 ~ 21974 + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; //21975 ~ 22014 + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; //22015 ~ 22054 + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; //22055 ~ 22094 + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; //22095 ~ 22134 + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; //22135 ~ 22174 + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; //22175 ~ 22214 + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; //22215 ~ 22254 + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; //22255 ~ 22294 + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; //22295 ~ 22334 + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; //22335 ~ 22374 + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; //22375 ~ 22414 + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; //22415 ~ 22454 + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; //22455 ~ 22494 + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; //22495 ~ 22534 + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; //22535 ~ 22574 + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; //22575 ~ 22614 + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; //22615 ~ 22654 + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; //22655 ~ 22694 + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; //22695 ~ 22734 + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; //22735 ~ 22774 + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; //22775 ~ 22814 + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; //22815 ~ 22854 + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; //22855 ~ 22894 + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; //22895 ~ 22934 + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; //22935 ~ 22974 + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; //22975 ~ 23014 + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; //23015 ~ 23054 + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; //23055 ~ 23094 + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; //23095 ~ 23134 + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; //23135 ~ 23174 + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; //23175 ~ 23214 + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; //23215 ~ 23254 + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; //23255 ~ 23294 + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; //23295 ~ 23334 + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; //23335 ~ 23374 + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; //23375 ~ 23414 + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; //23415 ~ 23454 + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; //23455 ~ 23494 + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; //23495 ~ 23534 + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; //23535 ~ 23574 + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; //23575 ~ 23614 + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; //23615 ~ 23654 + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; //23655 ~ 23694 + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; //23695 ~ 23734 + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; //23735 ~ 23774 + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; //23775 ~ 23814 + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; //23815 ~ 23854 + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; //23855 ~ 23875 + end + else //A环低温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; + end + end + +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/adf4371_a.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/adf4371_a.v new file mode 100644 index 00000000..dc928a78 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/adf4371_a.v @@ -0,0 +1,633 @@ + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2021/8/13 00:24:20 +// Design Name: +// Module Name: LMX2595 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: + +// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R) +// fPFD = fPFD = REFIN × ((1 + D)/(R × (1 + T))) +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +////////////////////////////////////////////////////////////////////////////////// + + +module adf4371_a(//20.375Ghz ~ 23.875Ghz +input sysclk ,//40MHZ +input arstn , +output cs , +input mux_out , +output sclk , +output sdio , +input [3:0] rf_en , +input SW_PLL , +input CAL_F , +input [3:0] ceshi_model , +input adf4371_hop , +output o_cfgover , +input[11:0] fre_code + ); + +localparam DATA_WIDTH = 24 ; +localparam DATA_LENTH = 72 ; +localparam WAIT_ld = 40000 ; +//***************************************************************************** +reg[7:0] cnt_word = 8'd0 ; +reg csb_reg = 1'b1 ; +reg[5:0] cnt_bits = 6'd0 ; +reg[DATA_WIDTH-1:0] cfgdata = 0, regdata = 0 ; +reg[3:0] state = 4'b000 ; +reg spi_sdo = 1'b0, spi_csb = 1'b1; +wire pll_locked ; +reg cfgover ; +reg[31:0] cnt_lock = 32'd0 ; +reg[31:0] cnt_locked = 32'd0 ; +wire[15:0] band ; +assign o_cfgover =cfgover ; +//----------------------------------- +assign pll_locked = mux_out ; +assign sclk = spi_csb ? 1'b0 : ~sysclk ; +assign cs = spi_csb & csb_reg ; +assign sdio = spi_sdo ; +//----------------------------------- + +wire [7:0] SI_BAND_SEL ; //VCO频段 +wire [7:0] SI_VCO_SEL_BIAS_CODE ; //[7:4]=VCO内核, [3:0]=VCO偏置 +reg[13:0] MOD2 ; +reg[13:0] FRAC2 ; +reg[24:0] FRAC1 ; +reg[15:0] INT ; + +assign SI_BAND_SEL = band[15:8] ; +assign SI_VCO_SEL_BIAS_CODE = band[7:0] ; + +reg[2:0] hop_en ; +reg[15:0] code ; +reg[11:0] pre_fre_code ; +reg[3:0] rf_en_r ; +reg[2:0] CAL_F_R ; + +reg [3:0] R_DIV ; +reg [3:0] D ; +wire[13:0] douta3 ; +wire[13:0] douta4 ; +wire[24:0] douta2 ; +wire[15:0] douta1 ; +//----------------------------------- + +INT_ROMb int_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta1) + ); + +// Instantiate the module +FRAC1 frac1_rom ( + .clka(sysclk), + .addra(code), + .douta(douta2) + ); + + +// FRAC1_ROM FRAC1_ROM ( +// .clka(sysclk), // input clka +// .addra(code), // input [11 : 0] addra +// .douta(douta2) // output [24 : 0] douta +//); + +frac2_rom frac2_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta4) + ); + +mod2_rom mod2_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta3) + ); + + +band_rom_a band_rom_a ( + .sysclk(sysclk), + .addra(code), + .douta(band) // output [15 : 0] douta + ); + + +//-------------------整数边界杂散用66.666666Mhz鉴相---------------------------------- +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + INT<=douta1; + else if(code==24 || code==26 ) + INT<=76; + else if(code==424 ) + INT<=77; + else if(code==426 ) + INT<=78; + else if(code==824 || code==826 ) + INT<=79; + else if(code==1224) + INT<=80; + else if(code==1226 ) + INT<=81; + else if(code==1624 || code==1626 ) + INT<=82; + else if(code==2024 ) + INT<=83; + else if(code==2026 ) + INT<=84; + else if(code==2424 || code==2426 ) + INT<=85; + else if(code==2824 ) + INT<=86; + else if( code==2826 ) + INT<=87; + else + INT<=douta1; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + FRAC1<=douta2; + else if(code==24 ) + FRAC1<=16651386; + else if(code==26 ) + FRAC1<=16903045; + else if(code==424 ) + FRAC1<=33428602; + else if(code==426 ) + FRAC1<=125829; + else if(code==824 ) + FRAC1<=16651386; + else if(code==826 ) + FRAC1<=16903045; + else if(code==1224) + FRAC1<=33428602; + else if(code==1226 ) + FRAC1<=125829; + else if(code==1624) + FRAC1<=16651386; + else if(code==1626 ) + FRAC1<=16903045; + else if(code==2024 ) + FRAC1<=33428602; + else if(code==2026 ) + FRAC1<=125829; + else if(code==2424 ) + FRAC1<=16651386; + else if(code==2426 ) + FRAC1<=16903045; + else if(code==2824 ) + FRAC1<=33428602; + else if( code==2826 ) + FRAC1<=125829; + else + FRAC1<=douta2; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + MOD2<=douta3; + else if(code==24 ) + MOD2<=25; + else if(code==26 ) + MOD2<=25; + else if(code==424 ) + MOD2<=25; + else if(code==426 ) + MOD2<=25; + else if(code==824 ) + MOD2<=25; + else if(code==826 ) + MOD2<=25; + else if(code==1224) + MOD2<=25; + else if(code==1226 ) + MOD2<=25; + else if(code==1624) + MOD2<=25; + else if(code==1626 ) + MOD2<=25; + else if(code==2024 ) + MOD2<=25; + else if(code==2026 ) + MOD2<=25; + else if(code==2424 ) + MOD2<=25; + else if(code==2426 ) + MOD2<=25; + else if(code==2824 ) + MOD2<=25; + else if( code==2826 ) + MOD2<=25; + else + MOD2<=douta3; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + FRAC2<=douta4; + else if(code==24 ) + FRAC2<=22; + else if(code==26 ) + FRAC2<=3; + else if(code==424 ) + FRAC2<=22; + else if(code==426 ) + FRAC2<=3; + else if(code==824 ) + FRAC2<=22; + else if(code==826 ) + FRAC2<=3; + else if(code==1224) + FRAC2<=22; + else if(code==1226 ) + FRAC2<=3; + else if(code==1624) + FRAC2<=22; + else if(code==1626 ) + FRAC2<=3; + else if(code==2024 ) + FRAC2<=22; + else if(code==2026 ) + FRAC2<=3; + else if(code==2424 ) + FRAC2<=22; + else if(code==2426 ) + FRAC2<=3; + else if(code==2824 ) + FRAC2<=22; + else if( code==2826 ) + FRAC2<=3; + else + FRAC2<=douta4; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn)begin + R_DIV<=4'b1; + D<=4'b0; + end + else if(code==24 || code==26 || code==424 || code==426 || code==824 || code==826|| code==1224 || code==1226 || code==1624 || code==1626 ||code==2024 || code==2026 ||code==2424 || code==2426 ||code==2824 || code==2826 ) + begin + R_DIV<= 4'd3; + D<=4'd2; + end + else + begin + R_DIV<=4'b1; + D<=4'b0; + end +end + +//---------------------------------------------------------------- + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + pre_fre_code<=11'h6d6; +else if(CAL_F_R==3'b011) + pre_fre_code<=fre_code; +else + pre_fre_code<=pre_fre_code; +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + code<=16'h0; +else if(hop_en==2'b01) + code<=fre_code; +else + code<=code; +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn)begin + hop_en <= 3'b0; + rf_en_r <= 4'b0; + CAL_F_R <= 3'b0; +end +else begin + hop_en <= {hop_en[1:0],adf4371_hop}; + CAL_F_R <= {CAL_F_R[1:0],CAL_F}; + rf_en_r <= rf_en ; +end +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + csb_reg <= 1'b1; +else + csb_reg <= spi_csb; +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + cnt_locked<=32'b0; +else if(cnt_locked==WAIT_ld) + cnt_locked<=32'b0; +else if(!pll_locked) + cnt_locked<=cnt_locked+1'b1; +else + cnt_locked<=32'b0; +end + +always@(posedge sysclk,negedge arstn)begin +if(~arstn)begin + cfgdata <= 0; + cnt_word <= 7'd0; + cnt_bits <= 6'd0; + state <= 4'b0; + cnt_lock <= 32'd0; + spi_csb <= 1'b1; + cfgover <= 1'b0; + spi_sdo <= 1'b0; +end +else begin + case(state) + 4'd0:begin + cnt_word <= 7'd0; + if(rf_en==1'b1) + state <= 4'd0; + else if(cnt_lock >= 32'd4000) + state <= 4'd1; + else + state <= state; + + if(rf_en==1'b0) + cnt_lock <= cnt_lock + 1'b1; + else + cnt_lock<=32'd0; + + end + 4'd1:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + if(rf_en==1'b1) + state <= 4'd0; + else + state <= 4'd2; + end + 4'd2:begin + cfgdata <= regdata; + cnt_bits <= 6'd0; + state <= 4'd3; + end + 4'd3:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd4; + cnt_word <= cnt_word + 1'b1; + end + cnt_lock <= 32'd0; + end + 4'd4:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_lock <= 32'd0; + cnt_bits <= 32'd0; + if(cnt_word == DATA_LENTH)begin + state <= 4'd5; + end + else + state <= 4'd1; + end + 4'd5:begin + if(cnt_lock>=40000 || pll_locked)begin + cnt_lock <= 32'd0 ; + state <= 4'd6 ; + end + else begin + cnt_lock <=cnt_lock+1'b1; + state <= state ; + end + end + 4'd6:begin + cnt_word <= 7'd0; + if(pll_locked) + state <= 4'd7 ; + else + state <= 4'b1 ; + end +//---------------------------------------------------------------- + 4'd7:begin//IDLE + cnt_word <= DATA_LENTH; + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_bits <= 6'd0; + cfgover <= 1'b0; + if(rf_en==4'b1) + state <= state; + else if(rf_en==4'b0 && rf_en_r==4'b1 ) + state <= 4'd0; + else if(hop_en==2'b10 || cnt_locked==WAIT_ld ) + state <= 4'd8; + else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT + state <= 4'd12; + else + state <= state; + end + 4'd8:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + state <= 4'd9; + end + 4'd9:begin + cfgdata <= regdata; + cnt_bits <= 6'd0; + state <= 4'd10; + end + 4'd10:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd11; + cnt_word <= cnt_word + 1'b1; + end + end + 4'd11:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_lock <= 32'd0; + cnt_bits <= 32'd0; + if(cnt_word == 8'd85)begin + state <= 4'd7; + end + else + state <= 4'd8; + end + 4'd12:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + state <= 4'd13; + end + 4'd13:begin + cnt_bits <= 6'd0; + state <= 4'd14; + if(ceshi_model==4'ha) + cfgdata<={16'h0025,8'h13}; + else if(ceshi_model==4'hb) + cfgdata<={16'h0025,8'h00}; + else if(SW_PLL) + cfgdata<={16'h0025,8'h13}; + else + cfgdata<={16'h0025,8'h00}; + end + 4'd14:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd7; + cfgover <= 1'b1; + cnt_word <= cnt_word ; + end + end + +//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#// + default: begin + spi_csb <= 1'b1; + state <= 4'd0; + cnt_lock <= 32'd0; + cnt_word <= 8'd0; + end + endcase +end +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + regdata <= {16'h0000,8'h18 }; + else case(cnt_word) + 8'd0 : regdata <= {16'h0000,8'h18 }; + 8'd1 : regdata <= {16'h0001,8'h00 }; + 8'd2 : regdata <= {16'h0003,8'h00 }; + 8'd3 : regdata <= {16'h0004,8'h00 }; + 8'd4 : regdata <= {16'h0005,8'h00 }; + 8'd5 : regdata <= {16'h0006,8'hFF }; + 8'd6 : regdata <= {16'h000C,8'h00 }; + 8'd7 : regdata <= {16'h000D,8'h00 }; + 8'd8 : regdata <= {16'h0010 ,INT[7:0] } ; + 8'd9 : regdata <= {16'h0011 ,INT[15:8] } ; + 8'd10 : regdata <= {16'h0012,8'h00 };//[6]No Autocalibration + //8'd10 : regdata <= {16'h0012,8'h40 };//[6]Autocalibration + 8'd11 : regdata <= {16'h0014 ,FRAC1[7:0]} ; + 8'd12 : regdata <= {16'h0015 ,FRAC1[15:8]} ; + 8'd13 : regdata <= {16'h0016 ,FRAC1[23:16]} ; + 8'd14 : regdata <= {16'h0017 ,FRAC2[6:0],FRAC1[24]} ; + 8'd15 : regdata <= {16'h0018 ,1'b0,FRAC2[13:7] } ; + 8'd16 : regdata <= {16'h0019 ,MOD2[7:0]} ; + 8'd17 : regdata <= {16'h001A ,2'b0,MOD2[13:8]} ; + 8'd18 : regdata <= {16'h001B,8'h00 }; + 8'd19 : regdata <= {16'h001C,8'h00 }; + 8'd20 : regdata <= {16'h001D,8'h00 }; + 8'd21 : regdata <= {16'h001E,8'h18 };//CP_CURRENT 电荷泵 + // 8'd21 : regdata <= { 16'h001E,cp,4'h8 };//CP_CURRENT 电荷泵 + 8'd22 : regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器 + 8'd23 : regdata <= {16'h0020,8'h1c };//digital lock detect 数字锁定ld + 8'd24 : regdata <= {16'h0021,8'h00 }; + 8'd25 : regdata <= {16'h0022,D,4'd0 };//[4]2分频 [5]double 2倍频器 + 8'd26 : regdata <= {16'h0023,8'h00 }; + 8'd27 : regdata <= {16'h0024,8'h80 };//Fout_clk DIV_SEL + 8'd28 : regdata <= {16'h0025,8'h13 };//X4_EN + 8'd29 : regdata <= {16'h0026,8'h1F }; + 8'd30 : regdata <= {16'h0027,8'hCD }; + //8'd30 : regdata <= {16'h0027,8'hCD }; + 8'd31 : regdata <= {16'h0028,8'h83 }; + 8'd32 : regdata <= {16'h002A,8'h00 }; + 8'd33 : regdata <= {16'h002B,8'h00 }; + 8'd34 : regdata <= {16'h002C,8'h44 }; + 8'd35 : regdata <= {16'h002D,8'h11 }; + 8'd36 : regdata <= {16'h002E,8'h12 }; + 8'd37 : regdata <= {16'h002F,8'h94 }; + 8'd38 : regdata <= {16'h0030,8'h2A }; + 8'd39 : regdata <= {16'h0031,8'h02 }; + 8'd40 : regdata <= {16'h0032,8'h04 }; + 8'd41 : regdata <= {16'h0033,8'h22 }; + 8'd42 : regdata <= {16'h0034,8'h25 }; + 8'd43 : regdata <= {16'h0035,8'hFA }; + 8'd44 : regdata <= {16'h0036,8'h30 }; + 8'd45 : regdata <= {16'h0037,SI_BAND_SEL} ;//VCO频段 + 8'd46 : regdata <= {16'h0038,SI_VCO_SEL_BIAS_CODE };//[7:4]=VCO内核,[3:0]VCO偏置 + 8'd47 : regdata <= {16'h0039,8'h07 }; + 8'd48 : regdata <= {16'h003A,8'h55 }; + 8'd49 : regdata <= {16'h003D,8'h00 }; + 8'd50 : regdata <= {16'h003E,8'h0C }; + 8'd51 : regdata <= {16'h003F,8'h80 }; + 8'd52 : regdata <= {16'h0040,8'h50 }; + 8'd53 : regdata <= {16'h0041,8'h28 }; + 8'd54 : regdata <= {16'h0042,8'h00 }; + 8'd55 : regdata <= {16'h0043,8'h00 }; + 8'd56 : regdata <= {16'h0044,8'h00 }; + 8'd57 : regdata <= {16'h0045,8'h00 }; + 8'd58 : regdata <= {16'h0046,8'h00 }; + 8'd59 : regdata <= {16'h0047,8'hC0 }; + 8'd60 : regdata <= {16'h0052,8'hF4 }; + 8'd61 : regdata <= {16'h006C,8'h00 }; + 8'd62 : regdata <= {16'h006E,8'h00 }; + 8'd63 : regdata <= {16'h006F,8'h00 }; + 8'd64 : regdata <= {16'h0070,8'hE3 }; + 8'd65 : regdata <= {16'h0071,8'h60 }; + 8'd66 : regdata <= {16'h0072,8'h32 }; + 8'd67 : regdata <= {16'h0073,8'h00 }; + 8'd68 : regdata <= {16'h0079,8'h00 }; + 8'd69 : regdata <= {16'h007A,8'h00 }; + 8'd70 : regdata <= {16'h007B,8'h00 }; + 8'd71 : regdata <= {16'h007C,8'h00 }; + + //跳频 + 8'd72:regdata <= { 16'h0022,D,4'd0 };//double D倍频器 + 8'd73:regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器 + 8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8] } ; + 8'd75:regdata <= { 16'h0019 ,MOD2[7:0] } ; + 8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7] } ; + 8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24] } ; + 8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] } ; + 8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] } ; + 8'd80:regdata <= { 16'h0014 ,FRAC1[7:0] } ; + 8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL } ; + 8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE } ; + 8'd83:regdata <= { 16'h0011 ,INT[15:8] } ; + 8'd84:regdata <= { 16'h0010 ,INT[7:0] } ; + + default: regdata <= regdata; +endcase +end + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/adf4371_b.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/adf4371_b.v new file mode 100644 index 00000000..77084408 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/adf4371_b.v @@ -0,0 +1,622 @@ + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2021/8/13 00:24:20 +// Design Name: +// Module Name: LMX2595 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: + +// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R) +// fPFD = fPFD = REFIN × ((1 + D)/(R × (1 + T))) +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +////////////////////////////////////////////////////////////////////////////////// + + +module adf4371_b(//20.375Ghz ~ 23.875Ghz +input sysclk ,//40MHZ +input arstn , +output cs , +input mux_out , +output sclk , +output sdio , +input [3:0] rf_en , +input CAL_F , +input SW_PLL , +input i_cfgover , +input [3:0] ceshi_model , +input adf4371_hop , +input[11:0] fre_code + ); + +localparam DATA_WIDTH = 24 ; +localparam DATA_LENTH = 72 ; +localparam WAIT_ld = 40000 ; +//***********************************************************************************************************// +reg[7:0] cnt_word = 8'd0 ; +reg csb_reg = 1'b1 ; +reg[5:0] cnt_bits = 6'd0 ; +reg[DATA_WIDTH-1:0] cfgdata = 0, regdata = 0 ; +reg[3:0] state = 4'b000 ; +reg spi_sdo = 1'b0, spi_csb = 1'b1; +wire pll_locked ; +reg[31:0] cnt_lock = 32'd0 ; +reg[31:0] cnt_locked = 32'd0 ; +wire[15:0] band ; + +//----------------------------------- +assign pll_locked = mux_out ; +assign sclk = spi_csb ? 1'b0 : ~sysclk ; +assign cs = spi_csb & csb_reg ; +assign sdio = spi_sdo ; +//----------------------------------- + +wire [7:0] SI_BAND_SEL ; //VCO频段 +wire [7:0] SI_VCO_SEL_BIAS_CODE ; //[7:4]=VCO内核, [3:0]=VCO偏置 +reg[13:0] MOD2 ; +reg[13:0] FRAC2 ; +reg[24:0] FRAC1 ; +reg[15:0] INT ; + +assign SI_BAND_SEL = band[15:8] ; +assign SI_VCO_SEL_BIAS_CODE = band[7:0] ; + +reg[2:0] hop_en; +reg[15:0] code; +reg[11:0] pre_fre_code; +reg[3:0] cp_r; +reg[3:0] rf_en_r; +reg[2:0] CAL_F_R; + +reg [3:0] R_DIV ; +reg [3:0] D ; +wire[13:0] douta3 ; +wire[13:0] douta4 ; +wire[24:0] douta2 ; +wire[15:0] douta1 ; + +//----------------------------------- +INT_ROMb int_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta1) + ); + +FRAC1 frac1_rom ( + .clka(sysclk), + .addra(code), + .douta(douta2) + ); + +// FRAC1_ROM FRAC1_ROM ( +// .clka(sysclk), // input clka +// .addra(code), // input [11 : 0] addra +// .douta(douta2) // output [24 : 0] douta +//); + +frac2_rom frac2_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta4) + ); + +mod2_rom mod2_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta3) + ); + + +band_rom_b band_rom_b ( + .sysclk(sysclk), + .addra(code), + .douta(band) // output [15 : 0] douta + ); + +//-------------------整数边界杂散用66.666666Mhz鉴相---------------------------------- + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + INT<=douta1; + else if(code==24 || code==26 ) + INT<=76; + else if(code==424 ) + INT<=77; + else if(code==426 ) + INT<=78; + else if(code==824 || code==826 ) + INT<=79; + else if(code==1224) + INT<=80; + else if(code==1226 ) + INT<=81; + else if(code==1624 || code==1626 ) + INT<=82; + else if(code==2024 ) + INT<=83; + else if(code==2026 ) + INT<=84; + else if(code==2424 || code==2426 ) + INT<=85; + else if(code==2824 ) + INT<=86; + else if( code==2826 ) + INT<=87; + else + INT<=douta1; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + FRAC1<=douta2; + else if(code==24 ) + FRAC1<=16651386; + else if(code==26 ) + FRAC1<=16903045; + else if(code==424 ) + FRAC1<=33428602; + else if(code==426 ) + FRAC1<=125829; + else if(code==824 ) + FRAC1<=16651386; + else if(code==826 ) + FRAC1<=16903045; + else if(code==1224) + FRAC1<=33428602; + else if(code==1226 ) + FRAC1<=125829; + else if(code==1624) + FRAC1<=16651386; + else if(code==1626 ) + FRAC1<=16903045; + else if(code==2024 ) + FRAC1<=33428602; + else if(code==2026 ) + FRAC1<=125829; + else if(code==2424 ) + FRAC1<=16651386; + else if(code==2426 ) + FRAC1<=16903045; + else if(code==2824 ) + FRAC1<=33428602; + else if( code==2826 ) + FRAC1<=125829; + else + FRAC1<=douta2; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + MOD2<=douta3; + else if(code==24 ) + MOD2<=25; + else if(code==26 ) + MOD2<=25; + else if(code==424 ) + MOD2<=25; + else if(code==426 ) + MOD2<=25; + else if(code==824 ) + MOD2<=25; + else if(code==826 ) + MOD2<=25; + else if(code==1224) + MOD2<=25; + else if(code==1226 ) + MOD2<=25; + else if(code==1624) + MOD2<=25; + else if(code==1626 ) + MOD2<=25; + else if(code==2024 ) + MOD2<=25; + else if(code==2026 ) + MOD2<=25; + else if(code==2424 ) + MOD2<=25; + else if(code==2426 ) + MOD2<=25; + else if(code==2824 ) + MOD2<=25; + else if( code==2826 ) + MOD2<=25; + else + MOD2<=douta3; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + FRAC2<=douta4; + else if(code==24 ) + FRAC2<=22; + else if(code==26 ) + FRAC2<=3; + else if(code==424 ) + FRAC2<=22; + else if(code==426 ) + FRAC2<=3; + else if(code==824 ) + FRAC2<=22; + else if(code==826 ) + FRAC2<=3; + else if(code==1224) + FRAC2<=22; + else if(code==1226 ) + FRAC2<=3; + else if(code==1624) + FRAC2<=22; + else if(code==1626 ) + FRAC2<=3; + else if(code==2024 ) + FRAC2<=22; + else if(code==2026 ) + FRAC2<=3; + else if(code==2424 ) + FRAC2<=22; + else if(code==2426 ) + FRAC2<=3; + else if(code==2824 ) + FRAC2<=22; + else if( code==2826 ) + FRAC2<=3; + else + FRAC2<=douta4; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn)begin + R_DIV<=4'b1; + D<=4'b0; + end + else if(code==24 || code==26 || code==424 || code==426 || code==824 || code==826|| code==1224 || code==1226 || code==1624 || code==1626 ||code==2024 || code==2026 ||code==2424 || code==2426 ||code==2824 || code==2826 ) + begin + R_DIV<= 4'd3; + D<=4'd2; + end + else + begin + R_DIV<=4'b1; + D<=4'b0; + end +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + pre_fre_code<=11'h6d6; +else if(CAL_F_R==3'b011) + pre_fre_code<=fre_code; +else + pre_fre_code<=pre_fre_code; +end + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + code<=16'h6d6; +else if(hop_en==2'b01) + code<=fre_code; +else + code<=code; +end + +always@(posedge sysclk,negedge arstn)begin +if(~arstn)begin + hop_en <= 3'b0; + CAL_F_R <= 3'b0; + rf_en_r <= 4'b0; +end +else begin + hop_en <= {hop_en[1:0],adf4371_hop}; + CAL_F_R <= {CAL_F_R[1:0],CAL_F}; + rf_en_r <= rf_en ; +end +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + csb_reg <= 1'b1; +else + csb_reg <= spi_csb; +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + cnt_locked<=32'b0; +else if(cnt_locked==WAIT_ld) + cnt_locked<=32'b0; +else if(!pll_locked) + cnt_locked<=cnt_locked+1'b1; +else + cnt_locked<=32'b0; +end + +always@(posedge sysclk,negedge arstn)begin +if(~arstn)begin + cfgdata <= 0; + cnt_word <= 7'd0; + cnt_bits <= 6'd0; + state <= 4'b0; + cnt_lock <= 32'd0; + spi_csb <= 1'b1; + spi_sdo <= 1'b0; +end +else begin + case(state) + 4'd0:begin + cnt_word <= 7'd0; + if(rf_en==1'b1) + state <= 4'd0; + else if(cnt_lock >= 32'd6000) + state <= 4'd1; + else + state <= state; + + if(rf_en==1'b0) + cnt_lock <= cnt_lock + 1'b1; + else + cnt_lock<=32'd0; + + end + 4'd1:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + state <= 4'd2; + end + 4'd2:begin + cfgdata <= regdata; + cnt_bits <= 6'd0; + state <= 4'd3; + end + 4'd3:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd4; + cnt_word <= cnt_word + 1'b1; + end + cnt_lock <= 32'd0; + end + 4'd4:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_lock <= 32'd0; + cnt_bits <= 32'd0; + if(cnt_word == DATA_LENTH)begin + state <= 4'd5; + end + else + state <= 4'd1; + end + 4'd5:begin + if(cnt_lock>=40000 || pll_locked)begin + cnt_lock <= 32'd0 ; + state <= 4'd6 ; + end + else begin + cnt_lock <=cnt_lock+1'b1; + state <= state ; + end + end + 4'd6:begin + cnt_word <= 7'd0; + if(pll_locked) + state <= 4'd7 ; + else + state <= 4'b1 ; + end +//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#// + 4'd7:begin//IDLE + cnt_word <= DATA_LENTH; + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_bits <= 6'd0; + if(rf_en==4'b1) + state <= state; + else if(rf_en==4'b0 && rf_en_r==4'b1 ) + state <= 4'd0; + else if(hop_en==2'b10 || cnt_locked==WAIT_ld ) + state <= 4'd8; + //else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT + else if(i_cfgover) + state <= 4'd12; + else + state <= state; + end + 4'd8:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + state <= 4'd9; + end + 4'd9:begin + cfgdata <= regdata; + cnt_bits <= 6'd0; + state <= 4'd10; + end + 4'd10:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd11; + cnt_word <= cnt_word + 1'b1; + end + end + 4'd11:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_lock <= 32'd0; + cnt_bits <= 32'd0; + if(cnt_word == 8'd85)begin + state <= 4'd7; + end + else + state <= 4'd8; + end + 4'd12:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + state <= 4'd13; + end + 4'd13:begin + cnt_bits <= 6'd0; + state <= 4'd14; + if(ceshi_model==4'hb) + cfgdata <= {16'h0025,8'h13}; + else if(ceshi_model==4'ha) + cfgdata <= {16'h0025,8'h00}; + else if (SW_PLL) + cfgdata <= {16'h0025,8'h00}; + else + cfgdata <= {16'h0025,8'h13}; + end + 4'd14:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd7; + cnt_word <= cnt_word ; + end + end +//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#// + default: begin + spi_csb <= 1'b1; + state <= 4'd0; + cnt_lock <= 32'd0; + cnt_word <= 8'd0; + end + endcase +end +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + regdata <= {16'h0000,8'h18 }; + else case(cnt_word) + 8'd0 : regdata <= {16'h0000,8'h18 }; + 8'd1 : regdata <= {16'h0001,8'h00 }; + 8'd2 : regdata <= {16'h0003,8'h00 }; + 8'd3 : regdata <= {16'h0004,8'h00 }; + 8'd4 : regdata <= {16'h0005,8'h00 }; + 8'd5 : regdata <= {16'h0006,8'hFF }; + 8'd6 : regdata <= {16'h000C,8'h00 }; + 8'd7 : regdata <= {16'h000D,8'h00 }; + 8'd8 : regdata <= {16'h0010 ,INT[7:0] } ; + 8'd9 : regdata <= {16'h0011 ,INT[15:8] } ; + 8'd10 : regdata <= {16'h0012,8'h00 };//[6]Autocalibration + //8'd10 : regdata <= {16'h0012,8'h40 };//[6]Autocalibration + 8'd11 : regdata <= {16'h0014 ,FRAC1[7:0]} ; + 8'd12 : regdata <= {16'h0015 ,FRAC1[15:8]} ; + 8'd13 : regdata <= {16'h0016 ,FRAC1[23:16]} ; + 8'd14 : regdata <= {16'h0017 ,FRAC2[6:0],FRAC1[24]} ; + 8'd15 : regdata <= {16'h0018 ,1'b0,FRAC2[13:7] } ; + 8'd16 : regdata <= {16'h0019 ,MOD2[7:0]} ; + 8'd17 : regdata <= {16'h001A ,2'b0,MOD2[13:8]} ; + 8'd18 : regdata <= {16'h001B,8'h00 }; + 8'd19 : regdata <= {16'h001C,8'h00 }; + 8'd20 : regdata <= {16'h001D,8'h00 }; + 8'd21 : regdata <= {16'h001E,8'h18 };//CP_CURRENT 电荷泵 + //8'd21 : regdata <= {16'h001E,cp,4'h8 };//CP_CURRENT 电荷泵 + 8'd22 : regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器 + 8'd23 : regdata <= {16'h0020,8'h1c };//digital lock detect 数字锁定ld + 8'd24 : regdata <= {16'h0021,8'h00 }; + 8'd25 : regdata <= { 16'h0022,D,4'd0 };//double D倍频器 + 8'd26 : regdata <= {16'h0023,8'h00 }; + 8'd27 : regdata <= {16'h0024,8'h80 };//DIV_SEL + 8'd28 : regdata <= {16'h0025,8'h13 };//X4_EN + 8'd29 : regdata <= {16'h0026,8'h1F }; + 8'd30 : regdata <= {16'h0027,8'hCD }; + //8'd30 : regdata <= {16'h0027,8'hCD }; + 8'd31 : regdata <= {16'h0028,8'h83 }; + 8'd32 : regdata <= {16'h002A,8'h00 }; + 8'd33 : regdata <= {16'h002B,8'h00 }; + 8'd34 : regdata <= {16'h002C,8'h44 }; + 8'd35 : regdata <= {16'h002D,8'h11 }; + 8'd36 : regdata <= {16'h002E,8'h12 }; + 8'd37 : regdata <= {16'h002F,8'h94 }; + 8'd38 : regdata <= {16'h0030,8'h2A }; + 8'd39 : regdata <= {16'h0031,8'h02 }; + 8'd40 : regdata <= {16'h0032,8'h04 }; + 8'd41 : regdata <= {16'h0033,8'h22 }; + 8'd42 : regdata <= {16'h0034,8'h25 }; + 8'd43 : regdata <= {16'h0035,8'hFA }; + 8'd44 : regdata <= {16'h0036,8'h30 }; + 8'd45 : regdata <= {16'h0037,SI_BAND_SEL} ;//VCO频段 + 8'd46 : regdata <= {16'h0038,SI_VCO_SEL_BIAS_CODE };//[7:4]=VCO内核,[3:0]VCO偏置 + 8'd47 : regdata <= {16'h0039,8'h07 }; + 8'd48 : regdata <= {16'h003A,8'h55 }; + 8'd49 : regdata <= {16'h003D,8'h00 }; + 8'd50 : regdata <= {16'h003E,8'h0C }; + 8'd51 : regdata <= {16'h003F,8'h80 }; + 8'd52 : regdata <= {16'h0040,8'h50 }; + 8'd53 : regdata <= {16'h0041,8'h28 }; + 8'd54 : regdata <= {16'h0042,8'h00 }; + 8'd55 : regdata <= {16'h0043,8'h00 }; + 8'd56 : regdata <= {16'h0044,8'h00 }; + 8'd57 : regdata <= {16'h0045,8'h00 }; + 8'd58 : regdata <= {16'h0046,8'h00 }; + 8'd59 : regdata <= {16'h0047,8'hC0 }; + 8'd60 : regdata <= {16'h0052,8'hF4 }; + 8'd61 : regdata <= {16'h006C,8'h00 }; + 8'd62 : regdata <= {16'h006E,8'h00 }; + 8'd63 : regdata <= {16'h006F,8'h00 }; + 8'd64 : regdata <= {16'h0070,8'hE3 }; + 8'd65 : regdata <= {16'h0071,8'h60 }; + 8'd66 : regdata <= {16'h0072,8'h32 }; + 8'd67 : regdata <= {16'h0073,8'h00 }; + 8'd68 : regdata <= {16'h0079,8'h00 }; + 8'd69 : regdata <= {16'h007A,8'h00 }; + 8'd70 : regdata <= {16'h007B,8'h00 }; + 8'd71 : regdata <= {16'h007C,8'h00 }; + + //跳频 + 8'd72:regdata <= { 16'h0022,D,4'd0 };//double D倍频器 + 8'd73:regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器 + 8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8] } ; + 8'd75:regdata <= { 16'h0019 ,MOD2[7:0] } ; + 8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7] } ; + 8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24] } ; + 8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] } ; + 8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] } ; + 8'd80:regdata <= { 16'h0014 ,FRAC1[7:0] } ; + 8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL } ; + 8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE } ; + 8'd83:regdata <= { 16'h0011 ,INT[15:8] } ; + 8'd84:regdata <= { 16'h0010 ,INT[7:0] } ; + + default: regdata <= regdata; +endcase +end + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/band_rom_a.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/band_rom_a.v new file mode 100644 index 00000000..71f7026c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/band_rom_a.v @@ -0,0 +1,3573 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 18:19:17 01/25/2022 +// Design Name: +// Module Name: band_rom +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module band_rom_a( +input sysclk, +input [11 : 0] addra, + +output reg[15:0] douta +); + +always@(posedge sysclk)begin + case(addra) + +0 : douta <= 16'h7426 ; +1 : douta <= 16'h7426 ; +2 : douta <= 16'h7426 ; +3 : douta <= 16'h7426 ; +4 : douta <= 16'h7426 ; +5 : douta <= 16'h7326 ; +6 : douta <= 16'h7326 ; +7 : douta <= 16'h7426 ; +8 : douta <= 16'h7426 ; +9 : douta <= 16'h7326 ; +10 : douta <= 16'h7326 ; +11 : douta <= 16'h7326 ; +12 : douta <= 16'h7326 ; +13 : douta <= 16'h7326 ; +14 : douta <= 16'h7326 ; +15 : douta <= 16'h7326 ; +16 : douta <= 16'h7326 ; +17 : douta <= 16'h7226 ; +18 : douta <= 16'h7326 ; +19 : douta <= 16'h7226 ; +20 : douta <= 16'h7226 ; +21 : douta <= 16'h7226 ; +22 : douta <= 16'h7226 ; +23 : douta <= 16'h7126 ; +24 : douta <= 16'h7126 ; +25 : douta <= 16'h7126 ; +26 : douta <= 16'h7226 ; +27 : douta <= 16'h7226 ; +28 : douta <= 16'h7226 ; +29 : douta <= 16'h7226 ; +30 : douta <= 16'h7226 ; +31 : douta <= 16'h7226 ; +32 : douta <= 16'h7226 ; +33 : douta <= 16'h7226 ; +34 : douta <= 16'h7226 ; +35 : douta <= 16'h7226 ; +36 : douta <= 16'h7126 ; +37 : douta <= 16'h7126 ; +38 : douta <= 16'h7126 ; +39 : douta <= 16'h7126 ; +40 : douta <= 16'h7126 ; +41 : douta <= 16'h7126 ; +42 : douta <= 16'h7126 ; +43 : douta <= 16'h7126 ; +44 : douta <= 16'h7126 ; +45 : douta <= 16'h7126 ; +46 : douta <= 16'h7126 ; +47 : douta <= 16'h7126 ; +48 : douta <= 16'h7126 ; +49 : douta <= 16'h7026 ; +50 : douta <= 16'h7026 ; +51 : douta <= 16'h7126 ; +52 : douta <= 16'h7026 ; +53 : douta <= 16'h7126 ; +54 : douta <= 16'h6F26 ; +55 : douta <= 16'h7126 ; +56 : douta <= 16'h7126 ; +57 : douta <= 16'h7126 ; +58 : douta <= 16'h7126 ; +59 : douta <= 16'h7026 ; +60 : douta <= 16'h7126 ; +61 : douta <= 16'h6E26 ; +62 : douta <= 16'h7026 ; +63 : douta <= 16'h6E26 ; +64 : douta <= 16'h7026 ; +65 : douta <= 16'h7026 ; +66 : douta <= 16'h7026 ; +67 : douta <= 16'h7026 ; +68 : douta <= 16'h7026 ; +69 : douta <= 16'h7026 ; +70 : douta <= 16'h7026 ; +71 : douta <= 16'h7026 ; +72 : douta <= 16'h7026 ; +73 : douta <= 16'h7026 ; +74 : douta <= 16'h7026 ; +75 : douta <= 16'h7026 ; +76 : douta <= 16'h7026 ; +77 : douta <= 16'h7026 ; +78 : douta <= 16'h7026 ; +79 : douta <= 16'h7026 ; +80 : douta <= 16'h7026 ; +81 : douta <= 16'h6F26 ; +82 : douta <= 16'h6F26 ; +83 : douta <= 16'h6F26 ; +84 : douta <= 16'h6F26 ; +85 : douta <= 16'h6F26 ; +86 : douta <= 16'h6E26 ; +87 : douta <= 16'h6E26 ; +88 : douta <= 16'h6E26 ; +89 : douta <= 16'h6E26 ; +90 : douta <= 16'h6E26 ; +91 : douta <= 16'h6E26 ; +92 : douta <= 16'h6E26 ; +93 : douta <= 16'h6E26 ; +94 : douta <= 16'h6E26 ; +95 : douta <= 16'h6E26 ; +96 : douta <= 16'h6E26 ; +97 : douta <= 16'h6E26 ; +98 : douta <= 16'h6E26 ; +99 : douta <= 16'h6E26 ; +100 : douta <= 16'h6E26 ; +101 : douta <= 16'h6E26 ; +102 : douta <= 16'h6E26 ; +103 : douta <= 16'h6E26 ; +104 : douta <= 16'h6E26 ; +105 : douta <= 16'h6E26 ; +106 : douta <= 16'h6E26 ; +107 : douta <= 16'h6D26 ; +108 : douta <= 16'h6E26 ; +109 : douta <= 16'h6D26 ; +110 : douta <= 16'h6D26 ; +111 : douta <= 16'h6D26 ; +112 : douta <= 16'h6D26 ; +113 : douta <= 16'h6D26 ; +114 : douta <= 16'h6D26 ; +115 : douta <= 16'h6D26 ; +116 : douta <= 16'h6D26 ; +117 : douta <= 16'h6D26 ; +118 : douta <= 16'h6D26 ; +119 : douta <= 16'h6D26 ; +120 : douta <= 16'h6D26 ; +121 : douta <= 16'h6C26 ; +122 : douta <= 16'h6D26 ; +123 : douta <= 16'h6D26 ; +124 : douta <= 16'h6C26 ; +125 : douta <= 16'h6D26 ; +126 : douta <= 16'h6D26 ; +127 : douta <= 16'h6D26 ; +128 : douta <= 16'h6D26 ; +129 : douta <= 16'h6D26 ; +130 : douta <= 16'h6D26 ; +131 : douta <= 16'h6D26 ; +132 : douta <= 16'h6D26 ; +133 : douta <= 16'h6C26 ; +134 : douta <= 16'h6C26 ; +135 : douta <= 16'h6C26 ; +136 : douta <= 16'h6C26 ; +137 : douta <= 16'h6C26 ; +138 : douta <= 16'h6C26 ; +139 : douta <= 16'h6C26 ; +140 : douta <= 16'h6C26 ; +141 : douta <= 16'h6C26 ; +142 : douta <= 16'h6C26 ; +143 : douta <= 16'h6C26 ; +144 : douta <= 16'h6C26 ; +145 : douta <= 16'h6C26 ; +146 : douta <= 16'h6C26 ; +147 : douta <= 16'h6C26 ; +148 : douta <= 16'h6C26 ; +149 : douta <= 16'h6C26 ; +150 : douta <= 16'h6C26 ; +151 : douta <= 16'h6C26 ; +152 : douta <= 16'h6C26 ; +153 : douta <= 16'h6B26 ; +154 : douta <= 16'h6B26 ; +155 : douta <= 16'h6B26 ; +156 : douta <= 16'h6B26 ; +157 : douta <= 16'h6B26 ; +158 : douta <= 16'h6B26 ; +159 : douta <= 16'h6B26 ; +160 : douta <= 16'h6B26 ; +161 : douta <= 16'h6B26 ; +162 : douta <= 16'h6A26 ; +163 : douta <= 16'h6A26 ; +164 : douta <= 16'h6A26 ; +165 : douta <= 16'h6A26 ; +166 : douta <= 16'h6A26 ; +167 : douta <= 16'h6A26 ; +168 : douta <= 16'h6926 ; +169 : douta <= 16'h6A26 ; +170 : douta <= 16'h6926 ; +171 : douta <= 16'h6A26 ; +172 : douta <= 16'h6926 ; +173 : douta <= 16'h6A26 ; +174 : douta <= 16'h6A26 ; +175 : douta <= 16'h6A26 ; +176 : douta <= 16'h6A26 ; +177 : douta <= 16'h6A26 ; +178 : douta <= 16'h6A26 ; +179 : douta <= 16'h6A26 ; +180 : douta <= 16'h6A26 ; +181 : douta <= 16'h6A26 ; +182 : douta <= 16'h6A26 ; +183 : douta <= 16'h6A26 ; +184 : douta <= 16'h6926 ; +185 : douta <= 16'h6926 ; +186 : douta <= 16'h6926 ; +187 : douta <= 16'h6926 ; +188 : douta <= 16'h6926 ; +189 : douta <= 16'h6926 ; +190 : douta <= 16'h6926 ; +191 : douta <= 16'h6926 ; +192 : douta <= 16'h6926 ; +193 : douta <= 16'h6926 ; +194 : douta <= 16'h6926 ; +195 : douta <= 16'h6826 ; +196 : douta <= 16'h6826 ; +197 : douta <= 16'h6826 ; +198 : douta <= 16'h6826 ; +199 : douta <= 16'h6826 ; +200 : douta <= 16'h6926 ; +201 : douta <= 16'h6926 ; +202 : douta <= 16'h6926 ; +203 : douta <= 16'h6926 ; +204 : douta <= 16'h6926 ; +205 : douta <= 16'h6926 ; +206 : douta <= 16'h6926 ; +207 : douta <= 16'h6926 ; +208 : douta <= 16'h6826 ; +209 : douta <= 16'h6826 ; +210 : douta <= 16'h6826 ; +211 : douta <= 16'h6826 ; +212 : douta <= 16'h6826 ; +213 : douta <= 16'h6826 ; +214 : douta <= 16'h6826 ; +215 : douta <= 16'h6826 ; +216 : douta <= 16'h6826 ; +217 : douta <= 16'h6826 ; +218 : douta <= 16'h6826 ; +219 : douta <= 16'h6726 ; +220 : douta <= 16'h6726 ; +221 : douta <= 16'h6826 ; +222 : douta <= 16'h6826 ; +223 : douta <= 16'h6826 ; +224 : douta <= 16'h6826 ; +225 : douta <= 16'h6826 ; +226 : douta <= 16'h6826 ; +227 : douta <= 16'h6826 ; +228 : douta <= 16'h6826 ; +229 : douta <= 16'h6826 ; +230 : douta <= 16'h6826 ; +231 : douta <= 16'h6826 ; +232 : douta <= 16'h6726 ; +233 : douta <= 16'h6726 ; +234 : douta <= 16'h6526 ; +235 : douta <= 16'h6526 ; +236 : douta <= 16'h6726 ; +237 : douta <= 16'h6726 ; +238 : douta <= 16'h6726 ; +239 : douta <= 16'h6726 ; +240 : douta <= 16'h6726 ; +241 : douta <= 16'h6626 ; +242 : douta <= 16'h6626 ; +243 : douta <= 16'h6626 ; +244 : douta <= 16'h6626 ; +245 : douta <= 16'h6626 ; +246 : douta <= 16'h6626 ; +247 : douta <= 16'h6626 ; +248 : douta <= 16'h6626 ; +249 : douta <= 16'h6626 ; +250 : douta <= 16'h6626 ; +251 : douta <= 16'h6626 ; +252 : douta <= 16'h6626 ; +253 : douta <= 16'h6626 ; +254 : douta <= 16'h6626 ; +255 : douta <= 16'h6626 ; +256 : douta <= 16'h6626 ; +257 : douta <= 16'h6626 ; +258 : douta <= 16'h6626 ; +259 : douta <= 16'h6626 ; +260 : douta <= 16'h6626 ; +261 : douta <= 16'h6626 ; +262 : douta <= 16'h6526 ; +263 : douta <= 16'h6626 ; +264 : douta <= 16'h6526 ; +265 : douta <= 16'h6526 ; +266 : douta <= 16'h6526 ; +267 : douta <= 16'h6526 ; +268 : douta <= 16'h6526 ; +269 : douta <= 16'h6526 ; +270 : douta <= 16'h6526 ; +271 : douta <= 16'h6526 ; +272 : douta <= 16'h6526 ; +273 : douta <= 16'h6526 ; +274 : douta <= 16'h6526 ; +275 : douta <= 16'h6526 ; +276 : douta <= 16'h6526 ; +277 : douta <= 16'h6426 ; +278 : douta <= 16'h6526 ; +279 : douta <= 16'h6526 ; +280 : douta <= 16'h6526 ; +281 : douta <= 16'h6526 ; +282 : douta <= 16'h6526 ; +283 : douta <= 16'h6526 ; +284 : douta <= 16'h6526 ; +285 : douta <= 16'h6526 ; +286 : douta <= 16'h6526 ; +287 : douta <= 16'h6526 ; +288 : douta <= 16'h6426 ; +289 : douta <= 16'h6426 ; +290 : douta <= 16'h6426 ; +291 : douta <= 16'h6426 ; +292 : douta <= 16'h6426 ; +293 : douta <= 16'h6426 ; +294 : douta <= 16'h6426 ; +295 : douta <= 16'h6426 ; +296 : douta <= 16'h6426 ; +297 : douta <= 16'h6426 ; +298 : douta <= 16'h6426 ; +299 : douta <= 16'h6426 ; +300 : douta <= 16'h6426 ; +301 : douta <= 16'h6426 ; +302 : douta <= 16'h6426 ; +303 : douta <= 16'h6426 ; +304 : douta <= 16'h6426 ; +305 : douta <= 16'h6326 ; +306 : douta <= 16'h6426 ; +307 : douta <= 16'h6326 ; +308 : douta <= 16'h6326 ; +309 : douta <= 16'h6326 ; +310 : douta <= 16'h6326 ; +311 : douta <= 16'h6426 ; +312 : douta <= 16'h6426 ; +313 : douta <= 16'h6326 ; +314 : douta <= 16'h6326 ; +315 : douta <= 16'h6326 ; +316 : douta <= 16'h6326 ; +317 : douta <= 16'h6326 ; +318 : douta <= 16'h6326 ; +319 : douta <= 16'h6226 ; +320 : douta <= 16'h6226 ; +321 : douta <= 16'h6226 ; +322 : douta <= 16'h6226 ; +323 : douta <= 16'h6226 ; +324 : douta <= 16'h6126 ; +325 : douta <= 16'h6226 ; +326 : douta <= 16'h6126 ; +327 : douta <= 16'h6126 ; +328 : douta <= 16'h6126 ; +329 : douta <= 16'h6226 ; +330 : douta <= 16'h6226 ; +331 : douta <= 16'h6226 ; +332 : douta <= 16'h6226 ; +333 : douta <= 16'h6226 ; +334 : douta <= 16'h6226 ; +335 : douta <= 16'h6226 ; +336 : douta <= 16'h6226 ; +337 : douta <= 16'h6226 ; +338 : douta <= 16'h6226 ; +339 : douta <= 16'h6226 ; +340 : douta <= 16'h6226 ; +341 : douta <= 16'h6126 ; +342 : douta <= 16'h6126 ; +343 : douta <= 16'h6126 ; +344 : douta <= 16'h6126 ; +345 : douta <= 16'h6126 ; +346 : douta <= 16'h6126 ; +347 : douta <= 16'h6126 ; +348 : douta <= 16'h6126 ; +349 : douta <= 16'h6126 ; +350 : douta <= 16'h6126 ; +351 : douta <= 16'h6126 ; +352 : douta <= 16'h6126 ; +353 : douta <= 16'h6126 ; +354 : douta <= 16'h6126 ; +355 : douta <= 16'h6026 ; +356 : douta <= 16'h6026 ; +357 : douta <= 16'h6126 ; +358 : douta <= 16'h6126 ; +359 : douta <= 16'h6126 ; +360 : douta <= 16'h6126 ; +361 : douta <= 16'h6126 ; +362 : douta <= 16'h6126 ; +363 : douta <= 16'h6126 ; +364 : douta <= 16'h6126 ; +365 : douta <= 16'h6126 ; +366 : douta <= 16'h6126 ; +367 : douta <= 16'h6126 ; +368 : douta <= 16'h6026 ; +369 : douta <= 16'h6026 ; +370 : douta <= 16'h6026 ; +371 : douta <= 16'h6026 ; +372 : douta <= 16'h6026 ; +373 : douta <= 16'h6026 ; +374 : douta <= 16'h6026 ; +375 : douta <= 16'h5F28 ; +376 : douta <= 16'h6026 ; +377 : douta <= 16'h6026 ; +378 : douta <= 16'h6026 ; +379 : douta <= 16'h5F28 ; +380 : douta <= 16'h6026 ; +381 : douta <= 16'h6026 ; +382 : douta <= 16'h6026 ; +383 : douta <= 16'h6026 ; +384 : douta <= 16'h6026 ; +385 : douta <= 16'h6026 ; +386 : douta <= 16'h5F28 ; +387 : douta <= 16'h6026 ; +388 : douta <= 16'h6026 ; +389 : douta <= 16'h6026 ; +390 : douta <= 16'h5E28 ; +391 : douta <= 16'h6026 ; +392 : douta <= 16'h6026 ; +393 : douta <= 16'h6026 ; +394 : douta <= 16'h6026 ; +395 : douta <= 16'h6026 ; +396 : douta <= 16'h6026 ; +397 : douta <= 16'h6026 ; +398 : douta <= 16'h6026 ; +399 : douta <= 16'h6026 ; +400 : douta <= 16'h5E28 ; +401 : douta <= 16'h5E28 ; +402 : douta <= 16'h5E28 ; +403 : douta <= 16'h5E28 ; +404 : douta <= 16'h5E28 ; +405 : douta <= 16'h5E28 ; +406 : douta <= 16'h5E28 ; +407 : douta <= 16'h5E28 ; +408 : douta <= 16'h5E28 ; +409 : douta <= 16'h5E28 ; +410 : douta <= 16'h5E28 ; +411 : douta <= 16'h5D28 ; +412 : douta <= 16'h5D28 ; +413 : douta <= 16'h5D28 ; +414 : douta <= 16'h5D28 ; +415 : douta <= 16'h5D28 ; +416 : douta <= 16'h5D28 ; +417 : douta <= 16'h5D28 ; +418 : douta <= 16'h5D28 ; +419 : douta <= 16'h5D28 ; +420 : douta <= 16'h5D28 ; +421 : douta <= 16'h5D28 ; +422 : douta <= 16'h5D28 ; +423 : douta <= 16'h5D28 ; +424 : douta <= 16'h5D28 ; +425 : douta <= 16'h5C28 ; +426 : douta <= 16'h5C28 ; +427 : douta <= 16'h5D28 ; +428 : douta <= 16'h5D28 ; +429 : douta <= 16'h5B28 ; +430 : douta <= 16'h5B28 ; +431 : douta <= 16'h5D28 ; +432 : douta <= 16'h5D28 ; +433 : douta <= 16'h5C28 ; +434 : douta <= 16'h5C28 ; +435 : douta <= 16'h5C28 ; +436 : douta <= 16'h5C28 ; +437 : douta <= 16'h5C28 ; +438 : douta <= 16'h5C28 ; +439 : douta <= 16'h5C28 ; +440 : douta <= 16'h5C28 ; +441 : douta <= 16'h5C28 ; +442 : douta <= 16'h5C28 ; +443 : douta <= 16'h5C28 ; +444 : douta <= 16'h5C28 ; +445 : douta <= 16'h5C28 ; +446 : douta <= 16'h5C28 ; +447 : douta <= 16'h5C28 ; +448 : douta <= 16'h5C28 ; +449 : douta <= 16'h5C28 ; +450 : douta <= 16'h5C28 ; +451 : douta <= 16'h5C28 ; +452 : douta <= 16'h5C28 ; +453 : douta <= 16'h5C28 ; +454 : douta <= 16'h5C28 ; +455 : douta <= 16'h5B28 ; +456 : douta <= 16'h5C28 ; +457 : douta <= 16'h5C28 ; +458 : douta <= 16'h5B28 ; +459 : douta <= 16'h5B28 ; +460 : douta <= 16'h5B28 ; +461 : douta <= 16'h5B28 ; +462 : douta <= 16'h5B28 ; +463 : douta <= 16'h5B28 ; +464 : douta <= 16'h5B28 ; +465 : douta <= 16'h5B28 ; +466 : douta <= 16'h5B28 ; +467 : douta <= 16'h5A28 ; +468 : douta <= 16'h5A28 ; +469 : douta <= 16'h5A28 ; +470 : douta <= 16'h5A28 ; +471 : douta <= 16'h5A28 ; +472 : douta <= 16'h5A28 ; +473 : douta <= 16'h5A28 ; +474 : douta <= 16'h5A28 ; +475 : douta <= 16'h5A28 ; +476 : douta <= 16'h5A28 ; +477 : douta <= 16'h5A28 ; +478 : douta <= 16'h5A28 ; +479 : douta <= 16'h5A28 ; +480 : douta <= 16'h5A28 ; +481 : douta <= 16'h5A28 ; +482 : douta <= 16'h5A28 ; +483 : douta <= 16'h5A28 ; +484 : douta <= 16'h5A28 ; +485 : douta <= 16'h5A28 ; +486 : douta <= 16'h5A28 ; +487 : douta <= 16'h5A28 ; +488 : douta <= 16'h5A28 ; +489 : douta <= 16'h5928 ; +490 : douta <= 16'h5928 ; +491 : douta <= 16'h5928 ; +492 : douta <= 16'h5928 ; +493 : douta <= 16'h5928 ; +494 : douta <= 16'h5928 ; +495 : douta <= 16'h5928 ; +496 : douta <= 16'h5928 ; +497 : douta <= 16'h5928 ; +498 : douta <= 16'h5928 ; +499 : douta <= 16'h5928 ; +500 : douta <= 16'h5928 ; +501 : douta <= 16'h5928 ; +502 : douta <= 16'h5828 ; +503 : douta <= 16'h5828 ; +504 : douta <= 16'h5828 ; +505 : douta <= 16'h5828 ; +506 : douta <= 16'h5828 ; +507 : douta <= 16'h5928 ; +508 : douta <= 16'h5928 ; +509 : douta <= 16'h5928 ; +510 : douta <= 16'h5928 ; +511 : douta <= 16'h5928 ; +512 : douta <= 16'h5928 ; +513 : douta <= 16'h5928 ; +514 : douta <= 16'h5828 ; +515 : douta <= 16'h5828 ; +516 : douta <= 16'h5828 ; +517 : douta <= 16'h5828 ; +518 : douta <= 16'h5828 ; +519 : douta <= 16'h5828 ; +520 : douta <= 16'h5828 ; +521 : douta <= 16'h5828 ; +522 : douta <= 16'h5828 ; +523 : douta <= 16'h5828 ; +524 : douta <= 16'h5828 ; +525 : douta <= 16'h5828 ; +526 : douta <= 16'h5828 ; +527 : douta <= 16'h5828 ; +528 : douta <= 16'h5828 ; +529 : douta <= 16'h5828 ; +530 : douta <= 16'h5828 ; +531 : douta <= 16'h5828 ; +532 : douta <= 16'h5728 ; +533 : douta <= 16'h5728 ; +534 : douta <= 16'h5728 ; +535 : douta <= 16'h5828 ; +536 : douta <= 16'h5828 ; +537 : douta <= 16'h5728 ; +538 : douta <= 16'h5728 ; +539 : douta <= 16'h5728 ; +540 : douta <= 16'h5728 ; +541 : douta <= 16'h5528 ; +542 : douta <= 16'h5728 ; +543 : douta <= 16'h5528 ; +544 : douta <= 16'h5728 ; +545 : douta <= 16'h5728 ; +546 : douta <= 16'h5728 ; +547 : douta <= 16'h5628 ; +548 : douta <= 16'h5628 ; +549 : douta <= 16'h5628 ; +550 : douta <= 16'h5628 ; +551 : douta <= 16'h5628 ; +552 : douta <= 16'h5628 ; +553 : douta <= 16'h5628 ; +554 : douta <= 16'h5628 ; +555 : douta <= 16'h5628 ; +556 : douta <= 16'h5628 ; +557 : douta <= 16'h5628 ; +558 : douta <= 16'h5628 ; +559 : douta <= 16'h5628 ; +560 : douta <= 16'h5628 ; +561 : douta <= 16'h5628 ; +562 : douta <= 16'h5628 ; +563 : douta <= 16'h5628 ; +564 : douta <= 16'h5628 ; +565 : douta <= 16'h5628 ; +566 : douta <= 16'h5628 ; +567 : douta <= 16'h5628 ; +568 : douta <= 16'h5628 ; +569 : douta <= 16'h5628 ; +570 : douta <= 16'h5628 ; +571 : douta <= 16'h5528 ; +572 : douta <= 16'h5528 ; +573 : douta <= 16'h5528 ; +574 : douta <= 16'h5528 ; +575 : douta <= 16'h5528 ; +576 : douta <= 16'h5528 ; +577 : douta <= 16'h5528 ; +578 : douta <= 16'h5528 ; +579 : douta <= 16'h5528 ; +580 : douta <= 16'h5528 ; +581 : douta <= 16'h5528 ; +582 : douta <= 16'h5528 ; +583 : douta <= 16'h5528 ; +584 : douta <= 16'h5528 ; +585 : douta <= 16'h5528 ; +586 : douta <= 16'h5428 ; +587 : douta <= 16'h5528 ; +588 : douta <= 16'h5528 ; +589 : douta <= 16'h5528 ; +590 : douta <= 16'h5528 ; +591 : douta <= 16'h5528 ; +592 : douta <= 16'h5528 ; +593 : douta <= 16'h5528 ; +594 : douta <= 16'h5528 ; +595 : douta <= 16'h5528 ; +596 : douta <= 16'h5428 ; +597 : douta <= 16'h5428 ; +598 : douta <= 16'h5428 ; +599 : douta <= 16'h5428 ; +600 : douta <= 16'h5428 ; +601 : douta <= 16'h5428 ; +602 : douta <= 16'h5428 ; +603 : douta <= 16'h5428 ; +604 : douta <= 16'h5428 ; +605 : douta <= 16'h5428 ; +606 : douta <= 16'h5428 ; +607 : douta <= 16'h5428 ; +608 : douta <= 16'h5428 ; +609 : douta <= 16'h5428 ; +610 : douta <= 16'h5428 ; +611 : douta <= 16'h5428 ; +612 : douta <= 16'h5428 ; +613 : douta <= 16'h5428 ; +614 : douta <= 16'h5428 ; +615 : douta <= 16'h5428 ; +616 : douta <= 16'h5328 ; +617 : douta <= 16'h5328 ; +618 : douta <= 16'h5328 ; +619 : douta <= 16'h5328 ; +620 : douta <= 16'h5428 ; +621 : douta <= 16'h5328 ; +622 : douta <= 16'h5328 ; +623 : douta <= 16'h5328 ; +624 : douta <= 16'h5328 ; +625 : douta <= 16'h5328 ; +626 : douta <= 16'h5328 ; +627 : douta <= 16'h5328 ; +628 : douta <= 16'h5328 ; +629 : douta <= 16'h5328 ; +630 : douta <= 16'h5328 ; +631 : douta <= 16'h5328 ; +632 : douta <= 16'h5328 ; +633 : douta <= 16'h5328 ; +634 : douta <= 16'h5228 ; +635 : douta <= 16'h5228 ; +636 : douta <= 16'h5128 ; +637 : douta <= 16'h5128 ; +638 : douta <= 16'h5128 ; +639 : douta <= 16'h5228 ; +640 : douta <= 16'h5228 ; +641 : douta <= 16'h5228 ; +642 : douta <= 16'h5228 ; +643 : douta <= 16'h5228 ; +644 : douta <= 16'h5228 ; +645 : douta <= 16'h5228 ; +646 : douta <= 16'h5228 ; +647 : douta <= 16'h5228 ; +648 : douta <= 16'h5228 ; +649 : douta <= 16'h5228 ; +650 : douta <= 16'h5228 ; +651 : douta <= 16'h5228 ; +652 : douta <= 16'h5228 ; +653 : douta <= 16'h5228 ; +654 : douta <= 16'h5228 ; +655 : douta <= 16'h5228 ; +656 : douta <= 16'h5128 ; +657 : douta <= 16'h5128 ; +658 : douta <= 16'h5128 ; +659 : douta <= 16'h5128 ; +660 : douta <= 16'h5128 ; +661 : douta <= 16'h5128 ; +662 : douta <= 16'h5128 ; +663 : douta <= 16'h5128 ; +664 : douta <= 16'h5128 ; +665 : douta <= 16'h5128 ; +666 : douta <= 16'h5128 ; +667 : douta <= 16'h5128 ; +668 : douta <= 16'h5128 ; +669 : douta <= 16'h5128 ; +670 : douta <= 16'h5128 ; +671 : douta <= 16'h5028 ; +672 : douta <= 16'h5028 ; +673 : douta <= 16'h5128 ; +674 : douta <= 16'h5128 ; +675 : douta <= 16'h5128 ; +676 : douta <= 16'h5128 ; +677 : douta <= 16'h5128 ; +678 : douta <= 16'h5128 ; +679 : douta <= 16'h5128 ; +680 : douta <= 16'h5128 ; +681 : douta <= 16'h5128 ; +682 : douta <= 16'h5028 ; +683 : douta <= 16'h5028 ; +684 : douta <= 16'h5028 ; +685 : douta <= 16'h4E28 ; +686 : douta <= 16'h5028 ; +687 : douta <= 16'h5028 ; +688 : douta <= 16'h4F28 ; +689 : douta <= 16'h5028 ; +690 : douta <= 16'h5028 ; +691 : douta <= 16'h5028 ; +692 : douta <= 16'h4F28 ; +693 : douta <= 16'h5028 ; +694 : douta <= 16'h5028 ; +695 : douta <= 16'h5028 ; +696 : douta <= 16'h5028 ; +697 : douta <= 16'h5028 ; +698 : douta <= 16'h5028 ; +699 : douta <= 16'h5028 ; +700 : douta <= 16'h5028 ; +701 : douta <= 16'h5028 ; +702 : douta <= 16'h5028 ; +703 : douta <= 16'h5028 ; +704 : douta <= 16'h5028 ; +705 : douta <= 16'h5028 ; +706 : douta <= 16'h5028 ; +707 : douta <= 16'h5028 ; +708 : douta <= 16'h4D28 ; +709 : douta <= 16'h4D28 ; +710 : douta <= 16'h4E28 ; +711 : douta <= 16'h4E28 ; +712 : douta <= 16'h4E28 ; +713 : douta <= 16'h4E28 ; +714 : douta <= 16'h4E28 ; +715 : douta <= 16'h4E28 ; +716 : douta <= 16'h4E28 ; +717 : douta <= 16'h4E28 ; +718 : douta <= 16'h4E28 ; +719 : douta <= 16'h4E28 ; +720 : douta <= 16'h4E28 ; +721 : douta <= 16'h4E28 ; +722 : douta <= 16'h4E28 ; +723 : douta <= 16'h4E28 ; +724 : douta <= 16'h4E28 ; +725 : douta <= 16'h4E28 ; +726 : douta <= 16'h4E28 ; +727 : douta <= 16'h4E28 ; +728 : douta <= 16'h4E28 ; +729 : douta <= 16'h4E28 ; +730 : douta <= 16'h4E28 ; +731 : douta <= 16'h4E28 ; +732 : douta <= 16'h4E28 ; +733 : douta <= 16'h4E28 ; +734 : douta <= 16'h4D28 ; +735 : douta <= 16'h4D28 ; +736 : douta <= 16'h4D28 ; +737 : douta <= 16'h4D28 ; +738 : douta <= 16'h4D28 ; +739 : douta <= 16'h4D28 ; +740 : douta <= 16'h4D28 ; +741 : douta <= 16'h4D28 ; +742 : douta <= 16'h4D28 ; +743 : douta <= 16'h4D28 ; +744 : douta <= 16'h4D28 ; +745 : douta <= 16'h4D28 ; +746 : douta <= 16'h4D28 ; +747 : douta <= 16'h4C28 ; +748 : douta <= 16'h4C28 ; +749 : douta <= 16'h4D28 ; +750 : douta <= 16'h4D28 ; +751 : douta <= 16'h4D28 ; +752 : douta <= 16'h4D28 ; +753 : douta <= 16'h4D28 ; +754 : douta <= 16'h4D28 ; +755 : douta <= 16'h4D28 ; +756 : douta <= 16'h4D28 ; +757 : douta <= 16'h4D28 ; +758 : douta <= 16'h4D28 ; +759 : douta <= 16'h4D28 ; +760 : douta <= 16'h4B28 ; +761 : douta <= 16'h4B28 ; +762 : douta <= 16'h4C28 ; +763 : douta <= 16'h4C28 ; +764 : douta <= 16'h4C28 ; +765 : douta <= 16'h4C28 ; +766 : douta <= 16'h4C28 ; +767 : douta <= 16'h4C28 ; +768 : douta <= 16'h4C28 ; +769 : douta <= 16'h4C28 ; +770 : douta <= 16'h4C28 ; +771 : douta <= 16'h4C28 ; +772 : douta <= 16'h4C28 ; +773 : douta <= 16'h4C28 ; +774 : douta <= 16'h4C28 ; +775 : douta <= 16'h4C28 ; +776 : douta <= 16'h4C28 ; +777 : douta <= 16'h4C28 ; +778 : douta <= 16'h4C28 ; +779 : douta <= 16'h4C28 ; +780 : douta <= 16'h4C28 ; +781 : douta <= 16'h4C28 ; +782 : douta <= 16'h4C28 ; +783 : douta <= 16'h4C28 ; +784 : douta <= 16'h4C28 ; +785 : douta <= 16'h4C28 ; +786 : douta <= 16'h4B28 ; +787 : douta <= 16'h4B28 ; +788 : douta <= 16'h4B28 ; +789 : douta <= 16'h4B28 ; +790 : douta <= 16'h4B28 ; +791 : douta <= 16'h4B28 ; +792 : douta <= 16'h4B28 ; +793 : douta <= 16'h4B28 ; +794 : douta <= 16'h4B28 ; +795 : douta <= 16'h4A28 ; +796 : douta <= 16'h4A28 ; +797 : douta <= 16'h4A28 ; +798 : douta <= 16'h4A28 ; +799 : douta <= 16'h4A28 ; +800 : douta <= 16'h4A28 ; +801 : douta <= 16'h4928 ; +802 : douta <= 16'h4A28 ; +803 : douta <= 16'h4928 ; +804 : douta <= 16'h4A28 ; +805 : douta <= 16'h4A28 ; +806 : douta <= 16'h4A28 ; +807 : douta <= 16'h4A28 ; +808 : douta <= 16'h4A28 ; +809 : douta <= 16'h4A28 ; +810 : douta <= 16'h4A28 ; +811 : douta <= 16'h4A28 ; +812 : douta <= 16'h4A28 ; +813 : douta <= 16'h4A28 ; +814 : douta <= 16'h4A28 ; +815 : douta <= 16'h4A28 ; +816 : douta <= 16'h4A28 ; +817 : douta <= 16'h4A28 ; +818 : douta <= 16'h4928 ; +819 : douta <= 16'h4928 ; +820 : douta <= 16'h4928 ; +821 : douta <= 16'h4928 ; +822 : douta <= 16'h4928 ; +823 : douta <= 16'h4928 ; +824 : douta <= 16'h4928 ; +825 : douta <= 16'h4928 ; +826 : douta <= 16'h4928 ; +827 : douta <= 16'h4928 ; +828 : douta <= 16'h4928 ; +829 : douta <= 16'h4928 ; +830 : douta <= 16'h4928 ; +831 : douta <= 16'h4828 ; +832 : douta <= 16'h4928 ; +833 : douta <= 16'h4928 ; +834 : douta <= 16'h4928 ; +835 : douta <= 16'h4928 ; +836 : douta <= 16'h4928 ; +837 : douta <= 16'h4928 ; +838 : douta <= 16'h4928 ; +839 : douta <= 16'h4928 ; +840 : douta <= 16'h4928 ; +841 : douta <= 16'h4928 ; +842 : douta <= 16'h4928 ; +843 : douta <= 16'h4928 ; +844 : douta <= 16'h4828 ; +845 : douta <= 16'h4828 ; +846 : douta <= 16'h4728 ; +847 : douta <= 16'h4728 ; +848 : douta <= 16'h4828 ; +849 : douta <= 16'h4828 ; +850 : douta <= 16'h4828 ; +851 : douta <= 16'h4828 ; +852 : douta <= 16'h4828 ; +853 : douta <= 16'h4828 ; +854 : douta <= 16'h4828 ; +855 : douta <= 16'h4828 ; +856 : douta <= 16'h4828 ; +857 : douta <= 16'h4828 ; +858 : douta <= 16'h4828 ; +859 : douta <= 16'h4828 ; +860 : douta <= 16'h4828 ; +861 : douta <= 16'h4828 ; +862 : douta <= 16'h4828 ; +863 : douta <= 16'h4828 ; +864 : douta <= 16'h4828 ; +865 : douta <= 16'h4828 ; +866 : douta <= 16'h4828 ; +867 : douta <= 16'h4828 ; +868 : douta <= 16'h4828 ; +869 : douta <= 16'h4528 ; +870 : douta <= 16'h4728 ; +871 : douta <= 16'h4528 ; +872 : douta <= 16'h4528 ; +873 : douta <= 16'h4728 ; +874 : douta <= 16'h4528 ; +875 : douta <= 16'h4728 ; +876 : douta <= 16'h4628 ; +877 : douta <= 16'h4628 ; +878 : douta <= 16'h4628 ; +879 : douta <= 16'h4628 ; +880 : douta <= 16'h4628 ; +881 : douta <= 16'h4628 ; +882 : douta <= 16'h4628 ; +883 : douta <= 16'h4628 ; +884 : douta <= 16'h4628 ; +885 : douta <= 16'h4628 ; +886 : douta <= 16'h4628 ; +887 : douta <= 16'h4628 ; +888 : douta <= 16'h4628 ; +889 : douta <= 16'h4628 ; +890 : douta <= 16'h4628 ; +891 : douta <= 16'h4628 ; +892 : douta <= 16'h4628 ; +893 : douta <= 16'h4628 ; +894 : douta <= 16'h4628 ; +895 : douta <= 16'h4628 ; +896 : douta <= 16'h4628 ; +897 : douta <= 16'h4528 ; +898 : douta <= 16'h4628 ; +899 : douta <= 16'h4528 ; +900 : douta <= 16'h4528 ; +901 : douta <= 16'h4528 ; +902 : douta <= 16'h4528 ; +903 : douta <= 16'h4528 ; +904 : douta <= 16'h4528 ; +905 : douta <= 16'h4528 ; +906 : douta <= 16'h4528 ; +907 : douta <= 16'h4528 ; +908 : douta <= 16'h4528 ; +909 : douta <= 16'h4528 ; +910 : douta <= 16'h4528 ; +911 : douta <= 16'h4528 ; +912 : douta <= 16'h4528 ; +913 : douta <= 16'h4428 ; +914 : douta <= 16'h4428 ; +915 : douta <= 16'h4528 ; +916 : douta <= 16'h4428 ; +917 : douta <= 16'h4428 ; +918 : douta <= 16'h4528 ; +919 : douta <= 16'h4528 ; +920 : douta <= 16'h4528 ; +921 : douta <= 16'h4528 ; +922 : douta <= 16'h4528 ; +923 : douta <= 16'h4528 ; +924 : douta <= 16'h4528 ; +925 : douta <= 16'h4528 ; +926 : douta <= 16'h4528 ; +927 : douta <= 16'h4428 ; +928 : douta <= 16'h4428 ; +929 : douta <= 16'h4428 ; +930 : douta <= 16'h4428 ; +931 : douta <= 16'h4428 ; +932 : douta <= 16'h4428 ; +933 : douta <= 16'h4428 ; +934 : douta <= 16'h4428 ; +935 : douta <= 16'h4428 ; +936 : douta <= 16'h4428 ; +937 : douta <= 16'h4428 ; +938 : douta <= 16'h4428 ; +939 : douta <= 16'h4428 ; +940 : douta <= 16'h4428 ; +941 : douta <= 16'h4428 ; +942 : douta <= 16'h4428 ; +943 : douta <= 16'h4428 ; +944 : douta <= 16'h4428 ; +945 : douta <= 16'h4428 ; +946 : douta <= 16'h4328 ; +947 : douta <= 16'h4328 ; +948 : douta <= 16'h4428 ; +949 : douta <= 16'h4328 ; +950 : douta <= 16'h4428 ; +951 : douta <= 16'h4428 ; +952 : douta <= 16'h4328 ; +953 : douta <= 16'h4328 ; +954 : douta <= 16'h4328 ; +955 : douta <= 16'h4328 ; +956 : douta <= 16'h4328 ; +957 : douta <= 16'h4328 ; +958 : douta <= 16'h4328 ; +959 : douta <= 16'h4328 ; +960 : douta <= 16'h4328 ; +961 : douta <= 16'h4328 ; +962 : douta <= 16'h4328 ; +963 : douta <= 16'h4228 ; +964 : douta <= 16'h4228 ; +965 : douta <= 16'h4228 ; +966 : douta <= 16'h4228 ; +967 : douta <= 16'h4228 ; +968 : douta <= 16'h4228 ; +969 : douta <= 16'h4228 ; +970 : douta <= 16'h4228 ; +971 : douta <= 16'h4228 ; +972 : douta <= 16'h4228 ; +973 : douta <= 16'h4228 ; +974 : douta <= 16'h4228 ; +975 : douta <= 16'h4228 ; +976 : douta <= 16'h4228 ; +977 : douta <= 16'h4228 ; +978 : douta <= 16'h4228 ; +979 : douta <= 16'h4228 ; +980 : douta <= 16'h4228 ; +981 : douta <= 16'h4228 ; +982 : douta <= 16'h4228 ; +983 : douta <= 16'h4228 ; +984 : douta <= 16'h4128 ; +985 : douta <= 16'h4128 ; +986 : douta <= 16'h4128 ; +987 : douta <= 16'h4128 ; +988 : douta <= 16'h4128 ; +989 : douta <= 16'h4128 ; +990 : douta <= 16'h4128 ; +991 : douta <= 16'h4128 ; +992 : douta <= 16'h4128 ; +993 : douta <= 16'h4128 ; +994 : douta <= 16'h4128 ; +995 : douta <= 16'h4128 ; +996 : douta <= 16'h4128 ; +997 : douta <= 16'h4128 ; +998 : douta <= 16'h4128 ; +999 : douta <= 16'h4128 ; +1000 : douta <= 16'h4128 ; +1001 : douta <= 16'h4128 ; +1002 : douta <= 16'h4128 ; +1003 : douta <= 16'h4128 ; +1004 : douta <= 16'h4028 ; +1005 : douta <= 16'h4128 ; +1006 : douta <= 16'h4128 ; +1007 : douta <= 16'h4128 ; +1008 : douta <= 16'h4128 ; +1009 : douta <= 16'h4128 ; +1010 : douta <= 16'h4128 ; +1011 : douta <= 16'h4128 ; +1012 : douta <= 16'h4128 ; +1013 : douta <= 16'h4128 ; +1014 : douta <= 16'h4128 ; +1015 : douta <= 16'h4028 ; +1016 : douta <= 16'h4028 ; +1017 : douta <= 16'h4028 ; +1018 : douta <= 16'h4028 ; +1019 : douta <= 16'h4028 ; +1020 : douta <= 16'h4028 ; +1021 : douta <= 16'h4028 ; +1022 : douta <= 16'h4028 ; +1023 : douta <= 16'h3F2A ; +1024 : douta <= 16'h4028 ; +1025 : douta <= 16'h4028 ; +1026 : douta <= 16'h3E2A ; +1027 : douta <= 16'h4028 ; +1028 : douta <= 16'h3F2A ; +1029 : douta <= 16'h4028 ; +1030 : douta <= 16'h4028 ; +1031 : douta <= 16'h4028 ; +1032 : douta <= 16'h4028 ; +1033 : douta <= 16'h4028 ; +1034 : douta <= 16'h4028 ; +1035 : douta <= 16'h4028 ; +1036 : douta <= 16'h4028 ; +1037 : douta <= 16'h4028 ; +1038 : douta <= 16'h4028 ; +1039 : douta <= 16'h4028 ; +1040 : douta <= 16'h4028 ; +1041 : douta <= 16'h4028 ; +1042 : douta <= 16'h4028 ; +1043 : douta <= 16'h4028 ; +1044 : douta <= 16'h4028 ; +1045 : douta <= 16'h4028 ; +1046 : douta <= 16'h4028 ; +1047 : douta <= 16'h4028 ; +1048 : douta <= 16'h4028 ; +1049 : douta <= 16'h4028 ; +1050 : douta <= 16'h3D2A ; +1051 : douta <= 16'h4028 ; +1052 : douta <= 16'h3E2A ; +1053 : douta <= 16'h3E2A ; +1054 : douta <= 16'h3E2A ; +1055 : douta <= 16'h3E2A ; +1056 : douta <= 16'h3E2A ; +1057 : douta <= 16'h3E2A ; +1058 : douta <= 16'h3E2A ; +1059 : douta <= 16'h3E2A ; +1060 : douta <= 16'h3E2A ; +1061 : douta <= 16'h3E2A ; +1062 : douta <= 16'h3E2A ; +1063 : douta <= 16'h3E2A ; +1064 : douta <= 16'h3E2A ; +1065 : douta <= 16'h3E2A ; +1066 : douta <= 16'h3E2A ; +1067 : douta <= 16'h3E2A ; +1068 : douta <= 16'h3E2A ; +1069 : douta <= 16'h3E2A ; +1070 : douta <= 16'h3E2A ; +1071 : douta <= 16'h3E2A ; +1072 : douta <= 16'h3E2A ; +1073 : douta <= 16'h3E2A ; +1074 : douta <= 16'h3E2A ; +1075 : douta <= 16'h3E2A ; +1076 : douta <= 16'h3D2A ; +1077 : douta <= 16'h3E2A ; +1078 : douta <= 16'h3D2A ; +1079 : douta <= 16'h3D2A ; +1080 : douta <= 16'h3D2A ; +1081 : douta <= 16'h3D2A ; +1082 : douta <= 16'h3D2A ; +1083 : douta <= 16'h3D2A ; +1084 : douta <= 16'h3D2A ; +1085 : douta <= 16'h3D2A ; +1086 : douta <= 16'h3D2A ; +1087 : douta <= 16'h3D2A ; +1088 : douta <= 16'h3D2A ; +1089 : douta <= 16'h3D2A ; +1090 : douta <= 16'h3D2A ; +1091 : douta <= 16'h3D2A ; +1092 : douta <= 16'h3C2A ; +1093 : douta <= 16'h3D2A ; +1094 : douta <= 16'h3D2A ; +1095 : douta <= 16'h3D2A ; +1096 : douta <= 16'h3C2A ; +1097 : douta <= 16'h3D2A ; +1098 : douta <= 16'h3D2A ; +1099 : douta <= 16'h3D2A ; +1100 : douta <= 16'h3D2A ; +1101 : douta <= 16'h3D2A ; +1102 : douta <= 16'h3C2A ; +1103 : douta <= 16'h3D2A ; +1104 : douta <= 16'h3B2A ; +1105 : douta <= 16'h3B2A ; +1106 : douta <= 16'h3B2A ; +1107 : douta <= 16'h3C2A ; +1108 : douta <= 16'h3C2A ; +1109 : douta <= 16'h3C2A ; +1110 : douta <= 16'h3C2A ; +1111 : douta <= 16'h3C2A ; +1112 : douta <= 16'h3C2A ; +1113 : douta <= 16'h3C2A ; +1114 : douta <= 16'h3C2A ; +1115 : douta <= 16'h3C2A ; +1116 : douta <= 16'h3C2A ; +1117 : douta <= 16'h3C2A ; +1118 : douta <= 16'h3C2A ; +1119 : douta <= 16'h3C2A ; +1120 : douta <= 16'h3C2A ; +1121 : douta <= 16'h3C2A ; +1122 : douta <= 16'h3C2A ; +1123 : douta <= 16'h3C2A ; +1124 : douta <= 16'h3C2A ; +1125 : douta <= 16'h3C2A ; +1126 : douta <= 16'h3C2A ; +1127 : douta <= 16'h3C2A ; +1128 : douta <= 16'h3C2A ; +1129 : douta <= 16'h3C2A ; +1130 : douta <= 16'h3C2A ; +1131 : douta <= 16'h3B2A ; +1132 : douta <= 16'h3B2A ; +1133 : douta <= 16'h3B2A ; +1134 : douta <= 16'h3B2A ; +1135 : douta <= 16'h3B2A ; +1136 : douta <= 16'h3B2A ; +1137 : douta <= 16'h3B2A ; +1138 : douta <= 16'h3A2A ; +1139 : douta <= 16'h3A2A ; +1140 : douta <= 16'h3A2A ; +1141 : douta <= 16'h3A2A ; +1142 : douta <= 16'h3A2A ; +1143 : douta <= 16'h3A2A ; +1144 : douta <= 16'h3A2A ; +1145 : douta <= 16'h3A2A ; +1146 : douta <= 16'h392A ; +1147 : douta <= 16'h392A ; +1148 : douta <= 16'h392A ; +1149 : douta <= 16'h3A2A ; +1150 : douta <= 16'h3A2A ; +1151 : douta <= 16'h3A2A ; +1152 : douta <= 16'h3A2A ; +1153 : douta <= 16'h3A2A ; +1154 : douta <= 16'h3A2A ; +1155 : douta <= 16'h3A2A ; +1156 : douta <= 16'h3A2A ; +1157 : douta <= 16'h3A2A ; +1158 : douta <= 16'h3A2A ; +1159 : douta <= 16'h3A2A ; +1160 : douta <= 16'h3A2A ; +1161 : douta <= 16'h3A2A ; +1162 : douta <= 16'h3A2A ; +1163 : douta <= 16'h392A ; +1164 : douta <= 16'h3A2A ; +1165 : douta <= 16'h392A ; +1166 : douta <= 16'h392A ; +1167 : douta <= 16'h392A ; +1168 : douta <= 16'h392A ; +1169 : douta <= 16'h392A ; +1170 : douta <= 16'h392A ; +1171 : douta <= 16'h392A ; +1172 : douta <= 16'h392A ; +1173 : douta <= 16'h392A ; +1174 : douta <= 16'h392A ; +1175 : douta <= 16'h392A ; +1176 : douta <= 16'h392A ; +1177 : douta <= 16'h392A ; +1178 : douta <= 16'h392A ; +1179 : douta <= 16'h382A ; +1180 : douta <= 16'h382A ; +1181 : douta <= 16'h392A ; +1182 : douta <= 16'h392A ; +1183 : douta <= 16'h392A ; +1184 : douta <= 16'h392A ; +1185 : douta <= 16'h392A ; +1186 : douta <= 16'h392A ; +1187 : douta <= 16'h392A ; +1188 : douta <= 16'h372A ; +1189 : douta <= 16'h372A ; +1190 : douta <= 16'h372A ; +1191 : douta <= 16'h372A ; +1192 : douta <= 16'h382A ; +1193 : douta <= 16'h382A ; +1194 : douta <= 16'h382A ; +1195 : douta <= 16'h382A ; +1196 : douta <= 16'h382A ; +1197 : douta <= 16'h382A ; +1198 : douta <= 16'h382A ; +1199 : douta <= 16'h382A ; +1200 : douta <= 16'h382A ; +1201 : douta <= 16'h382A ; +1202 : douta <= 16'h382A ; +1203 : douta <= 16'h382A ; +1204 : douta <= 16'h382A ; +1205 : douta <= 16'h382A ; +1206 : douta <= 16'h382A ; +1207 : douta <= 16'h382A ; +1208 : douta <= 16'h382A ; +1209 : douta <= 16'h382A ; +1210 : douta <= 16'h382A ; +1211 : douta <= 16'h382A ; +1212 : douta <= 16'h382A ; +1213 : douta <= 16'h382A ; +1214 : douta <= 16'h382A ; +1215 : douta <= 16'h382A ; +1216 : douta <= 16'h382A ; +1217 : douta <= 16'h372A ; +1218 : douta <= 16'h382A ; +1219 : douta <= 16'h372A ; +1220 : douta <= 16'h372A ; +1221 : douta <= 16'h372A ; +1222 : douta <= 16'h372A ; +1223 : douta <= 16'h372A ; +1224 : douta <= 16'h372A ; +1225 : douta <= 16'h372A ; +1226 : douta <= 16'h372A ; +1227 : douta <= 16'h362A ; +1228 : douta <= 16'h352A ; +1229 : douta <= 16'h362A ; +1230 : douta <= 16'h362A ; +1231 : douta <= 16'h362A ; +1232 : douta <= 16'h362A ; +1233 : douta <= 16'h362A ; +1234 : douta <= 16'h362A ; +1235 : douta <= 16'h362A ; +1236 : douta <= 16'h362A ; +1237 : douta <= 16'h362A ; +1238 : douta <= 16'h362A ; +1239 : douta <= 16'h362A ; +1240 : douta <= 16'h362A ; +1241 : douta <= 16'h362A ; +1242 : douta <= 16'h362A ; +1243 : douta <= 16'h362A ; +1244 : douta <= 16'h362A ; +1245 : douta <= 16'h362A ; +1246 : douta <= 16'h362A ; +1247 : douta <= 16'h362A ; +1248 : douta <= 16'h362A ; +1249 : douta <= 16'h362A ; +1250 : douta <= 16'h362A ; +1251 : douta <= 16'h362A ; +1252 : douta <= 16'h362A ; +1253 : douta <= 16'h352A ; +1254 : douta <= 16'h352A ; +1255 : douta <= 16'h352A ; +1256 : douta <= 16'h352A ; +1257 : douta <= 16'h352A ; +1258 : douta <= 16'h352A ; +1259 : douta <= 16'h352A ; +1260 : douta <= 16'h352A ; +1261 : douta <= 16'h352A ; +1262 : douta <= 16'h352A ; +1263 : douta <= 16'h352A ; +1264 : douta <= 16'h352A ; +1265 : douta <= 16'h352A ; +1266 : douta <= 16'h352A ; +1267 : douta <= 16'h342A ; +1268 : douta <= 16'h342A ; +1269 : douta <= 16'h352A ; +1270 : douta <= 16'h352A ; +1271 : douta <= 16'h352A ; +1272 : douta <= 16'h352A ; +1273 : douta <= 16'h352A ; +1274 : douta <= 16'h352A ; +1275 : douta <= 16'h352A ; +1276 : douta <= 16'h352A ; +1277 : douta <= 16'h352A ; +1278 : douta <= 16'h352A ; +1279 : douta <= 16'h352A ; +1280 : douta <= 16'h342A ; +1281 : douta <= 16'h342A ; +1282 : douta <= 16'h342A ; +1283 : douta <= 16'h342A ; +1284 : douta <= 16'h342A ; +1285 : douta <= 16'h342A ; +1286 : douta <= 16'h342A ; +1287 : douta <= 16'h342A ; +1288 : douta <= 16'h342A ; +1289 : douta <= 16'h342A ; +1290 : douta <= 16'h342A ; +1291 : douta <= 16'h342A ; +1292 : douta <= 16'h342A ; +1293 : douta <= 16'h342A ; +1294 : douta <= 16'h342A ; +1295 : douta <= 16'h342A ; +1296 : douta <= 16'h332A ; +1297 : douta <= 16'h332A ; +1298 : douta <= 16'h332A ; +1299 : douta <= 16'h342A ; +1300 : douta <= 16'h342A ; +1301 : douta <= 16'h342A ; +1302 : douta <= 16'h342A ; +1303 : douta <= 16'h342A ; +1304 : douta <= 16'h342A ; +1305 : douta <= 16'h332A ; +1306 : douta <= 16'h332A ; +1307 : douta <= 16'h332A ; +1308 : douta <= 16'h332A ; +1309 : douta <= 16'h332A ; +1310 : douta <= 16'h332A ; +1311 : douta <= 16'h332A ; +1312 : douta <= 16'h332A ; +1313 : douta <= 16'h332A ; +1314 : douta <= 16'h332A ; +1315 : douta <= 16'h322A ; +1316 : douta <= 16'h322A ; +1317 : douta <= 16'h322A ; +1318 : douta <= 16'h322A ; +1319 : douta <= 16'h322A ; +1320 : douta <= 16'h322A ; +1321 : douta <= 16'h312A ; +1322 : douta <= 16'h322A ; +1323 : douta <= 16'h312A ; +1324 : douta <= 16'h312A ; +1325 : douta <= 16'h322A ; +1326 : douta <= 16'h322A ; +1327 : douta <= 16'h322A ; +1328 : douta <= 16'h322A ; +1329 : douta <= 16'h322A ; +1330 : douta <= 16'h322A ; +1331 : douta <= 16'h322A ; +1332 : douta <= 16'h322A ; +1333 : douta <= 16'h322A ; +1334 : douta <= 16'h322A ; +1335 : douta <= 16'h322A ; +1336 : douta <= 16'h322A ; +1337 : douta <= 16'h322A ; +1338 : douta <= 16'h322A ; +1339 : douta <= 16'h322A ; +1340 : douta <= 16'h312A ; +1341 : douta <= 16'h312A ; +1342 : douta <= 16'h312A ; +1343 : douta <= 16'h312A ; +1344 : douta <= 16'h312A ; +1345 : douta <= 16'h312A ; +1346 : douta <= 16'h312A ; +1347 : douta <= 16'h312A ; +1348 : douta <= 16'h312A ; +1349 : douta <= 16'h312A ; +1350 : douta <= 16'h312A ; +1351 : douta <= 16'h312A ; +1352 : douta <= 16'h312A ; +1353 : douta <= 16'h312A ; +1354 : douta <= 16'h312A ; +1355 : douta <= 16'h312A ; +1356 : douta <= 16'h302A ; +1357 : douta <= 16'h312A ; +1358 : douta <= 16'h312A ; +1359 : douta <= 16'h312A ; +1360 : douta <= 16'h312A ; +1361 : douta <= 16'h312A ; +1362 : douta <= 16'h312A ; +1363 : douta <= 16'h312A ; +1364 : douta <= 16'h312A ; +1365 : douta <= 16'h312A ; +1366 : douta <= 16'h2F2A ; +1367 : douta <= 16'h302A ; +1368 : douta <= 16'h302A ; +1369 : douta <= 16'h302A ; +1370 : douta <= 16'h302A ; +1371 : douta <= 16'h302A ; +1372 : douta <= 16'h302A ; +1373 : douta <= 16'h302A ; +1374 : douta <= 16'h302A ; +1375 : douta <= 16'h302A ; +1376 : douta <= 16'h302A ; +1377 : douta <= 16'h302A ; +1378 : douta <= 16'h302A ; +1379 : douta <= 16'h302A ; +1380 : douta <= 16'h302A ; +1381 : douta <= 16'h302A ; +1382 : douta <= 16'h2F2A ; +1383 : douta <= 16'h302A ; +1384 : douta <= 16'h302A ; +1385 : douta <= 16'h302A ; +1386 : douta <= 16'h302A ; +1387 : douta <= 16'h302A ; +1388 : douta <= 16'h302A ; +1389 : douta <= 16'h302A ; +1390 : douta <= 16'h302A ; +1391 : douta <= 16'h2F2A ; +1392 : douta <= 16'h302A ; +1393 : douta <= 16'h302A ; +1394 : douta <= 16'h302A ; +1395 : douta <= 16'h2F2A ; +1396 : douta <= 16'h302A ; +1397 : douta <= 16'h2F2A ; +1398 : douta <= 16'h2F2A ; +1399 : douta <= 16'h2F2A ; +1400 : douta <= 16'h2E2A ; +1401 : douta <= 16'h2E2A ; +1402 : douta <= 16'h2D2A ; +1403 : douta <= 16'h2D2A ; +1404 : douta <= 16'h2D2A ; +1405 : douta <= 16'h2D2A ; +1406 : douta <= 16'h2E2A ; +1407 : douta <= 16'h2E2A ; +1408 : douta <= 16'h2E2A ; +1409 : douta <= 16'h2E2A ; +1410 : douta <= 16'h2E2A ; +1411 : douta <= 16'h2E2A ; +1412 : douta <= 16'h2E2A ; +1413 : douta <= 16'h2E2A ; +1414 : douta <= 16'h2E2A ; +1415 : douta <= 16'h2E2A ; +1416 : douta <= 16'h2E2A ; +1417 : douta <= 16'h2E2A ; +1418 : douta <= 16'h2E2A ; +1419 : douta <= 16'h2E2A ; +1420 : douta <= 16'h2E2A ; +1421 : douta <= 16'h2E2A ; +1422 : douta <= 16'h2E2A ; +1423 : douta <= 16'h2E2A ; +1424 : douta <= 16'h2E2A ; +1425 : douta <= 16'h2E2A ; +1426 : douta <= 16'h2E2A ; +1427 : douta <= 16'h2D2A ; +1428 : douta <= 16'h2E2A ; +1429 : douta <= 16'h2D2A ; +1430 : douta <= 16'h2D2A ; +1431 : douta <= 16'h2D2A ; +1432 : douta <= 16'h2D2A ; +1433 : douta <= 16'h2D2A ; +1434 : douta <= 16'h2D2A ; +1435 : douta <= 16'h2D2A ; +1436 : douta <= 16'h2D2A ; +1437 : douta <= 16'h2D2A ; +1438 : douta <= 16'h2D2A ; +1439 : douta <= 16'h2D2A ; +1440 : douta <= 16'h2D2A ; +1441 : douta <= 16'h2D2A ; +1442 : douta <= 16'h2D2A ; +1443 : douta <= 16'h2C2A ; +1444 : douta <= 16'h2D2A ; +1445 : douta <= 16'h2C2A ; +1446 : douta <= 16'h2D2A ; +1447 : douta <= 16'h2D2A ; +1448 : douta <= 16'h2D2A ; +1449 : douta <= 16'h2D2A ; +1450 : douta <= 16'h2D2A ; +1451 : douta <= 16'h2D2A ; +1452 : douta <= 16'h2D2A ; +1453 : douta <= 16'h2D2A ; +1454 : douta <= 16'h2D2A ; +1455 : douta <= 16'h2D2A ; +1456 : douta <= 16'h2C2A ; +1457 : douta <= 16'h2C2A ; +1458 : douta <= 16'h2C2A ; +1459 : douta <= 16'h2B2A ; +1460 : douta <= 16'h2B2A ; +1461 : douta <= 16'h2C2A ; +1462 : douta <= 16'h2C2A ; +1463 : douta <= 16'h2C2A ; +1464 : douta <= 16'h2C2A ; +1465 : douta <= 16'h2C2A ; +1466 : douta <= 16'h2C2A ; +1467 : douta <= 16'h2C2A ; +1468 : douta <= 16'h2C2A ; +1469 : douta <= 16'h2C2A ; +1470 : douta <= 16'h2C2A ; +1471 : douta <= 16'h2C2A ; +1472 : douta <= 16'h2C2A ; +1473 : douta <= 16'h2C2A ; +1474 : douta <= 16'h2C2A ; +1475 : douta <= 16'h2C2A ; +1476 : douta <= 16'h2C2A ; +1477 : douta <= 16'h2C2A ; +1478 : douta <= 16'h2C2A ; +1479 : douta <= 16'h2C2A ; +1480 : douta <= 16'h2C2A ; +1481 : douta <= 16'h2C2A ; +1482 : douta <= 16'h2C2A ; +1483 : douta <= 16'h2C2A ; +1484 : douta <= 16'h2C2A ; +1485 : douta <= 16'h2B2A ; +1486 : douta <= 16'h2B2A ; +1487 : douta <= 16'h2B2A ; +1488 : douta <= 16'h2B2A ; +1489 : douta <= 16'h2A2A ; +1490 : douta <= 16'h2B2A ; +1491 : douta <= 16'h2A2A ; +1492 : douta <= 16'h2A2A ; +1493 : douta <= 16'h2A2A ; +1494 : douta <= 16'h2A2A ; +1495 : douta <= 16'h2A2A ; +1496 : douta <= 16'h2A2A ; +1497 : douta <= 16'h2A2A ; +1498 : douta <= 16'h2A2A ; +1499 : douta <= 16'h2A2A ; +1500 : douta <= 16'h292A ; +1501 : douta <= 16'h292A ; +1502 : douta <= 16'h292A ; +1503 : douta <= 16'h2A2A ; +1504 : douta <= 16'h2A2A ; +1505 : douta <= 16'h2A2A ; +1506 : douta <= 16'h2A2A ; +1507 : douta <= 16'h2A2A ; +1508 : douta <= 16'h2A2A ; +1509 : douta <= 16'h2A2A ; +1510 : douta <= 16'h2A2A ; +1511 : douta <= 16'h2A2A ; +1512 : douta <= 16'h2A2A ; +1513 : douta <= 16'h2A2A ; +1514 : douta <= 16'h2A2A ; +1515 : douta <= 16'h292A ; +1516 : douta <= 16'h292A ; +1517 : douta <= 16'h292A ; +1518 : douta <= 16'h292A ; +1519 : douta <= 16'h292A ; +1520 : douta <= 16'h292A ; +1521 : douta <= 16'h292A ; +1522 : douta <= 16'h292A ; +1523 : douta <= 16'h292A ; +1524 : douta <= 16'h292A ; +1525 : douta <= 16'h292A ; +1526 : douta <= 16'h292A ; +1527 : douta <= 16'h292A ; +1528 : douta <= 16'h292A ; +1529 : douta <= 16'h292A ; +1530 : douta <= 16'h292A ; +1531 : douta <= 16'h292A ; +1532 : douta <= 16'h282A ; +1533 : douta <= 16'h282A ; +1534 : douta <= 16'h282A ; +1535 : douta <= 16'h292A ; +1536 : douta <= 16'h292A ; +1537 : douta <= 16'h292A ; +1538 : douta <= 16'h292A ; +1539 : douta <= 16'h292A ; +1540 : douta <= 16'h292A ; +1541 : douta <= 16'h292A ; +1542 : douta <= 16'h272A ; +1543 : douta <= 16'h292A ; +1544 : douta <= 16'h272A ; +1545 : douta <= 16'h272A ; +1546 : douta <= 16'h282A ; +1547 : douta <= 16'h282A ; +1548 : douta <= 16'h282A ; +1549 : douta <= 16'h282A ; +1550 : douta <= 16'h282A ; +1551 : douta <= 16'h282A ; +1552 : douta <= 16'h282A ; +1553 : douta <= 16'h282A ; +1554 : douta <= 16'h282A ; +1555 : douta <= 16'h282A ; +1556 : douta <= 16'h282A ; +1557 : douta <= 16'h282A ; +1558 : douta <= 16'h282A ; +1559 : douta <= 16'h282A ; +1560 : douta <= 16'h282A ; +1561 : douta <= 16'h282A ; +1562 : douta <= 16'h282A ; +1563 : douta <= 16'h282A ; +1564 : douta <= 16'h282A ; +1565 : douta <= 16'h282A ; +1566 : douta <= 16'h282A ; +1567 : douta <= 16'h282A ; +1568 : douta <= 16'h282A ; +1569 : douta <= 16'h282A ; +1570 : douta <= 16'h282A ; +1571 : douta <= 16'h282A ; +1572 : douta <= 16'h282A ; +1573 : douta <= 16'h282A ; +1574 : douta <= 16'h282A ; +1575 : douta <= 16'h272A ; +1576 : douta <= 16'h272A ; +1577 : douta <= 16'h272A ; +1578 : douta <= 16'h272A ; +1579 : douta <= 16'h272A ; +1580 : douta <= 16'h272A ; +1581 : douta <= 16'h272A ; +1582 : douta <= 16'h272A ; +1583 : douta <= 16'h262A ; +1584 : douta <= 16'h262A ; +1585 : douta <= 16'h252A ; +1586 : douta <= 16'h252A ; +1587 : douta <= 16'h262A ; +1588 : douta <= 16'h262A ; +1589 : douta <= 16'h252A ; +1590 : douta <= 16'h262A ; +1591 : douta <= 16'h262A ; +1592 : douta <= 16'h262A ; +1593 : douta <= 16'h262A ; +1594 : douta <= 16'h262A ; +1595 : douta <= 16'h262A ; +1596 : douta <= 16'h262A ; +1597 : douta <= 16'h262A ; +1598 : douta <= 16'h262A ; +1599 : douta <= 16'h262A ; +1600 : douta <= 16'h262A ; +1601 : douta <= 16'h262A ; +1602 : douta <= 16'h262A ; +1603 : douta <= 16'h262A ; +1604 : douta <= 16'h262A ; +1605 : douta <= 16'h262A ; +1606 : douta <= 16'h262A ; +1607 : douta <= 16'h262A ; +1608 : douta <= 16'h262A ; +1609 : douta <= 16'h252A ; +1610 : douta <= 16'h252A ; +1611 : douta <= 16'h252A ; +1612 : douta <= 16'h252A ; +1613 : douta <= 16'h252A ; +1614 : douta <= 16'h252A ; +1615 : douta <= 16'h252A ; +1616 : douta <= 16'h252A ; +1617 : douta <= 16'h252A ; +1618 : douta <= 16'h252A ; +1619 : douta <= 16'h252A ; +1620 : douta <= 16'h252A ; +1621 : douta <= 16'h252A ; +1622 : douta <= 16'h252A ; +1623 : douta <= 16'h252A ; +1624 : douta <= 16'h252A ; +1625 : douta <= 16'h242A ; +1626 : douta <= 16'h252A ; +1627 : douta <= 16'h252A ; +1628 : douta <= 16'h252A ; +1629 : douta <= 16'h252A ; +1630 : douta <= 16'h252A ; +1631 : douta <= 16'h252A ; +1632 : douta <= 16'h252A ; +1633 : douta <= 16'h252A ; +1634 : douta <= 16'h252A ; +1635 : douta <= 16'h252A ; +1636 : douta <= 16'h252A ; +1637 : douta <= 16'h252A ; +1638 : douta <= 16'h242A ; +1639 : douta <= 16'h242A ; +1640 : douta <= 16'h242A ; +1641 : douta <= 16'h242A ; +1642 : douta <= 16'h242A ; +1643 : douta <= 16'h242A ; +1644 : douta <= 16'h242A ; +1645 : douta <= 16'h242A ; +1646 : douta <= 16'h242A ; +1647 : douta <= 16'h242A ; +1648 : douta <= 16'h242A ; +1649 : douta <= 16'h242A ; +1650 : douta <= 16'h242A ; +1651 : douta <= 16'h242A ; +1652 : douta <= 16'h232A ; +1653 : douta <= 16'h232A ; +1654 : douta <= 16'h242A ; +1655 : douta <= 16'h242A ; +1656 : douta <= 16'h242A ; +1657 : douta <= 16'h242A ; +1658 : douta <= 16'h242A ; +1659 : douta <= 16'h242A ; +1660 : douta <= 16'h242A ; +1661 : douta <= 16'h242A ; +1662 : douta <= 16'h242A ; +1663 : douta <= 16'h242A ; +1664 : douta <= 16'h242A ; +1665 : douta <= 16'h232A ; +1666 : douta <= 16'h232A ; +1667 : douta <= 16'h232A ; +1668 : douta <= 16'h232A ; +1669 : douta <= 16'h232A ; +1670 : douta <= 16'h232A ; +1671 : douta <= 16'h232A ; +1672 : douta <= 16'h222A ; +1673 : douta <= 16'h222A ; +1674 : douta <= 16'h222A ; +1675 : douta <= 16'h222A ; +1676 : douta <= 16'h222A ; +1677 : douta <= 16'h222A ; +1678 : douta <= 16'h222A ; +1679 : douta <= 16'h222A ; +1680 : douta <= 16'h222A ; +1681 : douta <= 16'h212A ; +1682 : douta <= 16'h222A ; +1683 : douta <= 16'h212A ; +1684 : douta <= 16'h222A ; +1685 : douta <= 16'h222A ; +1686 : douta <= 16'h222A ; +1687 : douta <= 16'h222A ; +1688 : douta <= 16'h222A ; +1689 : douta <= 16'h222A ; +1690 : douta <= 16'h222A ; +1691 : douta <= 16'h222A ; +1692 : douta <= 16'h222A ; +1693 : douta <= 16'h222A ; +1694 : douta <= 16'h222A ; +1695 : douta <= 16'h222A ; +1696 : douta <= 16'h222A ; +1697 : douta <= 16'h222A ; +1698 : douta <= 16'h222A ; +1699 : douta <= 16'h212A ; +1700 : douta <= 16'h212A ; +1701 : douta <= 16'h212A ; +1702 : douta <= 16'h212A ; +1703 : douta <= 16'h212A ; +1704 : douta <= 16'h212A ; +1705 : douta <= 16'h212A ; +1706 : douta <= 16'h212A ; +1707 : douta <= 16'h212A ; +1708 : douta <= 16'h212A ; +1709 : douta <= 16'h212A ; +1710 : douta <= 16'h212A ; +1711 : douta <= 16'h212A ; +1712 : douta <= 16'h212A ; +1713 : douta <= 16'h212A ; +1714 : douta <= 16'h202A ; +1715 : douta <= 16'h202A ; +1716 : douta <= 16'h212A ; +1717 : douta <= 16'h212A ; +1718 : douta <= 16'h212A ; +1719 : douta <= 16'h212A ; +1720 : douta <= 16'h212A ; +1721 : douta <= 16'h212A ; +1722 : douta <= 16'h212A ; +1723 : douta <= 16'h212A ; +1724 : douta <= 16'h212A ; +1725 : douta <= 16'h212A ; +1726 : douta <= 16'h202A ; +1727 : douta <= 16'h212A ; +1728 : douta <= 16'h202A ; +1729 : douta <= 16'h202A ; +1730 : douta <= 16'h202A ; +1731 : douta <= 16'h202A ; +1732 : douta <= 16'h202A ; +1733 : douta <= 16'h202A ; +1734 : douta <= 16'h202A ; +1735 : douta <= 16'h202A ; +1736 : douta <= 16'h202A ; +1737 : douta <= 16'h202A ; +1738 : douta <= 16'h202A ; +1739 : douta <= 16'h202A ; +1740 : douta <= 16'h202A ; +1741 : douta <= 16'h202A ; +1742 : douta <= 16'h202A ; +1743 : douta <= 16'h202A ; +1744 : douta <= 16'h202A ; +1745 : douta <= 16'h202A ; +1746 : douta <= 16'h202A ; +1747 : douta <= 16'h202A ; +1748 : douta <= 16'h202A ; +1749 : douta <= 16'h202A ; +1750 : douta <= 16'h202A ; +1751 : douta <= 16'h1F2C ; +1752 : douta <= 16'h202A ; +1753 : douta <= 16'h202A ; +1754 : douta <= 16'h202A ; +1755 : douta <= 16'h202A ; +1756 : douta <= 16'h202A ; +1757 : douta <= 16'h1D2C ; +1758 : douta <= 16'h202A ; +1759 : douta <= 16'h202A ; +1760 : douta <= 16'h202A ; +1761 : douta <= 16'h202A ; +1762 : douta <= 16'h1E2C ; +1763 : douta <= 16'h202A ; +1764 : douta <= 16'h202A ; +1765 : douta <= 16'h202A ; +1766 : douta <= 16'h202A ; +1767 : douta <= 16'h1E2C ; +1768 : douta <= 16'h202A ; +1769 : douta <= 16'h1E2C ; +1770 : douta <= 16'h1E2C ; +1771 : douta <= 16'h1E2C ; +1772 : douta <= 16'h1E2C ; +1773 : douta <= 16'h1E2C ; +1774 : douta <= 16'h1E2C ; +1775 : douta <= 16'h1E2C ; +1776 : douta <= 16'h1E2C ; +1777 : douta <= 16'h1E2C ; +1778 : douta <= 16'h1E2C ; +1779 : douta <= 16'h1E2C ; +1780 : douta <= 16'h1E2C ; +1781 : douta <= 16'h1E2C ; +1782 : douta <= 16'h1E2C ; +1783 : douta <= 16'h1D2C ; +1784 : douta <= 16'h1D2C ; +1785 : douta <= 16'h1D2C ; +1786 : douta <= 16'h1D2C ; +1787 : douta <= 16'h1D2C ; +1788 : douta <= 16'h1D2C ; +1789 : douta <= 16'h1D2C ; +1790 : douta <= 16'h1D2C ; +1791 : douta <= 16'h1D2C ; +1792 : douta <= 16'h1D2C ; +1793 : douta <= 16'h1D2C ; +1794 : douta <= 16'h1D2C ; +1795 : douta <= 16'h1D2C ; +1796 : douta <= 16'h1D2C ; +1797 : douta <= 16'h1C2C ; +1798 : douta <= 16'h1C2C ; +1799 : douta <= 16'h1C2C ; +1800 : douta <= 16'h1C2C ; +1801 : douta <= 16'h1D2C ; +1802 : douta <= 16'h1D2C ; +1803 : douta <= 16'h1D2C ; +1804 : douta <= 16'h1D2C ; +1805 : douta <= 16'h1D2C ; +1806 : douta <= 16'h1D2C ; +1807 : douta <= 16'h1D2C ; +1808 : douta <= 16'h1D2C ; +1809 : douta <= 16'h1D2C ; +1810 : douta <= 16'h1D2C ; +1811 : douta <= 16'h1C2C ; +1812 : douta <= 16'h1C2C ; +1813 : douta <= 16'h1C2C ; +1814 : douta <= 16'h1C2C ; +1815 : douta <= 16'h1C2C ; +1816 : douta <= 16'h1C2C ; +1817 : douta <= 16'h1B2C ; +1818 : douta <= 16'h1C2C ; +1819 : douta <= 16'h1B2C ; +1820 : douta <= 16'h1B2C ; +1821 : douta <= 16'h1B2C ; +1822 : douta <= 16'h1C2C ; +1823 : douta <= 16'h1C2C ; +1824 : douta <= 16'h1C2C ; +1825 : douta <= 16'h1C2C ; +1826 : douta <= 16'h1C2C ; +1827 : douta <= 16'h1C2C ; +1828 : douta <= 16'h1C2C ; +1829 : douta <= 16'h1C2C ; +1830 : douta <= 16'h1C2C ; +1831 : douta <= 16'h1C2C ; +1832 : douta <= 16'h1C2C ; +1833 : douta <= 16'h1C2C ; +1834 : douta <= 16'h1C2C ; +1835 : douta <= 16'h1C2C ; +1836 : douta <= 16'h1C2C ; +1837 : douta <= 16'h1C2C ; +1838 : douta <= 16'h1C2C ; +1839 : douta <= 16'h1C2C ; +1840 : douta <= 16'h1B2C ; +1841 : douta <= 16'h1B2C ; +1842 : douta <= 16'h1B2C ; +1843 : douta <= 16'h1B2C ; +1844 : douta <= 16'h1B2C ; +1845 : douta <= 16'h1B2C ; +1846 : douta <= 16'h1B2C ; +1847 : douta <= 16'h1B2C ; +1848 : douta <= 16'h1B2C ; +1849 : douta <= 16'h1B2C ; +1850 : douta <= 16'h1A2C ; +1851 : douta <= 16'h1A2C ; +1852 : douta <= 16'h1A2C ; +1853 : douta <= 16'h1A2C ; +1854 : douta <= 16'h1A2C ; +1855 : douta <= 16'h1A2C ; +1856 : douta <= 16'h192C ; +1857 : douta <= 16'h192C ; +1858 : douta <= 16'h192C ; +1859 : douta <= 16'h1A2C ; +1860 : douta <= 16'h1A2C ; +1861 : douta <= 16'h1A2C ; +1862 : douta <= 16'h1A2C ; +1863 : douta <= 16'h1A2C ; +1864 : douta <= 16'h1A2C ; +1865 : douta <= 16'h1A2C ; +1866 : douta <= 16'h1A2C ; +1867 : douta <= 16'h1A2C ; +1868 : douta <= 16'h1A2C ; +1869 : douta <= 16'h1A2C ; +1870 : douta <= 16'h1A2C ; +1871 : douta <= 16'h1A2C ; +1872 : douta <= 16'h1A2C ; +1873 : douta <= 16'h1A2C ; +1874 : douta <= 16'h1A2C ; +1875 : douta <= 16'h1A2C ; +1876 : douta <= 16'h1A2C ; +1877 : douta <= 16'h1A2C ; +1878 : douta <= 16'h192C ; +1879 : douta <= 16'h192C ; +1880 : douta <= 16'h192C ; +1881 : douta <= 16'h192C ; +1882 : douta <= 16'h192C ; +1883 : douta <= 16'h192C ; +1884 : douta <= 16'h192C ; +1885 : douta <= 16'h192C ; +1886 : douta <= 16'h192C ; +1887 : douta <= 16'h192C ; +1888 : douta <= 16'h192C ; +1889 : douta <= 16'h192C ; +1890 : douta <= 16'h192C ; +1891 : douta <= 16'h192C ; +1892 : douta <= 16'h182C ; +1893 : douta <= 16'h192C ; +1894 : douta <= 16'h192C ; +1895 : douta <= 16'h192C ; +1896 : douta <= 16'h192C ; +1897 : douta <= 16'h192C ; +1898 : douta <= 16'h192C ; +1899 : douta <= 16'h192C ; +1900 : douta <= 16'h192C ; +1901 : douta <= 16'h192C ; +1902 : douta <= 16'h192C ; +1903 : douta <= 16'h192C ; +1904 : douta <= 16'h192C ; +1905 : douta <= 16'h192C ; +1906 : douta <= 16'h182C ; +1907 : douta <= 16'h182C ; +1908 : douta <= 16'h182C ; +1909 : douta <= 16'h172C ; +1910 : douta <= 16'h182C ; +1911 : douta <= 16'h172C ; +1912 : douta <= 16'h172C ; +1913 : douta <= 16'h172C ; +1914 : douta <= 16'h182C ; +1915 : douta <= 16'h182C ; +1916 : douta <= 16'h182C ; +1917 : douta <= 16'h182C ; +1918 : douta <= 16'h182C ; +1919 : douta <= 16'h182C ; +1920 : douta <= 16'h182C ; +1921 : douta <= 16'h182C ; +1922 : douta <= 16'h182C ; +1923 : douta <= 16'h182C ; +1924 : douta <= 16'h182C ; +1925 : douta <= 16'h182C ; +1926 : douta <= 16'h182C ; +1927 : douta <= 16'h182C ; +1928 : douta <= 16'h182C ; +1929 : douta <= 16'h182C ; +1930 : douta <= 16'h182C ; +1931 : douta <= 16'h182C ; +1932 : douta <= 16'h182C ; +1933 : douta <= 16'h182C ; +1934 : douta <= 16'h182C ; +1935 : douta <= 16'h172C ; +1936 : douta <= 16'h172C ; +1937 : douta <= 16'h172C ; +1938 : douta <= 16'h172C ; +1939 : douta <= 16'h172C ; +1940 : douta <= 16'h172C ; +1941 : douta <= 16'h172C ; +1942 : douta <= 16'h172C ; +1943 : douta <= 16'h152C ; +1944 : douta <= 16'h152C ; +1945 : douta <= 16'h152C ; +1946 : douta <= 16'h152C ; +1947 : douta <= 16'h152C ; +1948 : douta <= 16'h162C ; +1949 : douta <= 16'h162C ; +1950 : douta <= 16'h162C ; +1951 : douta <= 16'h162C ; +1952 : douta <= 16'h162C ; +1953 : douta <= 16'h162C ; +1954 : douta <= 16'h162C ; +1955 : douta <= 16'h162C ; +1956 : douta <= 16'h162C ; +1957 : douta <= 16'h162C ; +1958 : douta <= 16'h162C ; +1959 : douta <= 16'h162C ; +1960 : douta <= 16'h162C ; +1961 : douta <= 16'h162C ; +1962 : douta <= 16'h162C ; +1963 : douta <= 16'h162C ; +1964 : douta <= 16'h162C ; +1965 : douta <= 16'h162C ; +1966 : douta <= 16'h162C ; +1967 : douta <= 16'h162C ; +1968 : douta <= 16'h162C ; +1969 : douta <= 16'h162C ; +1970 : douta <= 16'h162C ; +1971 : douta <= 16'h162C ; +1972 : douta <= 16'h152C ; +1973 : douta <= 16'h152C ; +1974 : douta <= 16'h152C ; +1975 : douta <= 16'h152C ; +1976 : douta <= 16'h152C ; +1977 : douta <= 16'h152C ; +1978 : douta <= 16'h152C ; +1979 : douta <= 16'h152C ; +1980 : douta <= 16'h152C ; +1981 : douta <= 16'h152C ; +1982 : douta <= 16'h152C ; +1983 : douta <= 16'h152C ; +1984 : douta <= 16'h152C ; +1985 : douta <= 16'h152C ; +1986 : douta <= 16'h152C ; +1987 : douta <= 16'h142C ; +1988 : douta <= 16'h142C ; +1989 : douta <= 16'h152C ; +1990 : douta <= 16'h152C ; +1991 : douta <= 16'h152C ; +1992 : douta <= 16'h152C ; +1993 : douta <= 16'h152C ; +1994 : douta <= 16'h152C ; +1995 : douta <= 16'h152C ; +1996 : douta <= 16'h152C ; +1997 : douta <= 16'h152C ; +1998 : douta <= 16'h152C ; +1999 : douta <= 16'h152C ; +2000 : douta <= 16'h152C ; +2001 : douta <= 16'h152C ; +2002 : douta <= 16'h142C ; +2003 : douta <= 16'h142C ; +2004 : douta <= 16'h142C ; +2005 : douta <= 16'h142C ; +2006 : douta <= 16'h142C ; +2007 : douta <= 16'h142C ; +2008 : douta <= 16'h142C ; +2009 : douta <= 16'h142C ; +2010 : douta <= 16'h142C ; +2011 : douta <= 16'h142C ; +2012 : douta <= 16'h142C ; +2013 : douta <= 16'h142C ; +2014 : douta <= 16'h142C ; +2015 : douta <= 16'h142C ; +2016 : douta <= 16'h142C ; +2017 : douta <= 16'h142C ; +2018 : douta <= 16'h142C ; +2019 : douta <= 16'h122C ; +2020 : douta <= 16'h132C ; +2021 : douta <= 16'h142C ; +2022 : douta <= 16'h142C ; +2023 : douta <= 16'h142C ; +2024 : douta <= 16'h142C ; +2025 : douta <= 16'h142C ; +2026 : douta <= 16'h142C ; +2027 : douta <= 16'h132C ; +2028 : douta <= 16'h132C ; +2029 : douta <= 16'h132C ; +2030 : douta <= 16'h132C ; +2031 : douta <= 16'h132C ; +2032 : douta <= 16'h132C ; +2033 : douta <= 16'h132C ; +2034 : douta <= 16'h132C ; +2035 : douta <= 16'h132C ; +2036 : douta <= 16'h132C ; +2037 : douta <= 16'h122C ; +2038 : douta <= 16'h132C ; +2039 : douta <= 16'h122C ; +2040 : douta <= 16'h122C ; +2041 : douta <= 16'h122C ; +2042 : douta <= 16'h122C ; +2043 : douta <= 16'h112C ; +2044 : douta <= 16'h122C ; +2045 : douta <= 16'h112C ; +2046 : douta <= 16'h122C ; +2047 : douta <= 16'h122C ; +2048 : douta <= 16'h122C ; +2049 : douta <= 16'h122C ; +2050 : douta <= 16'h122C ; +2051 : douta <= 16'h122C ; +2052 : douta <= 16'h122C ; +2053 : douta <= 16'h122C ; +2054 : douta <= 16'h122C ; +2055 : douta <= 16'h122C ; +2056 : douta <= 16'h122C ; +2057 : douta <= 16'h122C ; +2058 : douta <= 16'h122C ; +2059 : douta <= 16'h122C ; +2060 : douta <= 16'h122C ; +2061 : douta <= 16'h122C ; +2062 : douta <= 16'h122C ; +2063 : douta <= 16'h122C ; +2064 : douta <= 16'h122C ; +2065 : douta <= 16'h122C ; +2066 : douta <= 16'h112C ; +2067 : douta <= 16'h112C ; +2068 : douta <= 16'h112C ; +2069 : douta <= 16'h112C ; +2070 : douta <= 16'h112C ; +2071 : douta <= 16'h112C ; +2072 : douta <= 16'h112C ; +2073 : douta <= 16'h112C ; +2074 : douta <= 16'h112C ; +2075 : douta <= 16'h112C ; +2076 : douta <= 16'h112C ; +2077 : douta <= 16'h112C ; +2078 : douta <= 16'h112C ; +2079 : douta <= 16'h112C ; +2080 : douta <= 16'h112C ; +2081 : douta <= 16'h102C ; +2082 : douta <= 16'h102C ; +2083 : douta <= 16'h102C ; +2084 : douta <= 16'h102C ; +2085 : douta <= 16'h112C ; +2086 : douta <= 16'h112C ; +2087 : douta <= 16'h112C ; +2088 : douta <= 16'h112C ; +2089 : douta <= 16'h112C ; +2090 : douta <= 16'h112C ; +2091 : douta <= 16'h0F2C ; +2092 : douta <= 16'h112C ; +2093 : douta <= 16'h112C ; +2094 : douta <= 16'h112C ; +2095 : douta <= 16'h102C ; +2096 : douta <= 16'h102C ; +2097 : douta <= 16'h102C ; +2098 : douta <= 16'h102C ; +2099 : douta <= 16'h102C ; +2100 : douta <= 16'h102C ; +2101 : douta <= 16'h102C ; +2102 : douta <= 16'h102C ; +2103 : douta <= 16'h102C ; +2104 : douta <= 16'h102C ; +2105 : douta <= 16'h102C ; +2106 : douta <= 16'h102C ; +2107 : douta <= 16'h102C ; +2108 : douta <= 16'h0E2C ; +2109 : douta <= 16'h102C ; +2110 : douta <= 16'h102C ; +2111 : douta <= 16'h102C ; +2112 : douta <= 16'h102C ; +2113 : douta <= 16'h102C ; +2114 : douta <= 16'h102C ; +2115 : douta <= 16'h102C ; +2116 : douta <= 16'h102C ; +2117 : douta <= 16'h102C ; +2118 : douta <= 16'h102C ; +2119 : douta <= 16'h102C ; +2120 : douta <= 16'h102C ; +2121 : douta <= 16'h102C ; +2122 : douta <= 16'h102C ; +2123 : douta <= 16'h102C ; +2124 : douta <= 16'h0F2C ; +2125 : douta <= 16'h0F2C ; +2126 : douta <= 16'h0F2C ; +2127 : douta <= 16'h0E2C ; +2128 : douta <= 16'h0F2C ; +2129 : douta <= 16'h0F2C ; +2130 : douta <= 16'h0F2C ; +2131 : douta <= 16'h0E2C ; +2132 : douta <= 16'h0E2C ; +2133 : douta <= 16'h0D2C ; +2134 : douta <= 16'h0D2C ; +2135 : douta <= 16'h0D2C ; +2136 : douta <= 16'h0E2C ; +2137 : douta <= 16'h0E2C ; +2138 : douta <= 16'h0E2C ; +2139 : douta <= 16'h0E2C ; +2140 : douta <= 16'h0E2C ; +2141 : douta <= 16'h0E2C ; +2142 : douta <= 16'h0E2C ; +2143 : douta <= 16'h0E2C ; +2144 : douta <= 16'h0E2C ; +2145 : douta <= 16'h0E2C ; +2146 : douta <= 16'h0E2C ; +2147 : douta <= 16'h0E2C ; +2148 : douta <= 16'h0E2C ; +2149 : douta <= 16'h0E2C ; +2150 : douta <= 16'h0E2C ; +2151 : douta <= 16'h0E2C ; +2152 : douta <= 16'h0E2C ; +2153 : douta <= 16'h0E2C ; +2154 : douta <= 16'h0E2C ; +2155 : douta <= 16'h0E2C ; +2156 : douta <= 16'h0E2C ; +2157 : douta <= 16'h0E2C ; +2158 : douta <= 16'h0D2C ; +2159 : douta <= 16'h0D2C ; +2160 : douta <= 16'h0D2C ; +2161 : douta <= 16'h0D2C ; +2162 : douta <= 16'h0D2C ; +2163 : douta <= 16'h0D2C ; +2164 : douta <= 16'h0D2C ; +2165 : douta <= 16'h0D2C ; +2166 : douta <= 16'h0D2C ; +2167 : douta <= 16'h0D2C ; +2168 : douta <= 16'h0D2C ; +2169 : douta <= 16'h0D2C ; +2170 : douta <= 16'h0D2C ; +2171 : douta <= 16'h0D2C ; +2172 : douta <= 16'h0C2C ; +2173 : douta <= 16'h0C2C ; +2174 : douta <= 16'h0C2C ; +2175 : douta <= 16'h0D2C ; +2176 : douta <= 16'h0C2C ; +2177 : douta <= 16'h0D2C ; +2178 : douta <= 16'h0D2C ; +2179 : douta <= 16'h0D2C ; +2180 : douta <= 16'h0D2C ; +2181 : douta <= 16'h0D2C ; +2182 : douta <= 16'h0D2C ; +2183 : douta <= 16'h0D2C ; +2184 : douta <= 16'h0D2C ; +2185 : douta <= 16'h0D2C ; +2186 : douta <= 16'h0D2C ; +2187 : douta <= 16'h0D2C ; +2188 : douta <= 16'h0D2C ; +2189 : douta <= 16'h0C2C ; +2190 : douta <= 16'h0C2C ; +2191 : douta <= 16'h0C2C ; +2192 : douta <= 16'h0C2C ; +2193 : douta <= 16'h0C2C ; +2194 : douta <= 16'h0C2C ; +2195 : douta <= 16'h0C2C ; +2196 : douta <= 16'h0B2C ; +2197 : douta <= 16'h0B2C ; +2198 : douta <= 16'h0B2C ; +2199 : douta <= 16'h0C2C ; +2200 : douta <= 16'h0C2C ; +2201 : douta <= 16'h0C2C ; +2202 : douta <= 16'h0C2C ; +2203 : douta <= 16'h0C2C ; +2204 : douta <= 16'h0C2C ; +2205 : douta <= 16'h0C2C ; +2206 : douta <= 16'h0C2C ; +2207 : douta <= 16'h0C2C ; +2208 : douta <= 16'h0C2C ; +2209 : douta <= 16'h0C2C ; +2210 : douta <= 16'h0C2C ; +2211 : douta <= 16'h0C2C ; +2212 : douta <= 16'h0C2C ; +2213 : douta <= 16'h0C2C ; +2214 : douta <= 16'h0C2C ; +2215 : douta <= 16'h0C2C ; +2216 : douta <= 16'h0C2C ; +2217 : douta <= 16'h0C2C ; +2218 : douta <= 16'h0C2C ; +2219 : douta <= 16'h0C2C ; +2220 : douta <= 16'h0B2C ; +2221 : douta <= 16'h0B2C ; +2222 : douta <= 16'h0B2C ; +2223 : douta <= 16'h0B2C ; +2224 : douta <= 16'h0B2C ; +2225 : douta <= 16'h0B2C ; +2226 : douta <= 16'h0A2C ; +2227 : douta <= 16'h0A2C ; +2228 : douta <= 16'h0A2C ; +2229 : douta <= 16'h0A2C ; +2230 : douta <= 16'h0A2C ; +2231 : douta <= 16'h0A2C ; +2232 : douta <= 16'h0A2C ; +2233 : douta <= 16'h0A2C ; +2234 : douta <= 16'h92C ; +2235 : douta <= 16'h0A2C ; +2236 : douta <= 16'h0A2C ; +2237 : douta <= 16'h92C ; +2238 : douta <= 16'h0A2C ; +2239 : douta <= 16'h0A2C ; +2240 : douta <= 16'h0A2C ; +2241 : douta <= 16'h0A2C ; +2242 : douta <= 16'h0A2C ; +2243 : douta <= 16'h0A2C ; +2244 : douta <= 16'h0A2C ; +2245 : douta <= 16'h0A2C ; +2246 : douta <= 16'h0A2C ; +2247 : douta <= 16'h0A2C ; +2248 : douta <= 16'h0A2C ; +2249 : douta <= 16'h0A2C ; +2250 : douta <= 16'h0A2C ; +2251 : douta <= 16'h0A2C ; +2252 : douta <= 16'h0A2C ; +2253 : douta <= 16'h92C ; +2254 : douta <= 16'h0A2C ; +2255 : douta <= 16'h92C ; +2256 : douta <= 16'h92C ; +2257 : douta <= 16'h92C ; +2258 : douta <= 16'h92C ; +2259 : douta <= 16'h92C ; +2260 : douta <= 16'h92C ; +2261 : douta <= 16'h92C ; +2262 : douta <= 16'h92C ; +2263 : douta <= 16'h92C ; +2264 : douta <= 16'h92C ; +2265 : douta <= 16'h92C ; +2266 : douta <= 16'h92C ; +2267 : douta <= 16'h92C ; +2268 : douta <= 16'h92C ; +2269 : douta <= 16'h92C ; +2270 : douta <= 16'h82C ; +2271 : douta <= 16'h82C ; +2272 : douta <= 16'h92C ; +2273 : douta <= 16'h92C ; +2274 : douta <= 16'h82C ; +2275 : douta <= 16'h92C ; +2276 : douta <= 16'h92C ; +2277 : douta <= 16'h92C ; +2278 : douta <= 16'h92C ; +2279 : douta <= 16'h92C ; +2280 : douta <= 16'h92C ; +2281 : douta <= 16'h92C ; +2282 : douta <= 16'h92C ; +2283 : douta <= 16'h92C ; +2284 : douta <= 16'h92C ; +2285 : douta <= 16'h92C ; +2286 : douta <= 16'h92C ; +2287 : douta <= 16'h82C ; +2288 : douta <= 16'h82C ; +2289 : douta <= 16'h82C ; +2290 : douta <= 16'h82C ; +2291 : douta <= 16'h82C ; +2292 : douta <= 16'h82C ; +2293 : douta <= 16'h82C ; +2294 : douta <= 16'h82C ; +2295 : douta <= 16'h82C ; +2296 : douta <= 16'h82C ; +2297 : douta <= 16'h82C ; +2298 : douta <= 16'h82C ; +2299 : douta <= 16'h82C ; +2300 : douta <= 16'h82C ; +2301 : douta <= 16'h82C ; +2302 : douta <= 16'h82C ; +2303 : douta <= 16'h82C ; +2304 : douta <= 16'h82C ; +2305 : douta <= 16'h82C ; +2306 : douta <= 16'h82C ; +2307 : douta <= 16'h82C ; +2308 : douta <= 16'h82C ; +2309 : douta <= 16'h82C ; +2310 : douta <= 16'h82C ; +2311 : douta <= 16'h82C ; +2312 : douta <= 16'h72C ; +2313 : douta <= 16'h72C ; +2314 : douta <= 16'h82C ; +2315 : douta <= 16'h82C ; +2316 : douta <= 16'h72C ; +2317 : douta <= 16'h72C ; +2318 : douta <= 16'h72C ; +2319 : douta <= 16'h72C ; +2320 : douta <= 16'h72C ; +2321 : douta <= 16'h72C ; +2322 : douta <= 16'h72C ; +2323 : douta <= 16'h72C ; +2324 : douta <= 16'h62C ; +2325 : douta <= 16'h62C ; +2326 : douta <= 16'h62C ; +2327 : douta <= 16'h52C ; +2328 : douta <= 16'h52C ; +2329 : douta <= 16'h52C ; +2330 : douta <= 16'h52C ; +2331 : douta <= 16'h62C ; +2332 : douta <= 16'h62C ; +2333 : douta <= 16'h62C ; +2334 : douta <= 16'h62C ; +2335 : douta <= 16'h62C ; +2336 : douta <= 16'h62C ; +2337 : douta <= 16'h62C ; +2338 : douta <= 16'h62C ; +2339 : douta <= 16'h62C ; +2340 : douta <= 16'h62C ; +2341 : douta <= 16'h62C ; +2342 : douta <= 16'h62C ; +2343 : douta <= 16'h62C ; +2344 : douta <= 16'h62C ; +2345 : douta <= 16'h62C ; +2346 : douta <= 16'h62C ; +2347 : douta <= 16'h62C ; +2348 : douta <= 16'h62C ; +2349 : douta <= 16'h62C ; +2350 : douta <= 16'h62C ; +2351 : douta <= 16'h62C ; +2352 : douta <= 16'h52C ; +2353 : douta <= 16'h52C ; +2354 : douta <= 16'h52C ; +2355 : douta <= 16'h52C ; +2356 : douta <= 16'h52C ; +2357 : douta <= 16'h52C ; +2358 : douta <= 16'h52C ; +2359 : douta <= 16'h52C ; +2360 : douta <= 16'h52C ; +2361 : douta <= 16'h52C ; +2362 : douta <= 16'h52C ; +2363 : douta <= 16'h52C ; +2364 : douta <= 16'h52C ; +2365 : douta <= 16'h52C ; +2366 : douta <= 16'h42C ; +2367 : douta <= 16'h42C ; +2368 : douta <= 16'h42C ; +2369 : douta <= 16'h42C ; +2370 : douta <= 16'h52C ; +2371 : douta <= 16'h52C ; +2372 : douta <= 16'h52C ; +2373 : douta <= 16'h52C ; +2374 : douta <= 16'h52C ; +2375 : douta <= 16'h52C ; +2376 : douta <= 16'h52C ; +2377 : douta <= 16'h52C ; +2378 : douta <= 16'h52C ; +2379 : douta <= 16'h52C ; +2380 : douta <= 16'h52C ; +2381 : douta <= 16'h52C ; +2382 : douta <= 16'h52C ; +2383 : douta <= 16'h42C ; +2384 : douta <= 16'h42C ; +2385 : douta <= 16'h42C ; +2386 : douta <= 16'h42C ; +2387 : douta <= 16'h42C ; +2388 : douta <= 16'h42C ; +2389 : douta <= 16'h42C ; +2390 : douta <= 16'h42C ; +2391 : douta <= 16'h42C ; +2392 : douta <= 16'h42C ; +2393 : douta <= 16'h42C ; +2394 : douta <= 16'h42C ; +2395 : douta <= 16'h42C ; +2396 : douta <= 16'h42C ; +2397 : douta <= 16'h42C ; +2398 : douta <= 16'h42C ; +2399 : douta <= 16'h42C ; +2400 : douta <= 16'h42C ; +2401 : douta <= 16'h22C ; +2402 : douta <= 16'h42C ; +2403 : douta <= 16'h42C ; +2404 : douta <= 16'h42C ; +2405 : douta <= 16'h42C ; +2406 : douta <= 16'h42C ; +2407 : douta <= 16'h42C ; +2408 : douta <= 16'h42C ; +2409 : douta <= 16'h42C ; +2410 : douta <= 16'h42C ; +2411 : douta <= 16'h42C ; +2412 : douta <= 16'h42C ; +2413 : douta <= 16'h32C ; +2414 : douta <= 16'h32C ; +2415 : douta <= 16'h32C ; +2416 : douta <= 16'h32C ; +2417 : douta <= 16'h32C ; +2418 : douta <= 16'h32C ; +2419 : douta <= 16'h32C ; +2420 : douta <= 16'h32C ; +2421 : douta <= 16'h32C ; +2422 : douta <= 16'h32C ; +2423 : douta <= 16'h22C ; +2424 : douta <= 16'h22C ; +2425 : douta <= 16'h22C ; +2426 : douta <= 16'h22C ; +2427 : douta <= 16'h22C ; +2428 : douta <= 16'h12C ; +2429 : douta <= 16'h22C ; +2430 : douta <= 16'h22C ; +2431 : douta <= 16'h22C ; +2432 : douta <= 16'h22C ; +2433 : douta <= 16'h22C ; +2434 : douta <= 16'h22C ; +2435 : douta <= 16'h22C ; +2436 : douta <= 16'h22C ; +2437 : douta <= 16'h22C ; +2438 : douta <= 16'h22C ; +2439 : douta <= 16'h22C ; +2440 : douta <= 16'h22C ; +2441 : douta <= 16'h22C ; +2442 : douta <= 16'h22C ; +2443 : douta <= 16'h22C ; +2444 : douta <= 16'h22C ; +2445 : douta <= 16'h22C ; +2446 : douta <= 16'h22C ; +2447 : douta <= 16'h22C ; +2448 : douta <= 16'h12C ; +2449 : douta <= 16'h12C ; +2450 : douta <= 16'h12C ; +2451 : douta <= 16'h12C ; +2452 : douta <= 16'h12C ; +2453 : douta <= 16'h12C ; +2454 : douta <= 16'h12C ; +2455 : douta <= 16'h12C ; +2456 : douta <= 16'h12C ; +2457 : douta <= 16'h12C ; +2458 : douta <= 16'h12C ; +2459 : douta <= 16'h12C ; +2460 : douta <= 16'h12C ; +2461 : douta <= 16'h12C ; +2462 : douta <= 16'h12C ; +2463 : douta <= 16'h02C ; +2464 : douta <= 16'h02C ; +2465 : douta <= 16'h12C ; +2466 : douta <= 16'h02C ; +2467 : douta <= 16'h12C ; +2468 : douta <= 16'h12C ; +2469 : douta <= 16'h12C ; +2470 : douta <= 16'h12C ; +2471 : douta <= 16'h12C ; +2472 : douta <= 16'h12C ; +2473 : douta <= 16'h12C ; +2474 : douta <= 16'h12C ; +2475 : douta <= 16'h12C ; +2476 : douta <= 16'h12C ; +2477 : douta <= 16'h12C ; +2478 : douta <= 16'h12C ; +2479 : douta <= 16'h02C ; +2480 : douta <= 16'h12C ; +2481 : douta <= 16'h02C ; +2482 : douta <= 16'h02C ; +2483 : douta <= 16'h02C ; +2484 : douta <= 16'hD040 ; +2485 : douta <= 16'h02C ; +2486 : douta <= 16'h02C ; +2487 : douta <= 16'h02C ; +2488 : douta <= 16'h02C ; +2489 : douta <= 16'h02C ; +2490 : douta <= 16'h02C ; +2491 : douta <= 16'h02C ; +2492 : douta <= 16'h02C ; +2493 : douta <= 16'hD040 ; +2494 : douta <= 16'h02C ; +2495 : douta <= 16'h02C ; +2496 : douta <= 16'h02C ; +2497 : douta <= 16'h02C ; +2498 : douta <= 16'h02C ; +2499 : douta <= 16'h02C ; +2500 : douta <= 16'h02C ; +2501 : douta <= 16'h02C ; +2502 : douta <= 16'h02C ; +2503 : douta <= 16'h02C ; +2504 : douta <= 16'h02C ; +2505 : douta <= 16'h02C ; +2506 : douta <= 16'h02C ; +2507 : douta <= 16'hCE40 ; +2508 : douta <= 16'h02C ; +2509 : douta <= 16'h02C ; +2510 : douta <= 16'hCE40 ; +2511 : douta <= 16'hCD40 ; +2512 : douta <= 16'hCD40 ; +2513 : douta <= 16'hCD40 ; +2514 : douta <= 16'hCD40 ; +2515 : douta <= 16'hCD40 ; +2516 : douta <= 16'hCD40 ; +2517 : douta <= 16'hCD40 ; +2518 : douta <= 16'hCD40 ; +2519 : douta <= 16'hCD40 ; +2520 : douta <= 16'hCD40 ; +2521 : douta <= 16'hCD40 ; +2522 : douta <= 16'hCC40 ; +2523 : douta <= 16'hCC40 ; +2524 : douta <= 16'hCC40 ; +2525 : douta <= 16'hCD40 ; +2526 : douta <= 16'hCD40 ; +2527 : douta <= 16'hCD40 ; +2528 : douta <= 16'hCD40 ; +2529 : douta <= 16'hCD40 ; +2530 : douta <= 16'hCC40 ; +2531 : douta <= 16'hCB40 ; +2532 : douta <= 16'hCB40 ; +2533 : douta <= 16'hCB40 ; +2534 : douta <= 16'hCB40 ; +2535 : douta <= 16'hCC40 ; +2536 : douta <= 16'hCC40 ; +2537 : douta <= 16'hCC40 ; +2538 : douta <= 16'hCC40 ; +2539 : douta <= 16'hCC40 ; +2540 : douta <= 16'hCC40 ; +2541 : douta <= 16'hCC40 ; +2542 : douta <= 16'hCC40 ; +2543 : douta <= 16'hCC40 ; +2544 : douta <= 16'hCC40 ; +2545 : douta <= 16'hCC40 ; +2546 : douta <= 16'hCC40 ; +2547 : douta <= 16'hCC40 ; +2548 : douta <= 16'hCC40 ; +2549 : douta <= 16'hCC40 ; +2550 : douta <= 16'hCB40 ; +2551 : douta <= 16'hCB40 ; +2552 : douta <= 16'hCB40 ; +2553 : douta <= 16'hCB40 ; +2554 : douta <= 16'hCB40 ; +2555 : douta <= 16'hCB40 ; +2556 : douta <= 16'hCA40 ; +2557 : douta <= 16'hCA40 ; +2558 : douta <= 16'hCA40 ; +2559 : douta <= 16'hCA40 ; +2560 : douta <= 16'hCA40 ; +2561 : douta <= 16'hCA40 ; +2562 : douta <= 16'hCA40 ; +2563 : douta <= 16'hCA40 ; +2564 : douta <= 16'hCA40 ; +2565 : douta <= 16'hCA40 ; +2566 : douta <= 16'hCA40 ; +2567 : douta <= 16'hC940 ; +2568 : douta <= 16'hCA40 ; +2569 : douta <= 16'hCA40 ; +2570 : douta <= 16'hCA40 ; +2571 : douta <= 16'hCA40 ; +2572 : douta <= 16'hCA40 ; +2573 : douta <= 16'hC940 ; +2574 : douta <= 16'hCA40 ; +2575 : douta <= 16'hC940 ; +2576 : douta <= 16'hC940 ; +2577 : douta <= 16'hC940 ; +2578 : douta <= 16'hC940 ; +2579 : douta <= 16'hC940 ; +2580 : douta <= 16'hC940 ; +2581 : douta <= 16'hC940 ; +2582 : douta <= 16'hC940 ; +2583 : douta <= 16'hC940 ; +2584 : douta <= 16'hC940 ; +2585 : douta <= 16'hC940 ; +2586 : douta <= 16'hC940 ; +2587 : douta <= 16'hC940 ; +2588 : douta <= 16'hC940 ; +2589 : douta <= 16'hC840 ; +2590 : douta <= 16'hC940 ; +2591 : douta <= 16'hC940 ; +2592 : douta <= 16'hC840 ; +2593 : douta <= 16'hC840 ; +2594 : douta <= 16'hC940 ; +2595 : douta <= 16'hC940 ; +2596 : douta <= 16'hC940 ; +2597 : douta <= 16'hC940 ; +2598 : douta <= 16'hC840 ; +2599 : douta <= 16'hC840 ; +2600 : douta <= 16'hC840 ; +2601 : douta <= 16'hC840 ; +2602 : douta <= 16'hC840 ; +2603 : douta <= 16'hC840 ; +2604 : douta <= 16'hC840 ; +2605 : douta <= 16'hC840 ; +2606 : douta <= 16'hC840 ; +2607 : douta <= 16'hC840 ; +2608 : douta <= 16'hC740 ; +2609 : douta <= 16'hC740 ; +2610 : douta <= 16'hC740 ; +2611 : douta <= 16'hC840 ; +2612 : douta <= 16'hC840 ; +2613 : douta <= 16'hC840 ; +2614 : douta <= 16'hC840 ; +2615 : douta <= 16'hC840 ; +2616 : douta <= 16'hC840 ; +2617 : douta <= 16'hC640 ; +2618 : douta <= 16'hC640 ; +2619 : douta <= 16'hC640 ; +2620 : douta <= 16'hC640 ; +2621 : douta <= 16'hC640 ; +2622 : douta <= 16'hC640 ; +2623 : douta <= 16'hC640 ; +2624 : douta <= 16'hC640 ; +2625 : douta <= 16'hC640 ; +2626 : douta <= 16'hC640 ; +2627 : douta <= 16'hC640 ; +2628 : douta <= 16'hC540 ; +2629 : douta <= 16'hC540 ; +2630 : douta <= 16'hC640 ; +2631 : douta <= 16'hC640 ; +2632 : douta <= 16'hC640 ; +2633 : douta <= 16'hC640 ; +2634 : douta <= 16'hC640 ; +2635 : douta <= 16'hC540 ; +2636 : douta <= 16'hC640 ; +2637 : douta <= 16'hC640 ; +2638 : douta <= 16'hC540 ; +2639 : douta <= 16'hC540 ; +2640 : douta <= 16'hC540 ; +2641 : douta <= 16'hC540 ; +2642 : douta <= 16'hC540 ; +2643 : douta <= 16'hC540 ; +2644 : douta <= 16'hC540 ; +2645 : douta <= 16'hC540 ; +2646 : douta <= 16'hC540 ; +2647 : douta <= 16'hC540 ; +2648 : douta <= 16'hC540 ; +2649 : douta <= 16'hC540 ; +2650 : douta <= 16'hC540 ; +2651 : douta <= 16'hC540 ; +2652 : douta <= 16'hC440 ; +2653 : douta <= 16'hC440 ; +2654 : douta <= 16'hC440 ; +2655 : douta <= 16'hC540 ; +2656 : douta <= 16'hC540 ; +2657 : douta <= 16'hC540 ; +2658 : douta <= 16'hC540 ; +2659 : douta <= 16'hC540 ; +2660 : douta <= 16'hC540 ; +2661 : douta <= 16'hC440 ; +2662 : douta <= 16'hC440 ; +2663 : douta <= 16'hC440 ; +2664 : douta <= 16'hC440 ; +2665 : douta <= 16'hC440 ; +2666 : douta <= 16'hC440 ; +2667 : douta <= 16'hC440 ; +2668 : douta <= 16'hC340 ; +2669 : douta <= 16'hC340 ; +2670 : douta <= 16'hC340 ; +2671 : douta <= 16'hC440 ; +2672 : douta <= 16'hC440 ; +2673 : douta <= 16'hC440 ; +2674 : douta <= 16'hC440 ; +2675 : douta <= 16'hC440 ; +2676 : douta <= 16'hC440 ; +2677 : douta <= 16'hC440 ; +2678 : douta <= 16'hC440 ; +2679 : douta <= 16'hC440 ; +2680 : douta <= 16'hC340 ; +2681 : douta <= 16'hC340 ; +2682 : douta <= 16'hC340 ; +2683 : douta <= 16'hC340 ; +2684 : douta <= 16'hC340 ; +2685 : douta <= 16'hC340 ; +2686 : douta <= 16'hC340 ; +2687 : douta <= 16'hC340 ; +2688 : douta <= 16'hC240 ; +2689 : douta <= 16'hC240 ; +2690 : douta <= 16'hC240 ; +2691 : douta <= 16'hC240 ; +2692 : douta <= 16'hC240 ; +2693 : douta <= 16'hC240 ; +2694 : douta <= 16'hC240 ; +2695 : douta <= 16'hC240 ; +2696 : douta <= 16'hC140 ; +2697 : douta <= 16'hC240 ; +2698 : douta <= 16'hC240 ; +2699 : douta <= 16'hC240 ; +2700 : douta <= 16'hC240 ; +2701 : douta <= 16'hC240 ; +2702 : douta <= 16'hC240 ; +2703 : douta <= 16'hC240 ; +2704 : douta <= 16'hC240 ; +2705 : douta <= 16'hC140 ; +2706 : douta <= 16'hC240 ; +2707 : douta <= 16'hC140 ; +2708 : douta <= 16'hC140 ; +2709 : douta <= 16'hC140 ; +2710 : douta <= 16'hC140 ; +2711 : douta <= 16'hC140 ; +2712 : douta <= 16'hC140 ; +2713 : douta <= 16'hC140 ; +2714 : douta <= 16'hC140 ; +2715 : douta <= 16'hC140 ; +2716 : douta <= 16'hC140 ; +2717 : douta <= 16'hC140 ; +2718 : douta <= 16'hC140 ; +2719 : douta <= 16'hC140 ; +2720 : douta <= 16'hC140 ; +2721 : douta <= 16'hC140 ; +2722 : douta <= 16'hC140 ; +2723 : douta <= 16'hC040 ; +2724 : douta <= 16'hC040 ; +2725 : douta <= 16'hC040 ; +2726 : douta <= 16'hC140 ; +2727 : douta <= 16'hC140 ; +2728 : douta <= 16'hC140 ; +2729 : douta <= 16'hC140 ; +2730 : douta <= 16'hC040 ; +2731 : douta <= 16'hC040 ; +2732 : douta <= 16'hC040 ; +2733 : douta <= 16'hC040 ; +2734 : douta <= 16'hC040 ; +2735 : douta <= 16'hC040 ; +2736 : douta <= 16'hC040 ; +2737 : douta <= 16'hC040 ; +2738 : douta <= 16'hC040 ; +2739 : douta <= 16'hC040 ; +2740 : douta <= 16'hC040 ; +2741 : douta <= 16'hC040 ; +2742 : douta <= 16'hC040 ; +2743 : douta <= 16'hC040 ; +2744 : douta <= 16'hBF40 ; +2745 : douta <= 16'hC040 ; +2746 : douta <= 16'hC040 ; +2747 : douta <= 16'hC040 ; +2748 : douta <= 16'hC040 ; +2749 : douta <= 16'hC040 ; +2750 : douta <= 16'hC040 ; +2751 : douta <= 16'hC040 ; +2752 : douta <= 16'hC040 ; +2753 : douta <= 16'hC040 ; +2754 : douta <= 16'hBE40 ; +2755 : douta <= 16'hBE40 ; +2756 : douta <= 16'hBE40 ; +2757 : douta <= 16'hBE40 ; +2758 : douta <= 16'hBE40 ; +2759 : douta <= 16'hBE40 ; +2760 : douta <= 16'hBE40 ; +2761 : douta <= 16'hBE40 ; +2762 : douta <= 16'hBE40 ; +2763 : douta <= 16'hBE40 ; +2764 : douta <= 16'hBE40 ; +2765 : douta <= 16'hBE40 ; +2766 : douta <= 16'hBE40 ; +2767 : douta <= 16'hBE40 ; +2768 : douta <= 16'hBD40 ; +2769 : douta <= 16'hBD40 ; +2770 : douta <= 16'hBE40 ; +2771 : douta <= 16'hBE40 ; +2772 : douta <= 16'hBE40 ; +2773 : douta <= 16'hBE40 ; +2774 : douta <= 16'hBE40 ; +2775 : douta <= 16'hBE40 ; +2776 : douta <= 16'hBE40 ; +2777 : douta <= 16'hBE40 ; +2778 : douta <= 16'hBD40 ; +2779 : douta <= 16'hBD40 ; +2780 : douta <= 16'hBD40 ; +2781 : douta <= 16'hBD40 ; +2782 : douta <= 16'hBD40 ; +2783 : douta <= 16'hBD40 ; +2784 : douta <= 16'hBD40 ; +2785 : douta <= 16'hBD40 ; +2786 : douta <= 16'hBD40 ; +2787 : douta <= 16'hBD40 ; +2788 : douta <= 16'hBD40 ; +2789 : douta <= 16'hBD40 ; +2790 : douta <= 16'hBD40 ; +2791 : douta <= 16'hBD40 ; +2792 : douta <= 16'hBC40 ; +2793 : douta <= 16'hBC40 ; +2794 : douta <= 16'hBC40 ; +2795 : douta <= 16'hBD40 ; +2796 : douta <= 16'hBC40 ; +2797 : douta <= 16'hBC40 ; +2798 : douta <= 16'hBC40 ; +2799 : douta <= 16'hBC40 ; +2800 : douta <= 16'hBB40 ; +2801 : douta <= 16'hBC40 ; +2802 : douta <= 16'hBB40 ; +2803 : douta <= 16'hBC40 ; +2804 : douta <= 16'hBC40 ; +2805 : douta <= 16'hBC40 ; +2806 : douta <= 16'hBC40 ; +2807 : douta <= 16'hBC40 ; +2808 : douta <= 16'hBC40 ; +2809 : douta <= 16'hBC40 ; +2810 : douta <= 16'hBC40 ; +2811 : douta <= 16'hBC40 ; +2812 : douta <= 16'hBC40 ; +2813 : douta <= 16'hBC40 ; +2814 : douta <= 16'hBC40 ; +2815 : douta <= 16'hBC40 ; +2816 : douta <= 16'hBC40 ; +2817 : douta <= 16'hBC40 ; +2818 : douta <= 16'hBC40 ; +2819 : douta <= 16'hBC40 ; +2820 : douta <= 16'hBB40 ; +2821 : douta <= 16'hBA40 ; +2822 : douta <= 16'hBA40 ; +2823 : douta <= 16'hBA40 ; +2824 : douta <= 16'hBA40 ; +2825 : douta <= 16'hBA40 ; +2826 : douta <= 16'hBA40 ; +2827 : douta <= 16'hBA40 ; +2828 : douta <= 16'hBA40 ; +2829 : douta <= 16'hBA40 ; +2830 : douta <= 16'hBA40 ; +2831 : douta <= 16'hBA40 ; +2832 : douta <= 16'hBA40 ; +2833 : douta <= 16'hBA40 ; +2834 : douta <= 16'hBA40 ; +2835 : douta <= 16'hB940 ; +2836 : douta <= 16'hB940 ; +2837 : douta <= 16'hBA40 ; +2838 : douta <= 16'hBA40 ; +2839 : douta <= 16'hBA40 ; +2840 : douta <= 16'hBA40 ; +2841 : douta <= 16'hB940 ; +2842 : douta <= 16'hB940 ; +2843 : douta <= 16'hB940 ; +2844 : douta <= 16'hB940 ; +2845 : douta <= 16'hB940 ; +2846 : douta <= 16'hB940 ; +2847 : douta <= 16'hB940 ; +2848 : douta <= 16'hB940 ; +2849 : douta <= 16'hB940 ; +2850 : douta <= 16'hB940 ; +2851 : douta <= 16'hB940 ; +2852 : douta <= 16'hB940 ; +2853 : douta <= 16'hB940 ; +2854 : douta <= 16'hB940 ; +2855 : douta <= 16'hB940 ; +2856 : douta <= 16'hB940 ; +2857 : douta <= 16'hB940 ; +2858 : douta <= 16'hB840 ; +2859 : douta <= 16'hB940 ; +2860 : douta <= 16'hB840 ; +2861 : douta <= 16'hB840 ; +2862 : douta <= 16'hB840 ; +2863 : douta <= 16'hB840 ; +2864 : douta <= 16'hB840 ; +2865 : douta <= 16'hB840 ; +2866 : douta <= 16'hB740 ; +2867 : douta <= 16'hB740 ; +2868 : douta <= 16'hB740 ; +2869 : douta <= 16'hB740 ; +2870 : douta <= 16'hB740 ; +2871 : douta <= 16'hB740 ; +2872 : douta <= 16'hB840 ; +2873 : douta <= 16'hB840 ; +2874 : douta <= 16'hB840 ; +2875 : douta <= 16'hB840 ; +2876 : douta <= 16'hB840 ; +2877 : douta <= 16'hB840 ; +2878 : douta <= 16'hB840 ; +2879 : douta <= 16'hB840 ; +2880 : douta <= 16'hB840 ; +2881 : douta <= 16'hB840 ; +2882 : douta <= 16'hB840 ; +2883 : douta <= 16'hB840 ; +2884 : douta <= 16'hB840 ; +2885 : douta <= 16'hB840 ; +2886 : douta <= 16'hB640 ; +2887 : douta <= 16'hB640 ; +2888 : douta <= 16'hB640 ; +2889 : douta <= 16'hB640 ; +2890 : douta <= 16'hB640 ; +2891 : douta <= 16'hB640 ; +2892 : douta <= 16'hB640 ; +2893 : douta <= 16'hB640 ; +2894 : douta <= 16'hB640 ; +2895 : douta <= 16'hB640 ; +2896 : douta <= 16'hB640 ; +2897 : douta <= 16'hB640 ; +2898 : douta <= 16'hB640 ; +2899 : douta <= 16'hB640 ; +2900 : douta <= 16'hB540 ; +2901 : douta <= 16'hB540 ; +2902 : douta <= 16'hB540 ; +2903 : douta <= 16'hB640 ; +2904 : douta <= 16'hB540 ; +2905 : douta <= 16'hB640 ; +2906 : douta <= 16'hB640 ; +2907 : douta <= 16'hB640 ; +2908 : douta <= 16'hB640 ; +2909 : douta <= 16'hB540 ; +2910 : douta <= 16'hB640 ; +2911 : douta <= 16'hB540 ; +2912 : douta <= 16'hB540 ; +2913 : douta <= 16'hB540 ; +2914 : douta <= 16'hB540 ; +2915 : douta <= 16'hB540 ; +2916 : douta <= 16'hB540 ; +2917 : douta <= 16'hB540 ; +2918 : douta <= 16'hB540 ; +2919 : douta <= 16'hB540 ; +2920 : douta <= 16'hB540 ; +2921 : douta <= 16'hB540 ; +2922 : douta <= 16'hB540 ; +2923 : douta <= 16'hB540 ; +2924 : douta <= 16'hB540 ; +2925 : douta <= 16'hB540 ; +2926 : douta <= 16'hB440 ; +2927 : douta <= 16'hB440 ; +2928 : douta <= 16'hB540 ; +2929 : douta <= 16'hB540 ; +2930 : douta <= 16'hB440 ; +2931 : douta <= 16'hB440 ; +2932 : douta <= 16'hB440 ; +2933 : douta <= 16'hB440 ; +2934 : douta <= 16'hB440 ; +2935 : douta <= 16'hB440 ; +2936 : douta <= 16'hB440 ; +2937 : douta <= 16'hB340 ; +2938 : douta <= 16'hB340 ; +2939 : douta <= 16'hB440 ; +2940 : douta <= 16'hB340 ; +2941 : douta <= 16'hB440 ; +2942 : douta <= 16'hB440 ; +2943 : douta <= 16'hB440 ; +2944 : douta <= 16'hB440 ; +2945 : douta <= 16'hB440 ; +2946 : douta <= 16'hB440 ; +2947 : douta <= 16'hB440 ; +2948 : douta <= 16'hB440 ; +2949 : douta <= 16'hB440 ; +2950 : douta <= 16'hB440 ; +2951 : douta <= 16'hB440 ; +2952 : douta <= 16'hB440 ; +2953 : douta <= 16'hB440 ; +2954 : douta <= 16'hB340 ; +2955 : douta <= 16'hB240 ; +2956 : douta <= 16'hB240 ; +2957 : douta <= 16'hB240 ; +2958 : douta <= 16'hB240 ; +2959 : douta <= 16'hB240 ; +2960 : douta <= 16'hB240 ; +2961 : douta <= 16'hB240 ; +2962 : douta <= 16'hB240 ; +2963 : douta <= 16'hB240 ; +2964 : douta <= 16'hB240 ; +2965 : douta <= 16'hB240 ; +2966 : douta <= 16'hB240 ; +2967 : douta <= 16'hB240 ; +2968 : douta <= 16'hB240 ; +2969 : douta <= 16'hB240 ; +2970 : douta <= 16'hB140 ; +2971 : douta <= 16'hB140 ; +2972 : douta <= 16'hB140 ; +2973 : douta <= 16'hB140 ; +2974 : douta <= 16'hB140 ; +2975 : douta <= 16'hB240 ; +2976 : douta <= 16'hB240 ; +2977 : douta <= 16'hB240 ; +2978 : douta <= 16'hB240 ; +2979 : douta <= 16'hB140 ; +2980 : douta <= 16'hB140 ; +2981 : douta <= 16'hB140 ; +2982 : douta <= 16'hB140 ; +2983 : douta <= 16'hB140 ; +2984 : douta <= 16'hB140 ; +2985 : douta <= 16'hB140 ; +2986 : douta <= 16'hB140 ; +2987 : douta <= 16'hB140 ; +2988 : douta <= 16'hB140 ; +2989 : douta <= 16'hB140 ; +2990 : douta <= 16'hB140 ; +2991 : douta <= 16'hB140 ; +2992 : douta <= 16'hB140 ; +2993 : douta <= 16'hB140 ; +2994 : douta <= 16'hB040 ; +2995 : douta <= 16'hB040 ; +2996 : douta <= 16'hB140 ; +2997 : douta <= 16'hB140 ; +2998 : douta <= 16'hB040 ; +2999 : douta <= 16'hB040 ; +3000 : douta <= 16'hB040 ; +3001 : douta <= 16'hB040 ; +3002 : douta <= 16'hB040 ; +3003 : douta <= 16'hB040 ; +3004 : douta <= 16'hB040 ; +3005 : douta <= 16'hB040 ; +3006 : douta <= 16'hB040 ; +3007 : douta <= 16'hB040 ; +3008 : douta <= 16'hB040 ; +3009 : douta <= 16'hB040 ; +3010 : douta <= 16'hB040 ; +3011 : douta <= 16'hB040 ; +3012 : douta <= 16'hB040 ; +3013 : douta <= 16'hB040 ; +3014 : douta <= 16'hB040 ; +3015 : douta <= 16'hB040 ; +3016 : douta <= 16'hB040 ; +3017 : douta <= 16'hB040 ; +3018 : douta <= 16'hB040 ; +3019 : douta <= 16'hB040 ; +3020 : douta <= 16'hB040 ; +3021 : douta <= 16'hB040 ; +3022 : douta <= 16'hB040 ; +3023 : douta <= 16'hB040 ; +3024 : douta <= 16'hB040 ; +3025 : douta <= 16'hAE40 ; +3026 : douta <= 16'hAE40 ; +3027 : douta <= 16'hAE40 ; +3028 : douta <= 16'hAE40 ; +3029 : douta <= 16'hAE40 ; +3030 : douta <= 16'hAE40 ; +3031 : douta <= 16'hAE40 ; +3032 : douta <= 16'hAE40 ; +3033 : douta <= 16'hAE40 ; +3034 : douta <= 16'hAE40 ; +3035 : douta <= 16'hAE40 ; +3036 : douta <= 16'hAD40 ; +3037 : douta <= 16'hAD40 ; +3038 : douta <= 16'hAD40 ; +3039 : douta <= 16'hAE40 ; +3040 : douta <= 16'hAE40 ; +3041 : douta <= 16'hAE40 ; +3042 : douta <= 16'hAE40 ; +3043 : douta <= 16'hAD40 ; +3044 : douta <= 16'hAE40 ; +3045 : douta <= 16'hAD40 ; +3046 : douta <= 16'hAD40 ; +3047 : douta <= 16'hAD40 ; +3048 : douta <= 16'hAD40 ; +3049 : douta <= 16'hAD40 ; +3050 : douta <= 16'hAD40 ; +3051 : douta <= 16'hAD40 ; +3052 : douta <= 16'hAD40 ; +3053 : douta <= 16'hAD40 ; +3054 : douta <= 16'hAD40 ; +3055 : douta <= 16'hAD40 ; +3056 : douta <= 16'hAD40 ; +3057 : douta <= 16'hAD40 ; +3058 : douta <= 16'hAD40 ; +3059 : douta <= 16'hAD40 ; +3060 : douta <= 16'hAC40 ; +3061 : douta <= 16'hAC40 ; +3062 : douta <= 16'hAC40 ; +3063 : douta <= 16'hAD40 ; +3064 : douta <= 16'hAC40 ; +3065 : douta <= 16'hAC40 ; +3066 : douta <= 16'hAC40 ; +3067 : douta <= 16'hAC40 ; +3068 : douta <= 16'hAC40 ; +3069 : douta <= 16'hAB40 ; +3070 : douta <= 16'hAB40 ; +3071 : douta <= 16'hAB40 ; +3072 : douta <= 16'hAB40 ; +3073 : douta <= 16'hAC40 ; +3074 : douta <= 16'hAB40 ; +3075 : douta <= 16'hAC40 ; +3076 : douta <= 16'hAC40 ; +3077 : douta <= 16'hAC40 ; +3078 : douta <= 16'hAC40 ; +3079 : douta <= 16'hAC40 ; +3080 : douta <= 16'hAC40 ; +3081 : douta <= 16'hAC40 ; +3082 : douta <= 16'hAC40 ; +3083 : douta <= 16'hAC40 ; +3084 : douta <= 16'hAC40 ; +3085 : douta <= 16'hAC40 ; +3086 : douta <= 16'hAC40 ; +3087 : douta <= 16'hAC40 ; +3088 : douta <= 16'hAC40 ; +3089 : douta <= 16'hAC40 ; +3090 : douta <= 16'hAA40 ; +3091 : douta <= 16'hAA40 ; +3092 : douta <= 16'hAA40 ; +3093 : douta <= 16'hAA40 ; +3094 : douta <= 16'hAA40 ; +3095 : douta <= 16'hAA40 ; +3096 : douta <= 16'hAA40 ; +3097 : douta <= 16'hAA40 ; +3098 : douta <= 16'hAA40 ; +3099 : douta <= 16'hAA40 ; +3100 : douta <= 16'hAA40 ; +3101 : douta <= 16'hAA40 ; +3102 : douta <= 16'hAA40 ; +3103 : douta <= 16'hAA40 ; +3104 : douta <= 16'hAA40 ; +3105 : douta <= 16'hAA40 ; +3106 : douta <= 16'hA940 ; +3107 : douta <= 16'hA940 ; +3108 : douta <= 16'hA940 ; +3109 : douta <= 16'hAA40 ; +3110 : douta <= 16'hAA40 ; +3111 : douta <= 16'hAA40 ; +3112 : douta <= 16'hA940 ; +3113 : douta <= 16'hA940 ; +3114 : douta <= 16'hA940 ; +3115 : douta <= 16'hA940 ; +3116 : douta <= 16'hA940 ; +3117 : douta <= 16'hA940 ; +3118 : douta <= 16'hA940 ; +3119 : douta <= 16'hA940 ; +3120 : douta <= 16'hA940 ; +3121 : douta <= 16'hA940 ; +3122 : douta <= 16'hA940 ; +3123 : douta <= 16'hA940 ; +3124 : douta <= 16'hA940 ; +3125 : douta <= 16'hA940 ; +3126 : douta <= 16'hA940 ; +3127 : douta <= 16'hA940 ; +3128 : douta <= 16'hA840 ; +3129 : douta <= 16'hA940 ; +3130 : douta <= 16'hA840 ; +3131 : douta <= 16'hA940 ; +3132 : douta <= 16'hA840 ; +3133 : douta <= 16'hA840 ; +3134 : douta <= 16'hA840 ; +3135 : douta <= 16'hA840 ; +3136 : douta <= 16'hA840 ; +3137 : douta <= 16'hA840 ; +3138 : douta <= 16'hA840 ; +3139 : douta <= 16'hA840 ; +3140 : douta <= 16'hA840 ; +3141 : douta <= 16'hA840 ; +3142 : douta <= 16'hA840 ; +3143 : douta <= 16'hA840 ; +3144 : douta <= 16'hA840 ; +3145 : douta <= 16'hA840 ; +3146 : douta <= 16'hA840 ; +3147 : douta <= 16'hA840 ; +3148 : douta <= 16'hA840 ; +3149 : douta <= 16'hA840 ; +3150 : douta <= 16'hA840 ; +3151 : douta <= 16'hA840 ; +3152 : douta <= 16'hA840 ; +3153 : douta <= 16'hA840 ; +3154 : douta <= 16'hA840 ; +3155 : douta <= 16'hA840 ; +3156 : douta <= 16'hA840 ; +3157 : douta <= 16'hA640 ; +3158 : douta <= 16'hA840 ; +3159 : douta <= 16'hA840 ; +3160 : douta <= 16'hA640 ; +3161 : douta <= 16'hA640 ; +3162 : douta <= 16'hA640 ; +3163 : douta <= 16'hA640 ; +3164 : douta <= 16'hA640 ; +3165 : douta <= 16'hA640 ; +3166 : douta <= 16'hA640 ; +3167 : douta <= 16'hA640 ; +3168 : douta <= 16'hA640 ; +3169 : douta <= 16'hA640 ; +3170 : douta <= 16'hA640 ; +3171 : douta <= 16'hA640 ; +3172 : douta <= 16'hA640 ; +3173 : douta <= 16'hA640 ; +3174 : douta <= 16'hA640 ; +3175 : douta <= 16'hA640 ; +3176 : douta <= 16'hA540 ; +3177 : douta <= 16'hA640 ; +3178 : douta <= 16'hA640 ; +3179 : douta <= 16'hA640 ; +3180 : douta <= 16'hA640 ; +3181 : douta <= 16'hA640 ; +3182 : douta <= 16'hA640 ; +3183 : douta <= 16'hA540 ; +3184 : douta <= 16'hA540 ; +3185 : douta <= 16'hA540 ; +3186 : douta <= 16'hA540 ; +3187 : douta <= 16'hA540 ; +3188 : douta <= 16'hA540 ; +3189 : douta <= 16'hA540 ; +3190 : douta <= 16'hA540 ; +3191 : douta <= 16'hA540 ; +3192 : douta <= 16'hA540 ; +3193 : douta <= 16'hA540 ; +3194 : douta <= 16'hA540 ; +3195 : douta <= 16'hA540 ; +3196 : douta <= 16'hA540 ; +3197 : douta <= 16'hA540 ; +3198 : douta <= 16'hA440 ; +3199 : douta <= 16'hA440 ; +3200 : douta <= 16'hA440 ; +3201 : douta <= 16'hA440 ; +3202 : douta <= 16'hA440 ; +3203 : douta <= 16'hA540 ; +3204 : douta <= 16'hA540 ; +3205 : douta <= 16'hA540 ; +3206 : douta <= 16'hA440 ; +3207 : douta <= 16'hA440 ; +3208 : douta <= 16'hA440 ; +3209 : douta <= 16'hA340 ; +3210 : douta <= 16'hA340 ; +3211 : douta <= 16'hA340 ; +3212 : douta <= 16'hA440 ; +3213 : douta <= 16'hA440 ; +3214 : douta <= 16'hA440 ; +3215 : douta <= 16'hA440 ; +3216 : douta <= 16'hA440 ; +3217 : douta <= 16'hA440 ; +3218 : douta <= 16'hA440 ; +3219 : douta <= 16'hA440 ; +3220 : douta <= 16'hA440 ; +3221 : douta <= 16'hA440 ; +3222 : douta <= 16'hA440 ; +3223 : douta <= 16'hA440 ; +3224 : douta <= 16'hA440 ; +3225 : douta <= 16'hA440 ; +3226 : douta <= 16'hA440 ; +3227 : douta <= 16'hA240 ; +3228 : douta <= 16'hA240 ; +3229 : douta <= 16'hA240 ; +3230 : douta <= 16'hA240 ; +3231 : douta <= 16'hA240 ; +3232 : douta <= 16'hA240 ; +3233 : douta <= 16'hA240 ; +3234 : douta <= 16'hA240 ; +3235 : douta <= 16'hA240 ; +3236 : douta <= 16'hA240 ; +3237 : douta <= 16'hA240 ; +3238 : douta <= 16'hA240 ; +3239 : douta <= 16'hA240 ; +3240 : douta <= 16'hA240 ; +3241 : douta <= 16'hA240 ; +3242 : douta <= 16'hA140 ; +3243 : douta <= 16'hA140 ; +3244 : douta <= 16'hA140 ; +3245 : douta <= 16'hA240 ; +3246 : douta <= 16'hA240 ; +3247 : douta <= 16'hA240 ; +3248 : douta <= 16'hA240 ; +3249 : douta <= 16'hA140 ; +3250 : douta <= 16'hA140 ; +3251 : douta <= 16'hA140 ; +3252 : douta <= 16'hA140 ; +3253 : douta <= 16'hA140 ; +3254 : douta <= 16'hA140 ; +3255 : douta <= 16'hA140 ; +3256 : douta <= 16'hA140 ; +3257 : douta <= 16'hA140 ; +3258 : douta <= 16'hA140 ; +3259 : douta <= 16'hA140 ; +3260 : douta <= 16'hA140 ; +3261 : douta <= 16'hA140 ; +3262 : douta <= 16'hA140 ; +3263 : douta <= 16'hA140 ; +3264 : douta <= 16'hA140 ; +3265 : douta <= 16'hA140 ; +3266 : douta <= 16'hA040 ; +3267 : douta <= 16'hA040 ; +3268 : douta <= 16'hA040 ; +3269 : douta <= 16'hA140 ; +3270 : douta <= 16'hA040 ; +3271 : douta <= 16'hA040 ; +3272 : douta <= 16'hA040 ; +3273 : douta <= 16'hA040 ; +3274 : douta <= 16'hA040 ; +3275 : douta <= 16'hA040 ; +3276 : douta <= 16'hA040 ; +3277 : douta <= 16'hA040 ; +3278 : douta <= 16'hA040 ; +3279 : douta <= 16'hA040 ; +3280 : douta <= 16'hA040 ; +3281 : douta <= 16'hA040 ; +3282 : douta <= 16'hA040 ; +3283 : douta <= 16'hA040 ; +3284 : douta <= 16'hA040 ; +3285 : douta <= 16'hA040 ; +3286 : douta <= 16'hA040 ; +3287 : douta <= 16'hA040 ; +3288 : douta <= 16'hA040 ; +3289 : douta <= 16'hA040 ; +3290 : douta <= 16'hA040 ; +3291 : douta <= 16'hA040 ; +3292 : douta <= 16'h9E42 ; +3293 : douta <= 16'hA040 ; +3294 : douta <= 16'hA040 ; +3295 : douta <= 16'hA040 ; +3296 : douta <= 16'hA040 ; +3297 : douta <= 16'hA040 ; +3298 : douta <= 16'hA040 ; +3299 : douta <= 16'hA040 ; +3300 : douta <= 16'hA040 ; +3301 : douta <= 16'hA040 ; +3302 : douta <= 16'h9F42 ; +3303 : douta <= 16'hA040 ; +3304 : douta <= 16'hA040 ; +3305 : douta <= 16'hA040 ; +3306 : douta <= 16'hA040 ; +3307 : douta <= 16'hA040 ; +3308 : douta <= 16'hA040 ; +3309 : douta <= 16'hA040 ; +3310 : douta <= 16'hA040 ; +3311 : douta <= 16'hA040 ; +3312 : douta <= 16'hA040 ; +3313 : douta <= 16'hA040 ; +3314 : douta <= 16'hA040 ; +3315 : douta <= 16'hA040 ; +3316 : douta <= 16'hA040 ; +3317 : douta <= 16'hA040 ; +3318 : douta <= 16'h9F42 ; +3319 : douta <= 16'hA040 ; +3320 : douta <= 16'hA040 ; +3321 : douta <= 16'hA040 ; +3322 : douta <= 16'hA040 ; +3323 : douta <= 16'hA040 ; +3324 : douta <= 16'h9E42 ; +3325 : douta <= 16'h9E42 ; +3326 : douta <= 16'h9E42 ; +3327 : douta <= 16'h9E42 ; +3328 : douta <= 16'h9E42 ; +3329 : douta <= 16'h9E42 ; +3330 : douta <= 16'h9E42 ; +3331 : douta <= 16'h9E42 ; +3332 : douta <= 16'h9E42 ; +3333 : douta <= 16'h9E42 ; +3334 : douta <= 16'h9E42 ; +3335 : douta <= 16'h9E42 ; +3336 : douta <= 16'h9E42 ; +3337 : douta <= 16'h9E42 ; +3338 : douta <= 16'h9E42 ; +3339 : douta <= 16'h9E42 ; +3340 : douta <= 16'h9E42 ; +3341 : douta <= 16'h9D42 ; +3342 : douta <= 16'h9E42 ; +3343 : douta <= 16'h9E42 ; +3344 : douta <= 16'h9E42 ; +3345 : douta <= 16'h9E42 ; +3346 : douta <= 16'h9E42 ; +3347 : douta <= 16'h9D42 ; +3348 : douta <= 16'h9D42 ; +3349 : douta <= 16'h9D42 ; +3350 : douta <= 16'h9D42 ; +3351 : douta <= 16'h9D42 ; +3352 : douta <= 16'h9D42 ; +3353 : douta <= 16'h9D42 ; +3354 : douta <= 16'h9D42 ; +3355 : douta <= 16'h9D42 ; +3356 : douta <= 16'h9D42 ; +3357 : douta <= 16'h9D42 ; +3358 : douta <= 16'h9D42 ; +3359 : douta <= 16'h9D42 ; +3360 : douta <= 16'h9D42 ; +3361 : douta <= 16'h9D42 ; +3362 : douta <= 16'h9D42 ; +3363 : douta <= 16'h9C42 ; +3364 : douta <= 16'h9C42 ; +3365 : douta <= 16'h9D42 ; +3366 : douta <= 16'h9C42 ; +3367 : douta <= 16'h9C42 ; +3368 : douta <= 16'h9C42 ; +3369 : douta <= 16'h9C42 ; +3370 : douta <= 16'h9C42 ; +3371 : douta <= 16'h9C42 ; +3372 : douta <= 16'h9C42 ; +3373 : douta <= 16'h9C42 ; +3374 : douta <= 16'h9C42 ; +3375 : douta <= 16'h9C42 ; +3376 : douta <= 16'h9C42 ; +3377 : douta <= 16'h9C42 ; +3378 : douta <= 16'h9C42 ; +3379 : douta <= 16'h9C42 ; +3380 : douta <= 16'h9B42 ; +3381 : douta <= 16'h9B42 ; +3382 : douta <= 16'h9C42 ; +3383 : douta <= 16'h9C42 ; +3384 : douta <= 16'h9C42 ; +3385 : douta <= 16'h9C42 ; +3386 : douta <= 16'h9C42 ; +3387 : douta <= 16'h9C42 ; +3388 : douta <= 16'h9C42 ; +3389 : douta <= 16'h9C42 ; +3390 : douta <= 16'h9C42 ; +3391 : douta <= 16'h9C42 ; +3392 : douta <= 16'h9C42 ; +3393 : douta <= 16'h9B42 ; +3394 : douta <= 16'h9B42 ; +3395 : douta <= 16'h9B42 ; +3396 : douta <= 16'h9B42 ; +3397 : douta <= 16'h9B42 ; +3398 : douta <= 16'h9A42 ; +3399 : douta <= 16'h9A42 ; +3400 : douta <= 16'h9A42 ; +3401 : douta <= 16'h9A42 ; +3402 : douta <= 16'h9A42 ; +3403 : douta <= 16'h9A42 ; +3404 : douta <= 16'h9A42 ; +3405 : douta <= 16'h9A42 ; +3406 : douta <= 16'h9A42 ; +3407 : douta <= 16'h9A42 ; +3408 : douta <= 16'h9A42 ; +3409 : douta <= 16'h9942 ; +3410 : douta <= 16'h9A42 ; +3411 : douta <= 16'h9A42 ; +3412 : douta <= 16'h9A42 ; +3413 : douta <= 16'h9A42 ; +3414 : douta <= 16'h9A42 ; +3415 : douta <= 16'h9A42 ; +3416 : douta <= 16'h9A42 ; +3417 : douta <= 16'h9A42 ; +3418 : douta <= 16'h9A42 ; +3419 : douta <= 16'h9A42 ; +3420 : douta <= 16'h9942 ; +3421 : douta <= 16'h9942 ; +3422 : douta <= 16'h9942 ; +3423 : douta <= 16'h9942 ; +3424 : douta <= 16'h9942 ; +3425 : douta <= 16'h9942 ; +3426 : douta <= 16'h9942 ; +3427 : douta <= 16'h9942 ; +3428 : douta <= 16'h9942 ; +3429 : douta <= 16'h9942 ; +3430 : douta <= 16'h9942 ; +3431 : douta <= 16'h9942 ; +3432 : douta <= 16'h9942 ; +3433 : douta <= 16'h9942 ; +3434 : douta <= 16'h9942 ; +3435 : douta <= 16'h9942 ; +3436 : douta <= 16'h9942 ; +3437 : douta <= 16'h9942 ; +3438 : douta <= 16'h9942 ; +3439 : douta <= 16'h9842 ; +3440 : douta <= 16'h9842 ; +3441 : douta <= 16'h9942 ; +3442 : douta <= 16'h9842 ; +3443 : douta <= 16'h9842 ; +3444 : douta <= 16'h9842 ; +3445 : douta <= 16'h9842 ; +3446 : douta <= 16'h9842 ; +3447 : douta <= 16'h9842 ; +3448 : douta <= 16'h9842 ; +3449 : douta <= 16'h9842 ; +3450 : douta <= 16'h9842 ; +3451 : douta <= 16'h9842 ; +3452 : douta <= 16'h9842 ; +3453 : douta <= 16'h9842 ; +3454 : douta <= 16'h9842 ; +3455 : douta <= 16'h9842 ; +3456 : douta <= 16'h9842 ; +3457 : douta <= 16'h9842 ; +3458 : douta <= 16'h9842 ; +3459 : douta <= 16'h9742 ; +3460 : douta <= 16'h9742 ; +3461 : douta <= 16'h9842 ; +3462 : douta <= 16'h9842 ; +3463 : douta <= 16'h9842 ; +3464 : douta <= 16'h9842 ; +3465 : douta <= 16'h9842 ; +3466 : douta <= 16'h9842 ; +3467 : douta <= 16'h9842 ; +3468 : douta <= 16'h9642 ; +3469 : douta <= 16'h9642 ; +3470 : douta <= 16'h9642 ; +3471 : douta <= 16'h9642 ; +3472 : douta <= 16'h9642 ; +3473 : douta <= 16'h9642 ; +3474 : douta <= 16'h9642 ; +3475 : douta <= 16'h9642 ; +3476 : douta <= 16'h9642 ; +3477 : douta <= 16'h9642 ; +3478 : douta <= 16'h9642 ; +3479 : douta <= 16'h9642 ; +3480 : douta <= 16'h9642 ; +3481 : douta <= 16'h9642 ; +3482 : douta <= 16'h9642 ; +3483 : douta <= 16'h9642 ; +3484 : douta <= 16'h9542 ; +3485 : douta <= 16'h9542 ; +3486 : douta <= 16'h9542 ; +3487 : douta <= 16'h9642 ; +3488 : douta <= 16'h9642 ; +3489 : douta <= 16'h9642 ; +3490 : douta <= 16'h9642 ; +3491 : douta <= 16'h9642 ; +3492 : douta <= 16'h9642 ; +3493 : douta <= 16'h9542 ; +3494 : douta <= 16'h9542 ; +3495 : douta <= 16'h9542 ; +3496 : douta <= 16'h9542 ; +3497 : douta <= 16'h9542 ; +3498 : douta <= 16'h9542 ; +3499 : douta <= 16'h9542 ; +3500 : douta <= 16'h9542 ; + + + +default:douta<=16'h9542; +endcase + +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/band_rom_b.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/band_rom_b.v new file mode 100644 index 00000000..e8d0539c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/band_rom_b.v @@ -0,0 +1,3573 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 18:19:17 01/25/2022 +// Design Name: +// Module Name: band_rom +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module band_rom_b( +input sysclk, +input [11 : 0] addra, + +output reg[15:0] douta +); + +always@(posedge sysclk)begin + case(addra) + +0 : douta <= 16'h7426 ; +1 : douta <= 16'h7426 ; +2 : douta <= 16'h7426 ; +3 : douta <= 16'h7426 ; +4 : douta <= 16'h7426 ; +5 : douta <= 16'h7326 ; +6 : douta <= 16'h7326 ; +7 : douta <= 16'h7426 ; +8 : douta <= 16'h7426 ; +9 : douta <= 16'h7326 ; +10 : douta <= 16'h7326 ; +11 : douta <= 16'h7326 ; +12 : douta <= 16'h7326 ; +13 : douta <= 16'h7326 ; +14 : douta <= 16'h7326 ; +15 : douta <= 16'h7326 ; +16 : douta <= 16'h7326 ; +17 : douta <= 16'h7226 ; +18 : douta <= 16'h7326 ; +19 : douta <= 16'h7226 ; +20 : douta <= 16'h7226 ; +21 : douta <= 16'h7226 ; +22 : douta <= 16'h7226 ; +23 : douta <= 16'h7126 ; +24 : douta <= 16'h7126 ; +25 : douta <= 16'h7126 ; +26 : douta <= 16'h7226 ; +27 : douta <= 16'h7226 ; +28 : douta <= 16'h7226 ; +29 : douta <= 16'h7226 ; +30 : douta <= 16'h7226 ; +31 : douta <= 16'h7226 ; +32 : douta <= 16'h7226 ; +33 : douta <= 16'h7226 ; +34 : douta <= 16'h7226 ; +35 : douta <= 16'h7226 ; +36 : douta <= 16'h7126 ; +37 : douta <= 16'h7126 ; +38 : douta <= 16'h7126 ; +39 : douta <= 16'h7126 ; +40 : douta <= 16'h7126 ; +41 : douta <= 16'h7126 ; +42 : douta <= 16'h7126 ; +43 : douta <= 16'h7126 ; +44 : douta <= 16'h7126 ; +45 : douta <= 16'h7126 ; +46 : douta <= 16'h7126 ; +47 : douta <= 16'h7126 ; +48 : douta <= 16'h7126 ; +49 : douta <= 16'h7026 ; +50 : douta <= 16'h7026 ; +51 : douta <= 16'h7126 ; +52 : douta <= 16'h7026 ; +53 : douta <= 16'h7126 ; +54 : douta <= 16'h6F26 ; +55 : douta <= 16'h7126 ; +56 : douta <= 16'h7126 ; +57 : douta <= 16'h7126 ; +58 : douta <= 16'h7126 ; +59 : douta <= 16'h7026 ; +60 : douta <= 16'h7126 ; +61 : douta <= 16'h6E26 ; +62 : douta <= 16'h7026 ; +63 : douta <= 16'h6E26 ; +64 : douta <= 16'h7026 ; +65 : douta <= 16'h7026 ; +66 : douta <= 16'h7026 ; +67 : douta <= 16'h7026 ; +68 : douta <= 16'h7026 ; +69 : douta <= 16'h7026 ; +70 : douta <= 16'h7026 ; +71 : douta <= 16'h7026 ; +72 : douta <= 16'h7026 ; +73 : douta <= 16'h7026 ; +74 : douta <= 16'h7026 ; +75 : douta <= 16'h7026 ; +76 : douta <= 16'h7026 ; +77 : douta <= 16'h7026 ; +78 : douta <= 16'h7026 ; +79 : douta <= 16'h7026 ; +80 : douta <= 16'h7026 ; +81 : douta <= 16'h6F26 ; +82 : douta <= 16'h6F26 ; +83 : douta <= 16'h6F26 ; +84 : douta <= 16'h6F26 ; +85 : douta <= 16'h6F26 ; +86 : douta <= 16'h6E26 ; +87 : douta <= 16'h6E26 ; +88 : douta <= 16'h6E26 ; +89 : douta <= 16'h6E26 ; +90 : douta <= 16'h6E26 ; +91 : douta <= 16'h6E26 ; +92 : douta <= 16'h6E26 ; +93 : douta <= 16'h6E26 ; +94 : douta <= 16'h6E26 ; +95 : douta <= 16'h6E26 ; +96 : douta <= 16'h6E26 ; +97 : douta <= 16'h6E26 ; +98 : douta <= 16'h6E26 ; +99 : douta <= 16'h6E26 ; +100 : douta <= 16'h6E26 ; +101 : douta <= 16'h6E26 ; +102 : douta <= 16'h6E26 ; +103 : douta <= 16'h6E26 ; +104 : douta <= 16'h6E26 ; +105 : douta <= 16'h6E26 ; +106 : douta <= 16'h6E26 ; +107 : douta <= 16'h6D26 ; +108 : douta <= 16'h6E26 ; +109 : douta <= 16'h6D26 ; +110 : douta <= 16'h6D26 ; +111 : douta <= 16'h6D26 ; +112 : douta <= 16'h6D26 ; +113 : douta <= 16'h6D26 ; +114 : douta <= 16'h6D26 ; +115 : douta <= 16'h6D26 ; +116 : douta <= 16'h6D26 ; +117 : douta <= 16'h6D26 ; +118 : douta <= 16'h6D26 ; +119 : douta <= 16'h6D26 ; +120 : douta <= 16'h6D26 ; +121 : douta <= 16'h6C26 ; +122 : douta <= 16'h6D26 ; +123 : douta <= 16'h6D26 ; +124 : douta <= 16'h6C26 ; +125 : douta <= 16'h6D26 ; +126 : douta <= 16'h6D26 ; +127 : douta <= 16'h6D26 ; +128 : douta <= 16'h6D26 ; +129 : douta <= 16'h6D26 ; +130 : douta <= 16'h6D26 ; +131 : douta <= 16'h6D26 ; +132 : douta <= 16'h6D26 ; +133 : douta <= 16'h6C26 ; +134 : douta <= 16'h6C26 ; +135 : douta <= 16'h6C26 ; +136 : douta <= 16'h6C26 ; +137 : douta <= 16'h6C26 ; +138 : douta <= 16'h6C26 ; +139 : douta <= 16'h6C26 ; +140 : douta <= 16'h6C26 ; +141 : douta <= 16'h6C26 ; +142 : douta <= 16'h6C26 ; +143 : douta <= 16'h6C26 ; +144 : douta <= 16'h6C26 ; +145 : douta <= 16'h6C26 ; +146 : douta <= 16'h6C26 ; +147 : douta <= 16'h6C26 ; +148 : douta <= 16'h6C26 ; +149 : douta <= 16'h6C26 ; +150 : douta <= 16'h6C26 ; +151 : douta <= 16'h6C26 ; +152 : douta <= 16'h6C26 ; +153 : douta <= 16'h6B26 ; +154 : douta <= 16'h6B26 ; +155 : douta <= 16'h6B26 ; +156 : douta <= 16'h6B26 ; +157 : douta <= 16'h6B26 ; +158 : douta <= 16'h6B26 ; +159 : douta <= 16'h6B26 ; +160 : douta <= 16'h6B26 ; +161 : douta <= 16'h6B26 ; +162 : douta <= 16'h6A26 ; +163 : douta <= 16'h6A26 ; +164 : douta <= 16'h6A26 ; +165 : douta <= 16'h6A26 ; +166 : douta <= 16'h6A26 ; +167 : douta <= 16'h6A26 ; +168 : douta <= 16'h6926 ; +169 : douta <= 16'h6A26 ; +170 : douta <= 16'h6926 ; +171 : douta <= 16'h6A26 ; +172 : douta <= 16'h6926 ; +173 : douta <= 16'h6A26 ; +174 : douta <= 16'h6A26 ; +175 : douta <= 16'h6A26 ; +176 : douta <= 16'h6A26 ; +177 : douta <= 16'h6A26 ; +178 : douta <= 16'h6A26 ; +179 : douta <= 16'h6A26 ; +180 : douta <= 16'h6A26 ; +181 : douta <= 16'h6A26 ; +182 : douta <= 16'h6A26 ; +183 : douta <= 16'h6A26 ; +184 : douta <= 16'h6926 ; +185 : douta <= 16'h6926 ; +186 : douta <= 16'h6926 ; +187 : douta <= 16'h6926 ; +188 : douta <= 16'h6926 ; +189 : douta <= 16'h6926 ; +190 : douta <= 16'h6926 ; +191 : douta <= 16'h6926 ; +192 : douta <= 16'h6926 ; +193 : douta <= 16'h6926 ; +194 : douta <= 16'h6926 ; +195 : douta <= 16'h6826 ; +196 : douta <= 16'h6826 ; +197 : douta <= 16'h6826 ; +198 : douta <= 16'h6826 ; +199 : douta <= 16'h6826 ; +200 : douta <= 16'h6926 ; +201 : douta <= 16'h6926 ; +202 : douta <= 16'h6926 ; +203 : douta <= 16'h6926 ; +204 : douta <= 16'h6926 ; +205 : douta <= 16'h6926 ; +206 : douta <= 16'h6926 ; +207 : douta <= 16'h6926 ; +208 : douta <= 16'h6826 ; +209 : douta <= 16'h6826 ; +210 : douta <= 16'h6826 ; +211 : douta <= 16'h6826 ; +212 : douta <= 16'h6826 ; +213 : douta <= 16'h6826 ; +214 : douta <= 16'h6826 ; +215 : douta <= 16'h6826 ; +216 : douta <= 16'h6826 ; +217 : douta <= 16'h6826 ; +218 : douta <= 16'h6826 ; +219 : douta <= 16'h6726 ; +220 : douta <= 16'h6726 ; +221 : douta <= 16'h6826 ; +222 : douta <= 16'h6826 ; +223 : douta <= 16'h6826 ; +224 : douta <= 16'h6826 ; +225 : douta <= 16'h6826 ; +226 : douta <= 16'h6826 ; +227 : douta <= 16'h6826 ; +228 : douta <= 16'h6826 ; +229 : douta <= 16'h6826 ; +230 : douta <= 16'h6826 ; +231 : douta <= 16'h6826 ; +232 : douta <= 16'h6726 ; +233 : douta <= 16'h6726 ; +234 : douta <= 16'h6526 ; +235 : douta <= 16'h6526 ; +236 : douta <= 16'h6726 ; +237 : douta <= 16'h6726 ; +238 : douta <= 16'h6726 ; +239 : douta <= 16'h6726 ; +240 : douta <= 16'h6726 ; +241 : douta <= 16'h6626 ; +242 : douta <= 16'h6626 ; +243 : douta <= 16'h6626 ; +244 : douta <= 16'h6626 ; +245 : douta <= 16'h6626 ; +246 : douta <= 16'h6626 ; +247 : douta <= 16'h6626 ; +248 : douta <= 16'h6626 ; +249 : douta <= 16'h6626 ; +250 : douta <= 16'h6626 ; +251 : douta <= 16'h6626 ; +252 : douta <= 16'h6626 ; +253 : douta <= 16'h6626 ; +254 : douta <= 16'h6626 ; +255 : douta <= 16'h6626 ; +256 : douta <= 16'h6626 ; +257 : douta <= 16'h6626 ; +258 : douta <= 16'h6626 ; +259 : douta <= 16'h6626 ; +260 : douta <= 16'h6626 ; +261 : douta <= 16'h6626 ; +262 : douta <= 16'h6526 ; +263 : douta <= 16'h6626 ; +264 : douta <= 16'h6526 ; +265 : douta <= 16'h6526 ; +266 : douta <= 16'h6526 ; +267 : douta <= 16'h6526 ; +268 : douta <= 16'h6526 ; +269 : douta <= 16'h6526 ; +270 : douta <= 16'h6526 ; +271 : douta <= 16'h6526 ; +272 : douta <= 16'h6526 ; +273 : douta <= 16'h6526 ; +274 : douta <= 16'h6526 ; +275 : douta <= 16'h6526 ; +276 : douta <= 16'h6526 ; +277 : douta <= 16'h6426 ; +278 : douta <= 16'h6526 ; +279 : douta <= 16'h6526 ; +280 : douta <= 16'h6526 ; +281 : douta <= 16'h6526 ; +282 : douta <= 16'h6526 ; +283 : douta <= 16'h6526 ; +284 : douta <= 16'h6526 ; +285 : douta <= 16'h6526 ; +286 : douta <= 16'h6526 ; +287 : douta <= 16'h6526 ; +288 : douta <= 16'h6426 ; +289 : douta <= 16'h6426 ; +290 : douta <= 16'h6426 ; +291 : douta <= 16'h6426 ; +292 : douta <= 16'h6426 ; +293 : douta <= 16'h6426 ; +294 : douta <= 16'h6426 ; +295 : douta <= 16'h6426 ; +296 : douta <= 16'h6426 ; +297 : douta <= 16'h6426 ; +298 : douta <= 16'h6426 ; +299 : douta <= 16'h6426 ; +300 : douta <= 16'h6426 ; +301 : douta <= 16'h6426 ; +302 : douta <= 16'h6426 ; +303 : douta <= 16'h6426 ; +304 : douta <= 16'h6426 ; +305 : douta <= 16'h6326 ; +306 : douta <= 16'h6426 ; +307 : douta <= 16'h6326 ; +308 : douta <= 16'h6326 ; +309 : douta <= 16'h6326 ; +310 : douta <= 16'h6326 ; +311 : douta <= 16'h6426 ; +312 : douta <= 16'h6426 ; +313 : douta <= 16'h6326 ; +314 : douta <= 16'h6326 ; +315 : douta <= 16'h6326 ; +316 : douta <= 16'h6326 ; +317 : douta <= 16'h6326 ; +318 : douta <= 16'h6326 ; +319 : douta <= 16'h6226 ; +320 : douta <= 16'h6226 ; +321 : douta <= 16'h6226 ; +322 : douta <= 16'h6226 ; +323 : douta <= 16'h6226 ; +324 : douta <= 16'h6126 ; +325 : douta <= 16'h6226 ; +326 : douta <= 16'h6126 ; +327 : douta <= 16'h6126 ; +328 : douta <= 16'h6126 ; +329 : douta <= 16'h6226 ; +330 : douta <= 16'h6226 ; +331 : douta <= 16'h6226 ; +332 : douta <= 16'h6226 ; +333 : douta <= 16'h6226 ; +334 : douta <= 16'h6226 ; +335 : douta <= 16'h6226 ; +336 : douta <= 16'h6226 ; +337 : douta <= 16'h6226 ; +338 : douta <= 16'h6226 ; +339 : douta <= 16'h6226 ; +340 : douta <= 16'h6226 ; +341 : douta <= 16'h6126 ; +342 : douta <= 16'h6126 ; +343 : douta <= 16'h6126 ; +344 : douta <= 16'h6126 ; +345 : douta <= 16'h6126 ; +346 : douta <= 16'h6126 ; +347 : douta <= 16'h6126 ; +348 : douta <= 16'h6126 ; +349 : douta <= 16'h6126 ; +350 : douta <= 16'h6126 ; +351 : douta <= 16'h6126 ; +352 : douta <= 16'h6126 ; +353 : douta <= 16'h6126 ; +354 : douta <= 16'h6126 ; +355 : douta <= 16'h6026 ; +356 : douta <= 16'h6026 ; +357 : douta <= 16'h6126 ; +358 : douta <= 16'h6126 ; +359 : douta <= 16'h6126 ; +360 : douta <= 16'h6126 ; +361 : douta <= 16'h6126 ; +362 : douta <= 16'h6126 ; +363 : douta <= 16'h6126 ; +364 : douta <= 16'h6126 ; +365 : douta <= 16'h6126 ; +366 : douta <= 16'h6126 ; +367 : douta <= 16'h6126 ; +368 : douta <= 16'h6026 ; +369 : douta <= 16'h6026 ; +370 : douta <= 16'h6026 ; +371 : douta <= 16'h6026 ; +372 : douta <= 16'h6026 ; +373 : douta <= 16'h6026 ; +374 : douta <= 16'h6026 ; +375 : douta <= 16'h5F28 ; +376 : douta <= 16'h6026 ; +377 : douta <= 16'h6026 ; +378 : douta <= 16'h6026 ; +379 : douta <= 16'h5F28 ; +380 : douta <= 16'h6026 ; +381 : douta <= 16'h6026 ; +382 : douta <= 16'h6026 ; +383 : douta <= 16'h6026 ; +384 : douta <= 16'h6026 ; +385 : douta <= 16'h6026 ; +386 : douta <= 16'h5F28 ; +387 : douta <= 16'h6026 ; +388 : douta <= 16'h6026 ; +389 : douta <= 16'h6026 ; +390 : douta <= 16'h5E28 ; +391 : douta <= 16'h6026 ; +392 : douta <= 16'h6026 ; +393 : douta <= 16'h6026 ; +394 : douta <= 16'h6026 ; +395 : douta <= 16'h6026 ; +396 : douta <= 16'h6026 ; +397 : douta <= 16'h6026 ; +398 : douta <= 16'h6026 ; +399 : douta <= 16'h6026 ; +400 : douta <= 16'h5E28 ; +401 : douta <= 16'h5E28 ; +402 : douta <= 16'h5E28 ; +403 : douta <= 16'h5E28 ; +404 : douta <= 16'h5E28 ; +405 : douta <= 16'h5E28 ; +406 : douta <= 16'h5E28 ; +407 : douta <= 16'h5E28 ; +408 : douta <= 16'h5E28 ; +409 : douta <= 16'h5E28 ; +410 : douta <= 16'h5E28 ; +411 : douta <= 16'h5D28 ; +412 : douta <= 16'h5D28 ; +413 : douta <= 16'h5D28 ; +414 : douta <= 16'h5D28 ; +415 : douta <= 16'h5D28 ; +416 : douta <= 16'h5D28 ; +417 : douta <= 16'h5D28 ; +418 : douta <= 16'h5D28 ; +419 : douta <= 16'h5D28 ; +420 : douta <= 16'h5D28 ; +421 : douta <= 16'h5D28 ; +422 : douta <= 16'h5D28 ; +423 : douta <= 16'h5D28 ; +424 : douta <= 16'h5D28 ; +425 : douta <= 16'h5C28 ; +426 : douta <= 16'h5C28 ; +427 : douta <= 16'h5D28 ; +428 : douta <= 16'h5D28 ; +429 : douta <= 16'h5B28 ; +430 : douta <= 16'h5B28 ; +431 : douta <= 16'h5D28 ; +432 : douta <= 16'h5D28 ; +433 : douta <= 16'h5C28 ; +434 : douta <= 16'h5C28 ; +435 : douta <= 16'h5C28 ; +436 : douta <= 16'h5C28 ; +437 : douta <= 16'h5C28 ; +438 : douta <= 16'h5C28 ; +439 : douta <= 16'h5C28 ; +440 : douta <= 16'h5C28 ; +441 : douta <= 16'h5C28 ; +442 : douta <= 16'h5C28 ; +443 : douta <= 16'h5C28 ; +444 : douta <= 16'h5C28 ; +445 : douta <= 16'h5C28 ; +446 : douta <= 16'h5C28 ; +447 : douta <= 16'h5C28 ; +448 : douta <= 16'h5C28 ; +449 : douta <= 16'h5C28 ; +450 : douta <= 16'h5C28 ; +451 : douta <= 16'h5C28 ; +452 : douta <= 16'h5C28 ; +453 : douta <= 16'h5C28 ; +454 : douta <= 16'h5C28 ; +455 : douta <= 16'h5B28 ; +456 : douta <= 16'h5C28 ; +457 : douta <= 16'h5C28 ; +458 : douta <= 16'h5B28 ; +459 : douta <= 16'h5B28 ; +460 : douta <= 16'h5B28 ; +461 : douta <= 16'h5B28 ; +462 : douta <= 16'h5B28 ; +463 : douta <= 16'h5B28 ; +464 : douta <= 16'h5B28 ; +465 : douta <= 16'h5B28 ; +466 : douta <= 16'h5B28 ; +467 : douta <= 16'h5A28 ; +468 : douta <= 16'h5A28 ; +469 : douta <= 16'h5A28 ; +470 : douta <= 16'h5A28 ; +471 : douta <= 16'h5A28 ; +472 : douta <= 16'h5A28 ; +473 : douta <= 16'h5A28 ; +474 : douta <= 16'h5A28 ; +475 : douta <= 16'h5A28 ; +476 : douta <= 16'h5A28 ; +477 : douta <= 16'h5A28 ; +478 : douta <= 16'h5A28 ; +479 : douta <= 16'h5A28 ; +480 : douta <= 16'h5A28 ; +481 : douta <= 16'h5A28 ; +482 : douta <= 16'h5A28 ; +483 : douta <= 16'h5A28 ; +484 : douta <= 16'h5A28 ; +485 : douta <= 16'h5A28 ; +486 : douta <= 16'h5A28 ; +487 : douta <= 16'h5A28 ; +488 : douta <= 16'h5A28 ; +489 : douta <= 16'h5928 ; +490 : douta <= 16'h5928 ; +491 : douta <= 16'h5928 ; +492 : douta <= 16'h5928 ; +493 : douta <= 16'h5928 ; +494 : douta <= 16'h5928 ; +495 : douta <= 16'h5928 ; +496 : douta <= 16'h5928 ; +497 : douta <= 16'h5928 ; +498 : douta <= 16'h5928 ; +499 : douta <= 16'h5928 ; +500 : douta <= 16'h5928 ; +501 : douta <= 16'h5928 ; +502 : douta <= 16'h5828 ; +503 : douta <= 16'h5828 ; +504 : douta <= 16'h5828 ; +505 : douta <= 16'h5828 ; +506 : douta <= 16'h5828 ; +507 : douta <= 16'h5928 ; +508 : douta <= 16'h5928 ; +509 : douta <= 16'h5928 ; +510 : douta <= 16'h5928 ; +511 : douta <= 16'h5928 ; +512 : douta <= 16'h5928 ; +513 : douta <= 16'h5928 ; +514 : douta <= 16'h5828 ; +515 : douta <= 16'h5828 ; +516 : douta <= 16'h5828 ; +517 : douta <= 16'h5828 ; +518 : douta <= 16'h5828 ; +519 : douta <= 16'h5828 ; +520 : douta <= 16'h5828 ; +521 : douta <= 16'h5828 ; +522 : douta <= 16'h5828 ; +523 : douta <= 16'h5828 ; +524 : douta <= 16'h5828 ; +525 : douta <= 16'h5828 ; +526 : douta <= 16'h5828 ; +527 : douta <= 16'h5828 ; +528 : douta <= 16'h5828 ; +529 : douta <= 16'h5828 ; +530 : douta <= 16'h5828 ; +531 : douta <= 16'h5828 ; +532 : douta <= 16'h5728 ; +533 : douta <= 16'h5728 ; +534 : douta <= 16'h5728 ; +535 : douta <= 16'h5828 ; +536 : douta <= 16'h5828 ; +537 : douta <= 16'h5728 ; +538 : douta <= 16'h5728 ; +539 : douta <= 16'h5728 ; +540 : douta <= 16'h5728 ; +541 : douta <= 16'h5528 ; +542 : douta <= 16'h5728 ; +543 : douta <= 16'h5528 ; +544 : douta <= 16'h5728 ; +545 : douta <= 16'h5728 ; +546 : douta <= 16'h5728 ; +547 : douta <= 16'h5628 ; +548 : douta <= 16'h5628 ; +549 : douta <= 16'h5628 ; +550 : douta <= 16'h5628 ; +551 : douta <= 16'h5628 ; +552 : douta <= 16'h5628 ; +553 : douta <= 16'h5628 ; +554 : douta <= 16'h5628 ; +555 : douta <= 16'h5628 ; +556 : douta <= 16'h5628 ; +557 : douta <= 16'h5628 ; +558 : douta <= 16'h5628 ; +559 : douta <= 16'h5628 ; +560 : douta <= 16'h5628 ; +561 : douta <= 16'h5628 ; +562 : douta <= 16'h5628 ; +563 : douta <= 16'h5628 ; +564 : douta <= 16'h5628 ; +565 : douta <= 16'h5628 ; +566 : douta <= 16'h5628 ; +567 : douta <= 16'h5628 ; +568 : douta <= 16'h5628 ; +569 : douta <= 16'h5628 ; +570 : douta <= 16'h5628 ; +571 : douta <= 16'h5528 ; +572 : douta <= 16'h5528 ; +573 : douta <= 16'h5528 ; +574 : douta <= 16'h5528 ; +575 : douta <= 16'h5528 ; +576 : douta <= 16'h5528 ; +577 : douta <= 16'h5528 ; +578 : douta <= 16'h5528 ; +579 : douta <= 16'h5528 ; +580 : douta <= 16'h5528 ; +581 : douta <= 16'h5528 ; +582 : douta <= 16'h5528 ; +583 : douta <= 16'h5528 ; +584 : douta <= 16'h5528 ; +585 : douta <= 16'h5528 ; +586 : douta <= 16'h5428 ; +587 : douta <= 16'h5528 ; +588 : douta <= 16'h5528 ; +589 : douta <= 16'h5528 ; +590 : douta <= 16'h5528 ; +591 : douta <= 16'h5528 ; +592 : douta <= 16'h5528 ; +593 : douta <= 16'h5528 ; +594 : douta <= 16'h5528 ; +595 : douta <= 16'h5528 ; +596 : douta <= 16'h5428 ; +597 : douta <= 16'h5428 ; +598 : douta <= 16'h5428 ; +599 : douta <= 16'h5428 ; +600 : douta <= 16'h5428 ; +601 : douta <= 16'h5428 ; +602 : douta <= 16'h5428 ; +603 : douta <= 16'h5428 ; +604 : douta <= 16'h5428 ; +605 : douta <= 16'h5428 ; +606 : douta <= 16'h5428 ; +607 : douta <= 16'h5428 ; +608 : douta <= 16'h5428 ; +609 : douta <= 16'h5428 ; +610 : douta <= 16'h5428 ; +611 : douta <= 16'h5428 ; +612 : douta <= 16'h5428 ; +613 : douta <= 16'h5428 ; +614 : douta <= 16'h5428 ; +615 : douta <= 16'h5428 ; +616 : douta <= 16'h5328 ; +617 : douta <= 16'h5328 ; +618 : douta <= 16'h5328 ; +619 : douta <= 16'h5328 ; +620 : douta <= 16'h5428 ; +621 : douta <= 16'h5328 ; +622 : douta <= 16'h5328 ; +623 : douta <= 16'h5328 ; +624 : douta <= 16'h5328 ; +625 : douta <= 16'h5328 ; +626 : douta <= 16'h5328 ; +627 : douta <= 16'h5328 ; +628 : douta <= 16'h5328 ; +629 : douta <= 16'h5328 ; +630 : douta <= 16'h5328 ; +631 : douta <= 16'h5328 ; +632 : douta <= 16'h5328 ; +633 : douta <= 16'h5328 ; +634 : douta <= 16'h5228 ; +635 : douta <= 16'h5228 ; +636 : douta <= 16'h5128 ; +637 : douta <= 16'h5128 ; +638 : douta <= 16'h5128 ; +639 : douta <= 16'h5228 ; +640 : douta <= 16'h5228 ; +641 : douta <= 16'h5228 ; +642 : douta <= 16'h5228 ; +643 : douta <= 16'h5228 ; +644 : douta <= 16'h5228 ; +645 : douta <= 16'h5228 ; +646 : douta <= 16'h5228 ; +647 : douta <= 16'h5228 ; +648 : douta <= 16'h5228 ; +649 : douta <= 16'h5228 ; +650 : douta <= 16'h5228 ; +651 : douta <= 16'h5228 ; +652 : douta <= 16'h5228 ; +653 : douta <= 16'h5228 ; +654 : douta <= 16'h5228 ; +655 : douta <= 16'h5228 ; +656 : douta <= 16'h5128 ; +657 : douta <= 16'h5128 ; +658 : douta <= 16'h5128 ; +659 : douta <= 16'h5128 ; +660 : douta <= 16'h5128 ; +661 : douta <= 16'h5128 ; +662 : douta <= 16'h5128 ; +663 : douta <= 16'h5128 ; +664 : douta <= 16'h5128 ; +665 : douta <= 16'h5128 ; +666 : douta <= 16'h5128 ; +667 : douta <= 16'h5128 ; +668 : douta <= 16'h5128 ; +669 : douta <= 16'h5128 ; +670 : douta <= 16'h5128 ; +671 : douta <= 16'h5028 ; +672 : douta <= 16'h5028 ; +673 : douta <= 16'h5128 ; +674 : douta <= 16'h5128 ; +675 : douta <= 16'h5128 ; +676 : douta <= 16'h5128 ; +677 : douta <= 16'h5128 ; +678 : douta <= 16'h5128 ; +679 : douta <= 16'h5128 ; +680 : douta <= 16'h5128 ; +681 : douta <= 16'h5128 ; +682 : douta <= 16'h5028 ; +683 : douta <= 16'h5028 ; +684 : douta <= 16'h5028 ; +685 : douta <= 16'h4E28 ; +686 : douta <= 16'h5028 ; +687 : douta <= 16'h5028 ; +688 : douta <= 16'h4F28 ; +689 : douta <= 16'h5028 ; +690 : douta <= 16'h5028 ; +691 : douta <= 16'h5028 ; +692 : douta <= 16'h4F28 ; +693 : douta <= 16'h5028 ; +694 : douta <= 16'h5028 ; +695 : douta <= 16'h5028 ; +696 : douta <= 16'h5028 ; +697 : douta <= 16'h5028 ; +698 : douta <= 16'h5028 ; +699 : douta <= 16'h5028 ; +700 : douta <= 16'h5028 ; +701 : douta <= 16'h5028 ; +702 : douta <= 16'h5028 ; +703 : douta <= 16'h5028 ; +704 : douta <= 16'h5028 ; +705 : douta <= 16'h5028 ; +706 : douta <= 16'h5028 ; +707 : douta <= 16'h5028 ; +708 : douta <= 16'h4D28 ; +709 : douta <= 16'h4D28 ; +710 : douta <= 16'h4E28 ; +711 : douta <= 16'h4E28 ; +712 : douta <= 16'h4E28 ; +713 : douta <= 16'h4E28 ; +714 : douta <= 16'h4E28 ; +715 : douta <= 16'h4E28 ; +716 : douta <= 16'h4E28 ; +717 : douta <= 16'h4E28 ; +718 : douta <= 16'h4E28 ; +719 : douta <= 16'h4E28 ; +720 : douta <= 16'h4E28 ; +721 : douta <= 16'h4E28 ; +722 : douta <= 16'h4E28 ; +723 : douta <= 16'h4E28 ; +724 : douta <= 16'h4E28 ; +725 : douta <= 16'h4E28 ; +726 : douta <= 16'h4E28 ; +727 : douta <= 16'h4E28 ; +728 : douta <= 16'h4E28 ; +729 : douta <= 16'h4E28 ; +730 : douta <= 16'h4E28 ; +731 : douta <= 16'h4E28 ; +732 : douta <= 16'h4E28 ; +733 : douta <= 16'h4E28 ; +734 : douta <= 16'h4D28 ; +735 : douta <= 16'h4D28 ; +736 : douta <= 16'h4D28 ; +737 : douta <= 16'h4D28 ; +738 : douta <= 16'h4D28 ; +739 : douta <= 16'h4D28 ; +740 : douta <= 16'h4D28 ; +741 : douta <= 16'h4D28 ; +742 : douta <= 16'h4D28 ; +743 : douta <= 16'h4D28 ; +744 : douta <= 16'h4D28 ; +745 : douta <= 16'h4D28 ; +746 : douta <= 16'h4D28 ; +747 : douta <= 16'h4C28 ; +748 : douta <= 16'h4C28 ; +749 : douta <= 16'h4D28 ; +750 : douta <= 16'h4D28 ; +751 : douta <= 16'h4D28 ; +752 : douta <= 16'h4D28 ; +753 : douta <= 16'h4D28 ; +754 : douta <= 16'h4D28 ; +755 : douta <= 16'h4D28 ; +756 : douta <= 16'h4D28 ; +757 : douta <= 16'h4D28 ; +758 : douta <= 16'h4D28 ; +759 : douta <= 16'h4D28 ; +760 : douta <= 16'h4B28 ; +761 : douta <= 16'h4B28 ; +762 : douta <= 16'h4C28 ; +763 : douta <= 16'h4C28 ; +764 : douta <= 16'h4C28 ; +765 : douta <= 16'h4C28 ; +766 : douta <= 16'h4C28 ; +767 : douta <= 16'h4C28 ; +768 : douta <= 16'h4C28 ; +769 : douta <= 16'h4C28 ; +770 : douta <= 16'h4C28 ; +771 : douta <= 16'h4C28 ; +772 : douta <= 16'h4C28 ; +773 : douta <= 16'h4C28 ; +774 : douta <= 16'h4C28 ; +775 : douta <= 16'h4C28 ; +776 : douta <= 16'h4C28 ; +777 : douta <= 16'h4C28 ; +778 : douta <= 16'h4C28 ; +779 : douta <= 16'h4C28 ; +780 : douta <= 16'h4C28 ; +781 : douta <= 16'h4C28 ; +782 : douta <= 16'h4C28 ; +783 : douta <= 16'h4C28 ; +784 : douta <= 16'h4C28 ; +785 : douta <= 16'h4C28 ; +786 : douta <= 16'h4B28 ; +787 : douta <= 16'h4B28 ; +788 : douta <= 16'h4B28 ; +789 : douta <= 16'h4B28 ; +790 : douta <= 16'h4B28 ; +791 : douta <= 16'h4B28 ; +792 : douta <= 16'h4B28 ; +793 : douta <= 16'h4B28 ; +794 : douta <= 16'h4B28 ; +795 : douta <= 16'h4A28 ; +796 : douta <= 16'h4A28 ; +797 : douta <= 16'h4A28 ; +798 : douta <= 16'h4A28 ; +799 : douta <= 16'h4A28 ; +800 : douta <= 16'h4A28 ; +801 : douta <= 16'h4928 ; +802 : douta <= 16'h4A28 ; +803 : douta <= 16'h4928 ; +804 : douta <= 16'h4A28 ; +805 : douta <= 16'h4A28 ; +806 : douta <= 16'h4A28 ; +807 : douta <= 16'h4A28 ; +808 : douta <= 16'h4A28 ; +809 : douta <= 16'h4A28 ; +810 : douta <= 16'h4A28 ; +811 : douta <= 16'h4A28 ; +812 : douta <= 16'h4A28 ; +813 : douta <= 16'h4A28 ; +814 : douta <= 16'h4A28 ; +815 : douta <= 16'h4A28 ; +816 : douta <= 16'h4A28 ; +817 : douta <= 16'h4A28 ; +818 : douta <= 16'h4928 ; +819 : douta <= 16'h4928 ; +820 : douta <= 16'h4928 ; +821 : douta <= 16'h4928 ; +822 : douta <= 16'h4928 ; +823 : douta <= 16'h4928 ; +824 : douta <= 16'h4928 ; +825 : douta <= 16'h4928 ; +826 : douta <= 16'h4928 ; +827 : douta <= 16'h4928 ; +828 : douta <= 16'h4928 ; +829 : douta <= 16'h4928 ; +830 : douta <= 16'h4928 ; +831 : douta <= 16'h4828 ; +832 : douta <= 16'h4928 ; +833 : douta <= 16'h4928 ; +834 : douta <= 16'h4928 ; +835 : douta <= 16'h4928 ; +836 : douta <= 16'h4928 ; +837 : douta <= 16'h4928 ; +838 : douta <= 16'h4928 ; +839 : douta <= 16'h4928 ; +840 : douta <= 16'h4928 ; +841 : douta <= 16'h4928 ; +842 : douta <= 16'h4928 ; +843 : douta <= 16'h4928 ; +844 : douta <= 16'h4828 ; +845 : douta <= 16'h4828 ; +846 : douta <= 16'h4728 ; +847 : douta <= 16'h4728 ; +848 : douta <= 16'h4828 ; +849 : douta <= 16'h4828 ; +850 : douta <= 16'h4828 ; +851 : douta <= 16'h4828 ; +852 : douta <= 16'h4828 ; +853 : douta <= 16'h4828 ; +854 : douta <= 16'h4828 ; +855 : douta <= 16'h4828 ; +856 : douta <= 16'h4828 ; +857 : douta <= 16'h4828 ; +858 : douta <= 16'h4828 ; +859 : douta <= 16'h4828 ; +860 : douta <= 16'h4828 ; +861 : douta <= 16'h4828 ; +862 : douta <= 16'h4828 ; +863 : douta <= 16'h4828 ; +864 : douta <= 16'h4828 ; +865 : douta <= 16'h4828 ; +866 : douta <= 16'h4828 ; +867 : douta <= 16'h4828 ; +868 : douta <= 16'h4828 ; +869 : douta <= 16'h4528 ; +870 : douta <= 16'h4728 ; +871 : douta <= 16'h4528 ; +872 : douta <= 16'h4528 ; +873 : douta <= 16'h4728 ; +874 : douta <= 16'h4528 ; +875 : douta <= 16'h4728 ; +876 : douta <= 16'h4628 ; +877 : douta <= 16'h4628 ; +878 : douta <= 16'h4628 ; +879 : douta <= 16'h4628 ; +880 : douta <= 16'h4628 ; +881 : douta <= 16'h4628 ; +882 : douta <= 16'h4628 ; +883 : douta <= 16'h4628 ; +884 : douta <= 16'h4628 ; +885 : douta <= 16'h4628 ; +886 : douta <= 16'h4628 ; +887 : douta <= 16'h4628 ; +888 : douta <= 16'h4628 ; +889 : douta <= 16'h4628 ; +890 : douta <= 16'h4628 ; +891 : douta <= 16'h4628 ; +892 : douta <= 16'h4628 ; +893 : douta <= 16'h4628 ; +894 : douta <= 16'h4628 ; +895 : douta <= 16'h4628 ; +896 : douta <= 16'h4628 ; +897 : douta <= 16'h4528 ; +898 : douta <= 16'h4628 ; +899 : douta <= 16'h4528 ; +900 : douta <= 16'h4528 ; +901 : douta <= 16'h4528 ; +902 : douta <= 16'h4528 ; +903 : douta <= 16'h4528 ; +904 : douta <= 16'h4528 ; +905 : douta <= 16'h4528 ; +906 : douta <= 16'h4528 ; +907 : douta <= 16'h4528 ; +908 : douta <= 16'h4528 ; +909 : douta <= 16'h4528 ; +910 : douta <= 16'h4528 ; +911 : douta <= 16'h4528 ; +912 : douta <= 16'h4528 ; +913 : douta <= 16'h4428 ; +914 : douta <= 16'h4428 ; +915 : douta <= 16'h4528 ; +916 : douta <= 16'h4428 ; +917 : douta <= 16'h4428 ; +918 : douta <= 16'h4528 ; +919 : douta <= 16'h4528 ; +920 : douta <= 16'h4528 ; +921 : douta <= 16'h4528 ; +922 : douta <= 16'h4528 ; +923 : douta <= 16'h4528 ; +924 : douta <= 16'h4528 ; +925 : douta <= 16'h4528 ; +926 : douta <= 16'h4528 ; +927 : douta <= 16'h4428 ; +928 : douta <= 16'h4428 ; +929 : douta <= 16'h4428 ; +930 : douta <= 16'h4428 ; +931 : douta <= 16'h4428 ; +932 : douta <= 16'h4428 ; +933 : douta <= 16'h4428 ; +934 : douta <= 16'h4428 ; +935 : douta <= 16'h4428 ; +936 : douta <= 16'h4428 ; +937 : douta <= 16'h4428 ; +938 : douta <= 16'h4428 ; +939 : douta <= 16'h4428 ; +940 : douta <= 16'h4428 ; +941 : douta <= 16'h4428 ; +942 : douta <= 16'h4428 ; +943 : douta <= 16'h4428 ; +944 : douta <= 16'h4428 ; +945 : douta <= 16'h4428 ; +946 : douta <= 16'h4328 ; +947 : douta <= 16'h4328 ; +948 : douta <= 16'h4428 ; +949 : douta <= 16'h4328 ; +950 : douta <= 16'h4428 ; +951 : douta <= 16'h4428 ; +952 : douta <= 16'h4328 ; +953 : douta <= 16'h4328 ; +954 : douta <= 16'h4328 ; +955 : douta <= 16'h4328 ; +956 : douta <= 16'h4328 ; +957 : douta <= 16'h4328 ; +958 : douta <= 16'h4328 ; +959 : douta <= 16'h4328 ; +960 : douta <= 16'h4328 ; +961 : douta <= 16'h4328 ; +962 : douta <= 16'h4328 ; +963 : douta <= 16'h4228 ; +964 : douta <= 16'h4228 ; +965 : douta <= 16'h4228 ; +966 : douta <= 16'h4228 ; +967 : douta <= 16'h4228 ; +968 : douta <= 16'h4228 ; +969 : douta <= 16'h4228 ; +970 : douta <= 16'h4228 ; +971 : douta <= 16'h4228 ; +972 : douta <= 16'h4228 ; +973 : douta <= 16'h4228 ; +974 : douta <= 16'h4228 ; +975 : douta <= 16'h4228 ; +976 : douta <= 16'h4228 ; +977 : douta <= 16'h4228 ; +978 : douta <= 16'h4228 ; +979 : douta <= 16'h4228 ; +980 : douta <= 16'h4228 ; +981 : douta <= 16'h4228 ; +982 : douta <= 16'h4228 ; +983 : douta <= 16'h4228 ; +984 : douta <= 16'h4128 ; +985 : douta <= 16'h4128 ; +986 : douta <= 16'h4128 ; +987 : douta <= 16'h4128 ; +988 : douta <= 16'h4128 ; +989 : douta <= 16'h4128 ; +990 : douta <= 16'h4128 ; +991 : douta <= 16'h4128 ; +992 : douta <= 16'h4128 ; +993 : douta <= 16'h4128 ; +994 : douta <= 16'h4128 ; +995 : douta <= 16'h4128 ; +996 : douta <= 16'h4128 ; +997 : douta <= 16'h4128 ; +998 : douta <= 16'h4128 ; +999 : douta <= 16'h4128 ; +1000 : douta <= 16'h4128 ; +1001 : douta <= 16'h4128 ; +1002 : douta <= 16'h4128 ; +1003 : douta <= 16'h4128 ; +1004 : douta <= 16'h4028 ; +1005 : douta <= 16'h4128 ; +1006 : douta <= 16'h4128 ; +1007 : douta <= 16'h4128 ; +1008 : douta <= 16'h4128 ; +1009 : douta <= 16'h4128 ; +1010 : douta <= 16'h4128 ; +1011 : douta <= 16'h4128 ; +1012 : douta <= 16'h4128 ; +1013 : douta <= 16'h4128 ; +1014 : douta <= 16'h4128 ; +1015 : douta <= 16'h4028 ; +1016 : douta <= 16'h4028 ; +1017 : douta <= 16'h4028 ; +1018 : douta <= 16'h4028 ; +1019 : douta <= 16'h4028 ; +1020 : douta <= 16'h4028 ; +1021 : douta <= 16'h4028 ; +1022 : douta <= 16'h4028 ; +1023 : douta <= 16'h3F2A ; +1024 : douta <= 16'h4028 ; +1025 : douta <= 16'h4028 ; +1026 : douta <= 16'h3E2A ; +1027 : douta <= 16'h4028 ; +1028 : douta <= 16'h3F2A ; +1029 : douta <= 16'h4028 ; +1030 : douta <= 16'h4028 ; +1031 : douta <= 16'h4028 ; +1032 : douta <= 16'h4028 ; +1033 : douta <= 16'h4028 ; +1034 : douta <= 16'h4028 ; +1035 : douta <= 16'h4028 ; +1036 : douta <= 16'h4028 ; +1037 : douta <= 16'h4028 ; +1038 : douta <= 16'h4028 ; +1039 : douta <= 16'h4028 ; +1040 : douta <= 16'h4028 ; +1041 : douta <= 16'h4028 ; +1042 : douta <= 16'h4028 ; +1043 : douta <= 16'h4028 ; +1044 : douta <= 16'h4028 ; +1045 : douta <= 16'h4028 ; +1046 : douta <= 16'h4028 ; +1047 : douta <= 16'h4028 ; +1048 : douta <= 16'h4028 ; +1049 : douta <= 16'h4028 ; +1050 : douta <= 16'h3D2A ; +1051 : douta <= 16'h4028 ; +1052 : douta <= 16'h3E2A ; +1053 : douta <= 16'h3E2A ; +1054 : douta <= 16'h3E2A ; +1055 : douta <= 16'h3E2A ; +1056 : douta <= 16'h3E2A ; +1057 : douta <= 16'h3E2A ; +1058 : douta <= 16'h3E2A ; +1059 : douta <= 16'h3E2A ; +1060 : douta <= 16'h3E2A ; +1061 : douta <= 16'h3E2A ; +1062 : douta <= 16'h3E2A ; +1063 : douta <= 16'h3E2A ; +1064 : douta <= 16'h3E2A ; +1065 : douta <= 16'h3E2A ; +1066 : douta <= 16'h3E2A ; +1067 : douta <= 16'h3E2A ; +1068 : douta <= 16'h3E2A ; +1069 : douta <= 16'h3E2A ; +1070 : douta <= 16'h3E2A ; +1071 : douta <= 16'h3E2A ; +1072 : douta <= 16'h3E2A ; +1073 : douta <= 16'h3E2A ; +1074 : douta <= 16'h3E2A ; +1075 : douta <= 16'h3E2A ; +1076 : douta <= 16'h3D2A ; +1077 : douta <= 16'h3E2A ; +1078 : douta <= 16'h3D2A ; +1079 : douta <= 16'h3D2A ; +1080 : douta <= 16'h3D2A ; +1081 : douta <= 16'h3D2A ; +1082 : douta <= 16'h3D2A ; +1083 : douta <= 16'h3D2A ; +1084 : douta <= 16'h3D2A ; +1085 : douta <= 16'h3D2A ; +1086 : douta <= 16'h3D2A ; +1087 : douta <= 16'h3D2A ; +1088 : douta <= 16'h3D2A ; +1089 : douta <= 16'h3D2A ; +1090 : douta <= 16'h3D2A ; +1091 : douta <= 16'h3D2A ; +1092 : douta <= 16'h3C2A ; +1093 : douta <= 16'h3D2A ; +1094 : douta <= 16'h3D2A ; +1095 : douta <= 16'h3D2A ; +1096 : douta <= 16'h3C2A ; +1097 : douta <= 16'h3D2A ; +1098 : douta <= 16'h3D2A ; +1099 : douta <= 16'h3D2A ; +1100 : douta <= 16'h3D2A ; +1101 : douta <= 16'h3D2A ; +1102 : douta <= 16'h3C2A ; +1103 : douta <= 16'h3D2A ; +1104 : douta <= 16'h3B2A ; +1105 : douta <= 16'h3B2A ; +1106 : douta <= 16'h3B2A ; +1107 : douta <= 16'h3C2A ; +1108 : douta <= 16'h3C2A ; +1109 : douta <= 16'h3C2A ; +1110 : douta <= 16'h3C2A ; +1111 : douta <= 16'h3C2A ; +1112 : douta <= 16'h3C2A ; +1113 : douta <= 16'h3C2A ; +1114 : douta <= 16'h3C2A ; +1115 : douta <= 16'h3C2A ; +1116 : douta <= 16'h3C2A ; +1117 : douta <= 16'h3C2A ; +1118 : douta <= 16'h3C2A ; +1119 : douta <= 16'h3C2A ; +1120 : douta <= 16'h3C2A ; +1121 : douta <= 16'h3C2A ; +1122 : douta <= 16'h3C2A ; +1123 : douta <= 16'h3C2A ; +1124 : douta <= 16'h3C2A ; +1125 : douta <= 16'h3C2A ; +1126 : douta <= 16'h3C2A ; +1127 : douta <= 16'h3C2A ; +1128 : douta <= 16'h3C2A ; +1129 : douta <= 16'h3C2A ; +1130 : douta <= 16'h3C2A ; +1131 : douta <= 16'h3B2A ; +1132 : douta <= 16'h3B2A ; +1133 : douta <= 16'h3B2A ; +1134 : douta <= 16'h3B2A ; +1135 : douta <= 16'h3B2A ; +1136 : douta <= 16'h3B2A ; +1137 : douta <= 16'h3B2A ; +1138 : douta <= 16'h3A2A ; +1139 : douta <= 16'h3A2A ; +1140 : douta <= 16'h3A2A ; +1141 : douta <= 16'h3A2A ; +1142 : douta <= 16'h3A2A ; +1143 : douta <= 16'h3A2A ; +1144 : douta <= 16'h3A2A ; +1145 : douta <= 16'h3A2A ; +1146 : douta <= 16'h392A ; +1147 : douta <= 16'h392A ; +1148 : douta <= 16'h392A ; +1149 : douta <= 16'h3A2A ; +1150 : douta <= 16'h3A2A ; +1151 : douta <= 16'h3A2A ; +1152 : douta <= 16'h3A2A ; +1153 : douta <= 16'h3A2A ; +1154 : douta <= 16'h3A2A ; +1155 : douta <= 16'h3A2A ; +1156 : douta <= 16'h3A2A ; +1157 : douta <= 16'h3A2A ; +1158 : douta <= 16'h3A2A ; +1159 : douta <= 16'h3A2A ; +1160 : douta <= 16'h3A2A ; +1161 : douta <= 16'h3A2A ; +1162 : douta <= 16'h3A2A ; +1163 : douta <= 16'h392A ; +1164 : douta <= 16'h3A2A ; +1165 : douta <= 16'h392A ; +1166 : douta <= 16'h392A ; +1167 : douta <= 16'h392A ; +1168 : douta <= 16'h392A ; +1169 : douta <= 16'h392A ; +1170 : douta <= 16'h392A ; +1171 : douta <= 16'h392A ; +1172 : douta <= 16'h392A ; +1173 : douta <= 16'h392A ; +1174 : douta <= 16'h392A ; +1175 : douta <= 16'h392A ; +1176 : douta <= 16'h392A ; +1177 : douta <= 16'h392A ; +1178 : douta <= 16'h392A ; +1179 : douta <= 16'h382A ; +1180 : douta <= 16'h382A ; +1181 : douta <= 16'h392A ; +1182 : douta <= 16'h392A ; +1183 : douta <= 16'h392A ; +1184 : douta <= 16'h392A ; +1185 : douta <= 16'h392A ; +1186 : douta <= 16'h392A ; +1187 : douta <= 16'h392A ; +1188 : douta <= 16'h372A ; +1189 : douta <= 16'h372A ; +1190 : douta <= 16'h372A ; +1191 : douta <= 16'h372A ; +1192 : douta <= 16'h382A ; +1193 : douta <= 16'h382A ; +1194 : douta <= 16'h382A ; +1195 : douta <= 16'h382A ; +1196 : douta <= 16'h382A ; +1197 : douta <= 16'h382A ; +1198 : douta <= 16'h382A ; +1199 : douta <= 16'h382A ; +1200 : douta <= 16'h382A ; +1201 : douta <= 16'h382A ; +1202 : douta <= 16'h382A ; +1203 : douta <= 16'h382A ; +1204 : douta <= 16'h382A ; +1205 : douta <= 16'h382A ; +1206 : douta <= 16'h382A ; +1207 : douta <= 16'h382A ; +1208 : douta <= 16'h382A ; +1209 : douta <= 16'h382A ; +1210 : douta <= 16'h382A ; +1211 : douta <= 16'h382A ; +1212 : douta <= 16'h382A ; +1213 : douta <= 16'h382A ; +1214 : douta <= 16'h382A ; +1215 : douta <= 16'h382A ; +1216 : douta <= 16'h382A ; +1217 : douta <= 16'h372A ; +1218 : douta <= 16'h382A ; +1219 : douta <= 16'h372A ; +1220 : douta <= 16'h372A ; +1221 : douta <= 16'h372A ; +1222 : douta <= 16'h372A ; +1223 : douta <= 16'h372A ; +1224 : douta <= 16'h372A ; +1225 : douta <= 16'h372A ; +1226 : douta <= 16'h372A ; +1227 : douta <= 16'h362A ; +1228 : douta <= 16'h352A ; +1229 : douta <= 16'h362A ; +1230 : douta <= 16'h362A ; +1231 : douta <= 16'h362A ; +1232 : douta <= 16'h362A ; +1233 : douta <= 16'h362A ; +1234 : douta <= 16'h362A ; +1235 : douta <= 16'h362A ; +1236 : douta <= 16'h362A ; +1237 : douta <= 16'h362A ; +1238 : douta <= 16'h362A ; +1239 : douta <= 16'h362A ; +1240 : douta <= 16'h362A ; +1241 : douta <= 16'h362A ; +1242 : douta <= 16'h362A ; +1243 : douta <= 16'h362A ; +1244 : douta <= 16'h362A ; +1245 : douta <= 16'h362A ; +1246 : douta <= 16'h362A ; +1247 : douta <= 16'h362A ; +1248 : douta <= 16'h362A ; +1249 : douta <= 16'h362A ; +1250 : douta <= 16'h362A ; +1251 : douta <= 16'h362A ; +1252 : douta <= 16'h362A ; +1253 : douta <= 16'h352A ; +1254 : douta <= 16'h352A ; +1255 : douta <= 16'h352A ; +1256 : douta <= 16'h352A ; +1257 : douta <= 16'h352A ; +1258 : douta <= 16'h352A ; +1259 : douta <= 16'h352A ; +1260 : douta <= 16'h352A ; +1261 : douta <= 16'h352A ; +1262 : douta <= 16'h352A ; +1263 : douta <= 16'h352A ; +1264 : douta <= 16'h352A ; +1265 : douta <= 16'h352A ; +1266 : douta <= 16'h352A ; +1267 : douta <= 16'h342A ; +1268 : douta <= 16'h342A ; +1269 : douta <= 16'h352A ; +1270 : douta <= 16'h352A ; +1271 : douta <= 16'h352A ; +1272 : douta <= 16'h352A ; +1273 : douta <= 16'h352A ; +1274 : douta <= 16'h352A ; +1275 : douta <= 16'h352A ; +1276 : douta <= 16'h352A ; +1277 : douta <= 16'h352A ; +1278 : douta <= 16'h352A ; +1279 : douta <= 16'h352A ; +1280 : douta <= 16'h342A ; +1281 : douta <= 16'h342A ; +1282 : douta <= 16'h342A ; +1283 : douta <= 16'h342A ; +1284 : douta <= 16'h342A ; +1285 : douta <= 16'h342A ; +1286 : douta <= 16'h342A ; +1287 : douta <= 16'h342A ; +1288 : douta <= 16'h342A ; +1289 : douta <= 16'h342A ; +1290 : douta <= 16'h342A ; +1291 : douta <= 16'h342A ; +1292 : douta <= 16'h342A ; +1293 : douta <= 16'h342A ; +1294 : douta <= 16'h342A ; +1295 : douta <= 16'h342A ; +1296 : douta <= 16'h332A ; +1297 : douta <= 16'h332A ; +1298 : douta <= 16'h332A ; +1299 : douta <= 16'h342A ; +1300 : douta <= 16'h342A ; +1301 : douta <= 16'h342A ; +1302 : douta <= 16'h342A ; +1303 : douta <= 16'h342A ; +1304 : douta <= 16'h342A ; +1305 : douta <= 16'h332A ; +1306 : douta <= 16'h332A ; +1307 : douta <= 16'h332A ; +1308 : douta <= 16'h332A ; +1309 : douta <= 16'h332A ; +1310 : douta <= 16'h332A ; +1311 : douta <= 16'h332A ; +1312 : douta <= 16'h332A ; +1313 : douta <= 16'h332A ; +1314 : douta <= 16'h332A ; +1315 : douta <= 16'h322A ; +1316 : douta <= 16'h322A ; +1317 : douta <= 16'h322A ; +1318 : douta <= 16'h322A ; +1319 : douta <= 16'h322A ; +1320 : douta <= 16'h322A ; +1321 : douta <= 16'h312A ; +1322 : douta <= 16'h322A ; +1323 : douta <= 16'h312A ; +1324 : douta <= 16'h312A ; +1325 : douta <= 16'h322A ; +1326 : douta <= 16'h322A ; +1327 : douta <= 16'h322A ; +1328 : douta <= 16'h322A ; +1329 : douta <= 16'h322A ; +1330 : douta <= 16'h322A ; +1331 : douta <= 16'h322A ; +1332 : douta <= 16'h322A ; +1333 : douta <= 16'h322A ; +1334 : douta <= 16'h322A ; +1335 : douta <= 16'h322A ; +1336 : douta <= 16'h322A ; +1337 : douta <= 16'h322A ; +1338 : douta <= 16'h322A ; +1339 : douta <= 16'h322A ; +1340 : douta <= 16'h312A ; +1341 : douta <= 16'h312A ; +1342 : douta <= 16'h312A ; +1343 : douta <= 16'h312A ; +1344 : douta <= 16'h312A ; +1345 : douta <= 16'h312A ; +1346 : douta <= 16'h312A ; +1347 : douta <= 16'h312A ; +1348 : douta <= 16'h312A ; +1349 : douta <= 16'h312A ; +1350 : douta <= 16'h312A ; +1351 : douta <= 16'h312A ; +1352 : douta <= 16'h312A ; +1353 : douta <= 16'h312A ; +1354 : douta <= 16'h312A ; +1355 : douta <= 16'h312A ; +1356 : douta <= 16'h302A ; +1357 : douta <= 16'h312A ; +1358 : douta <= 16'h312A ; +1359 : douta <= 16'h312A ; +1360 : douta <= 16'h312A ; +1361 : douta <= 16'h312A ; +1362 : douta <= 16'h312A ; +1363 : douta <= 16'h312A ; +1364 : douta <= 16'h312A ; +1365 : douta <= 16'h312A ; +1366 : douta <= 16'h2F2A ; +1367 : douta <= 16'h302A ; +1368 : douta <= 16'h302A ; +1369 : douta <= 16'h302A ; +1370 : douta <= 16'h302A ; +1371 : douta <= 16'h302A ; +1372 : douta <= 16'h302A ; +1373 : douta <= 16'h302A ; +1374 : douta <= 16'h302A ; +1375 : douta <= 16'h302A ; +1376 : douta <= 16'h302A ; +1377 : douta <= 16'h302A ; +1378 : douta <= 16'h302A ; +1379 : douta <= 16'h302A ; +1380 : douta <= 16'h302A ; +1381 : douta <= 16'h302A ; +1382 : douta <= 16'h2F2A ; +1383 : douta <= 16'h302A ; +1384 : douta <= 16'h302A ; +1385 : douta <= 16'h302A ; +1386 : douta <= 16'h302A ; +1387 : douta <= 16'h302A ; +1388 : douta <= 16'h302A ; +1389 : douta <= 16'h302A ; +1390 : douta <= 16'h302A ; +1391 : douta <= 16'h2F2A ; +1392 : douta <= 16'h302A ; +1393 : douta <= 16'h302A ; +1394 : douta <= 16'h302A ; +1395 : douta <= 16'h2F2A ; +1396 : douta <= 16'h302A ; +1397 : douta <= 16'h2F2A ; +1398 : douta <= 16'h2F2A ; +1399 : douta <= 16'h2F2A ; +1400 : douta <= 16'h2E2A ; +1401 : douta <= 16'h2E2A ; +1402 : douta <= 16'h2D2A ; +1403 : douta <= 16'h2D2A ; +1404 : douta <= 16'h2D2A ; +1405 : douta <= 16'h2D2A ; +1406 : douta <= 16'h2E2A ; +1407 : douta <= 16'h2E2A ; +1408 : douta <= 16'h2E2A ; +1409 : douta <= 16'h2E2A ; +1410 : douta <= 16'h2E2A ; +1411 : douta <= 16'h2E2A ; +1412 : douta <= 16'h2E2A ; +1413 : douta <= 16'h2E2A ; +1414 : douta <= 16'h2E2A ; +1415 : douta <= 16'h2E2A ; +1416 : douta <= 16'h2E2A ; +1417 : douta <= 16'h2E2A ; +1418 : douta <= 16'h2E2A ; +1419 : douta <= 16'h2E2A ; +1420 : douta <= 16'h2E2A ; +1421 : douta <= 16'h2E2A ; +1422 : douta <= 16'h2E2A ; +1423 : douta <= 16'h2E2A ; +1424 : douta <= 16'h2E2A ; +1425 : douta <= 16'h2E2A ; +1426 : douta <= 16'h2E2A ; +1427 : douta <= 16'h2D2A ; +1428 : douta <= 16'h2E2A ; +1429 : douta <= 16'h2D2A ; +1430 : douta <= 16'h2D2A ; +1431 : douta <= 16'h2D2A ; +1432 : douta <= 16'h2D2A ; +1433 : douta <= 16'h2D2A ; +1434 : douta <= 16'h2D2A ; +1435 : douta <= 16'h2D2A ; +1436 : douta <= 16'h2D2A ; +1437 : douta <= 16'h2D2A ; +1438 : douta <= 16'h2D2A ; +1439 : douta <= 16'h2D2A ; +1440 : douta <= 16'h2D2A ; +1441 : douta <= 16'h2D2A ; +1442 : douta <= 16'h2D2A ; +1443 : douta <= 16'h2C2A ; +1444 : douta <= 16'h2D2A ; +1445 : douta <= 16'h2C2A ; +1446 : douta <= 16'h2D2A ; +1447 : douta <= 16'h2D2A ; +1448 : douta <= 16'h2D2A ; +1449 : douta <= 16'h2D2A ; +1450 : douta <= 16'h2D2A ; +1451 : douta <= 16'h2D2A ; +1452 : douta <= 16'h2D2A ; +1453 : douta <= 16'h2D2A ; +1454 : douta <= 16'h2D2A ; +1455 : douta <= 16'h2D2A ; +1456 : douta <= 16'h2C2A ; +1457 : douta <= 16'h2C2A ; +1458 : douta <= 16'h2C2A ; +1459 : douta <= 16'h2B2A ; +1460 : douta <= 16'h2B2A ; +1461 : douta <= 16'h2C2A ; +1462 : douta <= 16'h2C2A ; +1463 : douta <= 16'h2C2A ; +1464 : douta <= 16'h2C2A ; +1465 : douta <= 16'h2C2A ; +1466 : douta <= 16'h2C2A ; +1467 : douta <= 16'h2C2A ; +1468 : douta <= 16'h2C2A ; +1469 : douta <= 16'h2C2A ; +1470 : douta <= 16'h2C2A ; +1471 : douta <= 16'h2C2A ; +1472 : douta <= 16'h2C2A ; +1473 : douta <= 16'h2C2A ; +1474 : douta <= 16'h2C2A ; +1475 : douta <= 16'h2C2A ; +1476 : douta <= 16'h2C2A ; +1477 : douta <= 16'h2C2A ; +1478 : douta <= 16'h2C2A ; +1479 : douta <= 16'h2C2A ; +1480 : douta <= 16'h2C2A ; +1481 : douta <= 16'h2C2A ; +1482 : douta <= 16'h2C2A ; +1483 : douta <= 16'h2C2A ; +1484 : douta <= 16'h2C2A ; +1485 : douta <= 16'h2B2A ; +1486 : douta <= 16'h2B2A ; +1487 : douta <= 16'h2B2A ; +1488 : douta <= 16'h2B2A ; +1489 : douta <= 16'h2A2A ; +1490 : douta <= 16'h2B2A ; +1491 : douta <= 16'h2A2A ; +1492 : douta <= 16'h2A2A ; +1493 : douta <= 16'h2A2A ; +1494 : douta <= 16'h2A2A ; +1495 : douta <= 16'h2A2A ; +1496 : douta <= 16'h2A2A ; +1497 : douta <= 16'h2A2A ; +1498 : douta <= 16'h2A2A ; +1499 : douta <= 16'h2A2A ; +1500 : douta <= 16'h292A ; +1501 : douta <= 16'h292A ; +1502 : douta <= 16'h292A ; +1503 : douta <= 16'h2A2A ; +1504 : douta <= 16'h2A2A ; +1505 : douta <= 16'h2A2A ; +1506 : douta <= 16'h2A2A ; +1507 : douta <= 16'h2A2A ; +1508 : douta <= 16'h2A2A ; +1509 : douta <= 16'h2A2A ; +1510 : douta <= 16'h2A2A ; +1511 : douta <= 16'h2A2A ; +1512 : douta <= 16'h2A2A ; +1513 : douta <= 16'h2A2A ; +1514 : douta <= 16'h2A2A ; +1515 : douta <= 16'h292A ; +1516 : douta <= 16'h292A ; +1517 : douta <= 16'h292A ; +1518 : douta <= 16'h292A ; +1519 : douta <= 16'h292A ; +1520 : douta <= 16'h292A ; +1521 : douta <= 16'h292A ; +1522 : douta <= 16'h292A ; +1523 : douta <= 16'h292A ; +1524 : douta <= 16'h292A ; +1525 : douta <= 16'h292A ; +1526 : douta <= 16'h292A ; +1527 : douta <= 16'h292A ; +1528 : douta <= 16'h292A ; +1529 : douta <= 16'h292A ; +1530 : douta <= 16'h292A ; +1531 : douta <= 16'h292A ; +1532 : douta <= 16'h282A ; +1533 : douta <= 16'h282A ; +1534 : douta <= 16'h282A ; +1535 : douta <= 16'h292A ; +1536 : douta <= 16'h292A ; +1537 : douta <= 16'h292A ; +1538 : douta <= 16'h292A ; +1539 : douta <= 16'h292A ; +1540 : douta <= 16'h292A ; +1541 : douta <= 16'h292A ; +1542 : douta <= 16'h272A ; +1543 : douta <= 16'h292A ; +1544 : douta <= 16'h272A ; +1545 : douta <= 16'h272A ; +1546 : douta <= 16'h282A ; +1547 : douta <= 16'h282A ; +1548 : douta <= 16'h282A ; +1549 : douta <= 16'h282A ; +1550 : douta <= 16'h282A ; +1551 : douta <= 16'h282A ; +1552 : douta <= 16'h282A ; +1553 : douta <= 16'h282A ; +1554 : douta <= 16'h282A ; +1555 : douta <= 16'h282A ; +1556 : douta <= 16'h282A ; +1557 : douta <= 16'h282A ; +1558 : douta <= 16'h282A ; +1559 : douta <= 16'h282A ; +1560 : douta <= 16'h282A ; +1561 : douta <= 16'h282A ; +1562 : douta <= 16'h282A ; +1563 : douta <= 16'h282A ; +1564 : douta <= 16'h282A ; +1565 : douta <= 16'h282A ; +1566 : douta <= 16'h282A ; +1567 : douta <= 16'h282A ; +1568 : douta <= 16'h282A ; +1569 : douta <= 16'h282A ; +1570 : douta <= 16'h282A ; +1571 : douta <= 16'h282A ; +1572 : douta <= 16'h282A ; +1573 : douta <= 16'h282A ; +1574 : douta <= 16'h282A ; +1575 : douta <= 16'h272A ; +1576 : douta <= 16'h272A ; +1577 : douta <= 16'h272A ; +1578 : douta <= 16'h272A ; +1579 : douta <= 16'h272A ; +1580 : douta <= 16'h272A ; +1581 : douta <= 16'h272A ; +1582 : douta <= 16'h272A ; +1583 : douta <= 16'h262A ; +1584 : douta <= 16'h262A ; +1585 : douta <= 16'h252A ; +1586 : douta <= 16'h252A ; +1587 : douta <= 16'h262A ; +1588 : douta <= 16'h262A ; +1589 : douta <= 16'h252A ; +1590 : douta <= 16'h262A ; +1591 : douta <= 16'h262A ; +1592 : douta <= 16'h262A ; +1593 : douta <= 16'h262A ; +1594 : douta <= 16'h262A ; +1595 : douta <= 16'h262A ; +1596 : douta <= 16'h262A ; +1597 : douta <= 16'h262A ; +1598 : douta <= 16'h262A ; +1599 : douta <= 16'h262A ; +1600 : douta <= 16'h262A ; +1601 : douta <= 16'h262A ; +1602 : douta <= 16'h262A ; +1603 : douta <= 16'h262A ; +1604 : douta <= 16'h262A ; +1605 : douta <= 16'h262A ; +1606 : douta <= 16'h262A ; +1607 : douta <= 16'h262A ; +1608 : douta <= 16'h262A ; +1609 : douta <= 16'h252A ; +1610 : douta <= 16'h252A ; +1611 : douta <= 16'h252A ; +1612 : douta <= 16'h252A ; +1613 : douta <= 16'h252A ; +1614 : douta <= 16'h252A ; +1615 : douta <= 16'h252A ; +1616 : douta <= 16'h252A ; +1617 : douta <= 16'h252A ; +1618 : douta <= 16'h252A ; +1619 : douta <= 16'h252A ; +1620 : douta <= 16'h252A ; +1621 : douta <= 16'h252A ; +1622 : douta <= 16'h252A ; +1623 : douta <= 16'h252A ; +1624 : douta <= 16'h252A ; +1625 : douta <= 16'h242A ; +1626 : douta <= 16'h252A ; +1627 : douta <= 16'h252A ; +1628 : douta <= 16'h252A ; +1629 : douta <= 16'h252A ; +1630 : douta <= 16'h252A ; +1631 : douta <= 16'h252A ; +1632 : douta <= 16'h252A ; +1633 : douta <= 16'h252A ; +1634 : douta <= 16'h252A ; +1635 : douta <= 16'h252A ; +1636 : douta <= 16'h252A ; +1637 : douta <= 16'h252A ; +1638 : douta <= 16'h242A ; +1639 : douta <= 16'h242A ; +1640 : douta <= 16'h242A ; +1641 : douta <= 16'h242A ; +1642 : douta <= 16'h242A ; +1643 : douta <= 16'h242A ; +1644 : douta <= 16'h242A ; +1645 : douta <= 16'h242A ; +1646 : douta <= 16'h242A ; +1647 : douta <= 16'h242A ; +1648 : douta <= 16'h242A ; +1649 : douta <= 16'h242A ; +1650 : douta <= 16'h242A ; +1651 : douta <= 16'h242A ; +1652 : douta <= 16'h232A ; +1653 : douta <= 16'h232A ; +1654 : douta <= 16'h242A ; +1655 : douta <= 16'h242A ; +1656 : douta <= 16'h242A ; +1657 : douta <= 16'h242A ; +1658 : douta <= 16'h242A ; +1659 : douta <= 16'h242A ; +1660 : douta <= 16'h242A ; +1661 : douta <= 16'h242A ; +1662 : douta <= 16'h242A ; +1663 : douta <= 16'h242A ; +1664 : douta <= 16'h242A ; +1665 : douta <= 16'h232A ; +1666 : douta <= 16'h232A ; +1667 : douta <= 16'h232A ; +1668 : douta <= 16'h232A ; +1669 : douta <= 16'h232A ; +1670 : douta <= 16'h232A ; +1671 : douta <= 16'h232A ; +1672 : douta <= 16'h222A ; +1673 : douta <= 16'h222A ; +1674 : douta <= 16'h222A ; +1675 : douta <= 16'h222A ; +1676 : douta <= 16'h222A ; +1677 : douta <= 16'h222A ; +1678 : douta <= 16'h222A ; +1679 : douta <= 16'h222A ; +1680 : douta <= 16'h222A ; +1681 : douta <= 16'h212A ; +1682 : douta <= 16'h222A ; +1683 : douta <= 16'h212A ; +1684 : douta <= 16'h222A ; +1685 : douta <= 16'h222A ; +1686 : douta <= 16'h222A ; +1687 : douta <= 16'h222A ; +1688 : douta <= 16'h222A ; +1689 : douta <= 16'h222A ; +1690 : douta <= 16'h222A ; +1691 : douta <= 16'h222A ; +1692 : douta <= 16'h222A ; +1693 : douta <= 16'h222A ; +1694 : douta <= 16'h222A ; +1695 : douta <= 16'h222A ; +1696 : douta <= 16'h222A ; +1697 : douta <= 16'h222A ; +1698 : douta <= 16'h222A ; +1699 : douta <= 16'h212A ; +1700 : douta <= 16'h212A ; +1701 : douta <= 16'h212A ; +1702 : douta <= 16'h212A ; +1703 : douta <= 16'h212A ; +1704 : douta <= 16'h212A ; +1705 : douta <= 16'h212A ; +1706 : douta <= 16'h212A ; +1707 : douta <= 16'h212A ; +1708 : douta <= 16'h212A ; +1709 : douta <= 16'h212A ; +1710 : douta <= 16'h212A ; +1711 : douta <= 16'h212A ; +1712 : douta <= 16'h212A ; +1713 : douta <= 16'h212A ; +1714 : douta <= 16'h202A ; +1715 : douta <= 16'h202A ; +1716 : douta <= 16'h212A ; +1717 : douta <= 16'h212A ; +1718 : douta <= 16'h212A ; +1719 : douta <= 16'h212A ; +1720 : douta <= 16'h212A ; +1721 : douta <= 16'h212A ; +1722 : douta <= 16'h212A ; +1723 : douta <= 16'h212A ; +1724 : douta <= 16'h212A ; +1725 : douta <= 16'h212A ; +1726 : douta <= 16'h202A ; +1727 : douta <= 16'h212A ; +1728 : douta <= 16'h202A ; +1729 : douta <= 16'h202A ; +1730 : douta <= 16'h202A ; +1731 : douta <= 16'h202A ; +1732 : douta <= 16'h202A ; +1733 : douta <= 16'h202A ; +1734 : douta <= 16'h202A ; +1735 : douta <= 16'h202A ; +1736 : douta <= 16'h202A ; +1737 : douta <= 16'h202A ; +1738 : douta <= 16'h202A ; +1739 : douta <= 16'h202A ; +1740 : douta <= 16'h202A ; +1741 : douta <= 16'h202A ; +1742 : douta <= 16'h202A ; +1743 : douta <= 16'h202A ; +1744 : douta <= 16'h202A ; +1745 : douta <= 16'h202A ; +1746 : douta <= 16'h202A ; +1747 : douta <= 16'h202A ; +1748 : douta <= 16'h202A ; +1749 : douta <= 16'h202A ; +1750 : douta <= 16'h202A ; +1751 : douta <= 16'h1F2C ; +1752 : douta <= 16'h202A ; +1753 : douta <= 16'h202A ; +1754 : douta <= 16'h202A ; +1755 : douta <= 16'h202A ; +1756 : douta <= 16'h202A ; +1757 : douta <= 16'h1D2C ; +1758 : douta <= 16'h202A ; +1759 : douta <= 16'h202A ; +1760 : douta <= 16'h202A ; +1761 : douta <= 16'h202A ; +1762 : douta <= 16'h1E2C ; +1763 : douta <= 16'h202A ; +1764 : douta <= 16'h202A ; +1765 : douta <= 16'h202A ; +1766 : douta <= 16'h202A ; +1767 : douta <= 16'h1E2C ; +1768 : douta <= 16'h202A ; +1769 : douta <= 16'h1E2C ; +1770 : douta <= 16'h1E2C ; +1771 : douta <= 16'h1E2C ; +1772 : douta <= 16'h1E2C ; +1773 : douta <= 16'h1E2C ; +1774 : douta <= 16'h1E2C ; +1775 : douta <= 16'h1E2C ; +1776 : douta <= 16'h1E2C ; +1777 : douta <= 16'h1E2C ; +1778 : douta <= 16'h1E2C ; +1779 : douta <= 16'h1E2C ; +1780 : douta <= 16'h1E2C ; +1781 : douta <= 16'h1E2C ; +1782 : douta <= 16'h1E2C ; +1783 : douta <= 16'h1D2C ; +1784 : douta <= 16'h1D2C ; +1785 : douta <= 16'h1D2C ; +1786 : douta <= 16'h1D2C ; +1787 : douta <= 16'h1D2C ; +1788 : douta <= 16'h1D2C ; +1789 : douta <= 16'h1D2C ; +1790 : douta <= 16'h1D2C ; +1791 : douta <= 16'h1D2C ; +1792 : douta <= 16'h1D2C ; +1793 : douta <= 16'h1D2C ; +1794 : douta <= 16'h1D2C ; +1795 : douta <= 16'h1D2C ; +1796 : douta <= 16'h1D2C ; +1797 : douta <= 16'h1C2C ; +1798 : douta <= 16'h1C2C ; +1799 : douta <= 16'h1C2C ; +1800 : douta <= 16'h1C2C ; +1801 : douta <= 16'h1D2C ; +1802 : douta <= 16'h1D2C ; +1803 : douta <= 16'h1D2C ; +1804 : douta <= 16'h1D2C ; +1805 : douta <= 16'h1D2C ; +1806 : douta <= 16'h1D2C ; +1807 : douta <= 16'h1D2C ; +1808 : douta <= 16'h1D2C ; +1809 : douta <= 16'h1D2C ; +1810 : douta <= 16'h1D2C ; +1811 : douta <= 16'h1C2C ; +1812 : douta <= 16'h1C2C ; +1813 : douta <= 16'h1C2C ; +1814 : douta <= 16'h1C2C ; +1815 : douta <= 16'h1C2C ; +1816 : douta <= 16'h1C2C ; +1817 : douta <= 16'h1B2C ; +1818 : douta <= 16'h1C2C ; +1819 : douta <= 16'h1B2C ; +1820 : douta <= 16'h1B2C ; +1821 : douta <= 16'h1B2C ; +1822 : douta <= 16'h1C2C ; +1823 : douta <= 16'h1C2C ; +1824 : douta <= 16'h1C2C ; +1825 : douta <= 16'h1C2C ; +1826 : douta <= 16'h1C2C ; +1827 : douta <= 16'h1C2C ; +1828 : douta <= 16'h1C2C ; +1829 : douta <= 16'h1C2C ; +1830 : douta <= 16'h1C2C ; +1831 : douta <= 16'h1C2C ; +1832 : douta <= 16'h1C2C ; +1833 : douta <= 16'h1C2C ; +1834 : douta <= 16'h1C2C ; +1835 : douta <= 16'h1C2C ; +1836 : douta <= 16'h1C2C ; +1837 : douta <= 16'h1C2C ; +1838 : douta <= 16'h1C2C ; +1839 : douta <= 16'h1C2C ; +1840 : douta <= 16'h1B2C ; +1841 : douta <= 16'h1B2C ; +1842 : douta <= 16'h1B2C ; +1843 : douta <= 16'h1B2C ; +1844 : douta <= 16'h1B2C ; +1845 : douta <= 16'h1B2C ; +1846 : douta <= 16'h1B2C ; +1847 : douta <= 16'h1B2C ; +1848 : douta <= 16'h1B2C ; +1849 : douta <= 16'h1B2C ; +1850 : douta <= 16'h1A2C ; +1851 : douta <= 16'h1A2C ; +1852 : douta <= 16'h1A2C ; +1853 : douta <= 16'h1A2C ; +1854 : douta <= 16'h1A2C ; +1855 : douta <= 16'h1A2C ; +1856 : douta <= 16'h192C ; +1857 : douta <= 16'h192C ; +1858 : douta <= 16'h192C ; +1859 : douta <= 16'h1A2C ; +1860 : douta <= 16'h1A2C ; +1861 : douta <= 16'h1A2C ; +1862 : douta <= 16'h1A2C ; +1863 : douta <= 16'h1A2C ; +1864 : douta <= 16'h1A2C ; +1865 : douta <= 16'h1A2C ; +1866 : douta <= 16'h1A2C ; +1867 : douta <= 16'h1A2C ; +1868 : douta <= 16'h1A2C ; +1869 : douta <= 16'h1A2C ; +1870 : douta <= 16'h1A2C ; +1871 : douta <= 16'h1A2C ; +1872 : douta <= 16'h1A2C ; +1873 : douta <= 16'h1A2C ; +1874 : douta <= 16'h1A2C ; +1875 : douta <= 16'h1A2C ; +1876 : douta <= 16'h1A2C ; +1877 : douta <= 16'h1A2C ; +1878 : douta <= 16'h192C ; +1879 : douta <= 16'h192C ; +1880 : douta <= 16'h192C ; +1881 : douta <= 16'h192C ; +1882 : douta <= 16'h192C ; +1883 : douta <= 16'h192C ; +1884 : douta <= 16'h192C ; +1885 : douta <= 16'h192C ; +1886 : douta <= 16'h192C ; +1887 : douta <= 16'h192C ; +1888 : douta <= 16'h192C ; +1889 : douta <= 16'h192C ; +1890 : douta <= 16'h192C ; +1891 : douta <= 16'h192C ; +1892 : douta <= 16'h182C ; +1893 : douta <= 16'h192C ; +1894 : douta <= 16'h192C ; +1895 : douta <= 16'h192C ; +1896 : douta <= 16'h192C ; +1897 : douta <= 16'h192C ; +1898 : douta <= 16'h192C ; +1899 : douta <= 16'h192C ; +1900 : douta <= 16'h192C ; +1901 : douta <= 16'h192C ; +1902 : douta <= 16'h192C ; +1903 : douta <= 16'h192C ; +1904 : douta <= 16'h192C ; +1905 : douta <= 16'h192C ; +1906 : douta <= 16'h182C ; +1907 : douta <= 16'h182C ; +1908 : douta <= 16'h182C ; +1909 : douta <= 16'h172C ; +1910 : douta <= 16'h182C ; +1911 : douta <= 16'h172C ; +1912 : douta <= 16'h172C ; +1913 : douta <= 16'h172C ; +1914 : douta <= 16'h182C ; +1915 : douta <= 16'h182C ; +1916 : douta <= 16'h182C ; +1917 : douta <= 16'h182C ; +1918 : douta <= 16'h182C ; +1919 : douta <= 16'h182C ; +1920 : douta <= 16'h182C ; +1921 : douta <= 16'h182C ; +1922 : douta <= 16'h182C ; +1923 : douta <= 16'h182C ; +1924 : douta <= 16'h182C ; +1925 : douta <= 16'h182C ; +1926 : douta <= 16'h182C ; +1927 : douta <= 16'h182C ; +1928 : douta <= 16'h182C ; +1929 : douta <= 16'h182C ; +1930 : douta <= 16'h182C ; +1931 : douta <= 16'h182C ; +1932 : douta <= 16'h182C ; +1933 : douta <= 16'h182C ; +1934 : douta <= 16'h182C ; +1935 : douta <= 16'h172C ; +1936 : douta <= 16'h172C ; +1937 : douta <= 16'h172C ; +1938 : douta <= 16'h172C ; +1939 : douta <= 16'h172C ; +1940 : douta <= 16'h172C ; +1941 : douta <= 16'h172C ; +1942 : douta <= 16'h172C ; +1943 : douta <= 16'h152C ; +1944 : douta <= 16'h152C ; +1945 : douta <= 16'h152C ; +1946 : douta <= 16'h152C ; +1947 : douta <= 16'h152C ; +1948 : douta <= 16'h162C ; +1949 : douta <= 16'h162C ; +1950 : douta <= 16'h162C ; +1951 : douta <= 16'h162C ; +1952 : douta <= 16'h162C ; +1953 : douta <= 16'h162C ; +1954 : douta <= 16'h162C ; +1955 : douta <= 16'h162C ; +1956 : douta <= 16'h162C ; +1957 : douta <= 16'h162C ; +1958 : douta <= 16'h162C ; +1959 : douta <= 16'h162C ; +1960 : douta <= 16'h162C ; +1961 : douta <= 16'h162C ; +1962 : douta <= 16'h162C ; +1963 : douta <= 16'h162C ; +1964 : douta <= 16'h162C ; +1965 : douta <= 16'h162C ; +1966 : douta <= 16'h162C ; +1967 : douta <= 16'h162C ; +1968 : douta <= 16'h162C ; +1969 : douta <= 16'h162C ; +1970 : douta <= 16'h162C ; +1971 : douta <= 16'h162C ; +1972 : douta <= 16'h152C ; +1973 : douta <= 16'h152C ; +1974 : douta <= 16'h152C ; +1975 : douta <= 16'h152C ; +1976 : douta <= 16'h152C ; +1977 : douta <= 16'h152C ; +1978 : douta <= 16'h152C ; +1979 : douta <= 16'h152C ; +1980 : douta <= 16'h152C ; +1981 : douta <= 16'h152C ; +1982 : douta <= 16'h152C ; +1983 : douta <= 16'h152C ; +1984 : douta <= 16'h152C ; +1985 : douta <= 16'h152C ; +1986 : douta <= 16'h152C ; +1987 : douta <= 16'h142C ; +1988 : douta <= 16'h142C ; +1989 : douta <= 16'h152C ; +1990 : douta <= 16'h152C ; +1991 : douta <= 16'h152C ; +1992 : douta <= 16'h152C ; +1993 : douta <= 16'h152C ; +1994 : douta <= 16'h152C ; +1995 : douta <= 16'h152C ; +1996 : douta <= 16'h152C ; +1997 : douta <= 16'h152C ; +1998 : douta <= 16'h152C ; +1999 : douta <= 16'h152C ; +2000 : douta <= 16'h152C ; +2001 : douta <= 16'h152C ; +2002 : douta <= 16'h142C ; +2003 : douta <= 16'h142C ; +2004 : douta <= 16'h142C ; +2005 : douta <= 16'h142C ; +2006 : douta <= 16'h142C ; +2007 : douta <= 16'h142C ; +2008 : douta <= 16'h142C ; +2009 : douta <= 16'h142C ; +2010 : douta <= 16'h142C ; +2011 : douta <= 16'h142C ; +2012 : douta <= 16'h142C ; +2013 : douta <= 16'h142C ; +2014 : douta <= 16'h142C ; +2015 : douta <= 16'h142C ; +2016 : douta <= 16'h142C ; +2017 : douta <= 16'h142C ; +2018 : douta <= 16'h142C ; +2019 : douta <= 16'h122C ; +2020 : douta <= 16'h132C ; +2021 : douta <= 16'h142C ; +2022 : douta <= 16'h142C ; +2023 : douta <= 16'h142C ; +2024 : douta <= 16'h142C ; +2025 : douta <= 16'h142C ; +2026 : douta <= 16'h142C ; +2027 : douta <= 16'h132C ; +2028 : douta <= 16'h132C ; +2029 : douta <= 16'h132C ; +2030 : douta <= 16'h132C ; +2031 : douta <= 16'h132C ; +2032 : douta <= 16'h132C ; +2033 : douta <= 16'h132C ; +2034 : douta <= 16'h132C ; +2035 : douta <= 16'h132C ; +2036 : douta <= 16'h132C ; +2037 : douta <= 16'h122C ; +2038 : douta <= 16'h132C ; +2039 : douta <= 16'h122C ; +2040 : douta <= 16'h122C ; +2041 : douta <= 16'h122C ; +2042 : douta <= 16'h122C ; +2043 : douta <= 16'h112C ; +2044 : douta <= 16'h122C ; +2045 : douta <= 16'h112C ; +2046 : douta <= 16'h122C ; +2047 : douta <= 16'h122C ; +2048 : douta <= 16'h122C ; +2049 : douta <= 16'h122C ; +2050 : douta <= 16'h122C ; +2051 : douta <= 16'h122C ; +2052 : douta <= 16'h122C ; +2053 : douta <= 16'h122C ; +2054 : douta <= 16'h122C ; +2055 : douta <= 16'h122C ; +2056 : douta <= 16'h122C ; +2057 : douta <= 16'h122C ; +2058 : douta <= 16'h122C ; +2059 : douta <= 16'h122C ; +2060 : douta <= 16'h122C ; +2061 : douta <= 16'h122C ; +2062 : douta <= 16'h122C ; +2063 : douta <= 16'h122C ; +2064 : douta <= 16'h122C ; +2065 : douta <= 16'h122C ; +2066 : douta <= 16'h112C ; +2067 : douta <= 16'h112C ; +2068 : douta <= 16'h112C ; +2069 : douta <= 16'h112C ; +2070 : douta <= 16'h112C ; +2071 : douta <= 16'h112C ; +2072 : douta <= 16'h112C ; +2073 : douta <= 16'h112C ; +2074 : douta <= 16'h112C ; +2075 : douta <= 16'h112C ; +2076 : douta <= 16'h112C ; +2077 : douta <= 16'h112C ; +2078 : douta <= 16'h112C ; +2079 : douta <= 16'h112C ; +2080 : douta <= 16'h112C ; +2081 : douta <= 16'h102C ; +2082 : douta <= 16'h102C ; +2083 : douta <= 16'h102C ; +2084 : douta <= 16'h102C ; +2085 : douta <= 16'h112C ; +2086 : douta <= 16'h112C ; +2087 : douta <= 16'h112C ; +2088 : douta <= 16'h112C ; +2089 : douta <= 16'h112C ; +2090 : douta <= 16'h112C ; +2091 : douta <= 16'h0F2C ; +2092 : douta <= 16'h112C ; +2093 : douta <= 16'h112C ; +2094 : douta <= 16'h112C ; +2095 : douta <= 16'h102C ; +2096 : douta <= 16'h102C ; +2097 : douta <= 16'h102C ; +2098 : douta <= 16'h102C ; +2099 : douta <= 16'h102C ; +2100 : douta <= 16'h102C ; +2101 : douta <= 16'h102C ; +2102 : douta <= 16'h102C ; +2103 : douta <= 16'h102C ; +2104 : douta <= 16'h102C ; +2105 : douta <= 16'h102C ; +2106 : douta <= 16'h102C ; +2107 : douta <= 16'h102C ; +2108 : douta <= 16'h0E2C ; +2109 : douta <= 16'h102C ; +2110 : douta <= 16'h102C ; +2111 : douta <= 16'h102C ; +2112 : douta <= 16'h102C ; +2113 : douta <= 16'h102C ; +2114 : douta <= 16'h102C ; +2115 : douta <= 16'h102C ; +2116 : douta <= 16'h102C ; +2117 : douta <= 16'h102C ; +2118 : douta <= 16'h102C ; +2119 : douta <= 16'h102C ; +2120 : douta <= 16'h102C ; +2121 : douta <= 16'h102C ; +2122 : douta <= 16'h102C ; +2123 : douta <= 16'h102C ; +2124 : douta <= 16'h0F2C ; +2125 : douta <= 16'h0F2C ; +2126 : douta <= 16'h0F2C ; +2127 : douta <= 16'h0E2C ; +2128 : douta <= 16'h0F2C ; +2129 : douta <= 16'h0F2C ; +2130 : douta <= 16'h0F2C ; +2131 : douta <= 16'h0E2C ; +2132 : douta <= 16'h0E2C ; +2133 : douta <= 16'h0D2C ; +2134 : douta <= 16'h0D2C ; +2135 : douta <= 16'h0D2C ; +2136 : douta <= 16'h0E2C ; +2137 : douta <= 16'h0E2C ; +2138 : douta <= 16'h0E2C ; +2139 : douta <= 16'h0E2C ; +2140 : douta <= 16'h0E2C ; +2141 : douta <= 16'h0E2C ; +2142 : douta <= 16'h0E2C ; +2143 : douta <= 16'h0E2C ; +2144 : douta <= 16'h0E2C ; +2145 : douta <= 16'h0E2C ; +2146 : douta <= 16'h0E2C ; +2147 : douta <= 16'h0E2C ; +2148 : douta <= 16'h0E2C ; +2149 : douta <= 16'h0E2C ; +2150 : douta <= 16'h0E2C ; +2151 : douta <= 16'h0E2C ; +2152 : douta <= 16'h0E2C ; +2153 : douta <= 16'h0E2C ; +2154 : douta <= 16'h0E2C ; +2155 : douta <= 16'h0E2C ; +2156 : douta <= 16'h0E2C ; +2157 : douta <= 16'h0E2C ; +2158 : douta <= 16'h0D2C ; +2159 : douta <= 16'h0D2C ; +2160 : douta <= 16'h0D2C ; +2161 : douta <= 16'h0D2C ; +2162 : douta <= 16'h0D2C ; +2163 : douta <= 16'h0D2C ; +2164 : douta <= 16'h0D2C ; +2165 : douta <= 16'h0D2C ; +2166 : douta <= 16'h0D2C ; +2167 : douta <= 16'h0D2C ; +2168 : douta <= 16'h0D2C ; +2169 : douta <= 16'h0D2C ; +2170 : douta <= 16'h0D2C ; +2171 : douta <= 16'h0D2C ; +2172 : douta <= 16'h0C2C ; +2173 : douta <= 16'h0C2C ; +2174 : douta <= 16'h0C2C ; +2175 : douta <= 16'h0D2C ; +2176 : douta <= 16'h0C2C ; +2177 : douta <= 16'h0D2C ; +2178 : douta <= 16'h0D2C ; +2179 : douta <= 16'h0D2C ; +2180 : douta <= 16'h0D2C ; +2181 : douta <= 16'h0D2C ; +2182 : douta <= 16'h0D2C ; +2183 : douta <= 16'h0D2C ; +2184 : douta <= 16'h0D2C ; +2185 : douta <= 16'h0D2C ; +2186 : douta <= 16'h0D2C ; +2187 : douta <= 16'h0D2C ; +2188 : douta <= 16'h0D2C ; +2189 : douta <= 16'h0C2C ; +2190 : douta <= 16'h0C2C ; +2191 : douta <= 16'h0C2C ; +2192 : douta <= 16'h0C2C ; +2193 : douta <= 16'h0C2C ; +2194 : douta <= 16'h0C2C ; +2195 : douta <= 16'h0C2C ; +2196 : douta <= 16'h0B2C ; +2197 : douta <= 16'h0B2C ; +2198 : douta <= 16'h0B2C ; +2199 : douta <= 16'h0C2C ; +2200 : douta <= 16'h0C2C ; +2201 : douta <= 16'h0C2C ; +2202 : douta <= 16'h0C2C ; +2203 : douta <= 16'h0C2C ; +2204 : douta <= 16'h0C2C ; +2205 : douta <= 16'h0C2C ; +2206 : douta <= 16'h0C2C ; +2207 : douta <= 16'h0C2C ; +2208 : douta <= 16'h0C2C ; +2209 : douta <= 16'h0C2C ; +2210 : douta <= 16'h0C2C ; +2211 : douta <= 16'h0C2C ; +2212 : douta <= 16'h0C2C ; +2213 : douta <= 16'h0C2C ; +2214 : douta <= 16'h0C2C ; +2215 : douta <= 16'h0C2C ; +2216 : douta <= 16'h0C2C ; +2217 : douta <= 16'h0C2C ; +2218 : douta <= 16'h0C2C ; +2219 : douta <= 16'h0C2C ; +2220 : douta <= 16'h0B2C ; +2221 : douta <= 16'h0B2C ; +2222 : douta <= 16'h0B2C ; +2223 : douta <= 16'h0B2C ; +2224 : douta <= 16'h0B2C ; +2225 : douta <= 16'h0B2C ; +2226 : douta <= 16'h0A2C ; +2227 : douta <= 16'h0A2C ; +2228 : douta <= 16'h0A2C ; +2229 : douta <= 16'h0A2C ; +2230 : douta <= 16'h0A2C ; +2231 : douta <= 16'h0A2C ; +2232 : douta <= 16'h0A2C ; +2233 : douta <= 16'h0A2C ; +2234 : douta <= 16'h92C ; +2235 : douta <= 16'h0A2C ; +2236 : douta <= 16'h0A2C ; +2237 : douta <= 16'h92C ; +2238 : douta <= 16'h0A2C ; +2239 : douta <= 16'h0A2C ; +2240 : douta <= 16'h0A2C ; +2241 : douta <= 16'h0A2C ; +2242 : douta <= 16'h0A2C ; +2243 : douta <= 16'h0A2C ; +2244 : douta <= 16'h0A2C ; +2245 : douta <= 16'h0A2C ; +2246 : douta <= 16'h0A2C ; +2247 : douta <= 16'h0A2C ; +2248 : douta <= 16'h0A2C ; +2249 : douta <= 16'h0A2C ; +2250 : douta <= 16'h0A2C ; +2251 : douta <= 16'h0A2C ; +2252 : douta <= 16'h0A2C ; +2253 : douta <= 16'h92C ; +2254 : douta <= 16'h0A2C ; +2255 : douta <= 16'h92C ; +2256 : douta <= 16'h92C ; +2257 : douta <= 16'h92C ; +2258 : douta <= 16'h92C ; +2259 : douta <= 16'h92C ; +2260 : douta <= 16'h92C ; +2261 : douta <= 16'h92C ; +2262 : douta <= 16'h92C ; +2263 : douta <= 16'h92C ; +2264 : douta <= 16'h92C ; +2265 : douta <= 16'h92C ; +2266 : douta <= 16'h92C ; +2267 : douta <= 16'h92C ; +2268 : douta <= 16'h92C ; +2269 : douta <= 16'h92C ; +2270 : douta <= 16'h82C ; +2271 : douta <= 16'h82C ; +2272 : douta <= 16'h92C ; +2273 : douta <= 16'h92C ; +2274 : douta <= 16'h82C ; +2275 : douta <= 16'h92C ; +2276 : douta <= 16'h92C ; +2277 : douta <= 16'h92C ; +2278 : douta <= 16'h92C ; +2279 : douta <= 16'h92C ; +2280 : douta <= 16'h92C ; +2281 : douta <= 16'h92C ; +2282 : douta <= 16'h92C ; +2283 : douta <= 16'h92C ; +2284 : douta <= 16'h92C ; +2285 : douta <= 16'h92C ; +2286 : douta <= 16'h92C ; +2287 : douta <= 16'h82C ; +2288 : douta <= 16'h82C ; +2289 : douta <= 16'h82C ; +2290 : douta <= 16'h82C ; +2291 : douta <= 16'h82C ; +2292 : douta <= 16'h82C ; +2293 : douta <= 16'h82C ; +2294 : douta <= 16'h82C ; +2295 : douta <= 16'h82C ; +2296 : douta <= 16'h82C ; +2297 : douta <= 16'h82C ; +2298 : douta <= 16'h82C ; +2299 : douta <= 16'h82C ; +2300 : douta <= 16'h82C ; +2301 : douta <= 16'h82C ; +2302 : douta <= 16'h82C ; +2303 : douta <= 16'h82C ; +2304 : douta <= 16'h82C ; +2305 : douta <= 16'h82C ; +2306 : douta <= 16'h82C ; +2307 : douta <= 16'h82C ; +2308 : douta <= 16'h82C ; +2309 : douta <= 16'h82C ; +2310 : douta <= 16'h82C ; +2311 : douta <= 16'h82C ; +2312 : douta <= 16'h72C ; +2313 : douta <= 16'h72C ; +2314 : douta <= 16'h82C ; +2315 : douta <= 16'h82C ; +2316 : douta <= 16'h72C ; +2317 : douta <= 16'h72C ; +2318 : douta <= 16'h72C ; +2319 : douta <= 16'h72C ; +2320 : douta <= 16'h72C ; +2321 : douta <= 16'h72C ; +2322 : douta <= 16'h72C ; +2323 : douta <= 16'h72C ; +2324 : douta <= 16'h62C ; +2325 : douta <= 16'h62C ; +2326 : douta <= 16'h62C ; +2327 : douta <= 16'h52C ; +2328 : douta <= 16'h52C ; +2329 : douta <= 16'h52C ; +2330 : douta <= 16'h52C ; +2331 : douta <= 16'h62C ; +2332 : douta <= 16'h62C ; +2333 : douta <= 16'h62C ; +2334 : douta <= 16'h62C ; +2335 : douta <= 16'h62C ; +2336 : douta <= 16'h62C ; +2337 : douta <= 16'h62C ; +2338 : douta <= 16'h62C ; +2339 : douta <= 16'h62C ; +2340 : douta <= 16'h62C ; +2341 : douta <= 16'h62C ; +2342 : douta <= 16'h62C ; +2343 : douta <= 16'h62C ; +2344 : douta <= 16'h62C ; +2345 : douta <= 16'h62C ; +2346 : douta <= 16'h62C ; +2347 : douta <= 16'h62C ; +2348 : douta <= 16'h62C ; +2349 : douta <= 16'h62C ; +2350 : douta <= 16'h62C ; +2351 : douta <= 16'h62C ; +2352 : douta <= 16'h52C ; +2353 : douta <= 16'h52C ; +2354 : douta <= 16'h52C ; +2355 : douta <= 16'h52C ; +2356 : douta <= 16'h52C ; +2357 : douta <= 16'h52C ; +2358 : douta <= 16'h52C ; +2359 : douta <= 16'h52C ; +2360 : douta <= 16'h52C ; +2361 : douta <= 16'h52C ; +2362 : douta <= 16'h52C ; +2363 : douta <= 16'h52C ; +2364 : douta <= 16'h52C ; +2365 : douta <= 16'h52C ; +2366 : douta <= 16'h42C ; +2367 : douta <= 16'h42C ; +2368 : douta <= 16'h42C ; +2369 : douta <= 16'h42C ; +2370 : douta <= 16'h52C ; +2371 : douta <= 16'h52C ; +2372 : douta <= 16'h52C ; +2373 : douta <= 16'h52C ; +2374 : douta <= 16'h52C ; +2375 : douta <= 16'h52C ; +2376 : douta <= 16'h52C ; +2377 : douta <= 16'h52C ; +2378 : douta <= 16'h52C ; +2379 : douta <= 16'h52C ; +2380 : douta <= 16'h52C ; +2381 : douta <= 16'h52C ; +2382 : douta <= 16'h52C ; +2383 : douta <= 16'h42C ; +2384 : douta <= 16'h42C ; +2385 : douta <= 16'h42C ; +2386 : douta <= 16'h42C ; +2387 : douta <= 16'h42C ; +2388 : douta <= 16'h42C ; +2389 : douta <= 16'h42C ; +2390 : douta <= 16'h42C ; +2391 : douta <= 16'h42C ; +2392 : douta <= 16'h42C ; +2393 : douta <= 16'h42C ; +2394 : douta <= 16'h42C ; +2395 : douta <= 16'h42C ; +2396 : douta <= 16'h42C ; +2397 : douta <= 16'h42C ; +2398 : douta <= 16'h42C ; +2399 : douta <= 16'h42C ; +2400 : douta <= 16'h42C ; +2401 : douta <= 16'h22C ; +2402 : douta <= 16'h42C ; +2403 : douta <= 16'h42C ; +2404 : douta <= 16'h42C ; +2405 : douta <= 16'h42C ; +2406 : douta <= 16'h42C ; +2407 : douta <= 16'h42C ; +2408 : douta <= 16'h42C ; +2409 : douta <= 16'h42C ; +2410 : douta <= 16'h42C ; +2411 : douta <= 16'h42C ; +2412 : douta <= 16'h42C ; +2413 : douta <= 16'h32C ; +2414 : douta <= 16'h32C ; +2415 : douta <= 16'h32C ; +2416 : douta <= 16'h32C ; +2417 : douta <= 16'h32C ; +2418 : douta <= 16'h32C ; +2419 : douta <= 16'h32C ; +2420 : douta <= 16'h32C ; +2421 : douta <= 16'h32C ; +2422 : douta <= 16'h32C ; +2423 : douta <= 16'h22C ; +2424 : douta <= 16'h22C ; +2425 : douta <= 16'h22C ; +2426 : douta <= 16'h22C ; +2427 : douta <= 16'h22C ; +2428 : douta <= 16'h12C ; +2429 : douta <= 16'h22C ; +2430 : douta <= 16'h22C ; +2431 : douta <= 16'h22C ; +2432 : douta <= 16'h22C ; +2433 : douta <= 16'h22C ; +2434 : douta <= 16'h22C ; +2435 : douta <= 16'h22C ; +2436 : douta <= 16'h22C ; +2437 : douta <= 16'h22C ; +2438 : douta <= 16'h22C ; +2439 : douta <= 16'h22C ; +2440 : douta <= 16'h22C ; +2441 : douta <= 16'h22C ; +2442 : douta <= 16'h22C ; +2443 : douta <= 16'h22C ; +2444 : douta <= 16'h22C ; +2445 : douta <= 16'h22C ; +2446 : douta <= 16'h22C ; +2447 : douta <= 16'h22C ; +2448 : douta <= 16'h12C ; +2449 : douta <= 16'h12C ; +2450 : douta <= 16'h12C ; +2451 : douta <= 16'h12C ; +2452 : douta <= 16'h12C ; +2453 : douta <= 16'h12C ; +2454 : douta <= 16'h12C ; +2455 : douta <= 16'h12C ; +2456 : douta <= 16'h12C ; +2457 : douta <= 16'h12C ; +2458 : douta <= 16'h12C ; +2459 : douta <= 16'h12C ; +2460 : douta <= 16'h12C ; +2461 : douta <= 16'h12C ; +2462 : douta <= 16'h12C ; +2463 : douta <= 16'h02C ; +2464 : douta <= 16'h02C ; +2465 : douta <= 16'h12C ; +2466 : douta <= 16'h02C ; +2467 : douta <= 16'h12C ; +2468 : douta <= 16'h12C ; +2469 : douta <= 16'h12C ; +2470 : douta <= 16'h12C ; +2471 : douta <= 16'h12C ; +2472 : douta <= 16'h12C ; +2473 : douta <= 16'h12C ; +2474 : douta <= 16'h12C ; +2475 : douta <= 16'h12C ; +2476 : douta <= 16'h12C ; +2477 : douta <= 16'h12C ; +2478 : douta <= 16'h12C ; +2479 : douta <= 16'h02C ; +2480 : douta <= 16'h12C ; +2481 : douta <= 16'h02C ; +2482 : douta <= 16'h02C ; +2483 : douta <= 16'h02C ; +2484 : douta <= 16'hD040 ; +2485 : douta <= 16'h02C ; +2486 : douta <= 16'h02C ; +2487 : douta <= 16'h02C ; +2488 : douta <= 16'h02C ; +2489 : douta <= 16'h02C ; +2490 : douta <= 16'h02C ; +2491 : douta <= 16'h02C ; +2492 : douta <= 16'h02C ; +2493 : douta <= 16'hD040 ; +2494 : douta <= 16'h02C ; +2495 : douta <= 16'h02C ; +2496 : douta <= 16'h02C ; +2497 : douta <= 16'h02C ; +2498 : douta <= 16'h02C ; +2499 : douta <= 16'h02C ; +2500 : douta <= 16'h02C ; +2501 : douta <= 16'h02C ; +2502 : douta <= 16'h02C ; +2503 : douta <= 16'h02C ; +2504 : douta <= 16'h02C ; +2505 : douta <= 16'h02C ; +2506 : douta <= 16'h02C ; +2507 : douta <= 16'hCE40 ; +2508 : douta <= 16'h02C ; +2509 : douta <= 16'h02C ; +2510 : douta <= 16'hCE40 ; +2511 : douta <= 16'hCD40 ; +2512 : douta <= 16'hCD40 ; +2513 : douta <= 16'hCD40 ; +2514 : douta <= 16'hCD40 ; +2515 : douta <= 16'hCD40 ; +2516 : douta <= 16'hCD40 ; +2517 : douta <= 16'hCD40 ; +2518 : douta <= 16'hCD40 ; +2519 : douta <= 16'hCD40 ; +2520 : douta <= 16'hCD40 ; +2521 : douta <= 16'hCD40 ; +2522 : douta <= 16'hCC40 ; +2523 : douta <= 16'hCC40 ; +2524 : douta <= 16'hCC40 ; +2525 : douta <= 16'hCD40 ; +2526 : douta <= 16'hCD40 ; +2527 : douta <= 16'hCD40 ; +2528 : douta <= 16'hCD40 ; +2529 : douta <= 16'hCD40 ; +2530 : douta <= 16'hCC40 ; +2531 : douta <= 16'hCB40 ; +2532 : douta <= 16'hCB40 ; +2533 : douta <= 16'hCB40 ; +2534 : douta <= 16'hCB40 ; +2535 : douta <= 16'hCC40 ; +2536 : douta <= 16'hCC40 ; +2537 : douta <= 16'hCC40 ; +2538 : douta <= 16'hCC40 ; +2539 : douta <= 16'hCC40 ; +2540 : douta <= 16'hCC40 ; +2541 : douta <= 16'hCC40 ; +2542 : douta <= 16'hCC40 ; +2543 : douta <= 16'hCC40 ; +2544 : douta <= 16'hCC40 ; +2545 : douta <= 16'hCC40 ; +2546 : douta <= 16'hCC40 ; +2547 : douta <= 16'hCC40 ; +2548 : douta <= 16'hCC40 ; +2549 : douta <= 16'hCC40 ; +2550 : douta <= 16'hCB40 ; +2551 : douta <= 16'hCB40 ; +2552 : douta <= 16'hCB40 ; +2553 : douta <= 16'hCB40 ; +2554 : douta <= 16'hCB40 ; +2555 : douta <= 16'hCB40 ; +2556 : douta <= 16'hCA40 ; +2557 : douta <= 16'hCA40 ; +2558 : douta <= 16'hCA40 ; +2559 : douta <= 16'hCA40 ; +2560 : douta <= 16'hCA40 ; +2561 : douta <= 16'hCA40 ; +2562 : douta <= 16'hCA40 ; +2563 : douta <= 16'hCA40 ; +2564 : douta <= 16'hCA40 ; +2565 : douta <= 16'hCA40 ; +2566 : douta <= 16'hCA40 ; +2567 : douta <= 16'hC940 ; +2568 : douta <= 16'hCA40 ; +2569 : douta <= 16'hCA40 ; +2570 : douta <= 16'hCA40 ; +2571 : douta <= 16'hCA40 ; +2572 : douta <= 16'hCA40 ; +2573 : douta <= 16'hC940 ; +2574 : douta <= 16'hCA40 ; +2575 : douta <= 16'hC940 ; +2576 : douta <= 16'hC940 ; +2577 : douta <= 16'hC940 ; +2578 : douta <= 16'hC940 ; +2579 : douta <= 16'hC940 ; +2580 : douta <= 16'hC940 ; +2581 : douta <= 16'hC940 ; +2582 : douta <= 16'hC940 ; +2583 : douta <= 16'hC940 ; +2584 : douta <= 16'hC940 ; +2585 : douta <= 16'hC940 ; +2586 : douta <= 16'hC940 ; +2587 : douta <= 16'hC940 ; +2588 : douta <= 16'hC940 ; +2589 : douta <= 16'hC840 ; +2590 : douta <= 16'hC940 ; +2591 : douta <= 16'hC940 ; +2592 : douta <= 16'hC840 ; +2593 : douta <= 16'hC840 ; +2594 : douta <= 16'hC940 ; +2595 : douta <= 16'hC940 ; +2596 : douta <= 16'hC940 ; +2597 : douta <= 16'hC940 ; +2598 : douta <= 16'hC840 ; +2599 : douta <= 16'hC840 ; +2600 : douta <= 16'hC840 ; +2601 : douta <= 16'hC840 ; +2602 : douta <= 16'hC840 ; +2603 : douta <= 16'hC840 ; +2604 : douta <= 16'hC840 ; +2605 : douta <= 16'hC840 ; +2606 : douta <= 16'hC840 ; +2607 : douta <= 16'hC840 ; +2608 : douta <= 16'hC740 ; +2609 : douta <= 16'hC740 ; +2610 : douta <= 16'hC740 ; +2611 : douta <= 16'hC840 ; +2612 : douta <= 16'hC840 ; +2613 : douta <= 16'hC840 ; +2614 : douta <= 16'hC840 ; +2615 : douta <= 16'hC840 ; +2616 : douta <= 16'hC840 ; +2617 : douta <= 16'hC640 ; +2618 : douta <= 16'hC640 ; +2619 : douta <= 16'hC640 ; +2620 : douta <= 16'hC640 ; +2621 : douta <= 16'hC640 ; +2622 : douta <= 16'hC640 ; +2623 : douta <= 16'hC640 ; +2624 : douta <= 16'hC640 ; +2625 : douta <= 16'hC640 ; +2626 : douta <= 16'hC640 ; +2627 : douta <= 16'hC640 ; +2628 : douta <= 16'hC540 ; +2629 : douta <= 16'hC540 ; +2630 : douta <= 16'hC640 ; +2631 : douta <= 16'hC640 ; +2632 : douta <= 16'hC640 ; +2633 : douta <= 16'hC640 ; +2634 : douta <= 16'hC640 ; +2635 : douta <= 16'hC540 ; +2636 : douta <= 16'hC640 ; +2637 : douta <= 16'hC640 ; +2638 : douta <= 16'hC540 ; +2639 : douta <= 16'hC540 ; +2640 : douta <= 16'hC540 ; +2641 : douta <= 16'hC540 ; +2642 : douta <= 16'hC540 ; +2643 : douta <= 16'hC540 ; +2644 : douta <= 16'hC540 ; +2645 : douta <= 16'hC540 ; +2646 : douta <= 16'hC540 ; +2647 : douta <= 16'hC540 ; +2648 : douta <= 16'hC540 ; +2649 : douta <= 16'hC540 ; +2650 : douta <= 16'hC540 ; +2651 : douta <= 16'hC540 ; +2652 : douta <= 16'hC440 ; +2653 : douta <= 16'hC440 ; +2654 : douta <= 16'hC440 ; +2655 : douta <= 16'hC540 ; +2656 : douta <= 16'hC540 ; +2657 : douta <= 16'hC540 ; +2658 : douta <= 16'hC540 ; +2659 : douta <= 16'hC540 ; +2660 : douta <= 16'hC540 ; +2661 : douta <= 16'hC440 ; +2662 : douta <= 16'hC440 ; +2663 : douta <= 16'hC440 ; +2664 : douta <= 16'hC440 ; +2665 : douta <= 16'hC440 ; +2666 : douta <= 16'hC440 ; +2667 : douta <= 16'hC440 ; +2668 : douta <= 16'hC340 ; +2669 : douta <= 16'hC340 ; +2670 : douta <= 16'hC340 ; +2671 : douta <= 16'hC440 ; +2672 : douta <= 16'hC440 ; +2673 : douta <= 16'hC440 ; +2674 : douta <= 16'hC440 ; +2675 : douta <= 16'hC440 ; +2676 : douta <= 16'hC440 ; +2677 : douta <= 16'hC440 ; +2678 : douta <= 16'hC440 ; +2679 : douta <= 16'hC440 ; +2680 : douta <= 16'hC340 ; +2681 : douta <= 16'hC340 ; +2682 : douta <= 16'hC340 ; +2683 : douta <= 16'hC340 ; +2684 : douta <= 16'hC340 ; +2685 : douta <= 16'hC340 ; +2686 : douta <= 16'hC340 ; +2687 : douta <= 16'hC340 ; +2688 : douta <= 16'hC240 ; +2689 : douta <= 16'hC240 ; +2690 : douta <= 16'hC240 ; +2691 : douta <= 16'hC240 ; +2692 : douta <= 16'hC240 ; +2693 : douta <= 16'hC240 ; +2694 : douta <= 16'hC240 ; +2695 : douta <= 16'hC240 ; +2696 : douta <= 16'hC140 ; +2697 : douta <= 16'hC240 ; +2698 : douta <= 16'hC240 ; +2699 : douta <= 16'hC240 ; +2700 : douta <= 16'hC240 ; +2701 : douta <= 16'hC240 ; +2702 : douta <= 16'hC240 ; +2703 : douta <= 16'hC240 ; +2704 : douta <= 16'hC240 ; +2705 : douta <= 16'hC140 ; +2706 : douta <= 16'hC240 ; +2707 : douta <= 16'hC140 ; +2708 : douta <= 16'hC140 ; +2709 : douta <= 16'hC140 ; +2710 : douta <= 16'hC140 ; +2711 : douta <= 16'hC140 ; +2712 : douta <= 16'hC140 ; +2713 : douta <= 16'hC140 ; +2714 : douta <= 16'hC140 ; +2715 : douta <= 16'hC140 ; +2716 : douta <= 16'hC140 ; +2717 : douta <= 16'hC140 ; +2718 : douta <= 16'hC140 ; +2719 : douta <= 16'hC140 ; +2720 : douta <= 16'hC140 ; +2721 : douta <= 16'hC140 ; +2722 : douta <= 16'hC140 ; +2723 : douta <= 16'hC040 ; +2724 : douta <= 16'hC040 ; +2725 : douta <= 16'hC040 ; +2726 : douta <= 16'hC140 ; +2727 : douta <= 16'hC140 ; +2728 : douta <= 16'hC140 ; +2729 : douta <= 16'hC140 ; +2730 : douta <= 16'hC040 ; +2731 : douta <= 16'hC040 ; +2732 : douta <= 16'hC040 ; +2733 : douta <= 16'hC040 ; +2734 : douta <= 16'hC040 ; +2735 : douta <= 16'hC040 ; +2736 : douta <= 16'hC040 ; +2737 : douta <= 16'hC040 ; +2738 : douta <= 16'hC040 ; +2739 : douta <= 16'hC040 ; +2740 : douta <= 16'hC040 ; +2741 : douta <= 16'hC040 ; +2742 : douta <= 16'hC040 ; +2743 : douta <= 16'hC040 ; +2744 : douta <= 16'hBF40 ; +2745 : douta <= 16'hC040 ; +2746 : douta <= 16'hC040 ; +2747 : douta <= 16'hC040 ; +2748 : douta <= 16'hC040 ; +2749 : douta <= 16'hC040 ; +2750 : douta <= 16'hC040 ; +2751 : douta <= 16'hC040 ; +2752 : douta <= 16'hC040 ; +2753 : douta <= 16'hC040 ; +2754 : douta <= 16'hBE40 ; +2755 : douta <= 16'hBE40 ; +2756 : douta <= 16'hBE40 ; +2757 : douta <= 16'hBE40 ; +2758 : douta <= 16'hBE40 ; +2759 : douta <= 16'hBE40 ; +2760 : douta <= 16'hBE40 ; +2761 : douta <= 16'hBE40 ; +2762 : douta <= 16'hBE40 ; +2763 : douta <= 16'hBE40 ; +2764 : douta <= 16'hBE40 ; +2765 : douta <= 16'hBE40 ; +2766 : douta <= 16'hBE40 ; +2767 : douta <= 16'hBE40 ; +2768 : douta <= 16'hBD40 ; +2769 : douta <= 16'hBD40 ; +2770 : douta <= 16'hBE40 ; +2771 : douta <= 16'hBE40 ; +2772 : douta <= 16'hBE40 ; +2773 : douta <= 16'hBE40 ; +2774 : douta <= 16'hBE40 ; +2775 : douta <= 16'hBE40 ; +2776 : douta <= 16'hBE40 ; +2777 : douta <= 16'hBE40 ; +2778 : douta <= 16'hBD40 ; +2779 : douta <= 16'hBD40 ; +2780 : douta <= 16'hBD40 ; +2781 : douta <= 16'hBD40 ; +2782 : douta <= 16'hBD40 ; +2783 : douta <= 16'hBD40 ; +2784 : douta <= 16'hBD40 ; +2785 : douta <= 16'hBD40 ; +2786 : douta <= 16'hBD40 ; +2787 : douta <= 16'hBD40 ; +2788 : douta <= 16'hBD40 ; +2789 : douta <= 16'hBD40 ; +2790 : douta <= 16'hBD40 ; +2791 : douta <= 16'hBD40 ; +2792 : douta <= 16'hBC40 ; +2793 : douta <= 16'hBC40 ; +2794 : douta <= 16'hBC40 ; +2795 : douta <= 16'hBD40 ; +2796 : douta <= 16'hBC40 ; +2797 : douta <= 16'hBC40 ; +2798 : douta <= 16'hBC40 ; +2799 : douta <= 16'hBC40 ; +2800 : douta <= 16'hBB40 ; +2801 : douta <= 16'hBC40 ; +2802 : douta <= 16'hBB40 ; +2803 : douta <= 16'hBC40 ; +2804 : douta <= 16'hBC40 ; +2805 : douta <= 16'hBC40 ; +2806 : douta <= 16'hBC40 ; +2807 : douta <= 16'hBC40 ; +2808 : douta <= 16'hBC40 ; +2809 : douta <= 16'hBC40 ; +2810 : douta <= 16'hBC40 ; +2811 : douta <= 16'hBC40 ; +2812 : douta <= 16'hBC40 ; +2813 : douta <= 16'hBC40 ; +2814 : douta <= 16'hBC40 ; +2815 : douta <= 16'hBC40 ; +2816 : douta <= 16'hBC40 ; +2817 : douta <= 16'hBC40 ; +2818 : douta <= 16'hBC40 ; +2819 : douta <= 16'hBC40 ; +2820 : douta <= 16'hBB40 ; +2821 : douta <= 16'hBA40 ; +2822 : douta <= 16'hBA40 ; +2823 : douta <= 16'hBA40 ; +2824 : douta <= 16'hBA40 ; +2825 : douta <= 16'hBA40 ; +2826 : douta <= 16'hBA40 ; +2827 : douta <= 16'hBA40 ; +2828 : douta <= 16'hBA40 ; +2829 : douta <= 16'hBA40 ; +2830 : douta <= 16'hBA40 ; +2831 : douta <= 16'hBA40 ; +2832 : douta <= 16'hBA40 ; +2833 : douta <= 16'hBA40 ; +2834 : douta <= 16'hBA40 ; +2835 : douta <= 16'hB940 ; +2836 : douta <= 16'hB940 ; +2837 : douta <= 16'hBA40 ; +2838 : douta <= 16'hBA40 ; +2839 : douta <= 16'hBA40 ; +2840 : douta <= 16'hBA40 ; +2841 : douta <= 16'hB940 ; +2842 : douta <= 16'hB940 ; +2843 : douta <= 16'hB940 ; +2844 : douta <= 16'hB940 ; +2845 : douta <= 16'hB940 ; +2846 : douta <= 16'hB940 ; +2847 : douta <= 16'hB940 ; +2848 : douta <= 16'hB940 ; +2849 : douta <= 16'hB940 ; +2850 : douta <= 16'hB940 ; +2851 : douta <= 16'hB940 ; +2852 : douta <= 16'hB940 ; +2853 : douta <= 16'hB940 ; +2854 : douta <= 16'hB940 ; +2855 : douta <= 16'hB940 ; +2856 : douta <= 16'hB940 ; +2857 : douta <= 16'hB940 ; +2858 : douta <= 16'hB840 ; +2859 : douta <= 16'hB940 ; +2860 : douta <= 16'hB840 ; +2861 : douta <= 16'hB840 ; +2862 : douta <= 16'hB840 ; +2863 : douta <= 16'hB840 ; +2864 : douta <= 16'hB840 ; +2865 : douta <= 16'hB840 ; +2866 : douta <= 16'hB740 ; +2867 : douta <= 16'hB740 ; +2868 : douta <= 16'hB740 ; +2869 : douta <= 16'hB740 ; +2870 : douta <= 16'hB740 ; +2871 : douta <= 16'hB740 ; +2872 : douta <= 16'hB840 ; +2873 : douta <= 16'hB840 ; +2874 : douta <= 16'hB840 ; +2875 : douta <= 16'hB840 ; +2876 : douta <= 16'hB840 ; +2877 : douta <= 16'hB840 ; +2878 : douta <= 16'hB840 ; +2879 : douta <= 16'hB840 ; +2880 : douta <= 16'hB840 ; +2881 : douta <= 16'hB840 ; +2882 : douta <= 16'hB840 ; +2883 : douta <= 16'hB840 ; +2884 : douta <= 16'hB840 ; +2885 : douta <= 16'hB840 ; +2886 : douta <= 16'hB640 ; +2887 : douta <= 16'hB640 ; +2888 : douta <= 16'hB640 ; +2889 : douta <= 16'hB640 ; +2890 : douta <= 16'hB640 ; +2891 : douta <= 16'hB640 ; +2892 : douta <= 16'hB640 ; +2893 : douta <= 16'hB640 ; +2894 : douta <= 16'hB640 ; +2895 : douta <= 16'hB640 ; +2896 : douta <= 16'hB640 ; +2897 : douta <= 16'hB640 ; +2898 : douta <= 16'hB640 ; +2899 : douta <= 16'hB640 ; +2900 : douta <= 16'hB540 ; +2901 : douta <= 16'hB540 ; +2902 : douta <= 16'hB540 ; +2903 : douta <= 16'hB640 ; +2904 : douta <= 16'hB540 ; +2905 : douta <= 16'hB640 ; +2906 : douta <= 16'hB640 ; +2907 : douta <= 16'hB640 ; +2908 : douta <= 16'hB640 ; +2909 : douta <= 16'hB540 ; +2910 : douta <= 16'hB640 ; +2911 : douta <= 16'hB540 ; +2912 : douta <= 16'hB540 ; +2913 : douta <= 16'hB540 ; +2914 : douta <= 16'hB540 ; +2915 : douta <= 16'hB540 ; +2916 : douta <= 16'hB540 ; +2917 : douta <= 16'hB540 ; +2918 : douta <= 16'hB540 ; +2919 : douta <= 16'hB540 ; +2920 : douta <= 16'hB540 ; +2921 : douta <= 16'hB540 ; +2922 : douta <= 16'hB540 ; +2923 : douta <= 16'hB540 ; +2924 : douta <= 16'hB540 ; +2925 : douta <= 16'hB540 ; +2926 : douta <= 16'hB440 ; +2927 : douta <= 16'hB440 ; +2928 : douta <= 16'hB540 ; +2929 : douta <= 16'hB540 ; +2930 : douta <= 16'hB440 ; +2931 : douta <= 16'hB440 ; +2932 : douta <= 16'hB440 ; +2933 : douta <= 16'hB440 ; +2934 : douta <= 16'hB440 ; +2935 : douta <= 16'hB440 ; +2936 : douta <= 16'hB440 ; +2937 : douta <= 16'hB340 ; +2938 : douta <= 16'hB340 ; +2939 : douta <= 16'hB440 ; +2940 : douta <= 16'hB340 ; +2941 : douta <= 16'hB440 ; +2942 : douta <= 16'hB440 ; +2943 : douta <= 16'hB440 ; +2944 : douta <= 16'hB440 ; +2945 : douta <= 16'hB440 ; +2946 : douta <= 16'hB440 ; +2947 : douta <= 16'hB440 ; +2948 : douta <= 16'hB440 ; +2949 : douta <= 16'hB440 ; +2950 : douta <= 16'hB440 ; +2951 : douta <= 16'hB440 ; +2952 : douta <= 16'hB440 ; +2953 : douta <= 16'hB440 ; +2954 : douta <= 16'hB340 ; +2955 : douta <= 16'hB240 ; +2956 : douta <= 16'hB240 ; +2957 : douta <= 16'hB240 ; +2958 : douta <= 16'hB240 ; +2959 : douta <= 16'hB240 ; +2960 : douta <= 16'hB240 ; +2961 : douta <= 16'hB240 ; +2962 : douta <= 16'hB240 ; +2963 : douta <= 16'hB240 ; +2964 : douta <= 16'hB240 ; +2965 : douta <= 16'hB240 ; +2966 : douta <= 16'hB240 ; +2967 : douta <= 16'hB240 ; +2968 : douta <= 16'hB240 ; +2969 : douta <= 16'hB240 ; +2970 : douta <= 16'hB140 ; +2971 : douta <= 16'hB140 ; +2972 : douta <= 16'hB140 ; +2973 : douta <= 16'hB140 ; +2974 : douta <= 16'hB140 ; +2975 : douta <= 16'hB240 ; +2976 : douta <= 16'hB240 ; +2977 : douta <= 16'hB240 ; +2978 : douta <= 16'hB240 ; +2979 : douta <= 16'hB140 ; +2980 : douta <= 16'hB140 ; +2981 : douta <= 16'hB140 ; +2982 : douta <= 16'hB140 ; +2983 : douta <= 16'hB140 ; +2984 : douta <= 16'hB140 ; +2985 : douta <= 16'hB140 ; +2986 : douta <= 16'hB140 ; +2987 : douta <= 16'hB140 ; +2988 : douta <= 16'hB140 ; +2989 : douta <= 16'hB140 ; +2990 : douta <= 16'hB140 ; +2991 : douta <= 16'hB140 ; +2992 : douta <= 16'hB140 ; +2993 : douta <= 16'hB140 ; +2994 : douta <= 16'hB040 ; +2995 : douta <= 16'hB040 ; +2996 : douta <= 16'hB140 ; +2997 : douta <= 16'hB140 ; +2998 : douta <= 16'hB040 ; +2999 : douta <= 16'hB040 ; +3000 : douta <= 16'hB040 ; +3001 : douta <= 16'hB040 ; +3002 : douta <= 16'hB040 ; +3003 : douta <= 16'hB040 ; +3004 : douta <= 16'hB040 ; +3005 : douta <= 16'hB040 ; +3006 : douta <= 16'hB040 ; +3007 : douta <= 16'hB040 ; +3008 : douta <= 16'hB040 ; +3009 : douta <= 16'hB040 ; +3010 : douta <= 16'hB040 ; +3011 : douta <= 16'hB040 ; +3012 : douta <= 16'hB040 ; +3013 : douta <= 16'hB040 ; +3014 : douta <= 16'hB040 ; +3015 : douta <= 16'hB040 ; +3016 : douta <= 16'hB040 ; +3017 : douta <= 16'hB040 ; +3018 : douta <= 16'hB040 ; +3019 : douta <= 16'hB040 ; +3020 : douta <= 16'hB040 ; +3021 : douta <= 16'hB040 ; +3022 : douta <= 16'hB040 ; +3023 : douta <= 16'hB040 ; +3024 : douta <= 16'hB040 ; +3025 : douta <= 16'hAE40 ; +3026 : douta <= 16'hAE40 ; +3027 : douta <= 16'hAE40 ; +3028 : douta <= 16'hAE40 ; +3029 : douta <= 16'hAE40 ; +3030 : douta <= 16'hAE40 ; +3031 : douta <= 16'hAE40 ; +3032 : douta <= 16'hAE40 ; +3033 : douta <= 16'hAE40 ; +3034 : douta <= 16'hAE40 ; +3035 : douta <= 16'hAE40 ; +3036 : douta <= 16'hAD40 ; +3037 : douta <= 16'hAD40 ; +3038 : douta <= 16'hAD40 ; +3039 : douta <= 16'hAE40 ; +3040 : douta <= 16'hAE40 ; +3041 : douta <= 16'hAE40 ; +3042 : douta <= 16'hAE40 ; +3043 : douta <= 16'hAD40 ; +3044 : douta <= 16'hAE40 ; +3045 : douta <= 16'hAD40 ; +3046 : douta <= 16'hAD40 ; +3047 : douta <= 16'hAD40 ; +3048 : douta <= 16'hAD40 ; +3049 : douta <= 16'hAD40 ; +3050 : douta <= 16'hAD40 ; +3051 : douta <= 16'hAD40 ; +3052 : douta <= 16'hAD40 ; +3053 : douta <= 16'hAD40 ; +3054 : douta <= 16'hAD40 ; +3055 : douta <= 16'hAD40 ; +3056 : douta <= 16'hAD40 ; +3057 : douta <= 16'hAD40 ; +3058 : douta <= 16'hAD40 ; +3059 : douta <= 16'hAD40 ; +3060 : douta <= 16'hAC40 ; +3061 : douta <= 16'hAC40 ; +3062 : douta <= 16'hAC40 ; +3063 : douta <= 16'hAD40 ; +3064 : douta <= 16'hAC40 ; +3065 : douta <= 16'hAC40 ; +3066 : douta <= 16'hAC40 ; +3067 : douta <= 16'hAC40 ; +3068 : douta <= 16'hAC40 ; +3069 : douta <= 16'hAB40 ; +3070 : douta <= 16'hAB40 ; +3071 : douta <= 16'hAB40 ; +3072 : douta <= 16'hAB40 ; +3073 : douta <= 16'hAC40 ; +3074 : douta <= 16'hAB40 ; +3075 : douta <= 16'hAC40 ; +3076 : douta <= 16'hAC40 ; +3077 : douta <= 16'hAC40 ; +3078 : douta <= 16'hAC40 ; +3079 : douta <= 16'hAC40 ; +3080 : douta <= 16'hAC40 ; +3081 : douta <= 16'hAC40 ; +3082 : douta <= 16'hAC40 ; +3083 : douta <= 16'hAC40 ; +3084 : douta <= 16'hAC40 ; +3085 : douta <= 16'hAC40 ; +3086 : douta <= 16'hAC40 ; +3087 : douta <= 16'hAC40 ; +3088 : douta <= 16'hAC40 ; +3089 : douta <= 16'hAC40 ; +3090 : douta <= 16'hAA40 ; +3091 : douta <= 16'hAA40 ; +3092 : douta <= 16'hAA40 ; +3093 : douta <= 16'hAA40 ; +3094 : douta <= 16'hAA40 ; +3095 : douta <= 16'hAA40 ; +3096 : douta <= 16'hAA40 ; +3097 : douta <= 16'hAA40 ; +3098 : douta <= 16'hAA40 ; +3099 : douta <= 16'hAA40 ; +3100 : douta <= 16'hAA40 ; +3101 : douta <= 16'hAA40 ; +3102 : douta <= 16'hAA40 ; +3103 : douta <= 16'hAA40 ; +3104 : douta <= 16'hAA40 ; +3105 : douta <= 16'hAA40 ; +3106 : douta <= 16'hA940 ; +3107 : douta <= 16'hA940 ; +3108 : douta <= 16'hA940 ; +3109 : douta <= 16'hAA40 ; +3110 : douta <= 16'hAA40 ; +3111 : douta <= 16'hAA40 ; +3112 : douta <= 16'hA940 ; +3113 : douta <= 16'hA940 ; +3114 : douta <= 16'hA940 ; +3115 : douta <= 16'hA940 ; +3116 : douta <= 16'hA940 ; +3117 : douta <= 16'hA940 ; +3118 : douta <= 16'hA940 ; +3119 : douta <= 16'hA940 ; +3120 : douta <= 16'hA940 ; +3121 : douta <= 16'hA940 ; +3122 : douta <= 16'hA940 ; +3123 : douta <= 16'hA940 ; +3124 : douta <= 16'hA940 ; +3125 : douta <= 16'hA940 ; +3126 : douta <= 16'hA940 ; +3127 : douta <= 16'hA940 ; +3128 : douta <= 16'hA840 ; +3129 : douta <= 16'hA940 ; +3130 : douta <= 16'hA840 ; +3131 : douta <= 16'hA940 ; +3132 : douta <= 16'hA840 ; +3133 : douta <= 16'hA840 ; +3134 : douta <= 16'hA840 ; +3135 : douta <= 16'hA840 ; +3136 : douta <= 16'hA840 ; +3137 : douta <= 16'hA840 ; +3138 : douta <= 16'hA840 ; +3139 : douta <= 16'hA840 ; +3140 : douta <= 16'hA840 ; +3141 : douta <= 16'hA840 ; +3142 : douta <= 16'hA840 ; +3143 : douta <= 16'hA840 ; +3144 : douta <= 16'hA840 ; +3145 : douta <= 16'hA840 ; +3146 : douta <= 16'hA840 ; +3147 : douta <= 16'hA840 ; +3148 : douta <= 16'hA840 ; +3149 : douta <= 16'hA840 ; +3150 : douta <= 16'hA840 ; +3151 : douta <= 16'hA840 ; +3152 : douta <= 16'hA840 ; +3153 : douta <= 16'hA840 ; +3154 : douta <= 16'hA840 ; +3155 : douta <= 16'hA840 ; +3156 : douta <= 16'hA840 ; +3157 : douta <= 16'hA640 ; +3158 : douta <= 16'hA840 ; +3159 : douta <= 16'hA840 ; +3160 : douta <= 16'hA640 ; +3161 : douta <= 16'hA640 ; +3162 : douta <= 16'hA640 ; +3163 : douta <= 16'hA640 ; +3164 : douta <= 16'hA640 ; +3165 : douta <= 16'hA640 ; +3166 : douta <= 16'hA640 ; +3167 : douta <= 16'hA640 ; +3168 : douta <= 16'hA640 ; +3169 : douta <= 16'hA640 ; +3170 : douta <= 16'hA640 ; +3171 : douta <= 16'hA640 ; +3172 : douta <= 16'hA640 ; +3173 : douta <= 16'hA640 ; +3174 : douta <= 16'hA640 ; +3175 : douta <= 16'hA640 ; +3176 : douta <= 16'hA540 ; +3177 : douta <= 16'hA640 ; +3178 : douta <= 16'hA640 ; +3179 : douta <= 16'hA640 ; +3180 : douta <= 16'hA640 ; +3181 : douta <= 16'hA640 ; +3182 : douta <= 16'hA640 ; +3183 : douta <= 16'hA540 ; +3184 : douta <= 16'hA540 ; +3185 : douta <= 16'hA540 ; +3186 : douta <= 16'hA540 ; +3187 : douta <= 16'hA540 ; +3188 : douta <= 16'hA540 ; +3189 : douta <= 16'hA540 ; +3190 : douta <= 16'hA540 ; +3191 : douta <= 16'hA540 ; +3192 : douta <= 16'hA540 ; +3193 : douta <= 16'hA540 ; +3194 : douta <= 16'hA540 ; +3195 : douta <= 16'hA540 ; +3196 : douta <= 16'hA540 ; +3197 : douta <= 16'hA540 ; +3198 : douta <= 16'hA440 ; +3199 : douta <= 16'hA440 ; +3200 : douta <= 16'hA440 ; +3201 : douta <= 16'hA440 ; +3202 : douta <= 16'hA440 ; +3203 : douta <= 16'hA540 ; +3204 : douta <= 16'hA540 ; +3205 : douta <= 16'hA540 ; +3206 : douta <= 16'hA440 ; +3207 : douta <= 16'hA440 ; +3208 : douta <= 16'hA440 ; +3209 : douta <= 16'hA340 ; +3210 : douta <= 16'hA340 ; +3211 : douta <= 16'hA340 ; +3212 : douta <= 16'hA440 ; +3213 : douta <= 16'hA440 ; +3214 : douta <= 16'hA440 ; +3215 : douta <= 16'hA440 ; +3216 : douta <= 16'hA440 ; +3217 : douta <= 16'hA440 ; +3218 : douta <= 16'hA440 ; +3219 : douta <= 16'hA440 ; +3220 : douta <= 16'hA440 ; +3221 : douta <= 16'hA440 ; +3222 : douta <= 16'hA440 ; +3223 : douta <= 16'hA440 ; +3224 : douta <= 16'hA440 ; +3225 : douta <= 16'hA440 ; +3226 : douta <= 16'hA440 ; +3227 : douta <= 16'hA240 ; +3228 : douta <= 16'hA240 ; +3229 : douta <= 16'hA240 ; +3230 : douta <= 16'hA240 ; +3231 : douta <= 16'hA240 ; +3232 : douta <= 16'hA240 ; +3233 : douta <= 16'hA240 ; +3234 : douta <= 16'hA240 ; +3235 : douta <= 16'hA240 ; +3236 : douta <= 16'hA240 ; +3237 : douta <= 16'hA240 ; +3238 : douta <= 16'hA240 ; +3239 : douta <= 16'hA240 ; +3240 : douta <= 16'hA240 ; +3241 : douta <= 16'hA240 ; +3242 : douta <= 16'hA140 ; +3243 : douta <= 16'hA140 ; +3244 : douta <= 16'hA140 ; +3245 : douta <= 16'hA240 ; +3246 : douta <= 16'hA240 ; +3247 : douta <= 16'hA240 ; +3248 : douta <= 16'hA240 ; +3249 : douta <= 16'hA140 ; +3250 : douta <= 16'hA140 ; +3251 : douta <= 16'hA140 ; +3252 : douta <= 16'hA140 ; +3253 : douta <= 16'hA140 ; +3254 : douta <= 16'hA140 ; +3255 : douta <= 16'hA140 ; +3256 : douta <= 16'hA140 ; +3257 : douta <= 16'hA140 ; +3258 : douta <= 16'hA140 ; +3259 : douta <= 16'hA140 ; +3260 : douta <= 16'hA140 ; +3261 : douta <= 16'hA140 ; +3262 : douta <= 16'hA140 ; +3263 : douta <= 16'hA140 ; +3264 : douta <= 16'hA140 ; +3265 : douta <= 16'hA140 ; +3266 : douta <= 16'hA040 ; +3267 : douta <= 16'hA040 ; +3268 : douta <= 16'hA040 ; +3269 : douta <= 16'hA140 ; +3270 : douta <= 16'hA040 ; +3271 : douta <= 16'hA040 ; +3272 : douta <= 16'hA040 ; +3273 : douta <= 16'hA040 ; +3274 : douta <= 16'hA040 ; +3275 : douta <= 16'hA040 ; +3276 : douta <= 16'hA040 ; +3277 : douta <= 16'hA040 ; +3278 : douta <= 16'hA040 ; +3279 : douta <= 16'hA040 ; +3280 : douta <= 16'hA040 ; +3281 : douta <= 16'hA040 ; +3282 : douta <= 16'hA040 ; +3283 : douta <= 16'hA040 ; +3284 : douta <= 16'hA040 ; +3285 : douta <= 16'hA040 ; +3286 : douta <= 16'hA040 ; +3287 : douta <= 16'hA040 ; +3288 : douta <= 16'hA040 ; +3289 : douta <= 16'hA040 ; +3290 : douta <= 16'hA040 ; +3291 : douta <= 16'hA040 ; +3292 : douta <= 16'h9E42 ; +3293 : douta <= 16'hA040 ; +3294 : douta <= 16'hA040 ; +3295 : douta <= 16'hA040 ; +3296 : douta <= 16'hA040 ; +3297 : douta <= 16'hA040 ; +3298 : douta <= 16'hA040 ; +3299 : douta <= 16'hA040 ; +3300 : douta <= 16'hA040 ; +3301 : douta <= 16'hA040 ; +3302 : douta <= 16'h9F42 ; +3303 : douta <= 16'hA040 ; +3304 : douta <= 16'hA040 ; +3305 : douta <= 16'hA040 ; +3306 : douta <= 16'hA040 ; +3307 : douta <= 16'hA040 ; +3308 : douta <= 16'hA040 ; +3309 : douta <= 16'hA040 ; +3310 : douta <= 16'hA040 ; +3311 : douta <= 16'hA040 ; +3312 : douta <= 16'hA040 ; +3313 : douta <= 16'hA040 ; +3314 : douta <= 16'hA040 ; +3315 : douta <= 16'hA040 ; +3316 : douta <= 16'hA040 ; +3317 : douta <= 16'hA040 ; +3318 : douta <= 16'h9F42 ; +3319 : douta <= 16'hA040 ; +3320 : douta <= 16'hA040 ; +3321 : douta <= 16'hA040 ; +3322 : douta <= 16'hA040 ; +3323 : douta <= 16'hA040 ; +3324 : douta <= 16'h9E42 ; +3325 : douta <= 16'h9E42 ; +3326 : douta <= 16'h9E42 ; +3327 : douta <= 16'h9E42 ; +3328 : douta <= 16'h9E42 ; +3329 : douta <= 16'h9E42 ; +3330 : douta <= 16'h9E42 ; +3331 : douta <= 16'h9E42 ; +3332 : douta <= 16'h9E42 ; +3333 : douta <= 16'h9E42 ; +3334 : douta <= 16'h9E42 ; +3335 : douta <= 16'h9E42 ; +3336 : douta <= 16'h9E42 ; +3337 : douta <= 16'h9E42 ; +3338 : douta <= 16'h9E42 ; +3339 : douta <= 16'h9E42 ; +3340 : douta <= 16'h9E42 ; +3341 : douta <= 16'h9D42 ; +3342 : douta <= 16'h9E42 ; +3343 : douta <= 16'h9E42 ; +3344 : douta <= 16'h9E42 ; +3345 : douta <= 16'h9E42 ; +3346 : douta <= 16'h9E42 ; +3347 : douta <= 16'h9D42 ; +3348 : douta <= 16'h9D42 ; +3349 : douta <= 16'h9D42 ; +3350 : douta <= 16'h9D42 ; +3351 : douta <= 16'h9D42 ; +3352 : douta <= 16'h9D42 ; +3353 : douta <= 16'h9D42 ; +3354 : douta <= 16'h9D42 ; +3355 : douta <= 16'h9D42 ; +3356 : douta <= 16'h9D42 ; +3357 : douta <= 16'h9D42 ; +3358 : douta <= 16'h9D42 ; +3359 : douta <= 16'h9D42 ; +3360 : douta <= 16'h9D42 ; +3361 : douta <= 16'h9D42 ; +3362 : douta <= 16'h9D42 ; +3363 : douta <= 16'h9C42 ; +3364 : douta <= 16'h9C42 ; +3365 : douta <= 16'h9D42 ; +3366 : douta <= 16'h9C42 ; +3367 : douta <= 16'h9C42 ; +3368 : douta <= 16'h9C42 ; +3369 : douta <= 16'h9C42 ; +3370 : douta <= 16'h9C42 ; +3371 : douta <= 16'h9C42 ; +3372 : douta <= 16'h9C42 ; +3373 : douta <= 16'h9C42 ; +3374 : douta <= 16'h9C42 ; +3375 : douta <= 16'h9C42 ; +3376 : douta <= 16'h9C42 ; +3377 : douta <= 16'h9C42 ; +3378 : douta <= 16'h9C42 ; +3379 : douta <= 16'h9C42 ; +3380 : douta <= 16'h9B42 ; +3381 : douta <= 16'h9B42 ; +3382 : douta <= 16'h9C42 ; +3383 : douta <= 16'h9C42 ; +3384 : douta <= 16'h9C42 ; +3385 : douta <= 16'h9C42 ; +3386 : douta <= 16'h9C42 ; +3387 : douta <= 16'h9C42 ; +3388 : douta <= 16'h9C42 ; +3389 : douta <= 16'h9C42 ; +3390 : douta <= 16'h9C42 ; +3391 : douta <= 16'h9C42 ; +3392 : douta <= 16'h9C42 ; +3393 : douta <= 16'h9B42 ; +3394 : douta <= 16'h9B42 ; +3395 : douta <= 16'h9B42 ; +3396 : douta <= 16'h9B42 ; +3397 : douta <= 16'h9B42 ; +3398 : douta <= 16'h9A42 ; +3399 : douta <= 16'h9A42 ; +3400 : douta <= 16'h9A42 ; +3401 : douta <= 16'h9A42 ; +3402 : douta <= 16'h9A42 ; +3403 : douta <= 16'h9A42 ; +3404 : douta <= 16'h9A42 ; +3405 : douta <= 16'h9A42 ; +3406 : douta <= 16'h9A42 ; +3407 : douta <= 16'h9A42 ; +3408 : douta <= 16'h9A42 ; +3409 : douta <= 16'h9942 ; +3410 : douta <= 16'h9A42 ; +3411 : douta <= 16'h9A42 ; +3412 : douta <= 16'h9A42 ; +3413 : douta <= 16'h9A42 ; +3414 : douta <= 16'h9A42 ; +3415 : douta <= 16'h9A42 ; +3416 : douta <= 16'h9A42 ; +3417 : douta <= 16'h9A42 ; +3418 : douta <= 16'h9A42 ; +3419 : douta <= 16'h9A42 ; +3420 : douta <= 16'h9942 ; +3421 : douta <= 16'h9942 ; +3422 : douta <= 16'h9942 ; +3423 : douta <= 16'h9942 ; +3424 : douta <= 16'h9942 ; +3425 : douta <= 16'h9942 ; +3426 : douta <= 16'h9942 ; +3427 : douta <= 16'h9942 ; +3428 : douta <= 16'h9942 ; +3429 : douta <= 16'h9942 ; +3430 : douta <= 16'h9942 ; +3431 : douta <= 16'h9942 ; +3432 : douta <= 16'h9942 ; +3433 : douta <= 16'h9942 ; +3434 : douta <= 16'h9942 ; +3435 : douta <= 16'h9942 ; +3436 : douta <= 16'h9942 ; +3437 : douta <= 16'h9942 ; +3438 : douta <= 16'h9942 ; +3439 : douta <= 16'h9842 ; +3440 : douta <= 16'h9842 ; +3441 : douta <= 16'h9942 ; +3442 : douta <= 16'h9842 ; +3443 : douta <= 16'h9842 ; +3444 : douta <= 16'h9842 ; +3445 : douta <= 16'h9842 ; +3446 : douta <= 16'h9842 ; +3447 : douta <= 16'h9842 ; +3448 : douta <= 16'h9842 ; +3449 : douta <= 16'h9842 ; +3450 : douta <= 16'h9842 ; +3451 : douta <= 16'h9842 ; +3452 : douta <= 16'h9842 ; +3453 : douta <= 16'h9842 ; +3454 : douta <= 16'h9842 ; +3455 : douta <= 16'h9842 ; +3456 : douta <= 16'h9842 ; +3457 : douta <= 16'h9842 ; +3458 : douta <= 16'h9842 ; +3459 : douta <= 16'h9742 ; +3460 : douta <= 16'h9742 ; +3461 : douta <= 16'h9842 ; +3462 : douta <= 16'h9842 ; +3463 : douta <= 16'h9842 ; +3464 : douta <= 16'h9842 ; +3465 : douta <= 16'h9842 ; +3466 : douta <= 16'h9842 ; +3467 : douta <= 16'h9842 ; +3468 : douta <= 16'h9642 ; +3469 : douta <= 16'h9642 ; +3470 : douta <= 16'h9642 ; +3471 : douta <= 16'h9642 ; +3472 : douta <= 16'h9642 ; +3473 : douta <= 16'h9642 ; +3474 : douta <= 16'h9642 ; +3475 : douta <= 16'h9642 ; +3476 : douta <= 16'h9642 ; +3477 : douta <= 16'h9642 ; +3478 : douta <= 16'h9642 ; +3479 : douta <= 16'h9642 ; +3480 : douta <= 16'h9642 ; +3481 : douta <= 16'h9642 ; +3482 : douta <= 16'h9642 ; +3483 : douta <= 16'h9642 ; +3484 : douta <= 16'h9542 ; +3485 : douta <= 16'h9542 ; +3486 : douta <= 16'h9542 ; +3487 : douta <= 16'h9642 ; +3488 : douta <= 16'h9642 ; +3489 : douta <= 16'h9642 ; +3490 : douta <= 16'h9642 ; +3491 : douta <= 16'h9642 ; +3492 : douta <= 16'h9642 ; +3493 : douta <= 16'h9542 ; +3494 : douta <= 16'h9542 ; +3495 : douta <= 16'h9542 ; +3496 : douta <= 16'h9542 ; +3497 : douta <= 16'h9542 ; +3498 : douta <= 16'h9542 ; +3499 : douta <= 16'h9542 ; +3500 : douta <= 16'h9542 ; + + + +default:douta<=16'h9542; +endcase + +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/ds18b20_temp.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/ds18b20_temp.v new file mode 100644 index 00000000..8c44794b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/ds18b20_temp.v @@ -0,0 +1,368 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:59:21 10/19/2020 +// Design Name: +// Module Name: DS18B20 +// Project Name: +// Target Devices: +// Tool versions: +// Description: + +//+125 0000 0111 1101 0000 07D0h +//+85* 0000 0101 0101 0000 0550h +//+25.0625 0000 0001 1001 0001 0191h +//+10.125 0000 0000 1010 0010 00A2h +//+0.5 0000 0000 0000 1000 0008h +//0 0000 0000 0000 0000 0000h +//-0.5 1111 1111 1111 1000 FFF8h +//-10.125 1111 1111 0101 1110 FF5Eh +//-25.0625 1111 1110 0110 1111 FE6Fh +//-55 1111 1100 1001 0000 FC90h +////////////////////////////////////////////////////////////////////////////////// +module ds18b20_temp( + input clk , //40_000_000 + input rstn , + inout dq , + output reg signed[15:0] temp_data //LSB =0.625 C +); + +parameter FRE = 40 ;// //clk为40M时钟，若clk为50M，则 FRE=50； + +parameter INIT = 3'b000 , //Gray code + WR_CMD = 3'b001 , + WAIT = 3'b011 , + INIT_AGAIN = 3'b010 , + RD_CMD = 3'b110 , + RD_TEMP = 3'b111 ; + +localparam WR_CC_44 = 16'h44cc ; +localparam WR_CC_BE = 16'hbecc ; +localparam cnt_max = FRE[31:1]-1 ; +localparam WAIT_TEMP_CNT = 20'd750_000 ;//750ms + +reg flag ; +reg [15:0] data_reg ; +reg [2:0] state ; +reg clk_1us ; +reg [31:0] cnt_1us ; +reg dq_en ; +reg dq_reg ; +reg [19:0] cnt ; +reg [3:0] bit_cnt ; + +assign dq = dq_en ? dq_reg : 1'bz; + +always@(posedge clk,negedge rstn) + if(!rstn) + cnt_1us<=32'b0; + else if(cnt_1us==cnt_max) + cnt_1us<=32'b0; + else + cnt_1us<=cnt_1us+1'b1; + +always@(posedge clk,negedge rstn) + if(!rstn) + clk_1us<=1'b0; + else if(cnt_1us==cnt_max) + clk_1us<=~clk_1us; + else + clk_1us<=clk_1us; + +always@(posedge clk_1us,negedge rstn) + if(!rstn) + begin + dq_en <=1'b1; + dq_reg <=1'b0; + state <=INIT; + cnt <=20'd0; + flag <=1'b0; + bit_cnt <=4'b0; + data_reg <=16'd0; + temp_data<=12'b0; + end + else case(state) + INIT :begin + //if(cnt==16'd999)begin //for sim + if(cnt==16'd9999) + cnt <=20'd0; + else if(cnt==16'd999&&flag)begin + cnt <=20'd0; + state<=WR_CMD; + end + else begin + cnt <=cnt+1'd1; + state<=INIT; + end + //------------------ + if(cnt==16'd9999)begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + //else if(cnt==16'd499)begin + else if(cnt==16'd599)begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + else begin + dq_en <=dq_en; + dq_reg<=dq_reg; + end + //------------------ + // if(cnt==20'd570)//&&dq==1'b0) + if(cnt==20'd670)//&&dq==1'b0) + flag<= ~dq; + else if(cnt==20'd999) + flag<=1'b0; + else + flag<=flag; + end + /* INIT :begin + //if(cnt==16'd999)begin //for sim + if(cnt==16'd999&&flag)begin + cnt <=20'd0; + state<=WR_CMD; + end + else begin + cnt <=cnt+1'd1; + state<=INIT; + end + //------------------ + if(cnt==16'd499)begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + else begin + dq_en <=dq_en; + dq_reg<=dq_reg; + end + //------------------ + if(cnt==20'd570)//&&dq==1'b0) + flag<= ~dq; + else if(cnt==20'd999) + flag<=1'b0; + else + flag<=flag; + end */ + WR_CMD :begin + if(cnt==20'd64 && bit_cnt==4'd15) + begin + bit_cnt<=4'd0; + state<=WAIT; + end + else if(cnt==20'd64) + begin + bit_cnt<=bit_cnt+1'd1; + state<=WR_CMD; + end + else + begin + bit_cnt<=bit_cnt; + state<=WR_CMD; + end + //------------------ + if(cnt==20'd64 && bit_cnt==4'd15) + cnt<=20'd0; + else if(cnt==20'd64) + cnt<=20'd0; + else + cnt<=cnt+1'd1; + //------------------ + if(WR_CC_44[bit_cnt]==1'b0 && cnt<=20'd62) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + else if(WR_CC_44[bit_cnt]==1'b1 && cnt<=20'd1) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + else + begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + end + WAIT : if(cnt==WAIT_TEMP_CNT) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + cnt<=20'd0; + state<=INIT_AGAIN; + end + else + begin + dq_en <=1'b1; + dq_reg<=1'b1; + cnt<=cnt+1'd1; + state<=WAIT; + end + INIT_AGAIN :begin + if(cnt==16'd999&&flag) + //if(cnt==16'd999) //for sim + begin + cnt <=20'd0; + state<=RD_CMD; + end + else + begin + cnt <=cnt+1'd1; + state<=INIT_AGAIN; + end + //------------------ + if(cnt==16'd499) + begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + else + begin + dq_en <=dq_en; + dq_reg<=dq_reg; + end + //------------------ + if(cnt==20'd570)//&&dq==1'b0) + flag<=~dq; + else if(cnt==20'd999) + flag<=1'b0; + else + flag<=flag; + end + RD_CMD :begin + if(cnt==20'd64 && bit_cnt==4'd15) + begin + bit_cnt<=4'd0; + state<=RD_TEMP; + end + else if(cnt==20'd64) + begin + bit_cnt<=bit_cnt+1'd1; + state<=RD_CMD; + end + else + begin + bit_cnt<=bit_cnt; + state<=RD_CMD; + end + //------------------ + if(cnt==20'd64 && bit_cnt==4'd15) + cnt<=20'd0; + else if(cnt==20'd64) + cnt<=20'd0; + else + cnt<=cnt+1'd1; + //------------------ + if(WR_CC_BE[bit_cnt]==1'b0 && cnt<=20'd62) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + else if(WR_CC_BE[bit_cnt]==1'b1 && cnt<=20'd1) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + else + begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + end + RD_TEMP :begin + if(cnt==20'd64 && bit_cnt==4'd15) + cnt <=20'd0; + else if(cnt==20'd64) + cnt<=20'd0; + else + cnt<=cnt+1'd1; + //------------------ + if(cnt<=20'd1|| (cnt==20'd64 && bit_cnt==4'd15)) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + else + begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + //------------------ + if(cnt==20'd64 && bit_cnt==4'd15) + begin + bit_cnt<=4'd0; + state<=INIT; + end + else if(cnt==20'd64) + begin + bit_cnt<=bit_cnt+1'd1; + state<=RD_TEMP; + end + else + begin + bit_cnt<=bit_cnt; + state<=RD_TEMP; + end + //------------------ + if(cnt==20'd8) + data_reg<={dq,data_reg[15:1]}; + else + data_reg<=data_reg; + //------------------ + if(cnt==20'd64 && bit_cnt==4'd15) + temp_data<=data_reg; + else + temp_data<=temp_data; + end + default: state<=INIT; + endcase + + +/* wire[33:0]SYNC_OUT; +wire[35:0]CONTROL0; +wire[35:0]CONTROL1; +wire[149:0]TRIG0; + + vio u_vio ( + .CONTROL (CONTROL0), // INOUT BUS [35:0] + .CLK (clk), // IN + .SYNC_OUT (SYNC_OUT) // OUT BUS [33:0] +); + + +icon u_icon ( + .CONTROL0 (CONTROL0), // INOUT BUS [35:0] + .CONTROL1 (CONTROL1) // INOUT BUS [35:0] +); + + +ila u_ila ( + .CONTROL (CONTROL1), // INOUT BUS [35:0] + .CLK (clk), // IN + .TRIG0 (TRIG0) // IN BUS [39:0] +); + + +assign TRIG0[2:0] = state ; +assign TRIG0[21:3] = cnt ; +assign TRIG0[22] = dq ; + */ + + + + + + + + + + + + + + + + +endmodule \ No newline at end of file diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/frac2_rom.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/frac2_rom.v new file mode 100644 index 00000000..21cbf383 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/frac2_rom.v @@ -0,0 +1,72 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:35:03 01/27/2022 +// Design Name: +// Module Name: mod2_rom +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module frac2_rom( +input sysclk, +input [11 : 0] addra, +output reg[13:0] douta +); + + +reg[11:0] addr=0; + +always@(posedge sysclk)begin + addr<=addra%25; +end + +always@(posedge sysclk)begin + case(addr) +0 : douta <= 0; +1 : douta <= 2; +2 : douta <= 4; +3 : douta <= 6; +4 : douta <= 8; +5 : douta <= 2; +6 : douta <= 12; +7 : douta <= 14; +8 : douta <= 16; +9 : douta <= 18; +10 : douta <= 4; +11 : douta <= 22; +12 : douta <= 24; +13 : douta <= 1; +14 : douta <= 3; +15 : douta <= 1; +16 : douta <= 7; +17 : douta <= 9; +18 : douta <= 11; +19 : douta <= 13; +20 : douta <= 3; +21 : douta <= 17; +22 : douta <= 19; +23 : douta <= 21; +24 : douta <= 23; +default:douta <= douta ; +endcase + +end + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/fre_caliatt.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/fre_caliatt.v new file mode 100644 index 00000000..fa1a0425 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/fre_caliatt.v @@ -0,0 +1,210 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:03:33 09/24/2021 +// Design Name: +// Module Name: fre_caliatt +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module fre_caliatt( +input i_clk , +input i_rstn , +output ENABLE , +output SC , +output SD , +output END_SYN , +input SDOUT , +input CAL_F , +input signed[7:0] i_temp , +input[15:0] i_fre_mode , +input[15:0] i_cal_fre_code , +input [3:0] cal1_mgc , +input [3:0] cal2_mgc , +input [3:0] cal3_mgc , +input [3:0] cal4_mgc , +input [3:0] i_ceshi_module , +input [40:0] SYNC_OUT , +input SW , +output [3:0] R_CAL1 , +output [3:0] R_CAL2 , +output [3:0] R_CAL3 , +output [3:0] R_CAL4 , +input [4:0] tx_mgc , +input [4:0] tx_cal_mgc , +output [4:0] T_CAL + ); + + +wire[15:0] fre_mode ; +wire[31:0] hop_fre_mode ; +assign fre_mode = i_cal_fre_code/40 ;//20.375Ghz~23.875Ghz +assign hop_fre_mode = i_cal_fre_code+20375 ;//20.375Ghz~23.875Ghz + + +wire [3:0] R_CAL4_r ; +wire [3:0] R_CAL3_r ; +wire [3:0] R_CAL2_r ; +wire [3:0] R_CAL1_r ; +wire [4:0] T_CAL_r ; +wire [31:0] data_in ; +reg [31:0] data_in_r ; +reg R_CAL_F ; +wire[15:0] cal_mgc_r ; +reg [15:0] cal_mgc_rr ; +reg tx_en ; +reg vio_en ; + + + + +always@(posedge i_clk) +begin + cal_mgc_rr <= cal_mgc_r; +end +//------------------vio_debug------------------------// +/* always@(posedge i_clk) +begin + vio_R_CAL_4 <= SYNC_OUT[4:0]; + vio_R_CAL_3 <= SYNC_OUT[9:5]; + vio_R_CAL_2 <= SYNC_OUT[14:10]; + vio_R_CAL_1 <= SYNC_OUT[19:15]; + vio_T_CAL <= SYNC_OUT[24:20]; + vio_en <= SYNC_OUT[25]; +end */ + +//------------------vio_debug------------------------// +assign R_CAL1 = R_CAL1_r + cal1_mgc ;//通道1 +assign R_CAL2 = R_CAL2_r + cal2_mgc ;//通道2 +assign R_CAL3 = R_CAL3_r + cal3_mgc ;//通道3 +assign R_CAL4 = R_CAL4_r + cal4_mgc ;//通道4 +assign T_CAL = ( i_ceshi_module==4'ha || i_ceshi_module==4'hb) ? (tx_mgc[4:0] + tx_cal_mgc) : (T_CAL_r + tx_cal_mgc) ;//发射通道，低衰减 + +assign cal_mgc_r = {cal1_mgc,cal2_mgc,cal3_mgc,cal4_mgc}; +assign data_in = { 4'h0,3'b0, + T_CAL , //发射通道 + R_CAL1[0], //接收通道1_1dB + R_CAL1[1], //接收通道1_2dB + R_CAL1[2], //接收通道1_4dB + R_CAL1[3], //接收通道1_8dB + R_CAL2[0], //接收通道2_1dB + R_CAL2[1], //接收通道2_2dB + R_CAL2[2], //接收通道2_4dB + R_CAL2[3], //接收通道2_8dB + R_CAL3[0], //接收通道3_1dB + R_CAL3[1], //接收通道3_2dB + R_CAL3[2], //接收通道3_4dB + R_CAL3[3], //接收通道3_8dB + R_CAL4 , // + 4'b0 }; +reg [31:0] cnt5us=0; + +always@(posedge i_clk)begin + if(cnt5us==2000) + cnt5us<=2000; + else + cnt5us<=cnt5us+1'b1; +end + +always@(posedge i_clk or negedge i_rstn)begin +if(!i_rstn) + R_CAL_F <= 1'b0; +else + R_CAL_F <= CAL_F; +end + +always@(posedge i_clk or negedge i_rstn)begin + if(!i_rstn) + tx_en<=1'b0; + else if(cnt5us==1999) + tx_en<=1'b1; + else if({R_CAL_F,CAL_F}==2'b01 || cal_mgc_rr!=cal_mgc_r) + tx_en<=1'b1; + else + tx_en<=1'b0; +end + + + +R_CAL_1 R_CAL_1 ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .i_temp(i_temp), + .fre_mode(fre_mode), + .R_CAL(R_CAL1_r) + ); + +R_CAL_2 R_CAL_2 ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .i_temp(i_temp), + .fre_mode(fre_mode), + .R_CAL(R_CAL2_r) + ); + +R_CAL_3 R_CAL_3 ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .i_temp(i_temp), + .fre_mode(fre_mode), + .R_CAL(R_CAL3_r) + ); + +R_CAL_4 R_CAL_4 ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .i_temp(i_temp), + .fre_mode(fre_mode), + .R_CAL(R_CAL4_r) + ); + + +T_CAL T_CAL__ ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .SW(SW), + .i_temp(i_temp), + .hop_fre_mode(hop_fre_mode), + .T_CAL_(T_CAL_r) + ); + + +spi_tx SPI_TX ( + .clk (i_clk ) , + .rstn (i_rstn ) , + .tx_en (tx_en ) , + .data_in (data_in ) , + .spi_cs (ENABLE ) , + .spi_sclk (SC ) , + .spi_sdo (SD ) , + .DARY (END_SYN ) + ); + + + + + + + + + + + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mgc_ctrl.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mgc_ctrl.v new file mode 100644 index 00000000..a7e2d733 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mgc_ctrl.v @@ -0,0 +1,434 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19:54:29 09/06/2021 +// Design Name: +// Module Name: mgc_ctrl +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mgc_ctrl( +input i_sys_clk , +input i_rst_n , +input i_TR_SW_F , +input i_TP_EN_F , +input i_CAL_F , +input i_T_MGC_EN_F , +input i_R_MGC_EN_F , + +input [15:0] i_fre_code , +input [7:0] i_tx_mgc , +input [7:0] i_rx1_mgc , +input [7:0] i_rx2_mgc , +input [7:0] i_rx3_mgc , +input [7:0] i_rx4_mgc , +input [3:0] i_ceshi_module, +output [15:0] o_current_fre_code, +output [15:0] o_cal_fre_code, +output [15:0] o_hop_fre_code, +output o_adf4371_hop1, +output o_adf4371_hop2, + +output o_SW, +output o_SW2, +output o_SW3, +output o_SW_C1, + +//ͨMGCƣ˥31dB1dBʼֱ̬ͨȫ1 +output o_T_MGC_1dB, +output o_T_MGC_2dB, +output o_T_MGC_4dB, +output o_T_MGC_8dB, +output o_T_MGC_16dB, +//ͨ1MGCƣ˥31dB1dBʼֱ̬ͨȫ1 +output reg[7:0] o_R_MGC_1, + +//ͨ2MGCƣ˥31dB1dBʼֱ̬ͨȫ1 +output reg[7:0] o_R_MGC_2, + +//ͨ3MGCƣ˥31dB1dBʼֱ̬ͨȫ1 +output reg[7:0] o_R_MGC_3, +//ͨ4MGCƣ˥31dB1dBʼֱ̬ͨȫ1 +output reg[7:0] o_R_MGC_4 + +); + + +reg TR_SW_F; +reg [2:0] TP_EN_r; +reg [2:0] T_MGC_EN_r; +reg [2:0] R_MGC_EN_r; +reg [2:0] R_CAL_F; +reg [15:0] hop_fre_code; +reg [15:0] current_fre_code; +wire [15:0] cal_fre_code; +reg [47:0] fre_code_a_b; +reg hop_en; +reg hop_en_r; +reg hop_en_rr; +reg cfg_en; +reg cfg_en_r; +reg cfg_en_rr; +reg hmc704_1_hop; +reg hmc704_2_hop; +reg [1:0] cnt_cfg; +reg [1:0] cnt_hop; + + +reg sw1; +reg sw2; +reg sw3; +reg SW_C1; + +reg T_MGC_1dB_r ; +reg T_MGC_2dB_r ; +reg T_MGC_4dB_r ; +reg T_MGC_8dB_r ; +reg T_MGC_16dB_r; + +assign o_SW = sw1; +assign o_SW2 = sw2; +assign o_SW3 = sw3; +assign o_SW_C1 = SW_C1; + +assign o_current_fre_code= current_fre_code; +assign o_cal_fre_code = cal_fre_code; +assign o_hop_fre_code = hop_fre_code; +assign o_adf4371_hop1 = hmc704_1_hop; +assign o_adf4371_hop2 = hmc704_2_hop; + +assign o_T_MGC_1dB = T_MGC_1dB_r ; +assign o_T_MGC_2dB = T_MGC_2dB_r ; +assign o_T_MGC_4dB = T_MGC_4dB_r ; +assign o_T_MGC_8dB = T_MGC_8dB_r ; +assign o_T_MGC_16dB = T_MGC_16dB_r ; + + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + TR_SW_F <= 1'b0; + TP_EN_r <= 3'b0; + T_MGC_EN_r <= 3'b0; + R_MGC_EN_r <= 3'b0; + R_CAL_F <= 3'b0; +end +else begin + TR_SW_F <= i_TR_SW_F; + TP_EN_r <= {TP_EN_r[1:0] ,i_TP_EN_F}; + T_MGC_EN_r <= {T_MGC_EN_r[1:0] ,i_T_MGC_EN_F}; + R_MGC_EN_r <= {R_MGC_EN_r[1:0] ,i_R_MGC_EN_F}; + R_CAL_F <= {R_CAL_F[1:0] ,i_CAL_F}; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + SW_C1 <= 1'b0; + current_fre_code <= 16'h6d6 ; +end +else begin + current_fre_code <= hop_en ? hop_fre_code : current_fre_code ; + if(TR_SW_F==1'b1)begin + if(current_fre_code<=1500)//20.375Ghz~21.875Ghz + SW_C1 <= 1'b1; + else //21.875Ghz~23.875Ghz + SW_C1 <= 1'b0; + end + else begin + SW_C1 <= SW_C1; + end +end +end + + +assign cal_fre_code = R_CAL_F==3'b001 ? hop_fre_code : cal_fre_code ; + + + + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + fre_code_a_b <= 48'h0000000006d6; +end +else if(cfg_en)begin + fre_code_a_b <= {fre_code_a_b[31:0],i_fre_code}; +end +else begin + fre_code_a_b <= fre_code_a_b; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + hop_en <= 1'b0; +end +else if(TP_EN_r==3'b011)begin + hop_en <= 1'b1; +end +else begin + hop_en <= 1'b0; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + hop_fre_code <= 16'h6d6; +end +else begin + hop_fre_code <= i_fre_code; +end +end + + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + cfg_en <= 1'b0; +end +else if(hop_fre_code != i_fre_code)begin + cfg_en <= 1'b1; +end +else begin + cfg_en <= 1'b0; +end +end + + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + hop_en_r <= 1'b0; + hop_en_rr <= 1'b0; +end +else begin + hop_en_r <= hop_en; + hop_en_rr <= hop_en_r; +end +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + cfg_en_r <= 1'b0; + cfg_en_rr <= 1'b0; +end +else begin + cfg_en_r <= cfg_en; + cfg_en_rr <= cfg_en_r; +end +end + +reg [15:0] pre_hop_fre_code; +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + cnt_hop <= 2'b00; +end +else if(cnt_hop == 2'b10)begin + cnt_hop <= 2'b00; +end +else if(~hop_en_r & hop_en && (pre_hop_fre_code!=hop_fre_code ))begin + cnt_hop <= cnt_hop + 1'b1; +end +else begin + cnt_hop <= cnt_hop; +end +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + cnt_cfg <= 2'b00; +end +else if(cnt_cfg == 2'b10)begin + cnt_cfg <= 2'b00; +end +else if(~cfg_en_r&cfg_en)begin + cnt_cfg <= cnt_cfg + 1'b1; +end +else begin + cnt_cfg <= cnt_cfg; +end +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n) + pre_hop_fre_code<=16'h6d6; +else if(hop_en_rr) + pre_hop_fre_code<=hop_fre_code; +else + pre_hop_fre_code<=pre_hop_fre_code; +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + sw1 <= 1'b1; + sw2 <= 1'b1; + sw3 <= 1'b0; +end +else if(i_ceshi_module==4'ha)//ԶУ׼صa +begin + sw1 <= 1'b0; + sw2 <= 1'b0; + sw3 <= 1'b1; +end +else if(i_ceshi_module==4'hb)//ԶУ׼صb +begin + sw1 <= 1'b1; + sw2 <= 1'b1; + sw3 <= 1'b0; +end +else if(hop_en_rr && pre_hop_fre_code != hop_fre_code)begin + if(cnt_hop == 2'b01)begin + sw1 <= 1'b0; + sw2 <= 1'b0; + sw3 <= 1'b1; + end + else begin + sw1 <= 1'b1; + sw2 <= 1'b1; + sw3 <= 1'b0; + end +end +else begin + sw1 <= sw1; + sw2 <= sw2; + sw3 <= sw3; +end +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b0; +end +else if(i_ceshi_module==4'ha&&cfg_en_rr)begin + hmc704_1_hop <= 1'b1; + hmc704_2_hop <= 1'b0; +end +else if(i_ceshi_module==4'hb&&cfg_en_rr)begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b1; +end +else if(cfg_en_rr)begin + if(fre_code_a_b[47:32]==fre_code_a_b[15:0])begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b0; + end + else if(cnt_cfg == 2'b01)begin + hmc704_1_hop <= 1'b1; + hmc704_2_hop <= 1'b0; + end + else begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b1; + end +end +else begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b0; +end +end + +/* always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + sw1 <= 1'b1; + sw2 <= 1'b1; + sw3 <= 1'b0; +end +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b0; +end +else if(cfg_en_rr)begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b1; +end +else begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b0; +end +end */ + + + + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + T_MGC_1dB_r <= 1'b0; + T_MGC_2dB_r <= 1'b0; + T_MGC_4dB_r <= 1'b0; + T_MGC_8dB_r <= 1'b0; + T_MGC_16dB_r <= 1'b0; +end +else if(i_ceshi_module==4'ha || i_ceshi_module==4'hb )begin + T_MGC_1dB_r <= 1'b0; + T_MGC_2dB_r <= 1'b0; + T_MGC_4dB_r <= 1'b0; + T_MGC_8dB_r <= 1'b0; + T_MGC_16dB_r <= 1'b0; +end +else if(T_MGC_EN_r==3'b011)begin + T_MGC_1dB_r <= i_tx_mgc[0]; + T_MGC_2dB_r <= i_tx_mgc[1]; + T_MGC_4dB_r <= i_tx_mgc[2]; + T_MGC_8dB_r <= i_tx_mgc[3]; + T_MGC_16dB_r <= i_tx_mgc[4]; +end +else begin + T_MGC_1dB_r <= T_MGC_1dB_r ; + T_MGC_2dB_r <= T_MGC_2dB_r ; + T_MGC_4dB_r <= T_MGC_4dB_r ; + T_MGC_8dB_r <= T_MGC_8dB_r ; + T_MGC_16dB_r <= T_MGC_16dB_r ; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + o_R_MGC_1 <= 1'b0; +end +else if(R_MGC_EN_r==3'b011)begin + o_R_MGC_1 <= i_rx1_mgc; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + o_R_MGC_2 <= 1'b0; +end +else if(R_MGC_EN_r==3'b011)begin + o_R_MGC_2 <= i_rx2_mgc; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + o_R_MGC_3 <= 1'b0; +end +else if(R_MGC_EN_r==3'b011)begin + o_R_MGC_3 <= i_rx3_mgc; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + o_R_MGC_4 <= 1'b0; +end +else if(R_MGC_EN_r==3'b011)begin + o_R_MGC_4 <= i_rx4_mgc; + +end +end + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mod2_rom.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mod2_rom.v new file mode 100644 index 00000000..399498b8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mod2_rom.v @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:35:03 01/27/2022 +// Design Name: +// Module Name: mod2_rom +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mod2_rom( +input sysclk, +input [11 : 0] addra, + +output reg[13:0] douta +); + +reg[11:0] addr=0; +always@(posedge sysclk)begin + addr<=addra%25; +end + +always@(posedge sysclk)begin + case(addr) +0 : douta <= 1 ; +1 : douta <= 25 ; +2 : douta <= 25 ; +3 : douta <= 25 ; +4 : douta <= 25 ; +5 : douta <= 5 ; +6 : douta <= 25 ; +7 : douta <= 25 ; +8 : douta <= 25 ; +9 : douta <= 25 ; +10 : douta <= 5 ; +11 : douta <= 25 ; +12 : douta <= 25 ; +13 : douta <= 25 ; +14 : douta <= 25 ; +15 : douta <= 5 ; +16 : douta <= 25 ; +17 : douta <= 25 ; +18 : douta <= 25 ; +19 : douta <= 25 ; +20 : douta <= 5 ; +21 : douta <= 25 ; +22 : douta <= 25 ; +23 : douta <= 25 ; +24 : douta <= 25 ; +default:douta <= douta ; +endcase + +end + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_master.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_master.v new file mode 100644 index 00000000..924ae74b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_master.v @@ -0,0 +1,150 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 20:42:39 09/29/2021 +// Design Name: +// Module Name: spi_master +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module spi_master #(parameter BIT_NUM = 95 )( + input i_clk , + input debug_clk , + input i_sys_rst_n , + input i_spi_sck , + input i_spi_cs , + output o_spi_sdo , + input i_spi_sdi , + input i_LD_LO3 , + input i_LD1 , + input i_LD2 , + input[3:0] i_cal1_mgc , + input[3:0] i_cal2_mgc , + input[3:0] i_cal3_mgc , + input[3:0] i_cal4_mgc , + input[7:0] i_temp , + input[31:0] i_frame_count + +); + +wire [BIT_NUM:0] data ; +reg [BIT_NUM:0] data_r ; +reg [BIT_NUM:0] data_reg ; +assign data={ 8'hAA , + i_temp , + 7'b0,i_LD_LO3 , + 7'b0,i_LD1 , + 7'b0,i_LD2 , + i_cal1_mgc,i_cal2_mgc , + i_cal3_mgc,i_cal4_mgc , + i_frame_count , + 8'hCC } ; + +wire spi_sck ; +wire spi_cs ; +reg spi_sdo ; +reg [2:0] reg_cs ; +reg [31:0] cnt ; + +assign spi_sck = i_spi_sck; +assign spi_cs = i_spi_cs; +assign o_spi_sdo = spi_sdo; + +always@(negedge spi_sck,negedge i_sys_rst_n)begin + if(!i_sys_rst_n) + reg_cs<=3'b111; + else + reg_cs<={reg_cs[1:0],i_spi_cs}; +end + +always@(negedge spi_sck,negedge i_sys_rst_n)begin + if(!i_sys_rst_n) + data_r<={8'hAA,80'b0,8'hCC}; + else if(reg_cs[2:1]==2'b10) + data_r<={8'hAA,data[87:8],8'hCC}; +end + +always@(negedge spi_sck,negedge i_sys_rst_n)begin + if(!i_sys_rst_n) + spi_sdo <= 1'b0 ; + else if(!spi_cs) + spi_sdo <= data_r[cnt]; + else + spi_sdo <= 1'b0 ; +end + +always@(posedge spi_sck,negedge i_sys_rst_n)begin + if(!i_sys_rst_n) + cnt<=BIT_NUM; + else if(spi_cs==1 | cnt==0) + cnt<=BIT_NUM; + else + cnt<=cnt-1; +end + +//------------debug------------ +always@(posedge spi_sck,negedge i_sys_rst_n)begin + if(!i_sys_rst_n) + data_reg <= 0 ; + else if(!spi_cs) + data_reg <= {data_reg,spi_sdo} ; + else + data_reg <= data_reg ; +end +//------------debug------------ + +/* +wire [40:0] SYNC_OUT ; +wire [35:0] CONTROL0 ; +wire [35:0] CONTROL1 ; +wire [150:0] TRIG0 ; + +vio u_vio ( + .CONTROL (CONTROL0), // INOUT BUS [35:0] + .CLK (i_clk), // IN + .SYNC_OUT (SYNC_OUT) // OUT BUS [33:0] +); + + +icon u_icon ( + .CONTROL0 (CONTROL0), // INOUT BUS [35:0] + .CONTROL1 (CONTROL1) // INOUT BUS [35:0] +); + + +ila u_ila ( + .CONTROL (CONTROL1), // INOUT BUS [35:0] + .CLK (debug_clk), // IN + .TRIG0 (TRIG0) // IN BUS [39:0] +); + + +assign TRIG0[0] = i_LD_LO3; +assign TRIG0[1] = i_LD1 ; +assign TRIG0[2] = i_LD2 ; +assign TRIG0[98:3] = data_r ; +assign TRIG0[101:99] = reg_cs ; +assign TRIG0[132:102] = cnt ; +assign TRIG0[133] = i_spi_sck ; +assign TRIG0[134] = i_spi_cs ; +assign TRIG0[135] = o_spi_sdo ; +assign TRIG0[136] = i_spi_sdi ; + + */ + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_salve.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_salve.v new file mode 100644 index 00000000..346cd4a6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_salve.v @@ -0,0 +1,171 @@ + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020/09/02 10:48:55 +// Design Name: +// Module Name: d +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// SPI时钟频率50MHz。每一帧数据12个字节，共96bit数据。 +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module spi_slave#( + parameter BIT_NUM = 96 +) +( +input i_sys_clk, +input i_sys_rst_n, + +input i_spi_sck, //从机在时钟下降沿采样数据 +input i_spi_cs, //低电平时从机接收数据指令 +input i_spi_sdi, +output [31:0] o_frame_count, //帧计数 +output [15:0] o_fre_code , //天线频率 +output [7:0] o_tx_mgc, //发射MGC +output [3:0] o_model, //模式字 +output [3:0] o_rf_en, //射频使能 +output [3:0] o_cal1_mgc, //接收校准1mgc +output [3:0] o_cal2_mgc, //接收校准2mgc +output [3:0] o_cal3_mgc, //接收校准3mgc +output [3:0] o_cal4_mgc, //接收校准4mgc +output [7:0] o_tx_cal_mgc, //发射校准mgc +output [7:0] o_rx1_mgc, //接收1mgc +output [7:0] o_rx2_mgc, //接收2mgc +output [7:0] o_rx3_mgc, //接收3mgc +output [7:0] o_rx4_mgc , //接收4mgc + +output [3:0] o_ceshi_model +); + +reg [BIT_NUM -1:0] receive_data; +reg [3:0] rf_en ; +reg [3:0] model; +reg [31:0] frame_count; +reg [11:0] fre_code; +reg [7:0] tx_mgc; +reg [7:0] rx1_mgc; +reg [7:0] rx2_mgc; +reg [7:0] rx3_mgc; +reg [7:0] rx4_mgc; +reg [3:0] cal1_mgc; +reg [3:0] cal2_mgc; +reg [3:0] cal3_mgc; +reg [3:0] cal4_mgc; +reg [7:0] tx_cal_mgc; +reg [3:0] ceshi_module; + + +assign o_frame_count= frame_count; +assign o_fre_code = {4'b0,fre_code}; +assign o_rf_en = rf_en; +assign o_model = model; +assign o_tx_mgc = tx_mgc; +assign o_cal1_mgc = cal1_mgc; +assign o_cal2_mgc = cal2_mgc; +assign o_cal3_mgc = cal3_mgc; +assign o_cal4_mgc = cal4_mgc; +assign o_tx_cal_mgc = tx_cal_mgc; +assign o_rx1_mgc = rx1_mgc; +assign o_rx2_mgc = rx2_mgc; +assign o_rx3_mgc = rx3_mgc; +assign o_rx4_mgc = rx4_mgc; +assign o_ceshi_model = ceshi_module; + +always @ ( negedge i_spi_sck or negedge i_sys_rst_n)begin +if( !i_sys_rst_n ) + receive_data <= 'b0; +else if(i_spi_cs == 1'b0) + receive_data <= {receive_data,i_spi_sdi}; +else + receive_data <= receive_data; +end + + +reg [2:0] cs_reg; + +always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin +if( !i_sys_rst_n ) + cs_reg <= 3'b111; +else + cs_reg <= {cs_reg[1:0],i_spi_cs}; +end + + + +always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin +if(!i_sys_rst_n)begin + tx_cal_mgc<=8'h0; +end +else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'hbb) && (receive_data[7:0] == 8'hdd))begin + tx_cal_mgc<=receive_data[15:8]; +end +else begin + tx_cal_mgc<=tx_cal_mgc; +end +end + +always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin +if(!i_sys_rst_n)begin + fre_code <= 12'h6d6; + tx_mgc <= 8'h00; + rf_en <= 4'b1; + model <= 4'b0; + frame_count <= 32'd1; + rx1_mgc <= 4'h0; + rx2_mgc <= 4'h0; + rx3_mgc <= 4'h0; + rx4_mgc <= 4'h0; + cal1_mgc <= 4'h0; + cal2_mgc <= 4'h0; + cal3_mgc <= 4'h0; + cal4_mgc <= 4'h0; + ceshi_module <= 4'h0; +end +else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'haa) && (receive_data[7:0] == 8'hcc))begin + frame_count <= frame_count+1'b1; + rf_en <= receive_data[87:84]; + model <= receive_data[83:80]; + ceshi_module<= receive_data[79:76]; + fre_code <= receive_data[75:64]; + tx_mgc <= receive_data[63:56]; + cal1_mgc <= receive_data[55:52]; + cal2_mgc <= receive_data[51:48]; + cal3_mgc <= receive_data[47:44]; + cal4_mgc <= receive_data[43:40]; + rx1_mgc <= receive_data[39:32]; + rx2_mgc <= receive_data[31:24]; + rx3_mgc <= receive_data[23:16]; + rx4_mgc <= receive_data[15:8]; +end +else begin + frame_count <= frame_count ; + rf_en <= rf_en ; + model <= model ; + fre_code <= fre_code ; + tx_mgc <= tx_mgc ; + cal1_mgc <= cal1_mgc ; + cal2_mgc <= cal2_mgc ; + cal3_mgc <= cal3_mgc ; + cal4_mgc <= cal4_mgc ; + rx1_mgc <= rx1_mgc ; + rx2_mgc <= rx2_mgc ; + rx3_mgc <= rx3_mgc ; + rx4_mgc <= rx4_mgc ; +end +end + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_tx.v b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_tx.v new file mode 100644 index 00000000..988e7713 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_tx.v @@ -0,0 +1,118 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:23:58 10/12/2020 +// Design Name: spiģ +// Module Name: spi +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module spi_tx #(parameter WHITH=32)( +input clk,//ϵͳʱ +input rstn,//첽λ +input tx_en,//ʹ +input [WHITH-1:0] data_in,// +output reg spi_cs, //Ƭѡ +output reg spi_sclk, //ͬʱӣclk/2 +output reg spi_sdo, //ݵ +output reg DARY +); + +//localparam [1:0] polaeity = 2'b10;//negedge ½ر +localparam [1:0] polaeity = 2'b01;//posedge Ͻر +reg [2:0] state ; //״̬ +reg [WHITH-1:0] reg_data;//λĴ +reg [5:0] cnt;//λ + +wire CPOL ; //ʱӿʱƽ +wire CPHA ; // +assign CPOL = polaeity[0] ; +assign CPHA = polaeity[1] ; + +always @(posedge clk,negedge rstn)begin +if(!rstn)begin + state <= 3'd0; + spi_cs <= 1'b1; + spi_sclk <= CPOL; + reg_data <= 1'd0; + cnt <= 5'b0; + spi_sdo <= 1'b0; + DARY <= 1'b1; +end +else begin + case(state) + 3'd0:begin//̬ + spi_sclk <= CPOL ; + spi_cs <= 1'b1 ; + spi_sdo <= 1'b0 ; + DARY <= 1'b1 ; + cnt <= 5'b0 ; + reg_data <= data_in ; + if(tx_en)//ʹһ״̬ + state <= 3'd1 ; + else + state <= state ; + end + 3'd1:begin + spi_cs <= 1'b0 ; + state <= 3'd2 ; + reg_data <= data_in ; + end + 3'd2:begin//λ̬ + spi_cs <= 1'b0 ; + reg_data <= reg_data<<1'b1 ; + spi_sdo <= reg_data[WHITH-1] ; + spi_sclk <= CPHA ; + state <= (cnt >= WHITH-1) ? 3'd4:3'd3; + end + 3'd3:begin//ʱӷת + cnt <= cnt+1'b1 ; + spi_sclk <= ~CPHA ; + state <= 3'd2 ; + end + 3'd4:begin//̬ + state <= 3'd5; + spi_sclk <= ~CPHA; + end + 3'd5:begin//̬ + state <= 3'd6; + DARY <= 0; + spi_sdo <= 1'b0 ; + spi_cs <= 1'b1 ; + end + 3'd6:begin//̬ + state <= 3'd7; + DARY <= 1; + spi_cs <= 1'b1 ; + end + 3'd7:begin//̬ + state <= 3'd8; + DARY <= 0; + end + 3'd8:begin//̬ + state <= 3'd0; + DARY <= 1; + end + default :state<=3'd0; + endcase +end +end + + + + + + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/ant_rf_ctrl.v b/projects/duifei/duifei_online_acq_par/rtl/ant_rf_ctrl.v new file mode 100644 index 00000000..4094f7fc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/ant_rf_ctrl.v @@ -0,0 +1,509 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2022/07/13 14:20:24 +// Design Name: +// Module Name: ant_rf_ctrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ant_rf_ctrl +( + input clk_48m , + input clk_96m , + input clk_32m , + input clk_19p2m , + input sys_rst , + + output ant_clk , + output ant_en , + output ant_data , + output ant_tr , + output ant_dary , + input ant_dout , + + output rf_standby , + output rf_sw_pll , + output rf_t , + output rf_r , + output rf_sw_bpf , + output rf_sclk1 , + output rf_sdio1 , + output rf_cs1 , + input rf_ld1 , + output rf_sclk2 , + output rf_sdio2 , + output rf_cs2 , + input rf_ld2 , + output rf_sclk3 , + output rf_sdio3 , + output rf_cs3 , + input rf_ld3 , + output rf_tmgc_16 , + output rf_tmgc_8 , + output rf_tmgc_4 , + output rf_tmgc_2 , + output rf_tmgc_1 , + output rf_rmgc_16 , + output rf_rmgc_8 , + output rf_rmgc_4 , + output rf_rmgc_2 , + output rf_rmgc_1 , + output rf_enable , + output rf_sc , + output rf_sd , + output rf_endsyn , + input rf_sdout , + inout rf_dq_wd , + output rf_sw_rx +); + + +(*dont_touch = "true"*) wire vio_switch ; // 键控开关，沿有效 +(*dont_touch = "true"*) wire vio_trdirection ; // 收发方向 +(*dont_touch = "true"*) wire [15:0] vio_frequency ; // 收发频率 +(*dont_touch = "true"*) wire [ 7:0] vio_emitMGC ; // 发送MGC +(*dont_touch = "true"*) wire [ 3:0] vio_ch01MGC ; // 1通道校准MGC +(*dont_touch = "true"*) wire [ 3:0] vio_ch02MGC ; // 2通道校准MGC +(*dont_touch = "true"*) wire [ 3:0] vio_ch03MGC ; // 3通道校准MGC +(*dont_touch = "true"*) wire [ 3:0] vio_ch04MGC ; // 4通道校准MGC +(*dont_touch = "true"*) wire [ 7:0] vio_recvMGC ; // 接收MGC +(*dont_touch = "true"*) wire [ 7:0] vio_AntMod ; // 天线工作模式 +(*dont_touch = "true"*) wire [15:0] vio_AntOffAxis ; // 天线离轴角 +(*dont_touch = "true"*) wire [15:0] vio_AntYaw ; // 天线偏航角 +(*dont_touch = "true"*) wire [15:0] vio_PrecessTime ; // 处理时间，从EN拉低到DARY拉低 + +(*dont_touch = "true"*)wire vio_mode_ant ; // 0定频手动，1扫频模式 +(*dont_touch = "true"*)wire vio_hop_start ; // 0跳频终止，1重新跳频 +(*dont_touch = "true"*)wire vio_standby ; // 0待机模式，1工作模式 +(*dont_touch = "true"*)wire [15:0] vio_hoptime ; // 单跳时间计数器 + +reg Ant_switch_D1 = 0; +reg data_valid = 0; +reg switch_valid = 0; +reg [95:0] RF_CtrlWord = 0; +reg [127:0] Ant_CtrlWord = 0; +reg [15:0] data_valid_countdown = 0; +reg [15:0] rst_countdown = 100; +reg [95:0] RF_CtrlWord_running = 0; +reg [127:0] Ant_CtrlWord_running = 0; +reg rst_n = 0; +reg SPI_SYN_F = 1; +reg SPI_MOSI_F = 1; +reg TP_EN_F = 0; +reg TR_MGC_F = 0; +reg CAL_F = 0; +reg PRF = 0; +wire SPI_MISO_F; +reg Ant_DATA = 0; +reg Ant_EN = 0; +reg Ant_DARY = 0; +reg Ant_TR = 0; + + + +//相控阵测试程序 +reg [15:0] cnt_freq_change = 16'd0; + +reg Ant_switch ; // 键控开关，沿有效 +reg [15:0] Ant_frequency; // 收发频率 +reg [ 7:0] Ant_mode ; // 相控阵模式 +reg [ 7:0] RF_mode ; // 射频模式 + +always @ (posedge clk_48m) begin + if(sys_rst) begin + Ant_switch <= 1'b0; + cnt_freq_change[15:0] <= 16'd0; + Ant_frequency[15:0] <= 16'd0; + RF_mode[7:0] <= 8'h10; + Ant_mode[7:0] <= 8'h0f; + end + else begin + if(vio_mode_ant) begin + if(vio_hop_start) begin + if(cnt_freq_change[15:0] == (vio_hoptime[15:0] - 16'd1)) begin + Ant_switch <= ~Ant_switch; + if(Ant_frequency[15:0] == 16'd3500) begin + Ant_frequency[15:0] <= 16'd0; + end + else begin + Ant_frequency[15:0] <= Ant_frequency[15:0] + 16'd1; + end + cnt_freq_change[15:0] <= 16'd0; + end + else begin + Ant_switch <= Ant_switch; + Ant_frequency[15:0] <= Ant_frequency[15:0]; + cnt_freq_change[15:0] <= cnt_freq_change[15:0] + 16'd1; + end + end + else begin + Ant_switch <= Ant_switch; + Ant_frequency[15:0] <= 16'd0; + cnt_freq_change[15:0] <= 16'd0; + end + end + else begin + Ant_switch <= vio_switch; + Ant_frequency[15:0] <= vio_frequency[15:0]; + cnt_freq_change[15:0] <= 16'd0; + end + + if(vio_standby) begin + RF_mode[7:0] <= 8'h10; + Ant_mode[7:0] <= 8'h0f; + end + else begin + RF_mode[7:0] <= 8'h00; + Ant_mode[7:0] <= vio_AntMod[7:0]; + end + end + +end + +always @(posedge clk_48m) + begin + Ant_switch_D1 <= Ant_switch; + if(Ant_switch_D1 != Ant_switch) + switch_valid <= 1'b1; + else + switch_valid <= 1'b0; + + if(switch_valid) + begin + RF_CtrlWord[95:88] <= 8'hAA; + RF_CtrlWord[87:80] <= RF_mode[7:0]; + RF_CtrlWord[79:64] <= Ant_frequency[15:0]; + RF_CtrlWord[63:56] <= vio_emitMGC[7:0]; + RF_CtrlWord[55:52] <= vio_ch01MGC[3:0]; + RF_CtrlWord[51:48] <= vio_ch02MGC[3:0]; + RF_CtrlWord[47:44] <= vio_ch03MGC[3:0]; + RF_CtrlWord[43:40] <= vio_ch04MGC[3:0]; + RF_CtrlWord[39:32] <= vio_recvMGC[7:0]; + RF_CtrlWord[31:8] <= 24'h00_0000; + RF_CtrlWord[7:0] <= 8'hCC; + + Ant_CtrlWord[127:120] <= 8'hAA; + Ant_CtrlWord[119:112] <= 8'h00; + Ant_CtrlWord[111:104] <= Ant_mode[7:0]; + Ant_CtrlWord[103: 88] <= vio_AntOffAxis[15:0]; + Ant_CtrlWord[ 87: 72] <= vio_AntYaw[15:0]; + Ant_CtrlWord[ 71: 56] <= Ant_frequency[15:0]; + Ant_CtrlWord[ 55: 8] <= 48'h00_00_00_00_00_00; + Ant_CtrlWord[ 7: 0] <= 8'hCC; + end + else + begin + RF_CtrlWord[95:0] <= RF_CtrlWord[95:0]; + Ant_CtrlWord[127:0] <= Ant_CtrlWord[127:0]; + end + + if(switch_valid) + data_valid_countdown[15:0] <= vio_PrecessTime[15:0]; + else if(data_valid_countdown[15:0] != 16'd0) + data_valid_countdown[15:0] <= data_valid_countdown[15:0] - 16'd1; + + + // RF控制 + if(data_valid_countdown[15:0] == vio_PrecessTime[15:0]) + RF_CtrlWord_running[95:0] <= RF_CtrlWord[95:0]; + else + RF_CtrlWord_running[95:0] <= {RF_CtrlWord_running[94:0],1'b0}; + + if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd96 && data_valid_countdown[15:0] < vio_PrecessTime[15:0]) + begin + SPI_SYN_F <= 1'b0; + SPI_MOSI_F <= RF_CtrlWord_running[95]; + end + else + begin + SPI_SYN_F <= 1'b1; + SPI_MOSI_F <= 1'b0; + end + + + if(data_valid_countdown[15:0] <= 16'd128 && data_valid_countdown[15:0] > 16'd80) + CAL_F <= 1'b1; + else + CAL_F <= 1'b0; + + if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0) + begin + TP_EN_F <= 1'b1; + TR_MGC_F <= 1'b1; + end + else + begin + TP_EN_F <= 1'b0; + TR_MGC_F <= 1'b0; + end + + if(data_valid_countdown[15:0] == 16'd48) + PRF <= vio_trdirection; + else + PRF <= PRF; + + if(sys_rst) + rst_countdown[15:0] <= 16'd100; + else if(rst_countdown[15:0] != 0) + begin + rst_countdown[15:0] <= rst_countdown[15:0] - 16'd1; + rst_n <= 1'b0; + end + else + begin + rst_countdown[15:0] <= rst_countdown[15:0]; + rst_n <= 1'b1; + end + + // 天线控制 + if(data_valid_countdown[15:0] == vio_PrecessTime[15:0]) + Ant_CtrlWord_running[127:0] <= Ant_CtrlWord[127:0]; + else + Ant_CtrlWord_running[127:0] <= {Ant_CtrlWord_running[126:0],1'b0}; + + if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd128 && data_valid_countdown[15:0] < vio_PrecessTime[15:0]) + begin + Ant_EN <= 1'b0; + Ant_DATA <= Ant_CtrlWord_running[127]; + end + else + begin + Ant_EN <= 1'b1; + Ant_DATA <= 1'b0; + end + + if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0) + Ant_DARY <= 1'b0; + else + Ant_DARY <= 1'b1; + + if(data_valid_countdown[15:0] == 16'd48) + Ant_TR <= vio_trdirection; + else + Ant_TR <= Ant_TR; + end + + +//RF recv_data +reg [1:0] state_rfdata; +reg SPI_SYN_F_d1 = 1'b0; +reg [15:0] cnt_rfdata = 16'd0; +reg [95:0] RF_RecvWord = 96'd0; +reg [95:0] RF_RecvWord_last = 96'd0; + +reg [7:0] RF_temperature = 8'd0 ; +reg [7:0] RF_IFlocked = 8'd0 ; +reg [7:0] RF_RFAlocked = 8'd0 ; +reg [7:0] RF_RFBlocked = 8'd0 ; +reg [3:0] RF_ch1mgc = 4'd0 ; +reg [3:0] RF_ch2mgc = 4'd0 ; +reg [3:0] RF_ch3mgc = 4'd0 ; +reg [3:0] RF_ch4mgc = 4'd0 ; +reg [31:0] RF_Framecount = 32'd0 ; + +always @ (posedge clk_48m) begin + if(sys_rst) begin + state_rfdata[1:0] <= 2'd0; + SPI_SYN_F_d1 <= 1'b0; + RF_RecvWord[95:0] <= 96'd0; + cnt_rfdata[15:0] <= 16'd0; + RF_temperature[7:0] <= 8'd0 ; + RF_IFlocked[7:0] <= 8'd0 ; + RF_RFAlocked[7:0] <= 8'd0 ; + RF_RFBlocked[7:0] <= 8'd0 ; + RF_ch1mgc[3:0] <= 4'd0 ; + RF_ch2mgc[3:0] <= 4'd0 ; + RF_ch3mgc[3:0] <= 4'd0 ; + RF_ch4mgc[3:0] <= 4'd0 ; + RF_Framecount[31:0] <= 32'd0; + end + else begin + RF_RecvWord[95:0] <= {RF_RecvWord[94:0],SPI_MISO_F}; + + if (RF_RecvWord[95:88] == 8'hAA && RF_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾 + RF_temperature[7:0] <= RF_RecvWord[87:80]; + RF_IFlocked[7:0] <= RF_RecvWord[79:72]; + RF_RFAlocked[7:0] <= RF_RecvWord[71:64]; + RF_RFBlocked[7:0] <= RF_RecvWord[63:56]; + RF_ch1mgc[3:0] <= RF_RecvWord[55:52]; + RF_ch2mgc[3:0] <= RF_RecvWord[51:48]; + RF_ch3mgc[3:0] <= RF_RecvWord[47:44]; + RF_ch4mgc[3:0] <= RF_RecvWord[43:40]; + RF_Framecount[31:0] <= RF_RecvWord[39:8]; + RF_RecvWord_last <= RF_RecvWord; + end + else begin // hold otherwise + RF_temperature[7:0] <= RF_temperature[7:0]; + RF_IFlocked[7:0] <= RF_IFlocked[7:0] ; + RF_RFAlocked[7:0] <= RF_RFAlocked[7:0] ; + RF_RFBlocked[7:0] <= RF_RFBlocked[7:0] ; + RF_ch1mgc[3:0] <= RF_ch1mgc[3:0] ; + RF_ch2mgc[3:0] <= RF_ch2mgc[3:0] ; + RF_ch3mgc[3:0] <= RF_ch3mgc[3:0] ; + RF_ch4mgc[3:0] <= RF_ch4mgc[3:0] ; + RF_Framecount[31:0] <= RF_Framecount[31:0]; + RF_RecvWord_last <= RF_RecvWord_last; + end + end +end +// 天线的输出时钟转换 +reg Ant_dclk_96m = 1; +wire [3:0] fifo_wr_din, fifo_rd_dout; +wire fifo_full, fifo_empty; +reg Ant_EN_96m = 0; +reg Ant_DATA_96m = 0; +reg Ant_DARY_96m = 1; +reg Ant_TR_96m = 0; +assign fifo_wr_din[3] = Ant_EN; +assign fifo_wr_din[2] = Ant_DATA; +assign fifo_wr_din[1] = Ant_DARY; +assign fifo_wr_din[0] = Ant_TR; +reg fifo_rd_en = 0; +reg fifo_rst = 0; +reg [8:0] Ant_clk_countdown = 0; +always @(posedge clk_96m) + begin + fifo_rst <= sys_rst; + + fifo_rd_en <= (fifo_rst == 1'b1)? 1'b0:!fifo_rd_en; + + if(fifo_rd_en) + {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= fifo_rd_dout[3:0]; + else + {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m}; + + if(fifo_rd_en && Ant_EN_96m && !fifo_rd_dout[3]) + Ant_clk_countdown[8:0] <= 9'd276; + else if(Ant_clk_countdown[8:0] != 9'd0) + Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0] - 9'd1; + else + Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0]; + end +assign ant_clk = !Ant_clk_countdown[0]; +assign ant_en = Ant_EN_96m; +assign ant_data = Ant_DATA_96m; +assign ant_tr = Ant_TR_96m; +assign ant_dary = Ant_DARY_96m; + +fifo_AntCtrl fifo_AntCtrl +( + .rst (fifo_rst ), // input wire rst + .wr_clk (clk_48m ), // input wire wr_clk + .rd_clk (clk_96m ), // input wire rd_clk + .din (fifo_wr_din[3:0] ), // input wire [3 : 0] din + .wr_en (!fifo_rst ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (fifo_rd_dout[3:0] ), // output wire [3 : 0] dout + .full (fifo_full ), // output wire full + .empty (fifo_empty ) // output wire empty +); +//Ant recv_data +reg [1:0] state_antdata; +reg Ant_EN_96m_d1 = 1'b0; +reg [15:0] cnt_antdata = 16'd0; +reg [95:0] Ant_RecvWord = 'b0; +reg [95:0] Ant_RecvWord_last = 'b0; + +reg [7:0] Ant_Ant_Volt = 8'd0 ; +reg [7:0] Ant_RF_Volt = 8'd0 ; +reg [7:0] Ant_IF_Volt = 8'd0 ; +reg [7:0] Ant_state = 8'd0 ; +reg [31:0] Ant_Framecount = 32'd0 ; + +always @ (posedge clk_96m) begin + if(sys_rst) begin + state_antdata[1:0] <= 2'd0; + Ant_EN_96m_d1 <= 1'b0; + Ant_RecvWord[95:0] <= 'd0; + cnt_antdata[15:0] <= 16'd0; + Ant_Ant_Volt[7:0] <= 8'd0 ; + Ant_RF_Volt[7:0] <= 8'd0 ; + Ant_IF_Volt[7:0] <= 8'd0 ; + Ant_state[7:0] <= 8'd0 ; + Ant_Framecount[31:0] <= 32'd0; + end + else begin + Ant_RecvWord[95:0] <= {Ant_RecvWord[94:0],ant_dout}; + + if(Ant_RecvWord[95:88] == 8'hAA && Ant_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾 + Ant_Ant_Volt[7:0] <= Ant_RecvWord[87:80]; + Ant_RF_Volt[7:0] <= Ant_RecvWord[79:72]; + Ant_IF_Volt[7:0] <= Ant_RecvWord[71:64]; + Ant_state[7:0] <= Ant_RecvWord[47:40]; + Ant_Framecount[31:0] <= Ant_RecvWord[39:8] ; + Ant_RecvWord_last <= Ant_RecvWord ; + end + else begin // hold otherwise + Ant_Ant_Volt[7:0] <= Ant_Ant_Volt[7:0] ; + Ant_RF_Volt[7:0] <= Ant_RF_Volt[7:0] ; + Ant_IF_Volt[7:0] <= Ant_IF_Volt[7:0] ; + Ant_state[7:0] <= Ant_state[7:0] ; + Ant_Framecount[31:0] <= Ant_Framecount[31:0] ; + Ant_RecvWord_last <= Ant_RecvWord_last ; + end + end + +end +Sisyif uut( + .clk_40m(clk_32m), + .clk_20m(clk_19p2m), + .SPI_CLK_F(clk_48m), + .rst_n(rst_n), + .SPI_SYN_F(SPI_SYN_F), + .SPI_MOSI_F(SPI_MOSI_F), + .SPI_MISO_F(SPI_MISO_F), + .TP_EN_F(TP_EN_F), + .TR_MGC_F(TR_MGC_F), + .CAL_F(CAL_F), + .PRF(PRF), + .standby(rf_standby), + .SW_PLL(rf_sw_pll), + .T(rf_t), + .R(rf_r), + .SW_BPF(rf_sw_bpf), + .SCLK1(rf_sclk1), + .SDIO1(rf_sdio1), + .CS1(rf_cs1), + .LD1(rf_ld1), + .SCLK2(rf_sclk2), + .SDIO2(rf_sdio2), + .CS2(rf_cs2), + .LD2(rf_ld2), + .SCLK3(rf_sclk3), + .SDIO3(rf_sdio3), + .CS3(rf_cs3), + .LD3(rf_ld3), + .TMGC_16db(rf_tmgc_16), + .TMGC_8db(rf_tmgc_8), + .TMGC_4db(rf_tmgc_4), + .TMGC_2db(rf_tmgc_2), + .TMGC_1db(rf_tmgc_1), + .RMGC_16db(rf_rmgc_16), + .RMGC_8db(rf_rmgc_8), + .RMGC_4db(rf_rmgc_4), + .RMGC_2db(rf_rmgc_2), + .RMGC_1db(rf_rmgc_1), + .ENABLE(rf_enable), + .SC(rf_sc), + .SD(rf_sd), + .END_SYN(rf_endsyn), + .SDOUT(rf_sdout), + .DQ_WD(rf_dq_wd), + .SW_RX(rf_sw_rx) + ); + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/clk_dist.v b/projects/duifei/duifei_online_acq_par/rtl/clk_dist.v new file mode 100644 index 00000000..8dfb48e4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/clk_dist.v @@ -0,0 +1,133 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/01 11:15:25 +// Design Name: +// Module Name: clk_dist +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Clock distribution module +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module clk_dist +( + // input clocks + input clk_250m_p , // generated by ad9516, 250mhz + input clk_250m_n , + input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz + input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz + + // output clocks & reset + // global reset + output sys_rst , // global reset signal, active high + output ant_rst , // phased-array & rf control reset signal, active high + + // pl signal processing clock + output sys_clk , // 41.6667mhz + output sys_clk_2x , // 83.3333mhz + output sys_clk_3x , // 125mhz + output sys_clk_4x , // 166.6667mhz + output sys_clk_ld , // system main clock locked indicator + + // ad9361-1 clocks + output ad9361_1_clk , // 41.6667mhz + output ad9361_1_clk_2x , // 83.3333mhz + output ad9361_1_clk_3x , // 125mhz + output ad9361_1_clk_4x , // 166.6667mhz + output ad9361_1_clk_ld , // ad9361-1 clock group locked indicator + + // ad9361-2 clocks + output ad9361_2_clk , // 41.6667mhz + output ad9361_2_clk_2x , // 83.3333mhz + output ad9361_2_clk_3x , // 125mhz + output ad9361_2_clk_4x , // 166.6667mhz + output ad9361_2_clk_ld , // ad9361-2 clock group locked indicator + + // phased-array & rf control clocks + output clk_96m , + output clk_48m , + output clk_32m , + output clk_19p2m +); + +assign sys_clk = ad9361_1_clk ; +assign sys_clk_2x = ad9361_1_clk_2x; +assign sys_clk_3x = ad9361_1_clk_3x; +assign sys_clk_4x = ad9361_1_clk_4x; +assign sys_clk_ld = ad9361_1_clk_ld; + +assign sys_rst = ~sys_clk_ld; + +ad9361_clk_gen_cmos_2t2r u_ad9361_1_clk_gen +( + // Clock out ports + .clk_out1 (ad9361_1_clk ), // output clk_out1 + .clk_out2 (ad9361_1_clk_2x ), // output clk_out2 + .clk_out3 (ad9361_1_clk_3x ), // output clk_out3 + .clk_out4 (ad9361_1_clk_4x ), // output clk_out4 + // Status and control signals + .locked (ad9361_1_clk_ld ), // output locked + // Clock in ports + .clk_in1 (ad9361_1_rx_data_clk ) // input clk_in1 +); + +ad9361_clk_gen_cmos_2t2r u_ad9361_2_clk_gen +( + // Clock out ports + .clk_out1 (ad9361_2_clk ), // output clk_out1 + .clk_out2 (ad9361_2_clk_2x ), // output clk_out2 + .clk_out3 (ad9361_2_clk_3x ), // output clk_out3 + .clk_out4 (ad9361_2_clk_4x ), // output clk_out4 + // Status and control signals + .locked (ad9361_2_clk_ld ), // output locked + // Clock in ports + .clk_in1 (ad9361_2_rx_data_clk ) // input clk_in1 +); + +wire ant_clk_stg1_96m; +wire ant_clk_stg1_ld; +wire ant_clk_stg2_ld; + +assign ant_rst = ~ant_clk_stg2_ld; + +ant_clk_gen_stg1 u_ant_clk_gen_stg1 +( + // Clock out ports + .clk_out1 (ant_clk_stg1_96m ), // output clk_out1 + // Status and control signals + .locked (ant_clk_stg1_ld ), // output locked + // Clock in ports + .clk_in1_p (clk_250m_p ), // input clk_in1_p + .clk_in1_n (clk_250m_n ) // input clk_in1_n +); + +ant_clk_gen_stg2 u_ant_clk_gen_stg2 +( + // Clock out ports + .clk_out1 (clk_96m ), // output clk_out1 + .clk_out2 (clk_48m ), // output clk_out2 + .clk_out3 (clk_32m ), // output clk_out3 + .clk_out4 (clk_19p2m ), // output clk_out4 + // Status and control signals + .locked (ant_clk_stg2_ld ), // output locked + // Clock in ports + .clk_in1 (ant_clk_stg1_96m ) // input clk_in1 +); + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/freq_comp.v b/projects/duifei/duifei_online_acq_par/rtl/freq_comp.v new file mode 100644 index 00000000..eb008429 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/freq_comp.v @@ -0,0 +1,715 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/06/2023 02:33:07 PM +// Design Name: +// Module Name: freq_comp +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module freq_comp +#( + parameter DATA_I_WIDTH = 12, + parameter DATA_O_WIDTH = 18, + + parameter FREQ_WORD_WIDTH = 32, + parameter FREQ_WORD_LOWER = -4194304, + parameter FREQ_WORD_UPPER = 4194303, + parameter FREQ_WORD_STEP = 1024, + + parameter MAX_DMF_NUM = 64, + parameter CHANNEL_NUM = 4, + + // length of pseudorandom bit sequence, need to be a power of 2 + parameter PRBS_LEN = 128, + // interpolation of input signal, need to be a power of 2 + parameter INTERP_RATE = 8, + // signal processing interpolation, need to be a power of 2 + parameter PROCESS_INTERP = 2, + // possible position of pn code + parameter PRBS_POS = PRBS_LEN*PROCESS_INTERP +) +( + // clock & reset + input clk , + input rst , + + // module enable switch + input freq_comp_start , + output freq_comp_busy , + + // input data + input rx_data_valid , + input [DATA_I_WIDTH-1 : 0] rx_ch1_i , + input [DATA_I_WIDTH-1 : 0] rx_ch1_q , + input [DATA_I_WIDTH-1 : 0] rx_ch2_i , + input [DATA_I_WIDTH-1 : 0] rx_ch2_q , + input [DATA_I_WIDTH-1 : 0] rx_ch3_i , + input [DATA_I_WIDTH-1 : 0] rx_ch3_q , + input [DATA_I_WIDTH-1 : 0] rx_ch4_i , + input [DATA_I_WIDTH-1 : 0] rx_ch4_q , + + // configuration + input [$clog2(MAX_DMF_NUM)-1 : 0] dmf_num_per_ch , + + input [FREQ_WORD_WIDTH-1 : 0] freq_manual , + input freq_manual_en , + + // output frequency result + output [FREQ_WORD_WIDTH-1 : 0] freq_target , + output freq_target_valid , + + // output dmf result + output ch_peak_valid , + + output [DATA_O_WIDTH-1 : 0] ch1_peak_value_abs , + output [DATA_O_WIDTH-1 : 0] ch1_peak_value_i , + output [DATA_O_WIDTH-1 : 0] ch1_peak_value_q , + output [$clog2(PRBS_POS)-1 : 0] ch1_peak_index , + + output [DATA_O_WIDTH-1 : 0] ch2_peak_value_abs , + output [DATA_O_WIDTH-1 : 0] ch2_peak_value_i , + output [DATA_O_WIDTH-1 : 0] ch2_peak_value_q , + output [$clog2(PRBS_POS)-1 : 0] ch2_peak_index , + + output [DATA_O_WIDTH-1 : 0] ch3_peak_value_abs , + output [DATA_O_WIDTH-1 : 0] ch3_peak_value_i , + output [DATA_O_WIDTH-1 : 0] ch3_peak_value_q , + output [$clog2(PRBS_POS)-1 : 0] ch3_peak_index , + + output [DATA_O_WIDTH-1 : 0] ch4_peak_value_abs , + output [DATA_O_WIDTH-1 : 0] ch4_peak_value_i , + output [DATA_O_WIDTH-1 : 0] ch4_peak_value_q , + output [$clog2(PRBS_POS)-1 : 0] ch4_peak_index +); + +localparam STATE_NUM = 5; +localparam [$clog2(STATE_NUM)-1:0] + STATE_IDLE = 0, + STATE_FREQ_SW = 1, + STATE_FREQ_DMF = 2, + STATE_CH_SW = 3, + STATE_CH_DMF = 4; + +localparam FREQ_WORD_LOWER_WIDTH = $clog2(FREQ_WORD_LOWER); +localparam FREQ_WORD_UPPER_WIDTH = $clog2(FREQ_WORD_UPPER); +localparam FREQ_WORD_STEP_WIDTH = $clog2(FREQ_WORD_STEP ); + +localparam DDS_DATA_WIDTH = 8; +localparam STABLE_COUNT_MOD = 16; + +localparam CMPY_A_WIDTH = DATA_I_WIDTH; +localparam CMPY_B_WIDTH = DDS_DATA_WIDTH; +localparam CMPY_P_WIDTH = CMPY_A_WIDTH+CMPY_B_WIDTH; +localparam CMPY_P_FULL_WIDTH = CMPY_P_WIDTH+1; +localparam CMPY_OUTPUT_WIDTH = DATA_I_WIDTH; + +genvar m; + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////// Center State Control ///////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// current and next state +reg [$clog2(STATE_NUM)-1 : 0] state_curr = STATE_IDLE; +reg [$clog2(STATE_NUM)-1 : 0] state_next = STATE_IDLE; + +// edge detection +reg freq_comp_start_d1 = 'b0; +reg freq_comp_start_d2 = 'b0; + +// stable counter, for dds frequency and complex multiplier to be ready +reg [$clog2(STABLE_COUNT_MOD)-1 : 0] cnt_stable = 'b0; + +// dmf finish indicator +wire dmf_freq_last_peak_valid; +wire dmf_ch_last_peak_valid [0 : CHANNEL_NUM-1]; + +// current frequency word +reg signed [FREQ_WORD_WIDTH-1 : 0] freq_word = 'b0; + +// frequency scan finish indicator +reg freq_end = 'b0; + +// ----------------------------------------------------------------------------- +// 1st always block, sequential state transition +// ----------------------------------------------------------------------------- +always @(posedge clk) begin + if (rst) begin + state_curr <= STATE_IDLE; + end + else begin + state_curr <= state_next; + end +end + +// ----------------------------------------------------------------------------- +// 2nd always block, combinational condition judgment +// ----------------------------------------------------------------------------- +always @(*) begin + case (state_curr) + STATE_IDLE: begin + if (rx_data_valid && (freq_comp_start_d2 != freq_comp_start_d1)) begin + // when input data valid & either edge of start signal is detected + state_next = STATE_FREQ_SW; + end + else begin + state_next = STATE_IDLE; + end + end + STATE_FREQ_SW: begin + if (cnt_stable == STABLE_COUNT_MOD-1) begin + // wait util dds frequency and complex multiplier is ready + state_next = STATE_FREQ_DMF; + end + else begin + state_next = STATE_FREQ_SW; + end + end + STATE_FREQ_DMF: begin + if (dmf_freq_last_peak_valid) begin + // when dmf is done, check if frequency compensation is over + state_next = freq_end ? STATE_CH_SW : STATE_FREQ_SW; + end + else begin + state_next = STATE_FREQ_DMF; + end + end + STATE_CH_SW : begin + if (cnt_stable == STABLE_COUNT_MOD-1) begin + // wait util dds frequency and complex multiplier is ready + state_next = STATE_CH_DMF; + end + else begin + state_next = STATE_CH_SW; + end + end + STATE_CH_DMF : begin + if (dmf_ch_last_peak_valid[0]) begin + // wait until dmf is done + state_next = STATE_IDLE; + end + else begin + state_next = STATE_CH_DMF; + end + end + default: begin + // hold + state_next = state_next; + end + endcase +end + +// ----------------------------------------------------------------------------- +// 3rd always block, the sequential FSM output +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// edge detection +// ----------------------------------------------------------------------------- +always @(posedge clk) begin + freq_comp_start_d1 <= freq_comp_start; + freq_comp_start_d2 <= freq_comp_start_d1; +end + +// ----------------------------------------------------------------------------- +// busy indicator +// ----------------------------------------------------------------------------- +reg freq_comp_busy_buf = 'b0; + +assign freq_comp_busy = freq_comp_busy_buf; + +always @(posedge clk) begin + if (rst) begin + freq_comp_busy_buf <= 'b0; + end + else begin + case (state_next) + // change between states + STATE_IDLE : freq_comp_busy_buf <= 1'b0; + STATE_FREQ_SW : freq_comp_busy_buf <= 1'b1; + STATE_FREQ_DMF: freq_comp_busy_buf <= 1'b1; + STATE_CH_SW : freq_comp_busy_buf <= 1'b1; + STATE_CH_DMF : freq_comp_busy_buf <= 1'b1; + default : freq_comp_busy_buf <= freq_comp_busy_buf; + endcase + end +end + +// ----------------------------------------------------------------------------- +// stable counter, for dds frequency and complex multiplier to be ready +// ----------------------------------------------------------------------------- +always @(posedge clk) begin + if (rst) begin + cnt_stable <= 'b0; + end + else case (state_curr) + // change within one state + STATE_FREQ_SW: cnt_stable <= cnt_stable + 1'b1; + STATE_CH_SW : cnt_stable <= cnt_stable + 1'b1; + default : cnt_stable <= 'b0; + endcase +end + +// ----------------------------------------------------------------------------- +// frequency word control +// ----------------------------------------------------------------------------- +// record the frequency word generating the maximum peak +reg [FREQ_WORD_WIDTH-1 : 0] max_freq_peak_freq = 'b0; + +always @(posedge clk) begin + if (rst) begin + freq_word <= FREQ_WORD_LOWER; + end + else case (state_next) + // change between states + STATE_FREQ_SW: begin + if (state_curr == STATE_IDLE) begin + // initialization + freq_word <= FREQ_WORD_LOWER; + end + else if (state_curr == STATE_FREQ_DMF) begin + // switch frequency + freq_word <= freq_word + FREQ_WORD_STEP; + end + end + STATE_CH_SW: begin + freq_word <= (freq_manual_en) ? freq_manual : max_freq_peak_freq; + end + default: begin + freq_word <= freq_word; + end + endcase +end + +// ----------------------------------------------------------------------------- +// frequency scan finish indicator +// ----------------------------------------------------------------------------- +always @(posedge clk) begin + if (rst) begin + freq_end <= 'b0; + end + else if (freq_word > FREQ_WORD_UPPER) begin + freq_end <= 1'b1; + end + else begin + freq_end <= 'b0; + end +end + + + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////// DDS ////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +localparam AXIS_FREQ_WORD_WIDTH = 8*((FREQ_WORD_WIDTH-1)/8+1); +localparam AXIS_DDS_DATA_WIDTH = 8*((DDS_DATA_WIDTH-1)/8+1); + +wire [DDS_DATA_WIDTH-1:0] sin_dds, cos_dds; +wire dds_valid; + +wire dds_s_axis_config_tvalid; +wire [AXIS_FREQ_WORD_WIDTH-1 : 0] dds_s_axis_config_ttdata; +wire dds_m_axis_data_tvalid ; +wire [2*AXIS_DDS_DATA_WIDTH-1 : 0] dds_m_axis_data_ttdata ; + +assign dds_s_axis_config_tvalid = freq_comp_busy; +assign dds_s_axis_config_ttdata = freq_word; +assign dds_valid = dds_m_axis_data_tvalid; +assign {sin_dds,cos_dds} = dds_m_axis_data_ttdata; + +dds_32b_8b u_dds_bb_shift +( + .aclk (clk ), // input wire aclk + .s_axis_config_tvalid (dds_s_axis_config_tvalid ), // input wire s_axis_config_tvalid + .s_axis_config_tdata (dds_s_axis_config_ttdata ), // input wire [31 : 0] s_axis_config_tdata + .m_axis_data_tvalid (dds_m_axis_data_tvalid ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (dds_m_axis_data_ttdata ) // output wire [15 : 0] m_axis_data_tdata +); + +//////////////////////////////////////////////////////////////////////////////// +///////////// Complex Multiplier for Frequency Shift Compensation ////////////// +//////////////////////////////////////////////////////////////////////////////// +localparam AXIS_CMPY_A_WIDTH = 8*((CMPY_A_WIDTH-1)/8+1); +localparam AXIS_CMPY_B_WIDTH = 8*((CMPY_B_WIDTH-1)/8+1); +localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_FULL_WIDTH-1)/8+1); + +// input data +wire [DATA_I_WIDTH-1 : 0] din_freq_real; +wire [DATA_I_WIDTH-1 : 0] din_freq_imag; + +assign din_freq_real = rx_ch2_i; +assign din_freq_imag = rx_ch2_q; + +// cmpy +wire [CMPY_OUTPUT_WIDTH-1 : 0] din_freq_cxr_real; +wire [CMPY_OUTPUT_WIDTH-1 : 0] din_freq_cxr_imag; +wire din_freq_cxr_valid; // declared ahead + +wire cmpy_a_valid; +wire [2*AXIS_CMPY_A_WIDTH-1 : 0] cmpy_a ; +wire cmpy_b_valid; +wire [2*AXIS_CMPY_B_WIDTH-1 : 0] cmpy_b ; +wire cmpy_p_valid; +wire [2*AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p ; + +assign cmpy_a_valid = freq_comp_busy; +assign cmpy_b_valid = dds_valid; +assign din_freq_cxr_valid = cmpy_p_valid; + +// sign bit extension to fit axis 8-bit data format +assign cmpy_a = {{(AXIS_CMPY_A_WIDTH-CMPY_A_WIDTH){din_freq_imag[DATA_I_WIDTH-1]}},din_freq_imag, + {(AXIS_CMPY_A_WIDTH-CMPY_A_WIDTH){din_freq_real[DATA_I_WIDTH-1]}},din_freq_real}; +assign cmpy_b = {{(AXIS_CMPY_B_WIDTH-CMPY_B_WIDTH){sin_dds[DDS_DATA_WIDTH-1]}},sin_dds, + {(AXIS_CMPY_B_WIDTH-CMPY_B_WIDTH){cos_dds[DDS_DATA_WIDTH-1]}},cos_dds}; + +if (CMPY_OUTPUT_WIDTH > CMPY_P_WIDTH) begin + // append zeros + assign din_freq_cxr_real = {cmpy_p[0 +: CMPY_P_WIDTH],{(CMPY_OUTPUT_WIDTH-CMPY_P_WIDTH){1'b0}}}; + assign din_freq_cxr_imag = {cmpy_p[AXIS_CMPY_P_WIDTH +: CMPY_P_WIDTH],{(CMPY_OUTPUT_WIDTH-CMPY_P_WIDTH){1'b0}}}; +end +else begin + // truncate valid msb + assign din_freq_cxr_real = cmpy_p[CMPY_P_WIDTH-1 -: CMPY_OUTPUT_WIDTH]; + assign din_freq_cxr_imag = cmpy_p[AXIS_CMPY_P_WIDTH+CMPY_P_WIDTH-1 -: CMPY_OUTPUT_WIDTH]; +end + +cmpy_12x8 u_cmpy_12x8_freq +( + .aclk (clk ), // input wire aclk + .s_axis_a_tvalid (cmpy_a_valid ), // input wire s_axis_a_tvalid + .s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid (cmpy_b_valid ), // input wire s_axis_b_tvalid + .s_axis_b_tdata (cmpy_b ), // input wire [15 : 0] s_axis_b_tdata + .m_axis_dout_tvalid (cmpy_p_valid ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (cmpy_p ) // output wire [47 : 0] m_axis_dout_tdata +); + +//////////////////////////////////////////////////////////////////////////////// +/////////// Digital Matched Filter for Frequency Shift Compensation //////////// +//////////////////////////////////////////////////////////////////////////////// +reg dmf_freq_start = 'b0; +wire dmf_freq_busy; + +wire dmf_freq_din_valid; +wire [DATA_I_WIDTH-1 : 0] dmf_freq_din_real; +wire [DATA_I_WIDTH-1 : 0] dmf_freq_din_imag; + +wire dmf_freq_peak_valid; +wire [DATA_O_WIDTH-1 : 0] dmf_freq_peak_value_abs; +wire [DATA_O_WIDTH-1 : 0] dmf_freq_peak_value_i; +wire [DATA_O_WIDTH-1 : 0] dmf_freq_peak_value_q; +wire [$clog2(PRBS_POS)-1 : 0] dmf_freq_peak_index; + +wire [DATA_O_WIDTH-1 : 0] dmf_freq_moduli_abs; + +assign dmf_freq_din_valid = din_freq_cxr_valid; + +if (DATA_I_WIDTH > CMPY_OUTPUT_WIDTH) begin + // append zeros + assign dmf_freq_din_real = {din_freq_cxr_real,{(DATA_I_WIDTH-CMPY_OUTPUT_WIDTH){1'b0}}}; + assign dmf_freq_din_imag = {din_freq_cxr_imag,{(DATA_I_WIDTH-CMPY_OUTPUT_WIDTH){1'b0}}}; +end +else begin + // truncate msb + assign dmf_freq_din_real = din_freq_cxr_real[CMPY_OUTPUT_WIDTH-1 -: DATA_I_WIDTH]; + assign dmf_freq_din_imag = din_freq_cxr_imag[CMPY_OUTPUT_WIDTH-1 -: DATA_I_WIDTH]; +end + + +// ----------------------------------------------------------------------------- +// dmf start control +// ----------------------------------------------------------------------------- +always @(posedge clk) begin + if (rst) begin + dmf_freq_start <= 'b0; + end + else case (state_next) + STATE_FREQ_DMF: dmf_freq_start <= (state_curr == STATE_FREQ_SW) ? ~dmf_freq_start : dmf_freq_start; + default: dmf_freq_start <= dmf_freq_start; + endcase +end + +// dmf instantiation +rx_dmf #( + .PRBS_LEN (PRBS_LEN ), + .INTERP_RATE (INTERP_RATE ), + .PROCESS_INTERP (PROCESS_INTERP ), + .DATA_I_WIDTH (DATA_I_WIDTH ), + .DATA_O_WIDTH (DATA_O_WIDTH ) +) u_rx_dmf_freq +( + .clk (clk ), + .rst (rst ), + + .dmf_start (dmf_freq_start ), + .dmf_busy (dmf_freq_busy ), + + .dmf_num (1 ), + + .din_valid (dmf_freq_din_valid ), + .din_real (dmf_freq_din_real ), + .din_imag (dmf_freq_din_imag ), + + .peak_valid (dmf_freq_peak_valid ), + .last_peak_valid(dmf_freq_last_peak_valid ), + .peak_value_abs (dmf_freq_peak_value_abs ), + .peak_value_i (dmf_freq_peak_value_i ), + .peak_value_q (dmf_freq_peak_value_q ), + .peak_index (dmf_freq_peak_index ) +); + +assign dmf_freq_moduli_abs = u_rx_dmf_freq.moduli_abs; + +// ----------------------------------------------------------------------------- +// peak finding at different frequencies +// ----------------------------------------------------------------------------- +reg max_freq_peak_valid = 'b0; +reg [DATA_O_WIDTH-1 : 0] max_freq_peak_value_abs = 'b0; +reg [DATA_O_WIDTH-1 : 0] max_freq_peak_value_i = 'b0; +reg [DATA_O_WIDTH-1 : 0] max_freq_peak_value_q = 'b0; +reg [$clog2(PRBS_POS)-1 : 0] max_freq_peak_index = 'b0; + +// output result to port +assign freq_target_valid = max_freq_peak_valid; +assign freq_target = max_freq_peak_freq; + +always @(posedge clk) begin + if (rst) begin + max_freq_peak_valid <= 'b0; + max_freq_peak_value_abs <= 'b0; + max_freq_peak_value_i <= 'b0; + max_freq_peak_value_q <= 'b0; + max_freq_peak_index <= 'b0; + max_freq_peak_freq <= 'b0; + end + else case (state_next) + STATE_IDLE: begin + max_freq_peak_valid <= 'b0; + max_freq_peak_value_abs <= 'b0; + max_freq_peak_value_i <= 'b0; + max_freq_peak_value_q <= 'b0; + max_freq_peak_index <= 'b0; + max_freq_peak_freq <= 'b0; + end + STATE_FREQ_SW: begin + if ((state_curr == STATE_FREQ_DMF) && (dmf_freq_peak_value_abs > max_freq_peak_value_abs)) begin + // at the end of [STATE_FREQ_DMF] state, check if peak is valid + max_freq_peak_value_abs <= dmf_freq_peak_value_abs; + max_freq_peak_value_i <= dmf_freq_peak_value_i ; + max_freq_peak_value_q <= dmf_freq_peak_value_q ; + max_freq_peak_index <= dmf_freq_peak_index ; + max_freq_peak_freq <= freq_word ; + end + else begin + // hold otherwise + max_freq_peak_value_abs <= max_freq_peak_value_abs; + max_freq_peak_value_i <= max_freq_peak_value_i ; + max_freq_peak_value_q <= max_freq_peak_value_q ; + max_freq_peak_index <= max_freq_peak_index ; + max_freq_peak_freq <= max_freq_peak_freq ; + end + end + STATE_CH_SW: begin + if (state_curr == STATE_FREQ_DMF) begin + // indicate the target frequency word is found + max_freq_peak_valid <= 1'b1; + end + else begin + max_freq_peak_valid <= 'b0; + end + end + default: begin + max_freq_peak_valid <= 'b0; + max_freq_peak_value_abs <= max_freq_peak_value_abs; + max_freq_peak_value_i <= max_freq_peak_value_i ; + max_freq_peak_value_q <= max_freq_peak_value_q ; + max_freq_peak_index <= max_freq_peak_index ; + max_freq_peak_freq <= max_freq_peak_freq ; + end + endcase +end + +//////////////////////////////////////////////////////////////////////////////// +//////////////////// Complex Multiplier for Signal Channels //////////////////// +//////////////////////////////////////////////////////////////////////////////// +// cmpy input +wire [CMPY_OUTPUT_WIDTH-1 : 0] din_ch_real [0 : CHANNEL_NUM-1]; +wire [CMPY_OUTPUT_WIDTH-1 : 0] din_ch_imag [0 : CHANNEL_NUM-1]; + +assign din_ch_real[0] = rx_ch1_i; +assign din_ch_real[1] = rx_ch2_i; +assign din_ch_real[2] = rx_ch3_i; +assign din_ch_real[3] = rx_ch4_i; +assign din_ch_imag[0] = rx_ch1_q; +assign din_ch_imag[1] = rx_ch2_q; +assign din_ch_imag[2] = rx_ch3_q; +assign din_ch_imag[3] = rx_ch4_q; + +// cmpy output +wire [CMPY_OUTPUT_WIDTH-1 : 0] din_ch_cxr_real [0 : CHANNEL_NUM-1]; +wire [CMPY_OUTPUT_WIDTH-1 : 0] din_ch_cxr_imag [0 : CHANNEL_NUM-1]; +wire din_ch_cxr_valid [0 : CHANNEL_NUM-1]; + +generate +for (m = 0; m < CHANNEL_NUM; m = m + 1) begin: cmpy_ch + + wire cmpy_a_valid; + wire [2*AXIS_CMPY_A_WIDTH-1 : 0] cmpy_a ; + wire cmpy_b_valid; + wire [2*AXIS_CMPY_B_WIDTH-1 : 0] cmpy_b ; + wire cmpy_p_valid; + wire [2*AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p ; + + assign cmpy_a_valid = freq_comp_busy; + assign cmpy_b_valid = dds_valid; + assign din_ch_cxr_valid[m] = cmpy_p_valid; + + // sign bit extension to fit axis 8-bit data format + assign cmpy_a = {{(AXIS_CMPY_A_WIDTH-CMPY_A_WIDTH){din_ch_imag[m][DATA_I_WIDTH-1]}},din_ch_imag[m], + {(AXIS_CMPY_A_WIDTH-CMPY_A_WIDTH){din_ch_real[m][DATA_I_WIDTH-1]}},din_ch_real[m]}; + assign cmpy_b = {{(AXIS_CMPY_B_WIDTH-CMPY_B_WIDTH){sin_dds[DDS_DATA_WIDTH-1]}},sin_dds, + {(AXIS_CMPY_B_WIDTH-CMPY_B_WIDTH){cos_dds[DDS_DATA_WIDTH-1]}},cos_dds}; + + if (CMPY_OUTPUT_WIDTH > CMPY_P_WIDTH) begin + // append zeros + assign din_ch_cxr_real[m] = {cmpy_p[0 +: CMPY_P_WIDTH],{(CMPY_OUTPUT_WIDTH-CMPY_P_WIDTH){1'b0}}}; + assign din_ch_cxr_imag[m] = {cmpy_p[AXIS_CMPY_P_WIDTH +: CMPY_P_WIDTH],{(CMPY_OUTPUT_WIDTH-CMPY_P_WIDTH){1'b0}}}; + end + else begin + // truncate valid msb + assign din_ch_cxr_real[m] = cmpy_p[CMPY_P_WIDTH-1 -: CMPY_OUTPUT_WIDTH]; + assign din_ch_cxr_imag[m] = cmpy_p[AXIS_CMPY_P_WIDTH+CMPY_P_WIDTH-1 -: CMPY_OUTPUT_WIDTH]; + end + + cmpy_12x8 u_cmpy_12x8_ch + ( + .aclk (clk ), // input wire aclk + .s_axis_a_tvalid (cmpy_a_valid ), // input wire s_axis_a_tvalid + .s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid (cmpy_b_valid ), // input wire s_axis_b_tvalid + .s_axis_b_tdata (cmpy_b ), // input wire [15 : 0] s_axis_b_tdata + .m_axis_dout_tvalid (cmpy_p_valid ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (cmpy_p ) // output wire [47 : 0] m_axis_dout_tdata + ); + +end +endgenerate + + +//////////////////////////////////////////////////////////////////////////////// +////////////////// Digital Matched Filter for Signal Channels ////////////////// +//////////////////////////////////////////////////////////////////////////////// +reg dmf_ch_start = 'b0; +wire dmf_ch_busy [0 : CHANNEL_NUM-1]; + +wire dmf_ch_din_valid [0 : CHANNEL_NUM-1]; +wire [DATA_I_WIDTH-1 : 0] dmf_ch_din_real [0 : CHANNEL_NUM-1]; +wire [DATA_I_WIDTH-1 : 0] dmf_ch_din_imag [0 : CHANNEL_NUM-1]; + +wire dmf_ch_peak_valid [0 : CHANNEL_NUM-1]; +wire [DATA_O_WIDTH-1 : 0] dmf_ch_peak_value_abs [0 : CHANNEL_NUM-1]; +wire [DATA_O_WIDTH-1 : 0] dmf_ch_peak_value_i [0 : CHANNEL_NUM-1]; +wire [DATA_O_WIDTH-1 : 0] dmf_ch_peak_value_q [0 : CHANNEL_NUM-1]; +wire [$clog2(PRBS_POS)-1 : 0] dmf_ch_peak_index [0 : CHANNEL_NUM-1]; + +wire [DATA_O_WIDTH-1 : 0] dmf_ch_moduli_abs [0 : CHANNEL_NUM-1]; + +// ----------------------------------------------------------------------------- +// dmf start control +// ----------------------------------------------------------------------------- +always @(posedge clk) begin + if (rst) begin + dmf_ch_start <= 'b0; + end + else case (state_next) + STATE_CH_DMF: dmf_ch_start <= (state_curr == STATE_CH_SW) ? ~dmf_ch_start : dmf_ch_start; + default: dmf_ch_start <= dmf_ch_start; + endcase +end + +generate +for (m = 0; m < CHANNEL_NUM; m = m + 1) begin: dmf_ch + + assign dmf_ch_din_valid[m] = din_ch_cxr_valid[m]; + + if (DATA_I_WIDTH > CMPY_OUTPUT_WIDTH) begin + // append zeros + assign dmf_ch_din_real[m] = {din_ch_cxr_real[m],{(DATA_I_WIDTH-CMPY_OUTPUT_WIDTH){1'b0}}}; + assign dmf_ch_din_imag[m] = {din_ch_cxr_imag[m],{(DATA_I_WIDTH-CMPY_OUTPUT_WIDTH){1'b0}}}; + end + else begin + // truncate msb + assign dmf_ch_din_real[m] = din_ch_cxr_real[m][CMPY_OUTPUT_WIDTH-1 -: DATA_I_WIDTH]; + assign dmf_ch_din_imag[m] = din_ch_cxr_imag[m][CMPY_OUTPUT_WIDTH-1 -: DATA_I_WIDTH]; + end + + // dmf instantiation + rx_dmf #( + .PRBS_LEN (PRBS_LEN ), + .INTERP_RATE (INTERP_RATE ), + .PROCESS_INTERP (PROCESS_INTERP ), + .DATA_I_WIDTH (DATA_I_WIDTH ), + .DATA_O_WIDTH (DATA_O_WIDTH ) + ) u_rx_dmf_ch + ( + .clk (clk ), + .rst (rst ), + + .dmf_start (dmf_ch_start ), + .dmf_busy (dmf_ch_busy[m] ), + + .dmf_num (dmf_num_per_ch ), + + .din_valid (dmf_ch_din_valid[m] ), + .din_real (dmf_ch_din_real[m] ), + .din_imag (dmf_ch_din_imag[m] ), + + .peak_valid (dmf_ch_peak_valid[m] ), + .last_peak_valid(dmf_ch_last_peak_valid[m] ), + .peak_value_abs (dmf_ch_peak_value_abs[m] ), + .peak_value_i (dmf_ch_peak_value_i[m] ), + .peak_value_q (dmf_ch_peak_value_q[m] ), + .peak_index (dmf_ch_peak_index[m] ) + ); + + assign dmf_ch_moduli_abs[m] = u_rx_dmf_ch.moduli_abs; + +end +endgenerate + +assign ch_peak_valid = dmf_ch_peak_valid[0]; + +assign ch1_peak_value_abs = dmf_ch_peak_value_abs[0]; +assign ch1_peak_value_i = dmf_ch_peak_value_i[0] ; +assign ch1_peak_value_q = dmf_ch_peak_value_q [0] ; +assign ch1_peak_index = dmf_ch_peak_index[0] ; + +assign ch2_peak_value_abs = dmf_ch_peak_value_abs[1]; +assign ch2_peak_value_i = dmf_ch_peak_value_i[1] ; +assign ch2_peak_value_q = dmf_ch_peak_value_q [1] ; +assign ch2_peak_index = dmf_ch_peak_index[1] ; + +assign ch3_peak_value_abs = dmf_ch_peak_value_abs[2]; +assign ch3_peak_value_i = dmf_ch_peak_value_i[2] ; +assign ch3_peak_value_q = dmf_ch_peak_value_q [2] ; +assign ch3_peak_index = dmf_ch_peak_index[2] ; + +assign ch4_peak_value_abs = dmf_ch_peak_value_abs[3]; +assign ch4_peak_value_i = dmf_ch_peak_value_i[3] ; +assign ch4_peak_value_q = dmf_ch_peak_value_q [3] ; +assign ch4_peak_index = dmf_ch_peak_index[3] ; + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v b/projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v new file mode 100644 index 00000000..dcd1f84f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v @@ -0,0 +1,167 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/05/06 15:37:29 +// Design Name: +// Module Name: rf_auto_switch_freq +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module rf_auto_switch_freq( + input clk , + input rst , + // vio control + input start , // rise-edge active, if start, change freq word to the first + input rf_ctrl_mode , // 1 : auto switch, 0 : manual switch + input switch_next_freq , // rise-edge active + input switch_last_freq , // rise-edge active + input [15:0] cnt_valid_to_switch , // clock number from valid to switch + // input + input [15:0] freq_hop_words_vio , + input hop_words_valid_vio , + input freq_hop_switch_vio , + // output + output reg [15:0] freq_hop_words_auto = 11'd0 , + output reg hop_words_valid_auto = 1'd0 , + output reg freq_hop_switch_auto = 1'd0 +); + +//************************* rise-edge detect *********************************** +reg start_d1 = 1'b0; +reg start_d2 = 1'b0; +reg start_pulse = 1'b0; +reg switch_next_freq_d1 = 1'b0; +reg switch_next_freq_d2 = 1'b0; +reg [9:0] switch_next_freq_pulse = 10'd0; +reg switch_last_freq_d1 = 1'b0; +reg switch_last_freq_d2 = 1'b0; +reg [9:0] switch_last_freq_pulse = 10'd0; +always @ (posedge clk) + if(rst) begin + start_d1 <= 1'b0; + start_d2 <= 1'b0; + start_pulse <= 1'b0; + switch_next_freq_d1 <= 1'b0; + switch_next_freq_d2 <= 1'b0; + switch_next_freq_pulse <= 10'd0; + switch_last_freq_d1 <= 1'b0; + switch_last_freq_d2 <= 1'b0; + switch_last_freq_pulse <= 10'd0; + end else begin + start_d1 <= start; + start_d2 <= start_d1; + start_pulse <= start_d1 & ~start_d2; + switch_next_freq_d1 <= switch_next_freq; + switch_next_freq_d2 <= switch_next_freq_d1; + switch_next_freq_pulse[0] <= switch_next_freq_d1 & ~switch_next_freq_d2; + switch_next_freq_pulse[9:1] <= switch_next_freq_pulse[8:0]; + switch_last_freq_d1 <= switch_last_freq; + switch_last_freq_d2 <= switch_last_freq_d1; + switch_last_freq_pulse[0] <= switch_last_freq_d1 & ~switch_last_freq_d2; + switch_last_freq_pulse[9:1] <= switch_last_freq_pulse[8:0]; + end + +//******************** local freq word control ********************************* +reg [15:0] local_freq_word = 16'd0; +reg local_freq_word_valid = 1'b0; +reg local_freq_word_switch = 1'b0; +reg [7:0] freq_word_cnt = 8'd0; // range 0 -> 80 +wire [15:0] rom_freq_word_dout; +// 2 clock latency +rom_freq_word rom_freq_word_inst( + .clka (clk ), + .addra (freq_word_cnt[6:0] ), + .douta (rom_freq_word_dout ) +); + +always @ (posedge clk) + if(rst | start_pulse) + freq_word_cnt <= 8'd0; + else if(freq_word_cnt == 8'd80 && switch_next_freq_pulse[0]) + freq_word_cnt <= 8'd0; + else if(freq_word_cnt == 8'd0 && switch_last_freq_pulse[0]) + freq_word_cnt <= 8'd80; + else if(switch_next_freq_pulse[0]) + freq_word_cnt <= freq_word_cnt + 1'b1; + else if(switch_last_freq_pulse[0]) + freq_word_cnt <= freq_word_cnt - 1'b1; + else + freq_word_cnt <= freq_word_cnt; + +always @ (posedge clk) + if(rst | start_pulse) + local_freq_word_valid <= 1'b0; + else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4]) + local_freq_word_valid <= 1'b1; + else + local_freq_word_valid <= 1'b0; + +reg [15:0] freq_word_valid_cnt = 16'd0; +always @ (posedge clk) + if(rst | start_pulse) + freq_word_valid_cnt <= 16'd0; + else if(freq_word_valid_cnt == cnt_valid_to_switch) + freq_word_valid_cnt <= 16'd0; + else if(local_freq_word_valid) + freq_word_valid_cnt <= freq_word_valid_cnt + 1'b1; + else if(freq_word_valid_cnt != 16'd0) + freq_word_valid_cnt <= freq_word_valid_cnt + 1'b1; + else + freq_word_valid_cnt <= freq_word_valid_cnt; + +always @ (posedge clk) + if(rst | start_pulse) + local_freq_word_switch <= 1'b0; + else if(freq_word_valid_cnt == cnt_valid_to_switch) + local_freq_word_switch <= ~local_freq_word_switch; + else + local_freq_word_switch <= local_freq_word_switch; + +always @ (posedge clk) + if(rst | start_pulse) + local_freq_word <= 16'd0; + else + local_freq_word <= rom_freq_word_dout; + +//******************** output freq switch signal ******************************* +// freq_hop_words_auto +always @ (posedge clk) + if(rst | start_pulse) + freq_hop_words_auto <= 11'd0; + else if(rf_ctrl_mode) + freq_hop_words_auto <= local_freq_word; + else + freq_hop_words_auto <= freq_hop_words_vio; + +// hop_words_valid_auto +always @ (posedge clk) + if(rst | start_pulse) + hop_words_valid_auto <= 1'b0; + else if(rf_ctrl_mode) + hop_words_valid_auto <= local_freq_word_valid; + else + hop_words_valid_auto <= hop_words_valid_vio; + +// freq_hop_switch_auto +always @ (posedge clk) + if(rst | start_pulse) + freq_hop_switch_auto <= 1'b0; + else if(rf_ctrl_mode) + freq_hop_switch_auto <= local_freq_word_switch; + else + freq_hop_switch_auto <= freq_hop_switch_vio; + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/rx_dmf.v b/projects/duifei/duifei_online_acq_par/rtl/rx_dmf.v new file mode 100644 index 00000000..466f6124 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/rx_dmf.v @@ -0,0 +1,471 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 04/25/2023 05:53:44 PM +// Design Name: +// Module Name: rx_dmf +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module rx_dmf +#( + // length of pseudorandom bit sequence, need to be a power of 2 + parameter PRBS_LEN = 128, + // interpolation of input signal, need to be a power of 2 + parameter INTERP_RATE = 8, + // signal processing interpolation, need to be a power of 2 + parameter PROCESS_INTERP = 2, + // possible position of pn code + parameter PRBS_POS = PRBS_LEN*PROCESS_INTERP, + parameter MAX_DMF_NUM = 64, + parameter DATA_I_WIDTH = 12, + parameter DATA_O_WIDTH = 18 +) +( + input clk , + input rst , + + input dmf_start , + output dmf_busy , + + input din_valid , + input [DATA_I_WIDTH-1 : 0] din_real , + input [DATA_I_WIDTH-1 : 0] din_imag , + + input [$clog2(MAX_DMF_NUM+1)-1 : 0] dmf_num , + + output peak_valid , + output last_peak_valid , + output [DATA_O_WIDTH-1 : 0] peak_value_abs , + output [DATA_O_WIDTH-1 : 0] peak_value_i , + output [DATA_O_WIDTH-1 : 0] peak_value_q , + output [$clog2(PRBS_POS)-1 : 0] peak_index +); + +localparam CMPLX_DIM = 2; +localparam APPROX_ABS_WIDTH = 29; +localparam ABS_WIDTH = 18; + +localparam DMF_I_WIDTH = 12; +localparam DMF_O_WIDTH = DMF_I_WIDTH+$clog2(PRBS_POS); + +localparam AXIS_DMF_I_WIDTH = 8*((DMF_I_WIDTH-1)/8+1); +localparam AXIS_DMF_O_WIDTH = 8*((DMF_O_WIDTH-1)/8+1); + +genvar m; +integer i; + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////// Center State Control ///////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +reg dmf_busy_buf = 'b0; +reg dmf_start_d1 = 'b0; +reg dmf_start_d2 = 'b0; +reg [$clog2(MAX_DMF_NUM)-1 : 0] cnt_dmf_num = 'b0; + +reg moduli_max_valid = 'b0; + +assign dmf_busy = dmf_busy_buf; + +always @(posedge clk) begin + dmf_start_d1 <= dmf_start; + dmf_start_d2 <= dmf_start_d1; +end + +always @(posedge clk) begin + if (rst) begin + cnt_dmf_num <= 'b0; + end + else if (dmf_busy) begin + cnt_dmf_num <= (moduli_max_valid) ? cnt_dmf_num + 1'b1 : cnt_dmf_num; + end + else begin + cnt_dmf_num <= 'b0; + end +end + +always @(posedge clk) begin + if (rst) begin + dmf_busy_buf <= 'b0; + end + else if (cnt_dmf_num == dmf_num+1) begin + // clear when output is valid + dmf_busy_buf <= 'b0; + end + else if (din_valid && (dmf_start_d2 != dmf_start_d1) && (dmf_num != 'b0)) begin + // set when either edge is detected + dmf_busy_buf <= 1'b1; + end + else begin + // otherwise keep + dmf_busy_buf <= dmf_busy_buf; + end +end + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////// Decimation Counter ////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +reg [$clog2(INTERP_RATE/PROCESS_INTERP)-1 : 0] cnt_deci = 'b0; +reg din_deci_valid = 'b0; + +always @(posedge clk) begin + if (rst) begin + cnt_deci <= 'b0; + end + else if (dmf_busy && din_valid) begin + cnt_deci <= cnt_deci + 1'b1; + end + else begin + cnt_deci <= 'b0; + end +end + +always @(posedge clk) begin + if (rst) begin + din_deci_valid <= 'b0; + end + else begin + din_deci_valid <= (cnt_deci == INTERP_RATE/PROCESS_INTERP-1) ? 1'b1 : 'b0; + end +end + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Digital Matched Filter //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// input & output signals +wire [AXIS_DMF_I_WIDTH-1 : 0] dmf_axis_i_real; +wire [AXIS_DMF_I_WIDTH-1 : 0] dmf_axis_i_imag; +wire signed [AXIS_DMF_O_WIDTH-1 : 0] dmf_axis_o_real; +wire signed [AXIS_DMF_O_WIDTH-1 : 0] dmf_axis_o_imag; +wire signed [DMF_O_WIDTH-1 : 0] dmf_o_real; +wire signed [DMF_O_WIDTH-1 : 0] dmf_o_imag; +wire dmf_o_valid; + +// dmf input data formatting +if (AXIS_DMF_I_WIDTH > DATA_I_WIDTH) begin + // sign extension to fit 8-bit axis data format + assign dmf_axis_i_real = {{(AXIS_DMF_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real}; + assign dmf_axis_i_imag = {{(AXIS_DMF_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag}; +end +else begin + // truncate msb + assign dmf_axis_i_real = din_real[DATA_I_WIDTH-1 -: AXIS_DMF_I_WIDTH]; + assign dmf_axis_i_imag = din_imag[DATA_I_WIDTH-1 -: AXIS_DMF_I_WIDTH]; +end + +// dmf output data formatting, truncate valid bits +assign dmf_o_real = dmf_axis_o_real[DMF_O_WIDTH-1 -: DMF_O_WIDTH]; +assign dmf_o_imag = dmf_axis_o_imag[DMF_O_WIDTH-1 -: DMF_O_WIDTH]; + +// fir port definition +wire s_axis_data_tvalid_real; +wire s_axis_data_tready_real; +wire [AXIS_DMF_I_WIDTH-1 : 0] s_axis_data_ttdata_real; +wire m_axis_data_tvalid_real; +wire [AXIS_DMF_O_WIDTH-1 : 0] m_axis_data_ttdata_real; + +wire s_axis_data_tvalid_imag; +wire s_axis_data_tready_imag; +wire [AXIS_DMF_I_WIDTH-1 : 0] s_axis_data_ttdata_imag; +wire m_axis_data_tvalid_imag; +wire [AXIS_DMF_O_WIDTH-1 : 0] m_axis_data_ttdata_imag; + +// fir port connection +assign s_axis_data_tvalid_real = din_deci_valid; +assign s_axis_data_ttdata_real = dmf_axis_i_real; +assign dmf_axis_o_real = m_axis_data_ttdata_real; + +assign s_axis_data_tvalid_imag = din_deci_valid; +assign s_axis_data_ttdata_imag = dmf_axis_i_imag; +assign dmf_axis_o_imag = m_axis_data_ttdata_imag; + +assign dmf_o_valid = m_axis_data_tvalid_real; + +// fir ip core instantiation +fir_prbs7_invert_rep2 u_dmf_real +( + .aclk (clk ), // input wire aclk + .aresetn (dmf_busy ), // input aresetn + .s_axis_data_tvalid (s_axis_data_tvalid_real), // input wire s_axis_data_tvalid + .s_axis_data_tready (s_axis_data_tready_real), // output wire s_axis_data_tready + .s_axis_data_tdata (s_axis_data_ttdata_real), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid (m_axis_data_tvalid_real), // output wire m_axis_data_tvalid + .m_axis_data_tdata (m_axis_data_ttdata_real) // output wire [23 : 0] m_axis_data_tdata +); + +fir_prbs7_invert_rep2 u_dmf_imag +( + .aclk (clk ), // input wire aclk + .aresetn (dmf_busy ), // input aresetn + .s_axis_data_tvalid (s_axis_data_tvalid_imag), // input wire s_axis_data_tvalid + .s_axis_data_tready (s_axis_data_tready_imag), // output wire s_axis_data_tready + .s_axis_data_tdata (s_axis_data_ttdata_imag), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid (m_axis_data_tvalid_imag), // output wire m_axis_data_tvalid + .m_axis_data_tdata (m_axis_data_ttdata_imag) // output wire [23 : 0] m_axis_data_tdata +); + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////////// Chip Counter ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +localparam PEAK_ABS_DELAY = 6; // 5 for multiplier, 1 for adder + +reg [$clog2(PRBS_POS)-1 : 0] cnt_chip = 'b0; +reg [$clog2(PRBS_POS)-1 : 0] cnt_chip_delay [0 : PEAK_ABS_DELAY-1]; + +always @(posedge clk) begin + if (rst) begin + cnt_chip <= 'b0; + end + else if (dmf_busy) begin + cnt_chip <= (dmf_o_valid) ? cnt_chip + 1'b1 : cnt_chip; + end + else begin + cnt_chip <= 'b0; + end +end + +always @(posedge clk) begin + + for (i = 1; i < PEAK_ABS_DELAY; i = i + 1) begin + cnt_chip_delay[i] <= cnt_chip_delay[i-1]; + end + + cnt_chip_delay[0] <= cnt_chip; +end + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////// Accumulation & Peak Search ////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// moduli +wire moduli_valid; +reg moduli_valid_delay [0 : PEAK_ABS_DELAY-1]; +wire [ABS_WIDTH-1 : 0] moduli_real; +wire [ABS_WIDTH-1 : 0] moduli_imag; +reg [ABS_WIDTH-1 : 0] moduli_real_delay [0 : PEAK_ABS_DELAY-1]; +reg [ABS_WIDTH-1 : 0] moduli_imag_delay [0 : PEAK_ABS_DELAY-1]; + +assign moduli_valid = dmf_o_valid; + +if (ABS_WIDTH > DMF_O_WIDTH) begin + // append zeros + assign moduli_real = {dmf_o_real,{(ABS_WIDTH-DMF_O_WIDTH){1'b0}}}; + assign moduli_imag = {dmf_o_imag,{(ABS_WIDTH-DMF_O_WIDTH){1'b0}}}; +end +else begin + // truncate msb + assign moduli_real = dmf_o_real[DMF_O_WIDTH-1 -: ABS_WIDTH]; + assign moduli_imag = dmf_o_imag[DMF_O_WIDTH-1 -: ABS_WIDTH]; +end + +always @(posedge clk) begin + + for (i = 1; i < PEAK_ABS_DELAY; i = i + 1) begin + moduli_valid_delay[i] <= moduli_valid_delay[i-1]; + moduli_real_delay[i] <= moduli_real_delay[i-1]; + moduli_imag_delay[i] <= moduli_imag_delay[i-1]; + end + + moduli_valid_delay[0] <= moduli_valid; + moduli_real_delay[0] <= moduli_real; + moduli_imag_delay[0] <= moduli_imag; +end + +wire [2*ABS_WIDTH-1 : 0] moduli_real_square; +wire [2*ABS_WIDTH-1 : 0] moduli_imag_square; +reg [ABS_WIDTH-1 : 0] moduli_abs_square = 'b0; +wire [DATA_O_WIDTH-1 : 0] moduli_abs; +wire moduli_abs_valid; + +assign moduli_abs_valid = moduli_valid_delay[PEAK_ABS_DELAY-1]; + +if (DATA_O_WIDTH > ABS_WIDTH) begin + // append zeros + assign moduli_abs = {moduli_abs_square,{(DATA_O_WIDTH-ABS_WIDTH){1'b0}}}; +end +else begin + // truncate msb + assign moduli_abs = moduli_abs_square[ABS_WIDTH-1 -: DATA_O_WIDTH]; +end + +always @(posedge clk) begin + if (rst) begin + moduli_abs_square <= 'b0; + end + else begin + moduli_abs_square <= moduli_real_square[(2*ABS_WIDTH-1) -: (ABS_WIDTH-1)] + moduli_imag_square[(2*ABS_WIDTH-1) -: (ABS_WIDTH-1)]; + end +end + +mult_18x18 u_mult_real +( + .CLK(clk ), // input wire CLK + .A (moduli_real ), // input wire [17 : 0] A + .B (moduli_real ), // input wire [17 : 0] B + .P (moduli_real_square ) // output wire [17 : 0] P +); + +mult_18x18 u_mult_imag +( + .CLK(clk ), // input wire CLK + .A (moduli_imag ), // input wire [17 : 0] A + .B (moduli_imag ), // input wire [17 : 0] B + .P (moduli_imag_square ) // output wire [17 : 0] P +); + +// wire accum_current_valid; + +// assign accum_current_valid = dmf_o_valid; + +// wire [APPROX_ABS_WIDTH-2 : 0] accum_moduli_real; +// wire [APPROX_ABS_WIDTH-2 : 0] accum_moduli_imag; +// wire [APPROX_ABS_WIDTH-1 : 0] accum_moduli_abs ; +// wire accum_current_abs_valid; +// wire [DATA_O_WIDTH-1 : 0] accum_current_abs; + +// if (APPROX_ABS_WIDTH-1 > DMF_O_WIDTH) begin +// // append zeros +// assign accum_moduli_real = {dmf_o_real,{(APPROX_ABS_WIDTH-1-DMF_O_WIDTH){1'b0}}}; +// assign accum_moduli_imag = {dmf_o_imag,{(APPROX_ABS_WIDTH-1-DMF_O_WIDTH){1'b0}}}; +// end +// else begin +// // truncate msb +// assign accum_moduli_real = dmf_o_real[DMF_O_WIDTH-1 -: (APPROX_ABS_WIDTH-1)]; +// assign accum_moduli_imag = dmf_o_imag[DMF_O_WIDTH-1 -: (APPROX_ABS_WIDTH-1)]; +// end + +// if (DATA_O_WIDTH > APPROX_ABS_WIDTH) begin +// // append zeros +// assign accum_current_abs = {accum_moduli_abs,{(DATA_O_WIDTH-APPROX_ABS_WIDTH){1'b0}}}; +// end +// else begin +// // truncate msb +// assign accum_current_abs = accum_moduli_abs[APPROX_ABS_WIDTH-1 -: DATA_O_WIDTH]; +// end + +// ApproxAbs u_accum_abs +// ( +// .clk (clk ), +// .Nd (accum_current_valid ), +// .Dini (accum_moduli_real ), +// .Dinq (accum_moduli_imag ), +// .Abs_Rdy (accum_current_abs_valid), +// .Abs_Dout (accum_moduli_abs ) +// ); + +// peak record +reg [DATA_O_WIDTH-1 : 0] moduli_max_abs = 'b0; +reg [DATA_O_WIDTH-1 : 0] moduli_max_real = 'b0; +reg [DATA_O_WIDTH-1 : 0] moduli_max_imag = 'b0; +reg [$clog2(PRBS_POS)-1 : 0] moduli_max_index = 'b0; + +always @(posedge clk) begin + if (rst) begin + moduli_max_valid <= 'b0; + moduli_max_abs <= 'b0; + moduli_max_real <= 'b0; + moduli_max_imag <= 'b0; + moduli_max_index <= 'b0; + end + else if (dmf_busy) begin + if (moduli_abs_valid) begin + if ((cnt_chip_delay[PEAK_ABS_DELAY-1] == 0) || (moduli_abs > moduli_max_abs)) begin + // reset when chip counter reaches zero or record peak + moduli_max_abs <= moduli_abs ; + moduli_max_real <= moduli_real_delay[PEAK_ABS_DELAY-1]; + moduli_max_imag <= moduli_imag_delay[PEAK_ABS_DELAY-1]; + moduli_max_index <= cnt_chip_delay[PEAK_ABS_DELAY-1] ; + end + else begin + moduli_max_abs <= moduli_max_abs; + moduli_max_real <= moduli_max_real; + moduli_max_imag <= moduli_max_imag; + moduli_max_index <= moduli_max_index; + end + + if (cnt_chip_delay[PEAK_ABS_DELAY-1] == PRBS_POS-1) begin + // peak record valid when chip counter reaches maximum value + moduli_max_valid <= 1'b1; + end + else begin + moduli_max_valid <= 'b0; + end + end + else begin + moduli_max_valid <= 'b0; + moduli_max_abs <= moduli_max_abs; + moduli_max_real <= moduli_max_real; + moduli_max_imag <= moduli_max_imag; + moduli_max_index <= moduli_max_index; + end + end + else begin + moduli_max_valid <= 'b0; + moduli_max_abs <= 'b0; + moduli_max_real <= 'b0; + moduli_max_imag <= 'b0; + moduli_max_index <= 'b0; + end +end + +// register output +reg peak_valid_buf = 1'b0; +reg last_peak_valid_buf = 1'b0; +reg [DATA_O_WIDTH-1 : 0] peak_value_abs_buf = 'b0; +reg [DATA_O_WIDTH-1 : 0] peak_value_i_buf = 'b0; +reg [DATA_O_WIDTH-1 : 0] peak_value_q_buf = 'b0; +reg [$clog2(PRBS_POS)-1 : 0] peak_index_buf = 'b0; + +assign peak_valid = peak_valid_buf ; +assign last_peak_valid = last_peak_valid_buf; +assign peak_value_abs = peak_value_abs_buf ; +assign peak_value_i = peak_value_i_buf ; +assign peak_value_q = peak_value_q_buf ; +assign peak_index = peak_index_buf ; + +always @(posedge clk) begin + if (rst) begin + peak_valid_buf <= 'b0; + last_peak_valid_buf <= 'b0; + peak_value_abs_buf <= 'b0; + peak_value_i_buf <= 'b0; + peak_value_q_buf <= 'b0; + peak_index_buf <= 'b0; + end + else if (moduli_max_valid && (cnt_dmf_num != 'b0)) begin + peak_valid_buf <= 1'b1; + peak_value_abs_buf <= moduli_max_abs ; + peak_value_i_buf <= moduli_max_real ; + peak_value_q_buf <= moduli_max_imag ; + peak_index_buf <= moduli_max_index; + + last_peak_valid_buf<= (cnt_dmf_num == dmf_num) ? 1'b1 : 'b0; + end + else begin + peak_valid_buf <= 1'b0; + last_peak_valid_buf <= 1'b0; + peak_value_abs_buf <= peak_value_abs_buf; + peak_value_i_buf <= peak_value_i_buf ; + peak_value_q_buf <= peak_value_q_buf ; + peak_index_buf <= peak_index_buf ; + end +end + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/rx_pre_process/ad9361_phase_cal_coarse.v b/projects/duifei/duifei_online_acq_par/rtl/rx_pre_process/ad9361_phase_cal_coarse.v new file mode 100644 index 00000000..fcfba608 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/rx_pre_process/ad9361_phase_cal_coarse.v @@ -0,0 +1,443 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/09/14 16:45:10 +// Last Modified Data: 2023/02/12 17:10 +// Design Name: +// Module Name: ad9361_phase_cal_coarse +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// 2022/09/14 16:45:10 - File Created +// 2023/02/12 17:10 - 修改：校准未完成时，将输入信号寄存输出。 +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_phase_cal_coarse +#( + parameter COUNTER_MOD = 48, + parameter PEAK_POS = 12, + parameter ADC_DATA_WIDTH = 12 +) +( + // clock & reset + input clk , + input rst , + // control interface + input ad9361_1_cal_start , + output ad9361_1_cal_done , + input ad9361_2_cal_start , + output ad9361_2_cal_done , + output ad9361_cal_result , + output ad9361_cal_valid , + input ad9361_recal , + // input data interface + input [ADC_DATA_WIDTH-1:0] rx_ch1_i , + input [ADC_DATA_WIDTH-1:0] rx_ch1_q , + input [ADC_DATA_WIDTH-1:0] rx_ch2_i , + input [ADC_DATA_WIDTH-1:0] rx_ch2_q , + input [ADC_DATA_WIDTH-1:0] rx_ch3_i , + input [ADC_DATA_WIDTH-1:0] rx_ch3_q , + input [ADC_DATA_WIDTH-1:0] rx_ch4_i , + input [ADC_DATA_WIDTH-1:0] rx_ch4_q , + // output data interface + output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q +); + +localparam STATE_IDLE = 2'd0; +localparam STATE_CAL_1 = 2'd1; +localparam STATE_CAL_2 = 2'd2; +localparam STATE_DONE = 2'd3; + +// buffer input control signals +reg ad9361_1_cal_start_d1 = 'b0; +reg ad9361_1_cal_start_d2 = 'b0; +reg ad9361_2_cal_start_d1 = 'b0; +reg ad9361_2_cal_start_d2 = 'b0; +reg ad9361_recal_d1 = 'b0; +reg ad9361_recal_d2 = 'b0; + +always @(posedge clk) begin + ad9361_1_cal_start_d1 <= ad9361_1_cal_start; + ad9361_1_cal_start_d2 <= ad9361_1_cal_start_d1; + + ad9361_2_cal_start_d1 <= ad9361_2_cal_start; + ad9361_2_cal_start_d2 <= ad9361_2_cal_start_d1; + + ad9361_recal_d1 <= ad9361_recal; + ad9361_recal_d2 <= ad9361_recal_d1; +end + +// center state machine +reg [ 1:0] curr_state = STATE_IDLE; + +always @(posedge clk) begin + if (rst) begin + curr_state <= STATE_IDLE; + end + else begin + case (curr_state) + STATE_IDLE: begin + // move to next state when [ad9361_1_cal_start] asserts + curr_state <= ad9361_1_cal_start_d2 ? STATE_CAL_1 : STATE_IDLE; + end + STATE_CAL_1: begin + // move to next state when 1st cal finishes [ad9361_2_cal_start] asserts + curr_state <= (ad9361_1_cal_done && ad9361_2_cal_start_d2) ? STATE_CAL_2 : STATE_CAL_1; + end + STATE_CAL_2: begin + // move to next state when 2nd cal finishes + curr_state <= ad9361_2_cal_done ? STATE_DONE : STATE_CAL_2; + end + STATE_DONE: begin + // move to ILDA state when it needs to recal + curr_state <= (ad9361_recal_d2) ? STATE_IDLE : STATE_DONE; + end + default: begin + curr_state <= STATE_IDLE; + end + endcase + end +end + +// +reg rx_ch2_i_msb_d1 = 'b0; +reg cnt_start = 'b0; +reg cnt_start_flag = 'b0; +reg [$clog2(COUNTER_MOD)-1:0] cnt = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_ch2_i_rec = 'b0; +reg rx_ch2_i_rec_flag = 'b0; + +assign ad9361_1_cal_done = rx_ch2_i_rec_flag; + +always @(posedge clk) begin + if (rst) begin + rx_ch2_i_msb_d1 <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + rx_ch2_i_msb_d1 <= 'b0; + end + else if (curr_state == STATE_CAL_1) begin + rx_ch2_i_msb_d1 <= rx_ch2_i[ADC_DATA_WIDTH-1]; + end + else begin + rx_ch2_i_msb_d1 <= rx_ch2_i_msb_d1; + end +end + +always @(posedge clk) begin + if (rst) begin + cnt_start <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + cnt_start <= 'b0; + end + else if (curr_state == STATE_CAL_1 && ~cnt_start) begin + // assert when the 1st falling edge of msb of rx_ch2_i is detected + cnt_start <= (rx_ch2_i_msb_d1 & ~rx_ch2_i[ADC_DATA_WIDTH-1]) ? 1'b1 : 1'b0; + end + else begin + cnt_start <= cnt_start; + end +end + +always @(posedge clk) begin + if (rst) begin + cnt <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + cnt <= 'b0; + end + else if (cnt_start) begin + cnt <= (cnt == COUNTER_MOD - 1) ? 'b0 : cnt + 1'b1; + end + else begin + cnt <= cnt; + end +end + +always @(posedge clk) begin + if (rst) begin + rx_ch2_i_rec <= 'b0; + rx_ch2_i_rec_flag <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + rx_ch2_i_rec <= 'b0; + rx_ch2_i_rec_flag <= 'b0; + end + else if (curr_state == STATE_CAL_1 && cnt == PEAK_POS && ~rx_ch2_i_rec_flag) begin + rx_ch2_i_rec <= rx_ch2_i; + rx_ch2_i_rec_flag <= 1'b1; + end + else begin + rx_ch2_i_rec <= rx_ch2_i_rec; + rx_ch2_i_rec_flag <= rx_ch2_i_rec_flag; + end +end + +// +reg [ADC_DATA_WIDTH-1:0] rx_ch4_i_rec = 'b0; +reg rx_ch4_i_rec_flag = 'b0; + +assign ad9361_2_cal_done = rx_ch4_i_rec_flag; + +always @(posedge clk) begin + if (rst) begin + rx_ch4_i_rec <= 'b0; + rx_ch4_i_rec_flag <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + rx_ch4_i_rec <= 'b0; + rx_ch4_i_rec_flag <= 'b0; + end + else if (curr_state == STATE_CAL_2 && cnt == COUNTER_MOD/4 && ~rx_ch4_i_rec_flag) begin + rx_ch4_i_rec <= rx_ch4_i; + rx_ch4_i_rec_flag <= 1'b1; + end + else begin + rx_ch4_i_rec <= rx_ch4_i_rec; + rx_ch4_i_rec_flag <= rx_ch4_i_rec_flag; + end +end + + +reg ad9361_cal_valid_buf = 'b0; +reg ad9361_cal_result_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q_buf = 'b0; + +assign ad9361_cal_valid = ad9361_cal_valid_buf; +assign ad9361_cal_result = ad9361_cal_result_buf; +assign rx_cal_ch1_i = rx_cal_ch1_i_buf; +assign rx_cal_ch2_i = rx_cal_ch2_i_buf; +assign rx_cal_ch3_i = rx_cal_ch3_i_buf; +assign rx_cal_ch4_i = rx_cal_ch4_i_buf; +assign rx_cal_ch1_q = rx_cal_ch1_q_buf; +assign rx_cal_ch2_q = rx_cal_ch2_q_buf; +assign rx_cal_ch3_q = rx_cal_ch3_q_buf; +assign rx_cal_ch4_q = rx_cal_ch4_q_buf; + +always @(posedge clk) begin + if (rst) begin + ad9361_cal_valid_buf <= 'b0; + ad9361_cal_result_buf <= 'b0; + rx_cal_ch1_i_buf <= 'b0; + rx_cal_ch2_i_buf <= 'b0; + rx_cal_ch3_i_buf <= 'b0; + rx_cal_ch4_i_buf <= 'b0; + rx_cal_ch1_q_buf <= 'b0; + rx_cal_ch2_q_buf <= 'b0; + rx_cal_ch3_q_buf <= 'b0; + rx_cal_ch4_q_buf <= 'b0; + end + else if (curr_state == STATE_DONE) begin + ad9361_cal_valid_buf <= 1'b1; + + if (rx_ch2_i_rec[ADC_DATA_WIDTH-1] == rx_ch4_i_rec[ADC_DATA_WIDTH-1]) begin + ad9361_cal_result_buf <= 'b0; + rx_cal_ch1_i_buf <= rx_ch1_i; + rx_cal_ch2_i_buf <= -rx_ch2_i; + rx_cal_ch3_i_buf <= rx_ch3_i; + rx_cal_ch4_i_buf <= -rx_ch4_i; + rx_cal_ch1_q_buf <= rx_ch1_q; + rx_cal_ch2_q_buf <= -rx_ch2_q; + rx_cal_ch3_q_buf <= rx_ch3_q; + rx_cal_ch4_q_buf <= -rx_ch4_q; + end + else begin + ad9361_cal_result_buf <= 'b1; + rx_cal_ch1_i_buf <= rx_ch1_i; + rx_cal_ch2_i_buf <= -rx_ch2_i; + rx_cal_ch3_i_buf <= -rx_ch3_i; + rx_cal_ch4_i_buf <= rx_ch4_i; + rx_cal_ch1_q_buf <= rx_ch1_q; + rx_cal_ch2_q_buf <= -rx_ch2_q; + rx_cal_ch3_q_buf <= -rx_ch3_q; + rx_cal_ch4_q_buf <= rx_ch4_q; + end + end + else begin + ad9361_cal_valid_buf <= 1'b0; + ad9361_cal_result_buf <= ad9361_cal_result_buf; + rx_cal_ch1_i_buf <= rx_ch1_i; + rx_cal_ch2_i_buf <= rx_ch2_i; + rx_cal_ch3_i_buf <= rx_ch3_i; + rx_cal_ch4_i_buf <= rx_ch4_i; + rx_cal_ch1_q_buf <= rx_ch1_q; + rx_cal_ch2_q_buf <= rx_ch2_q; + rx_cal_ch3_q_buf <= rx_ch3_q; + rx_cal_ch4_q_buf <= rx_ch4_q; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/09/15 11:12:45 +// Last Modified Data: 2022/11/02 +// Design Name: +// Module Name: tb_ad9361_cal_coarse +// Project Name: +// Target Devices: +// Tool Versions: +// Description: testbench for [ad9361_phase_cal_coarse] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// module tb_ad9361_cal_coarse; + +// reg clk = 'b0; +// reg rst = 1'b1; + +// reg ad9361_1_cal_start = 'b0; +// wire ad9361_1_cal_done ; +// reg ad9361_2_cal_start = 'b0; +// wire ad9361_2_cal_done ; +// wire ad9361_cal_result ; +// wire ad9361_cal_valid; +// reg ad9361_recal = 'b0; + +// // phase difference of 180 degree +// reg [11:0] rx_ch1_i = 12'd2047; +// reg [11:0] rx_ch1_q = 12'd2047; +// reg [11:0] rx_ch2_i = -12'd2047; +// reg [11:0] rx_ch2_q = -12'd2047; +// reg [11:0] rx_ch3_q = -12'd2047; +// reg [11:0] rx_ch3_i = -12'd2047; +// reg [11:0] rx_ch4_i = 12'd2047; +// reg [11:0] rx_ch4_q = 12'd2047; + +// wire [11:0] rx_cal_ch1_i; +// wire [11:0] rx_cal_ch2_i; +// wire [11:0] rx_cal_ch3_i; +// wire [11:0] rx_cal_ch4_i; +// wire [11:0] rx_cal_ch1_q; +// wire [11:0] rx_cal_ch2_q; +// wire [11:0] rx_cal_ch3_q; +// wire [11:0] rx_cal_ch4_q; + +// ad9361_phase_cal #( +// .COUNTER_MOD (48), +// .PEAK_POS (12) +// ) u_ad9361_phase_cal +// ( +// // clock & reset +// .clk (clk ), // input clk +// .rst (rst ), // input rst +// // control interface +// .ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start +// .ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done +// .ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start +// .ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done +// .ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result +// .ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid +// .ad9361_recal (ad9361_recal ), // input ad9361_recal +// // input data interface +// .rx_ch1_i (rx_ch1_i ), // input [11:0] rx_ch1_i +// .rx_ch2_i (rx_ch2_i ), // input [11:0] rx_ch2_i +// .rx_ch3_i (rx_ch3_i ), // input [11:0] rx_ch3_i +// .rx_ch4_i (rx_ch4_i ), // input [11:0] rx_ch4_i +// .rx_ch1_q (rx_ch1_q ), // input [11:0] rx_ch1_q +// .rx_ch2_q (rx_ch2_q ), // input [11:0] rx_ch2_q +// .rx_ch3_q (rx_ch3_q ), // input [11:0] rx_ch3_q +// .rx_ch4_q (rx_ch4_q ), // input [11:0] rx_ch4_q +// // output data interface +// .rx_cal_ch1_i (rx_cal_ch1_i ), // output [11:0] rx_cal_ch1_i +// .rx_cal_ch2_i (rx_cal_ch2_i ), // output [11:0] rx_cal_ch2_i +// .rx_cal_ch3_i (rx_cal_ch3_i ), // output [11:0] rx_cal_ch3_i +// .rx_cal_ch4_i (rx_cal_ch4_i ), // output [11:0] rx_cal_ch4_i +// .rx_cal_ch1_q (rx_cal_ch1_q ), // output [11:0] rx_cal_ch1_q +// .rx_cal_ch2_q (rx_cal_ch2_q ), // output [11:0] rx_cal_ch2_q +// .rx_cal_ch3_q (rx_cal_ch3_q ), // output [11:0] rx_cal_ch3_q +// .rx_cal_ch4_q (rx_cal_ch4_q ) // output [11:0] rx_cal_ch4_q +// ); + +// initial begin +// #102 +// rst = 1'b0; +// #100 +// ad9361_1_cal_start = 1'b1; +// end + +// initial begin +// #10000 +// ad9361_recal = 1'b1; +// #20 +// ad9361_recal = 1'b0; +// end + +// always begin +// #2 clk = ~clk; +// end + +// always begin +// #72 +// rx_ch1_i = ~rx_ch1_i; +// rx_ch2_i = ~rx_ch2_i; +// rx_ch3_i = ~rx_ch3_i; +// rx_ch4_i = ~rx_ch4_i; +// #24 +// rx_ch1_q = ~rx_ch1_q; +// rx_ch2_q = ~rx_ch2_q; +// rx_ch3_q = ~rx_ch3_q; +// rx_ch4_q = ~rx_ch4_q; +// end + +// always @(posedge clk) begin +// if (ad9361_1_cal_done) begin +// ad9361_2_cal_start <= 1'b1; +// end +// else begin +// ad9361_2_cal_start <= 1'b0; +// end +// end + +// endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/system_top.v b/projects/duifei/duifei_online_acq_par/rtl/system_top.v new file mode 100644 index 00000000..063ed425 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/system_top.v @@ -0,0 +1,981 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2021/12/14 15:54:11 +// Design Name: +// Module Name: system_top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module system_top +( + /*************************************************************************** + * Contents + * 01. Clocks + * 02. HMC7044 Interface + * 03. AD9361-1 Interface + * 04. AD9361-2 Interface + * 05. Phased-Array Control + * 06. RF Synthesizer Control + * 07. Debug IO + * 08. DDR and Fixed-io (Do NOT Modify) + **************************************************************************/ + + // ************************************************************************* + // ******************************** Clocks ********************************* + // ************************************************************************* + // fpga logic clock + input clk_250m_p , // generated by hmc7044, 250mhz + input clk_250m_n , + // ad9361 buffered clock + input ad9361_1_buffer_clk , // derived from ad9361 input clock + input ad9361_2_buffer_clk , // derived from ad9361 input clock + // ************************************************************************* + // *************************** HMC7044 Interface *************************** + // ************************************************************************* + // spi interface + output hmc7044_spi_clk , + output hmc7044_spi_csn , + inout hmc7044_spi_sdio , + // control signals + output hmc7044_reset , // hmc7044 active-high reset signal, set to 0 in normal operation + output hmc7044_sync , // hmc7044 multichip synchronization signal, set to 0 if not used + // gpio + inout [ 3:0] hmc7044_gpio , + // ************************************************************************* + // ************************** AD9361-1 Interface *************************** + // ************************************************************************* + // rx data (rx channels are tied to ground physically) + input ad9361_1_rx_data_clk, // ad9361 rx data clock, 96mhz + input ad9361_1_rx_frame , + input [11:0] ad9361_1_rx_data , + // tx data + output ad9361_1_tx_fb_clk , + output ad9361_1_tx_frame , + output [11:0] ad9361_1_tx_data , + // spi interface + output ad9361_1_spi_clk , + output ad9361_1_spi_csn , + output ad9361_1_spi_mosi , + input ad9361_1_spi_miso , + // control signals + output ad9361_1_reset_b , // ad9361 active-low reset control + output ad9361_1_en_agc , // ad9361 manual agc control + output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed) + output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed) + input [ 3:0] ad9361_1_ctrl_in , + output [ 7:0] ad9361_1_ctrl_out , + output ad9361_sync , + // ************************************************************************* + // ************************** AD9361-2 Interface *************************** + // ************************************************************************* + // rx data (rx channels are tied to ground physically) + input ad9361_2_rx_data_clk, + input ad9361_2_rx_frame , + input [11:0] ad9361_2_rx_data , + // tx data + output ad9361_2_tx_fb_clk , + output ad9361_2_tx_frame , + output [11:0] ad9361_2_tx_data , + // spi interface + output ad9361_2_spi_clk , + output ad9361_2_spi_csn , + output ad9361_2_spi_mosi , + input ad9361_2_spi_miso , + // control signals + output ad9361_2_reset_b , // ad9361 active-low reset control + output ad9361_2_en_agc , // ad9361 manual agc control + output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed) + output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed) + input [ 3:0] ad9361_2_ctrl_in , + output [ 7:0] ad9361_2_ctrl_out , + // ************************************************************************* + // ************************* Phased-Array Control ************************** + // ************************************************************************* + output ant_clk , + output ant_en , + output ant_data , + output ant_tr , + output ant_dary , + input ant_dout , + // ************************************************************************* + // ************************ RF Synthesizer Control ************************* + // ************************************************************************* + output rf_standby , + output rf_sw_pll , + output rf_t , + output rf_r , + output rf_sw_bpf , + output rf_sclk1 , + output rf_sdio1 , + output rf_cs1 , + input rf_ld1 , + output rf_sclk2 , + output rf_sdio2 , + output rf_cs2 , + input rf_ld2 , + output rf_sclk3 , + output rf_sdio3 , + output rf_cs3 , + input rf_ld3 , + output rf_tmgc_16 , + output rf_tmgc_8 , + output rf_tmgc_4 , + output rf_tmgc_2 , + output rf_tmgc_1 , + output rf_rmgc_16 , + output rf_rmgc_8 , + output rf_rmgc_4 , + output rf_rmgc_2 , + output rf_rmgc_1 , + output rf_enable , + output rf_sc , + output rf_sd , + output rf_endsyn , + input rf_sdout , + inout rf_dq_wd , + output rf_sw_rx , + // ************************************************************************* + // ******************************* Debug IO ******************************** + // ************************************************************************* + // 3.3v ports + output uart1_txd , + input uart1_rxd , + output uart2_txd , + input uart2_rxd , + output uart3_txd , + input uart3_rxd , + // 1.8v ports + inout debug_io_1 , + inout debug_io_2 , + // 3.3v ports + inout debug_io_3 , + inout debug_io_4 , + inout debug_io_5 , + inout debug_io_6 , + inout debug_io_7 , + // ************************************************************************* + // ******************* DDR and Fixed-io (Do NOT Modify) ******************** + // ************************************************************************* + // ddr + inout [14:0] ddr_addr , + inout [ 2:0] ddr_ba , + inout ddr_cas_n , + inout ddr_ck_n , + inout ddr_ck_p , + inout ddr_cke , + inout ddr_cs_n , + inout [ 3:0] ddr_dm , + inout [31:0] ddr_dq , + inout [ 3:0] ddr_dqs_n , + inout [ 3:0] ddr_dqs_p , + inout ddr_odt , + inout ddr_ras_n , + inout ddr_reset_n , + inout ddr_we_n , + // fixed-io + inout fixed_io_ddr_vrn , + inout fixed_io_ddr_vrp , + inout [53:0] fixed_io_mio , + inout fixed_io_ps_clk , + inout fixed_io_ps_porb , + inout fixed_io_ps_srstb +); + + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////// System Clock Generation //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// global reset +wire sys_rst ; // global reset signal, active high +wire ant_rst ; // phased-array & rf control reset signal, active high + +// pl signal processing clock +wire sys_clk ; // 48MHz 41.6667MHz +wire sys_clk_2x ; // 96MHz 83.3333MHz +wire sys_clk_3x ; // 144MHz 125MHz +wire sys_clk_4x ; // 192MHz 166.6667MHz +wire sys_clk_ld ; // system main clock locked indicator + +// ad9361-1 clocks +wire ad9361_1_clk ; // 48MHz 41.6667MHz +wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz +wire ad9361_1_clk_3x ; // 144MHz 125MHz +wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz +wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator + +// ad9361-2 clocks +wire ad9361_2_clk ; // 48MHz 41.6667MHz +wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz +wire ad9361_2_clk_3x ; // 144MHz 125MHz +wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz +wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator + +// phased-array & rf control clocks +wire clk_96m ; +wire clk_48m ; +wire clk_32m ; +wire clk_19p2m ; + +clk_dist u_clk_dist +( + // input clocks + .clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz + .clk_250m_n (clk_250m_n ), + .ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz + .ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz + + // output clocks & reset + // global reset + .sys_rst (sys_rst ), // global reset signal, active high + .ant_rst (ant_rst ), // phased-array & rf control reset signal, active high + + // pl signal processing clock + .sys_clk (sys_clk ), // 48MHz 41.6667MHz + .sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz + .sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz + .sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz + .sys_clk_ld (sys_clk_ld ), // system main clock locked indicator + + // ad9361-1 clocks + .ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz + .ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz + .ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz + .ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz + .ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator + + // ad9361-2 clocks + .ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz + .ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz + .ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz + .ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz + .ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator + + // phased-array & rf control clocks + .clk_96m (clk_96m ), + .clk_48m (clk_48m ), + .clk_32m (clk_32m ), + .clk_19p2m (clk_19p2m ) +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Block Design Interface //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// gpio +wire [47:0] gpio_i; +wire [47:0] gpio_o; +wire [47:0] gpio_t; +wire ad9361_rx_fifo_rst; +wire ad9361_1_cal_start; +wire ad9361_1_cal_done; +wire ad9361_2_cal_start; +wire ad9361_2_cal_done; +wire ad9361_cal_result; +wire ad9361_recal; + +assign gpio_i[47:47] = gpio_o[47:47]; + +// hmc7044 +assign hmc7044_reset = gpio_o[ 0]; // hmc7044 reset +assign hmc7044_sync = gpio_o[ 1]; // hmc7044 multichip synchronization +assign hmc7044_gpio[0] = gpio_t[ 2] ? gpio_i[ 2] : gpio_o[ 2]; +assign hmc7044_gpio[1] = gpio_t[ 3] ? gpio_i[ 3] : gpio_o[ 3]; +assign hmc7044_gpio[2] = gpio_t[ 4] ? gpio_i[ 4] : gpio_o[ 4]; +assign hmc7044_gpio[3] = gpio_t[ 5] ? gpio_i[ 5] : gpio_o[ 5]; +// ad9361-1 +assign ad9361_1_txnrx = gpio_o[ 6]; // ad9361 enable state machine control +assign ad9361_1_enable = gpio_o[ 7]; // ad9361 enable state machine control +assign ad9361_1_en_agc = gpio_o[ 8]; // ad9361 agc control +assign ad9361_1_reset_b = gpio_o[ 9]; // ad9361 reset +assign ad9361_1_ctrl_out = gpio_o[17:10]; +assign gpio_i[21:18] = ad9361_1_ctrl_in; +// ad9361-2 +assign ad9361_2_txnrx = gpio_o[22]; // ad9361 enable state machine control +assign ad9361_2_enable = gpio_o[23]; // ad9361 enable state machine control +assign ad9361_2_en_agc = gpio_o[24]; // ad9361 agc control +assign ad9361_2_reset_b = gpio_o[25]; // ad9361 reset +assign ad9361_2_ctrl_out = gpio_o[33:26]; +assign gpio_i[37:34] = ad9361_2_ctrl_in; +// ad9361 multichip sync +assign ad9361_sync = gpio_o[38]; +assign ad9361_rx_fifo_rst = gpio_o[39]; +assign ad9361_1_cal_start = gpio_o[40]; +assign ad9361_2_cal_start = gpio_o[41]; +assign ad9361_recal = gpio_o[42]; +assign ad9361_tx_switch = gpio_o[43]; +assign gpio_i[44] = ad9361_1_cal_done; +assign gpio_i[45] = ad9361_2_cal_done; +assign gpio_i[46] = ad9361_cal_result; + +// spi interface +wire spi_sclk ; +wire [ 2:0] spi_cs ; +reg spi_sdi ; +wire spi_sdo ; +wire spi_sdo_t ; +wire spi_three_wire; +wire spi_active ; + +// hmc7044 - three-wire spi +assign hmc7044_spi_clk = spi_sclk; +assign hmc7044_spi_csn = spi_cs[0]; +assign hmc7044_spi_sdio = spi_sdo_t ? 1'bz : spi_sdo; +// ad9361-1 - three-wire spi or four-wire spi +assign ad9361_1_spi_clk = spi_sclk; +assign ad9361_1_spi_csn = spi_cs[1]; +assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; +// ad9361-2 - three-wire spi or four-wire spi +assign ad9361_2_spi_clk = spi_sclk; +assign ad9361_2_spi_csn = spi_cs[2]; +assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; +// select sdi signal +always @(*) begin + if (~hmc7044_spi_csn) + spi_sdi = hmc7044_spi_sdio; + else if (~ad9361_1_spi_csn) + spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso; + else if (~ad9361_2_spi_csn) + spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso; + else + spi_sdi = 1'bz; +end + +// ps clock +wire ps_clk_50M; +wire ps_clk_200M; + +system_bd_wrapper u_system_bd_wrapper +( + // ddr + .ddr_addr (ddr_addr ), // inout [14:0]ddr_addr + .ddr_ba (ddr_ba ), // inout [2:0]ddr_ba + .ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n + .ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n + .ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p + .ddr_cke (ddr_cke ), // inout ddr_cke + .ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n + .ddr_dm (ddr_dm ), // inout [3:0]ddr_dm + .ddr_dq (ddr_dq ), // inout [31:0]ddr_dq + .ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n + .ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p + .ddr_odt (ddr_odt ), // inout ddr_odt + .ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n + .ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n + .ddr_we_n (ddr_we_n ), // inout ddr_we_n + + // fixed-io + .fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn + .fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp + .fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio + .fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk + .fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb + .fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb + + // gpio, for control signals + .gpio_i (gpio_i ), // input [47:0]gpio_i + .gpio_o (gpio_o ), // output [47:0]gpio_o + .gpio_t (gpio_t ), // output [47:0]gpio_t + + // spi interface + .spi_sclk (spi_sclk ), // output spi_sclk + .spi_cs (spi_cs ), // output [2:0]spi_cs + .spi_sdi (spi_sdi ), // input [0:0]spi_sdi + .spi_sdo (spi_sdo ), // output spi_sdo + .spi_sdo_t (spi_sdo_t ), // output spi_sdo_t + .spi_three_wire (spi_three_wire ), // output spi_three_wire + .spi_active (spi_active ), // output spi_active + + // ps clock + .ps_clk_50M (ps_clk_50M ), // output ps_clk_50M + .ps_clk_200M (ps_clk_200M ) // output ps_clk_200M +); + + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// RF control ////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// rf auto switch frequency function +wire rf_auto_start_vio ; +wire rf_ctrl_mode_vio ; +wire switch_next_freq_vio; +wire switch_last_freq_vio; +wire [15:0] cnt_valid_to_switch_vio; + +(*dont_touch = "true"*) wire vio_switch; +(*dont_touch = "true"*) wire vio_switch_auto; +(*dont_touch = "true"*) wire [15:0] vio_frequency; +(*dont_touch = "true"*) wire [15:0] vio_frequency_auto; +wire hop_words_valid_auto; + +rf_auto_switch_freq u_rf_auto_switch_freq( + .clk (clk_48m ), + .rst (sys_rst ), + // vio control + .start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first + .rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch + .switch_next_freq (switch_next_freq_vio ), // rise-edge active + .switch_last_freq (switch_last_freq_vio ), // rise-edge active + .cnt_valid_to_switch (cnt_valid_to_switch_vio ), + // input + .freq_hop_words_vio (vio_frequency[15:0] ), + .hop_words_valid_vio (1'b0 ), + .freq_hop_switch_vio (vio_switch ), + // output + .freq_hop_words_auto (vio_frequency_auto[15:0] ), + .hop_words_valid_auto (hop_words_valid_auto ), + .freq_hop_switch_auto (vio_switch_auto ) +); + +ant_rf_ctrl u_ant_rf_ctrl +( + .clk_48m (clk_48m ), // input clk_48m + .clk_96m (clk_96m ), // input clk_96m + .clk_32m (clk_32m ), // input clk_32m + .clk_19p2m (clk_19p2m ), // input clk_19p2m + .sys_rst (ant_rst ), // input sys_rst + + .ant_clk (ant_clk ), // output ant_clk + .ant_en (ant_en ), // output ant_en + .ant_data (ant_data ), // output ant_data + .ant_tr (ant_tr ), // output ant_tr + .ant_dary (ant_dary ), // output ant_dary + .ant_dout (ant_dout ), // input ant_dout + + .rf_standby (rf_standby ), // output rf_standby + .rf_sw_pll (rf_sw_pll ), // output rf_sw_pll + .rf_t (rf_t ), // output rf_t + .rf_r (rf_r ), // output rf_r + .rf_sw_bpf (rf_sw_bpf ), // output rf_sw_bpf + .rf_sclk1 (rf_sclk1 ), // output rf_sclk1 + .rf_sdio1 (rf_sdio1 ), // output rf_sdio1 + .rf_cs1 (rf_cs1 ), // output rf_cs1 + .rf_ld1 (rf_ld1 ), // input rf_ld1 + .rf_sclk2 (rf_sclk2 ), // output rf_sclk2 + .rf_sdio2 (rf_sdio2 ), // output rf_sdio2 + .rf_cs2 (rf_cs2 ), // output rf_cs2 + .rf_ld2 (rf_ld2 ), // input rf_ld2 + .rf_sclk3 (rf_sclk3 ), // output rf_sclk3 + .rf_sdio3 (rf_sdio3 ), // output rf_sdio3 + .rf_cs3 (rf_cs3 ), // output rf_cs3 + .rf_ld3 (rf_ld3 ), // input rf_ld3 + .rf_tmgc_16 (rf_tmgc_16 ), // output rf_tmgc_16 + .rf_tmgc_8 (rf_tmgc_8 ), // output rf_tmgc_8 + .rf_tmgc_4 (rf_tmgc_4 ), // output rf_tmgc_4 + .rf_tmgc_2 (rf_tmgc_2 ), // output rf_tmgc_2 + .rf_tmgc_1 (rf_tmgc_1 ), // output rf_tmgc_1 + .rf_rmgc_16 (rf_rmgc_16 ), // output rf_rmgc_16 + .rf_rmgc_8 (rf_rmgc_8 ), // output rf_rmgc_8 + .rf_rmgc_4 (rf_rmgc_4 ), // output rf_rmgc_4 + .rf_rmgc_2 (rf_rmgc_2 ), // output rf_rmgc_2 + .rf_rmgc_1 (rf_rmgc_1 ), // output rf_rmgc_1 + .rf_enable (rf_enable ), // output rf_enable + .rf_sc (rf_sc ), // output rf_sc + .rf_sd (rf_sd ), // output rf_sd + .rf_endsyn (rf_endsyn ), // output rf_endsyn + .rf_sdout (rf_sdout ), // input rf_sdout + .rf_dq_wd (rf_dq_wd ), // inout rf_dq_wd + .rf_sw_rx (rf_sw_rx ) // output rf_sw_rx +); + +assign u_ant_rf_ctrl.vio_switch = vio_switch_auto ; +assign u_ant_rf_ctrl.vio_frequency = vio_frequency_auto; + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// Tx Signal /////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// baseband signal +wire [11:0] tx_data_i; +wire [11:0] tx_data_q; +wire [11:0] tx_ch1_i; +wire [11:0] tx_ch1_q; +wire [11:0] tx_ch2_i; +wire [11:0] tx_ch2_q; + +ad9361_tx_map_cmos_dual u_ad9361_tx_map +( + .clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in + .clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst + + .tx_data_clk (sys_clk ), // input tx_data_clk + .tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst + + .tx_ch1_i (tx_ch1_i ), // input [11:0] tx_ch1_i + .tx_ch1_q (tx_ch1_q ), // input [11:0] tx_ch1_q + .tx_ch2_i (tx_ch2_i ), // input [11:0] tx_ch2_i + .tx_ch2_q (tx_ch2_q ), // input [11:0] tx_ch2_q + .clk_out (ad9361_1_tx_fb_clk ), // output clk_out + .tx_frame (ad9361_1_tx_frame ), // output tx_frame + .tx_data (ad9361_1_tx_data ) // output [11:0] tx_data +); + +assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk; +// assign ad9361_2_tx_frame = ad9361_1_tx_frame ; +// assign ad9361_2_tx_data = ad9361_1_tx_data ; + +tx_pre_process #( + .CAL_MOD_FINE (0) +) u_tx_pre_process +( + // clock & reset + .clk (sys_clk ), + .rst (sys_rst ), + // input data + .tx_data_ch1_i (tx_data_i ), + .tx_data_ch1_q (tx_data_q ), + .tx_data_ch2_i (tx_data_i ), + .tx_data_ch2_q (tx_data_q ), + // ad9361 calibration interface + .ad9361_tx_switch (ad9361_tx_switch ), + // + .bb_rshift (1'b0 ), + // output data + .tx_ch1_i (tx_ch1_i ), + .tx_ch1_q (tx_ch1_q ), + .tx_ch2_i (tx_ch2_i ), + .tx_ch2_q (tx_ch2_q ) +); + +// <---------------------------------------------------------------------------> +// <--------------------- insert transmitter logic below ----------------------> +// <---------------------------------------------------------------------------> +wire [ 1:0] waveform_sel; +wire sweep_on ; +wire [31:0] freq_set ; +wire [ 1:0] iq_sel ; +wire [ 3:0] bb_rshift ; + +tx_qpsk u_tx_qpsk +( + .clk (sys_clk ), // input clk + .rst (sys_rst ), // input rst + .tx_data_i (tx_data_i ), // output [11:0] tx_data_i + .tx_data_q (tx_data_q ), // output [11:0] tx_data_q + // debug ports + .waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel + .sweep_on (sweep_on ), // input sweep_on + .freq_set (freq_set ), // input [31:0] freq_set + .iq_sel (iq_sel ), // input [ 1:0] iq_sel + .bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift +); + + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// Rx Signals ////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +wire [11:0] rx_ch1_i, rx_ch1_q; +wire [11:0] rx_ch2_i, rx_ch2_q; +wire [11:0] rx_ch3_i, rx_ch3_q; +wire [11:0] rx_ch4_i, rx_ch4_q; + +wire [11:0] rx_cal_ch1_i, rx_cal_ch1_q; +wire [11:0] rx_cal_ch2_i, rx_cal_ch2_q; +wire [11:0] rx_cal_ch3_i, rx_cal_ch3_q; +wire [11:0] rx_cal_ch4_i, rx_cal_ch4_q; + +ad9361_rx_map_cmos_dual u_ad9361_1_rx_map +( + .clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in + .clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst + + .rx_data_clk (sys_clk ), // input rx_data_clk + .rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst + + .rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst + + .rx_frame (ad9361_1_rx_frame ), // input rx_frame + .rx_data (ad9361_1_rx_data ), // input [11:0] rx_data + .rx_ch1_i (rx_ch1_i ), // output [11:0] rx_ch1_i + .rx_ch1_q (rx_ch1_q ), // output [11:0] rx_ch1_q + .rx_ch2_i (rx_ch2_i ), // output [11:0] rx_ch2_i + .rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q +); + +ad9361_rx_map_cmos_dual u_ad9361_2_rx_map +( + .clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in + .clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst + + .rx_data_clk (sys_clk ), // input rx_data_clk + .rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst + + .rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst + + .rx_frame (ad9361_2_rx_frame ), // input rx_frame + .rx_data (ad9361_2_rx_data ), // input [11:0] rx_data + .rx_ch1_i (rx_ch3_i ), // output [11:0] rx_ch1_i + .rx_ch1_q (rx_ch3_q ), // output [11:0] rx_ch1_q + .rx_ch2_i (rx_ch4_i ), // output [11:0] rx_ch2_i + .rx_ch2_q (rx_ch4_q ) // output [11:0] rx_ch2_q +); + +ad9361_phase_cal_coarse u_ad9361_phase_cal +( + // clock & reset + .clk (sys_clk ), // input clk + .rst (sys_rst ), // input rst + // control interface + .ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start + .ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done + .ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start + .ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done + .ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result + .ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid + .ad9361_recal (ad9361_recal ), // input ad9361_recal + // input data interface + .rx_ch1_i (rx_ch1_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch1_i + .rx_ch1_q (rx_ch1_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch1_q + .rx_ch2_i (rx_ch2_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch2_i + .rx_ch2_q (rx_ch2_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch2_q + .rx_ch3_i (rx_ch3_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch3_i + .rx_ch3_q (rx_ch3_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch3_q + .rx_ch4_i (rx_ch4_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch4_i + .rx_ch4_q (rx_ch4_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch4_q + // output data interface + .rx_cal_ch1_i (rx_cal_ch1_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i + .rx_cal_ch1_q (rx_cal_ch1_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q + .rx_cal_ch2_i (rx_cal_ch2_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i + .rx_cal_ch2_q (rx_cal_ch2_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q + .rx_cal_ch3_i (rx_cal_ch3_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i + .rx_cal_ch3_q (rx_cal_ch3_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q + .rx_cal_ch4_i (rx_cal_ch4_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i + .rx_cal_ch4_q (rx_cal_ch4_q ) // output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q +); + +// <---------------------------------------------------------------------------> +// <----------------------- insert receiver logic below -----------------------> +// <---------------------------------------------------------------------------> +wire freq_comp_start ; +wire freq_comp_busy ; +wire [7:0] dmf_num_per_ch ; +wire [31:0] freq_manual ; +wire freq_manual_en ; +wire [31:0] freq_target ; +wire freq_target_valid; + +wire ch_peak_valid ; +wire [17:0] ch1_peak_value_abs ; +wire [17:0] ch1_peak_value_i ; +wire [17:0] ch1_peak_value_q ; +wire [ 9:0] ch1_peak_index ; +wire [17:0] ch2_peak_value_abs ; +wire [17:0] ch2_peak_value_i ; +wire [17:0] ch2_peak_value_q ; +wire [ 9:0] ch2_peak_index ; +wire [17:0] ch3_peak_value_abs ; +wire [17:0] ch3_peak_value_i ; +wire [17:0] ch3_peak_value_q ; +wire [ 9:0] ch3_peak_index ; +wire [17:0] ch4_peak_value_abs ; +wire [17:0] ch4_peak_value_i ; +wire [17:0] ch4_peak_value_q ; +wire [ 9:0] ch4_peak_index ; + +freq_comp #( + .FREQ_WORD_LOWER (-4194304 ), + .FREQ_WORD_UPPER (4194303 ), + .FREQ_WORD_STEP (1024 ) +) u_freq_comp +( + // clock & reset + .clk (sys_clk ), // input clk + .rst (sys_rst ), // input rst + + // input data + .freq_comp_start (freq_comp_start ), // input freq_comp_start + .freq_comp_busy (freq_comp_busy ), // output freq_comp_busy + + .rx_data_valid (ad9361_cal_valid ), // input rx_data_valid + .rx_ch1_i (rx_cal_ch1_i ), // input [DATA_I_WIDTH-1 : 0] rx_ch1_i + .rx_ch1_q (rx_cal_ch1_q ), // input [DATA_I_WIDTH-1 : 0] rx_ch1_q + .rx_ch2_i (rx_cal_ch2_i ), // input [DATA_I_WIDTH-1 : 0] rx_ch2_i + .rx_ch2_q (rx_cal_ch2_q ), // input [DATA_I_WIDTH-1 : 0] rx_ch2_q + .rx_ch3_i (rx_cal_ch3_i ), // input [DATA_I_WIDTH-1 : 0] rx_ch3_i + .rx_ch3_q (rx_cal_ch3_q ), // input [DATA_I_WIDTH-1 : 0] rx_ch3_q + .rx_ch4_i (rx_cal_ch4_i ), // input [DATA_I_WIDTH-1 : 0] rx_ch4_i + .rx_ch4_q (rx_cal_ch4_q ), // input [DATA_I_WIDTH-1 : 0] rx_ch4_q + + // configuration + .dmf_num_per_ch (dmf_num_per_ch ), // input [$clog2(MAX_DMF_NUM)-1 : 0] dmf_num_per_ch + + .freq_manual (freq_manual ), // input [FREQ_WORD_WIDTH-1 : 0] freq_manual + .freq_manual_en (freq_manual_en ), // input freq_manual_en + + // output frequency result + .freq_target (freq_target ), // output [FREQ_WORD_WIDTH-1 : 0] freq_target + .freq_target_valid (freq_target_valid ), // output freq_target_valid + + // output dmf result + .ch_peak_valid (ch_peak_valid ), // output ch_peak_valid + + .ch1_peak_value_abs (ch1_peak_value_abs ), // output reg [DATA_O_WIDTH-1 : 0] ch1_peak_value_abs + .ch1_peak_value_i (ch1_peak_value_i ), // output reg [DATA_O_WIDTH-1 : 0] ch1_peak_value_i + .ch1_peak_value_q (ch1_peak_value_q ), // output reg [DATA_O_WIDTH-1 : 0] ch1_peak_value_q + .ch1_peak_index (ch1_peak_index ), // output reg [$clog2(PRBS_POS-1) : 0] ch1_peak_index + + .ch2_peak_value_abs (ch2_peak_value_abs ), // output reg [DATA_O_WIDTH-1 : 0] ch2_peak_value_abs + .ch2_peak_value_i (ch2_peak_value_i ), // output reg [DATA_O_WIDTH-1 : 0] ch2_peak_value_i + .ch2_peak_value_q (ch2_peak_value_q ), // output reg [DATA_O_WIDTH-1 : 0] ch2_peak_value_q + .ch2_peak_index (ch2_peak_index ), // output reg [$clog2(PRBS_POS-1) : 0] ch2_peak_index + + .ch3_peak_value_abs (ch3_peak_value_abs ), // output reg [DATA_O_WIDTH-1 : 0] ch3_peak_value_abs + .ch3_peak_value_i (ch3_peak_value_i ), // output reg [DATA_O_WIDTH-1 : 0] ch3_peak_value_i + .ch3_peak_value_q (ch3_peak_value_q ), // output reg [DATA_O_WIDTH-1 : 0] ch3_peak_value_q + .ch3_peak_index (ch3_peak_index ), // output reg [$clog2(PRBS_POS-1) : 0] ch3_peak_index + + .ch4_peak_value_abs (ch4_peak_value_abs ), // output reg [DATA_O_WIDTH-1 : 0] ch4_peak_value_abs + .ch4_peak_value_i (ch4_peak_value_i ), // output reg [DATA_O_WIDTH-1 : 0] ch4_peak_value_i + .ch4_peak_value_q (ch4_peak_value_q ), // output reg [DATA_O_WIDTH-1 : 0] ch4_peak_value_q + .ch4_peak_index (ch4_peak_index ) // output reg [$clog2(PRBS_POS-1) : 0] ch4_peak_index +); + + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////// ILAs and VIOs ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +vio_clk_ld_rd u_vio_clk_ld_rd +( + .clk (sys_clk ), + .probe_in0 (ad9361_1_clk_ld), + .probe_in1 (ad9361_2_clk_ld) +); + +vio_rfcontrl u_vio_rfcontrl +( + .clk (clk_48m ), // input wire clk + .probe_out0 (vio_switch ), // output wire [0 : 0] probe_out0 + .probe_out1 (u_ant_rf_ctrl.vio_trdirection ), // output wire [0 : 0] probe_out1 + .probe_out2 (vio_frequency[15:0] ), // output wire [15 : 0] probe_out2 + .probe_out3 (u_ant_rf_ctrl.vio_emitMGC[7:0] ), // output wire [7 : 0] probe_out3 + .probe_out4 (u_ant_rf_ctrl.vio_ch01MGC[3:0] ), // output wire [3 : 0] probe_out4 + .probe_out5 (u_ant_rf_ctrl.vio_ch02MGC[3:0] ), // output wire [3 : 0] probe_out5 + .probe_out6 (u_ant_rf_ctrl.vio_ch03MGC[3:0] ), // output wire [3 : 0] probe_out6 + .probe_out7 (u_ant_rf_ctrl.vio_ch04MGC[3:0] ), // output wire [3 : 0] probe_out7 + .probe_out8 (u_ant_rf_ctrl.vio_recvMGC[7:0] ), // output wire [7 : 0] probe_out8 + .probe_out9 (u_ant_rf_ctrl.vio_AntMod[7:0] ), // output wire [7 : 0] probe_out9 + .probe_out10(u_ant_rf_ctrl.vio_AntOffAxis[15:0] ), // output wire [15 : 0] probe_out10 + .probe_out11(u_ant_rf_ctrl.vio_AntYaw[15:0] ), // output wire [15 : 0] probe_out11 + .probe_out12(u_ant_rf_ctrl.vio_PrecessTime[15:0] ), // output wire [15 : 0] probe_out12 + .probe_out13(rf_auto_start_vio ), // output wire [0 : 0] probe_out13 + .probe_out14(rf_ctrl_mode_vio ), // output wire [0 : 0] probe_out14 + .probe_out15(switch_next_freq_vio ), // output wire [0 : 0] probe_out15 + .probe_out16(switch_last_freq_vio ), // output wire [0 : 0] probe_out16 + .probe_out17(cnt_valid_to_switch_vio[15:0] ), // output wire [15: 0] probe_out17 + .probe_in0 (vio_frequency_auto[15:0] ) // input wire [10: 0] probe_in0 +); + +vio_ant_test u_vio_ant_test +( + .clk (clk_48m ), + .probe_out0 (u_ant_rf_ctrl.vio_mode_ant ), + .probe_out1 (u_ant_rf_ctrl.vio_hop_start ), + .probe_out2 (u_ant_rf_ctrl.vio_standby ), + .probe_out3 (u_ant_rf_ctrl.vio_hoptime[15:0] ) +); + +ila_rfcontrl u_ila_rfcontrl +( + .clk (clk_48m ), // input wire clk + .probe0 (u_ant_rf_ctrl.SPI_MOSI_F ), // input wire [0:0] + .probe1 (u_ant_rf_ctrl.SPI_MISO_F ), // input wire [0:0] + .probe2 (u_ant_rf_ctrl.SPI_SYN_F ), // input wire [0:0] + .probe3 (u_ant_rf_ctrl.TP_EN_F ), // input wire [0:0] + .probe4 (u_ant_rf_ctrl.TR_MGC_F ), // input wire [0:0] + .probe5 (u_ant_rf_ctrl.CAL_F ), // input wire [0:0] + .probe6 (u_ant_rf_ctrl.PRF ), // input wire [0:0] + .probe7 (u_ant_rf_ctrl.rf_standby ), // input wire [0:0] + .probe8 (u_ant_rf_ctrl.rf_sw_pll ), // input wire [0:0] + .probe9 (u_ant_rf_ctrl.rf_t ), // input wire [0:0] + .probe10(u_ant_rf_ctrl.rf_r ), // input wire [0:0] + .probe11(u_ant_rf_ctrl.rf_sw_bpf ), // input wire [0:0] + .probe12(u_ant_rf_ctrl.rf_sclk1 ), // input wire [0:0] + .probe13(u_ant_rf_ctrl.rf_sdio1 ), // input wire [0:0] + .probe14(u_ant_rf_ctrl.rf_cs1 ), // input wire [0:0] + .probe15(u_ant_rf_ctrl.rf_ld1 ), // input wire [0:0] + .probe16(u_ant_rf_ctrl.rf_sclk2 ), // input wire [0:0] + .probe17(u_ant_rf_ctrl.rf_sdio2 ), // input wire [0:0] + .probe18(u_ant_rf_ctrl.rf_cs2 ), // input wire [0:0] + .probe19(u_ant_rf_ctrl.rf_ld2 ), // input wire [0:0] + .probe20(u_ant_rf_ctrl.rf_sclk3 ), // input wire [0:0] + .probe21(u_ant_rf_ctrl.rf_sdio3 ), // input wire [0:0] + .probe22(u_ant_rf_ctrl.rf_cs3 ), // input wire [0:0] + .probe23(u_ant_rf_ctrl.rf_ld3 ), // input wire [0:0] + .probe24(u_ant_rf_ctrl.rf_tmgc_16 ), // input wire [0:0] + .probe25(u_ant_rf_ctrl.rf_tmgc_8 ), // input wire [0:0] + .probe26(u_ant_rf_ctrl.rf_tmgc_4 ), // input wire [0:0] + .probe27(u_ant_rf_ctrl.rf_tmgc_2 ), // input wire [0:0] + .probe28(u_ant_rf_ctrl.rf_tmgc_1 ), // input wire [0:0] + .probe29(u_ant_rf_ctrl.rf_rmgc_16 ), // input wire [0:0] + .probe30(u_ant_rf_ctrl.rf_rmgc_8 ), // input wire [0:0] + .probe31(u_ant_rf_ctrl.rf_rmgc_4 ), // input wire [0:0] + .probe32(u_ant_rf_ctrl.rf_rmgc_2 ), // input wire [0:0] + .probe33(u_ant_rf_ctrl.rf_rmgc_1 ), // input wire [0:0] + .probe34(u_ant_rf_ctrl.rf_enable ), // input wire [0:0] + .probe35(u_ant_rf_ctrl.rf_sc ), // input wire [0:0] + .probe36(u_ant_rf_ctrl.rf_sd ), // input wire [0:0] + .probe37(u_ant_rf_ctrl.rf_endsyn ), // input wire [0:0] + .probe38(u_ant_rf_ctrl.rf_sdout ), // input wire [0:0] + .probe39(u_ant_rf_ctrl.state_rfdata[1:0] ), // input wire [0:0] + .probe40(u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [0:0] + .probe41(u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [0:0] + .probe42(u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [0:0] + .probe43(u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [0:0] + .probe44(u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [0:0] + .probe45(u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [0:0] + .probe46(u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [0:0] + .probe47(u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [0:0] + .probe48(u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [0:0] + .probe49(u_ant_rf_ctrl.RF_RecvWord[95:0] ) // input wire [0:0] +); + +ila_AntCtrl u_ila_AntCtrl +( + .clk (clk_96m ), // input wire clk + .probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0 + .probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1 + .probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2 + .probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3 + .probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4 + .probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5 + .probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5 + .probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5 + .probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5 + .probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5 + .probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5 + .probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5 + .probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5 +); + +vio_rf_rd u_vio_rf_rd ( + .clk (clk_96m ), // input wire clk + .probe_in0 (u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [7 : 0] probe_in0 + .probe_in1 (u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [7 : 0] probe_in1 + .probe_in2 (u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [7 : 0] probe_in2 + .probe_in3 (u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [7 : 0] probe_in3 + .probe_in4 (u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [3 : 0] probe_in4 + .probe_in5 (u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [3 : 0] probe_in5 + .probe_in6 (u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [3 : 0] probe_in6 + .probe_in7 (u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [3 : 0] probe_in7 + .probe_in8 (u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [31 : 0] probe_in8 + .probe_in9 (u_ant_rf_ctrl.RF_RecvWord_last ) // input wire [95 : 0] probe_in9 +); + +vio_ant_rd u_vio_ant_rd ( + .clk (clk_96m ), // input wire clk + .probe_in0 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [7 : 0] probe_in0 + .probe_in1 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [7 : 0] probe_in1 + .probe_in2 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [7 : 0] probe_in2 + .probe_in3 (u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [7 : 0] probe_in3 + .probe_in4 (u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [31 : 0] probe_in4 + .probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [95 : 0] probe_in5 +); + +ila_2x12x1024 u_ila_tx +( + .clk (sys_clk ), // input wire clk + .probe0 (tx_ch1_i ), // input wire [11:0] probe0 + .probe1 (tx_ch1_q ) // input wire [11:0] probe1 +); + +ila_8x12x8192 u_ila_rx +( + .clk (sys_clk ), // input wire clk + .probe0 (rx_cal_ch1_i ), // input wire [11:0] probe0 + .probe1 (rx_cal_ch1_q ), // input wire [11:0] probe1 + .probe2 (rx_cal_ch2_i ), // input wire [11:0] probe2 + .probe3 (rx_cal_ch2_q ), // input wire [11:0] probe3 + .probe4 (rx_cal_ch3_i ), // input wire [11:0] probe4 + .probe5 (rx_cal_ch3_q ), // input wire [11:0] probe5 + .probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6 + .probe7 (rx_cal_ch4_q ) // input wire [11:0] probe7 +); + +ila_cal u_ila_cal +( + .clk (sys_clk ), // input wire clk + .probe0 (u_ad9361_phase_cal.ad9361_1_cal_start_d2 ), // input wire [0:0] probe0 + .probe1 (u_ad9361_phase_cal.ad9361_1_cal_done ), // input wire [0:0] probe1 + .probe2 (u_ad9361_phase_cal.ad9361_2_cal_start_d2 ), // input wire [0:0] probe2 + .probe3 (u_ad9361_phase_cal.ad9361_2_cal_done ), // input wire [0:0] probe3 + .probe4 (u_ad9361_phase_cal.ad9361_cal_result ), // input wire [0:0] probe4 + .probe5 (u_ad9361_phase_cal.ad9361_recal_d2 ), // input wire [0:0] probe5 + .probe6 (u_ad9361_phase_cal.curr_state ), // input wire [1:0] probe6 + .probe7 (rx_ch2_i ), // input wire [11:0] probe7 + .probe8 (rx_ch2_q ), // input wire [11:0] probe8 + .probe9 (rx_ch4_i ), // input wire [11:0] probe9 + .probe10(rx_ch4_q ), // input wire [11:0] probe10 + .probe11(rx_cal_ch2_i ), // input wire [11:0] probe11 + .probe12(rx_cal_ch2_q ), // input wire [11:0] probe12 + .probe13(rx_cal_ch4_i ), // input wire [11:0] probe13 + .probe14(rx_cal_ch4_q ) // input wire [11:0] probe14 +); + +vio_manual_ctrl u_vio_manual_ctrl +( + .clk (sys_clk ), // input wire clk + .probe_out0 (waveform_sel[1:0] ), // output wire [1 : 0] probe_out0 + .probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1 + .probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2 + .probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3 + .probe_out4 (bb_rshift[3:0] ) // output wire [3 : 0] probe_out4 +); + +vio_freq_comp u_vio_freq_comp +( + .clk (sys_clk ), // input wire clk + .probe_in0 (freq_comp_busy ), // input wire [0 : 0] probe_in0 + .probe_out0 (freq_comp_start ), // output wire [0 : 0] probe_out0 + .probe_out1 (dmf_num_per_ch ), // output wire [7 : 0] probe_out1 + .probe_out2 (freq_manual_en ), // output wire [0 : 0] probe_out2 + .probe_out3 (freq_manual ) // output wire [31 : 0] probe_out3 +); + +ila_freq_comp u_ila_freq_comp +( + .clk (sys_clk ), // input wire clk + .probe0 (ch_peak_valid ), // input wire [0:0] probe0 + .probe1 (ch1_peak_value_i ), // input wire [17:0] probe1 + .probe2 (ch1_peak_value_q ), // input wire [17:0] probe2 + .probe3 (ch2_peak_value_i ), // input wire [17:0] probe3 + .probe4 (ch2_peak_value_q ), // input wire [17:0] probe4 + .probe5 (ch3_peak_value_i ), // input wire [17:0] probe5 + .probe6 (ch3_peak_value_q ), // input wire [17:0] probe6 + .probe7 (ch4_peak_value_i ), // input wire [17:0] probe7 + .probe8 (ch4_peak_value_q ), // input wire [17:0] probe8 + .probe9 (ch1_peak_index ), // input wire [7:0] probe9 + .probe10(ch2_peak_index ), // input wire [7:0] probe10 + .probe11(ch3_peak_index ), // input wire [7:0] probe11 + .probe12(ch4_peak_index ), // input wire [7:0] probe12 + .probe13(freq_comp_start ), // input wire [0:0] probe13 + .probe14(u_freq_comp.state_curr ), // input wire [2:0] probe14 + .probe15(u_freq_comp.din_freq_cxr_real ), // input wire [11:0] probe15 + .probe16(u_freq_comp.din_freq_cxr_imag ), // input wire [11:0] probe16 + .probe17(u_freq_comp.dmf_freq_moduli_abs ), // input wire [17:0] probe17 + .probe18(u_freq_comp.dmf_ch_moduli_abs[0] ), // input wire [17:0] probe18 + .probe19(u_freq_comp.dmf_ch_moduli_abs[1] ), // input wire [17:0] probe19 + .probe20(u_freq_comp.dmf_ch_moduli_abs[2] ), // input wire [17:0] probe20 + .probe21(u_freq_comp.dmf_ch_moduli_abs[3] ), // input wire [17:0] probe21 + .probe22(u_freq_comp.freq_word ), // input wire [31:0] probe22 + .probe23(vio_frequency_auto[11:0] ) // input wire [11:0] probe23 +); + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/tx_pre_process.v b/projects/duifei/duifei_online_acq_par/rtl/tx_pre_process.v new file mode 100644 index 00000000..7b0b7e1a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/tx_pre_process.v @@ -0,0 +1,138 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2023/02/25 15:20:22 +// Design Name: +// Module Name: tx_pre_process +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tx_pre_process +#( + parameter ADC_DATA_WIDTH = 12, + parameter PRBS = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)] + parameter PRBS_LEN = 128, // length of pseudorandom bit sequence + parameter INTERP_FACTOR = 8, // interpolation factor, max inter-channel delay ranges in [-INTERP_FACTOR+1,INTERP_FACTOR-1] + parameter CAL_MOD_FINE = 1 +) +( + // clock & reset + input clk , + input rst , + // input data + input [ADC_DATA_WIDTH-1:0] tx_data_ch1_i , + input [ADC_DATA_WIDTH-1:0] tx_data_ch1_q , + input [ADC_DATA_WIDTH-1:0] tx_data_ch2_i , + input [ADC_DATA_WIDTH-1:0] tx_data_ch2_q , + // ad9361 calibration interface + input ad9361_tx_switch , + // + input [$clog2(ADC_DATA_WIDTH)-1:0] bb_rshift, + // output data + output [ADC_DATA_WIDTH-1:0] tx_ch1_i , + output [ADC_DATA_WIDTH-1:0] tx_ch1_q , + output [ADC_DATA_WIDTH-1:0] tx_ch2_i , + output [ADC_DATA_WIDTH-1:0] tx_ch2_q +); + +integer i; + +// square shaped bpsk signal +reg [$clog2(PRBS_LEN*INTERP_FACTOR)-1 : 0] chip_interp_cnt = 'b0; +reg signed [ADC_DATA_WIDTH-1:0] tx_pn_i = 'b0; +reg signed [ADC_DATA_WIDTH-1:0] tx_pn_q = 'b0; + +if (CAL_MOD_FINE == 1) begin + +always @(posedge clk) begin + if (rst) begin + chip_interp_cnt <= 'b0; + end + else begin + chip_interp_cnt <= chip_interp_cnt + 1'b1; + end +end + +always @(posedge clk) begin + if (rst) begin + tx_pn_i <= 'b0; + tx_pn_q <= 'b0; + end + else begin + tx_pn_i <= PRBS[chip_interp_cnt[$clog2(PRBS_LEN*INTERP_FACTOR)-1 -: $clog2(PRBS_LEN)]] ? {1'b0,{(ADC_DATA_WIDTH-1){1'b1}}} : {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1}; // (1 or 0) ? 4'b0111 : 4'b1001 + tx_pn_q <= PRBS[chip_interp_cnt[$clog2(PRBS_LEN*INTERP_FACTOR)-1 -: $clog2(PRBS_LEN)]] ? {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1} : {1'b0,{(ADC_DATA_WIDTH-1){1'b1}}}; // (1 or 0) ? 4'b1001 : 4'b0111 + end +end + +end // if (CAL_MOD_FINE == 1) + +// buffer input control signals (clock domain crossing from ps to pl clock domain) +reg ad9361_tx_switch_d1 = 'b0; +reg ad9361_tx_switch_d2 = 'b0; + +wire signed [ADC_DATA_WIDTH-1:0] tx_dc_i = {1'b0,{(ADC_DATA_WIDTH-2){1'b1}},1'b1}; +wire signed [ADC_DATA_WIDTH-1:0] tx_dc_q = {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1}; + +always @(posedge clk) begin + ad9361_tx_switch_d1 <= ad9361_tx_switch; + ad9361_tx_switch_d2 <= ad9361_tx_switch_d1; +end + +reg [ADC_DATA_WIDTH-1 : 0] tx_ch1_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] tx_ch1_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] tx_ch2_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] tx_ch2_q_buf = 'b0; + +assign tx_ch1_i = tx_ch1_i_buf; +assign tx_ch1_q = tx_ch1_q_buf; +assign tx_ch2_i = tx_ch2_i_buf; +assign tx_ch2_q = tx_ch2_q_buf; + +always @(posedge clk) begin + if (rst) begin + tx_ch1_i_buf <= 'b0; + tx_ch1_q_buf <= 'b0; + tx_ch2_i_buf <= 'b0; + tx_ch2_q_buf <= 'b0; + end + else if (ad9361_tx_switch_d2) begin +if (CAL_MOD_FINE == 1) begin + tx_ch1_i_buf <= tx_pn_i >>> bb_rshift; + tx_ch1_q_buf <= tx_pn_q >>> bb_rshift; + tx_ch2_i_buf <= tx_pn_i >>> bb_rshift; + tx_ch2_q_buf <= tx_pn_q >>> bb_rshift; +end // CAL_MOD_FINE == 1 +else begin + tx_ch1_i_buf <= tx_dc_i >>> bb_rshift; + tx_ch1_q_buf <= tx_dc_q >>> bb_rshift; + tx_ch2_i_buf <= tx_dc_i >>> bb_rshift; + tx_ch2_q_buf <= tx_dc_q >>> bb_rshift; +end // CAL_MOD_FINE != 1 + end + else begin + tx_ch1_i_buf <= tx_data_ch1_i; + tx_ch1_q_buf <= tx_data_ch1_q; + tx_ch2_i_buf <= tx_data_ch2_i; + tx_ch2_q_buf <= tx_data_ch2_q; + end +end + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/testbenches/tb_freq_comp.v b/projects/duifei/duifei_online_acq_par/testbenches/tb_freq_comp.v new file mode 100644 index 00000000..3008f02b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/testbenches/tb_freq_comp.v @@ -0,0 +1,93 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/06/2023 03:39:20 PM +// Design Name: +// Module Name: tb_freq_comp +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_freq_comp; + +reg clk = 1'b1; +reg rst = 1'b1; +reg freq_comp_start = 'b0; +wire freq_comp_busy; + +wire [11:0] tx_data_i, tx_data_q; +wire [31:0] freq_target; +wire freq_target_valid; + +initial begin + #102; + rst = 1'b0; + #1000; + freq_comp_start = ~freq_comp_start; + #1000; + wait (freq_comp_busy == 0); + #1000; + freq_comp_start = ~freq_comp_start; +end + +always #10 clk = ~clk; + +tx_qpsk u_tx_qpsk +( + .clk (clk ), + .rst (rst ), + + .tx_data_i (tx_data_i ), + .tx_data_q (tx_data_q ), + // debug ports + .waveform_sel (2'd1 ), + .sweep_on (1'b0 ), + .freq_set ('b0 ), + .iq_sel (2'b11 ), + .bb_rshift (4'd0 ) +); + +freq_comp #( + .FREQ_WORD_LOWER(-1024 ), + .FREQ_WORD_UPPER(1023 ), + .FREQ_WORD_STEP (1024 ) +)u_freq_comp +( + .clk (clk ), + .rst (rst ), + + .freq_comp_start (freq_comp_start ), + .freq_comp_busy (freq_comp_busy ), + + .rx_data_valid (~rst ), + .rx_ch1_i (tx_data_i ), + .rx_ch1_q (tx_data_q ), + .rx_ch2_i (tx_data_q ), + .rx_ch2_q (tx_data_i ), + .rx_ch3_i (tx_data_i ), + .rx_ch3_q (tx_data_i ), + .rx_ch4_i (tx_data_q ), + .rx_ch4_q (tx_data_q ), + + .dmf_num_per_ch (2 ), + + .freq_manual (327680 ), + .freq_manual_en (1'b0 ), + + .freq_target (freq_target ), + .freq_target_valid (freq_target_valid ) +); + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/testbenches/tb_rx_dmf.v b/projects/duifei/duifei_online_acq_par/testbenches/tb_rx_dmf.v new file mode 100644 index 00000000..a8120dc1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/testbenches/tb_rx_dmf.v @@ -0,0 +1,128 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/25/2023 06:48:44 PM +// Design Name: +// Module Name: tb_rx_dmf +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_rx_dmf; + +// length of pseudorandom bit sequence, need to be a power of 2 +localparam PRBS_LEN = 128; +// interpolation of input signal, need to be a power of 2 +localparam INTERP_RATE = 8; +// signal processing interpolation, need to be a power of 2 +localparam PROCESS_INTERP = 4; +localparam PRBS_LEN_INTERP = PRBS_LEN*PROCESS_INTERP; +// number of accumulated symbols, need to be a power of 2 +localparam ACC_SYM_NUM = 4; + +localparam MAX_DMF_NUM = 64; +localparam DATA_I_WIDTH = 12; +localparam DATA_O_WIDTH = 18; + +reg clk = 1'b1; +reg rst = 1'b1; +reg dmf_start = 'b0; +wire dmf_busy; +wire last_peak_valid; + +wire [11:0] tx_data_i, tx_data_q; + +reg [31:0] freq_set = 'b0; + +wire peak_valid ; +wire [DATA_O_WIDTH-1 : 0] peak_value_abs ; +wire [DATA_O_WIDTH-1 : 0] peak_value_i ; +wire [DATA_O_WIDTH-1 : 0] peak_value_q ; +wire [$clog2(PRBS_LEN_INTERP)-1 : 0] peak_index ; + +initial begin + #102; + rst = 1'b0; + #1000; + dmf_start = ~dmf_start; + + wait (last_peak_valid == 1); + freq_set = -32'd2048; + #1000; + dmf_start = ~dmf_start; + + wait (last_peak_valid == 1); + freq_set = 32'd1; + #1000; + dmf_start = ~dmf_start; + + wait (last_peak_valid == 1); + freq_set = 32'd2048; + #1000; + dmf_start = ~dmf_start; + + wait (last_peak_valid == 1); + freq_set = 32'd4096; + #1000; + dmf_start = ~dmf_start; + + wait (last_peak_valid == 1); + freq_set = 32'd6144; + #1000; + dmf_start = ~dmf_start; +end + +always #10 clk = ~clk; + +tx_qpsk u_tx_qpsk +( + .clk (clk ), + .rst (rst ), + + .tx_data_i (tx_data_i ), + .tx_data_q (tx_data_q ), + // debug ports + .waveform_sel (2'd1 ), + .sweep_on (1'b0 ), + .freq_set (freq_set ), + .iq_sel (2'b11 ), + .bb_rshift (4'd0 ) +); + +rx_dmf #( + .ACC_SYM_NUM (ACC_SYM_NUM ) +) u_rx_dmf +( + .clk (clk ), + .rst (rst ), + + .dmf_start (dmf_start ), + .dmf_busy (dmf_busy ), + + .dmf_num (2 ), + + .din_valid (~rst ), + .din_real (tx_data_i ), + .din_imag (tx_data_i ), + + .peak_valid (peak_valid ), + .last_peak_valid(last_peak_valid), + .peak_value_abs (peak_value_abs ), + .peak_value_i (peak_value_i ), + .peak_value_q (peak_value_q ), + .peak_index (peak_index ) +); + +endmodule