diff --git a/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc b/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc index aa626a8f..9ef2d8eb 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc +++ b/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc @@ -49,15 +49,15 @@ set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports {freq_h set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[10]} ] set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[11]} ] -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports tx_gain ] -set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports rx_gain ] -set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS25} [get_ports clk_12M ] -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports CS_rf ] +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports rf_spi_attn_mosi ] +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports rf_spi_attn_miso ] +set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS25} [get_ports rf_spi_attn_clk ] +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports rf_spi_attn_csn ] set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports tx_gain_on ] set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports rx_gain_on ] set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports hop_words_valid ] set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports freq_hop_switch ] # Sync Signal -set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports sync_signal_out ] ;# Bank9, not used before -set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports sync_gnd ] ;# Bank9, not used before \ No newline at end of file +# set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports sync_signal_out ] ;# Bank9, not used before +# set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports sync_gnd ] ;# Bank9, not used before \ No newline at end of file diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test.xcix index 9a1af0b8..17709344 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test.xcix +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test.xcix @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:201d0f64179aee646661c351fafb6cfc75a99fba1d94d3bd0bdf24148f8a1e87 -size 27581687 +oid sha256:7e19bde720556bdf513ea67c52864a65aa92b2849a9690ee2c7a129e6f20ab98 +size 27527162 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test.veo index 734438ec..3c388d87 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test.veo +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test.veo @@ -65,8 +65,7 @@ ila_rf_test your_instance_name ( .probe5(probe5), // input wire [0:0] probe5 .probe6(probe6), // input wire [0:0] probe6 .probe7(probe7), // input wire [0:0] probe7 - .probe8(probe8), // input wire [0:0] probe8 - .probe9(probe9) // input wire [11:0] probe9 + .probe8(probe8) // input wire [0:0] probe8 ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.v index cbf75d90..3f479824 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:19d8ad4109babf969bdfe516c397a62b469ce49220b24c8d85e150a3319d7151 -size 1824426 +oid sha256:3d47d3dabdcbb400334417d066754c9a8d7ddb51ab61d53031313ca992bf2dec +size 1720330 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.vhdl index 680381a6..003de129 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.vhdl +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:449f65ac341f50fe588c835e11213443114b29b0fa40133ee2f5f46c10dbcd55 -size 3440051 +oid sha256:f570072ef78e8472d8edb322980829ae72dc5d73c2628f7b76e5af9bb1fd3507 +size 3317304 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.v index be350621..97a72b9b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Thu May 18 12:55:28 2023 +// Date : Mon Jul 3 16:32:04 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v +// /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/ila_rf_test_synth_1/ila_rf_test_stub.v // Design : ila_rf_test // Purpose : Stub declaration of top-level module interface // Device : xc7z100ffg900-2 @@ -15,8 +15,8 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "ila,Vivado 2019.1.3" *) module ila_rf_test(clk, probe0, probe1, probe2, probe3, probe4, probe5, - probe6, probe7, probe8, probe9) -/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]" */; + probe6, probe7, probe8) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0]" */; input clk; input [11:0]probe0; input [0:0]probe1; @@ -27,5 +27,4 @@ module ila_rf_test(clk, probe0, probe1, probe2, probe3, probe4, probe5, input [0:0]probe6; input [0:0]probe7; input [0:0]probe8; - input [11:0]probe9; endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.vhdl index ae79d844..05f8efe9 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.vhdl +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Thu May 18 12:55:28 2023 +-- Date : Mon Jul 3 16:32:04 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl +-- /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl -- Design : ila_rf_test -- Purpose : Stub declaration of top-level module interface -- Device : xc7z100ffg900-2 @@ -23,8 +23,7 @@ entity ila_rf_test is probe5 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe6 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe7 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe8 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 ) + probe8 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end ila_rf_test; @@ -33,7 +32,7 @@ architecture stub of ila_rf_test is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; begin diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/sim/ila_rf_test.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/sim/ila_rf_test.v index 76b0a200..4f81fa2e 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/sim/ila_rf_test.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/sim/ila_rf_test.v @@ -58,8 +58,7 @@ probe4, probe5, probe6, probe7, -probe8, -probe9 +probe8 ); input clk; @@ -74,7 +73,6 @@ input [0 : 0] probe5; input [0 : 0] probe6; input [0 : 0] probe7; input [0 : 0] probe8; -input [11 : 0] probe9; endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/sim/vio_rf_control.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/sim/vio_RF_control.v similarity index 83% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/sim/vio_rf_control.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/sim/vio_RF_control.v index 0a3ca737..2c99c0a3 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/sim/vio_rf_control.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/sim/vio_RF_control.v @@ -46,9 +46,9 @@ // // DO NOT MODIFY THIS FILE. `timescale 1ns / 1ps -module vio_rf_control ( +module vio_RF_control ( clk, -probe_in0, + probe_out0, probe_out1, probe_out2, @@ -57,35 +57,20 @@ probe_out4, probe_out5, probe_out6, probe_out7, -probe_out8, -probe_out9, -probe_out10, -probe_out11, -probe_out12, -probe_out13, -probe_out14, -probe_out15 +probe_out8 ); input clk; -input [10 : 0] probe_in0; output reg [0 : 0] probe_out0 = 'h0 ; output reg [1 : 0] probe_out1 = 'h0 ; output reg [0 : 0] probe_out2 = 'h0 ; -output reg [5 : 0] probe_out3 = 'h08 ; -output reg [5 : 0] probe_out4 = 'h38 ; +output reg [7 : 0] probe_out3 = 'h03 ; +output reg [7 : 0] probe_out4 = 'h23 ; output reg [11 : 0] probe_out5 = 'h3E8 ; output reg [0 : 0] probe_out6 = 'h0 ; output reg [0 : 0] probe_out7 = 'h0 ; output reg [0 : 0] probe_out8 = 'h0 ; -output reg [0 : 0] probe_out9 = 'h0 ; -output reg [0 : 0] probe_out10 = 'h0 ; -output reg [0 : 0] probe_out11 = 'h0 ; -output reg [0 : 0] probe_out12 = 'h0 ; -output reg [31 : 0] probe_out13 = 'h00000000 ; -output reg [0 : 0] probe_out14 = 'h0 ; -output reg [31 : 0] probe_out15 = 'h00000000 ; endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.veo similarity index 72% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.veo rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.veo index 76f0f1df..13870dbc 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.veo +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.veo @@ -54,24 +54,21 @@ // (in parentheses) to your own signal names. //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -vio_rf_test your_instance_name ( - .clk(clk), // input wire clk - .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 - .probe_out1(probe_out1), // output wire [7 : 0] probe_out1 - .probe_out2(probe_out2), // output wire [7 : 0] probe_out2 - .probe_out3(probe_out3), // output wire [31 : 0] probe_out3 - .probe_out4(probe_out4), // output wire [0 : 0] probe_out4 - .probe_out5(probe_out5), // output wire [11 : 0] probe_out5 - .probe_out6(probe_out6), // output wire [11 : 0] probe_out6 - .probe_out7(probe_out7), // output wire [31 : 0] probe_out7 - .probe_out8(probe_out8), // output wire [31 : 0] probe_out8 - .probe_out9(probe_out9), // output wire [63 : 0] probe_out9 - .probe_out10(probe_out10), // output wire [4 : 0] probe_out10 - .probe_out11(probe_out11) // output wire [0 : 0] probe_out11 +vio_RF_control your_instance_name ( + .clk(clk), // input wire clk + .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [1 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [7 : 0] probe_out3 + .probe_out4(probe_out4), // output wire [7 : 0] probe_out4 + .probe_out5(probe_out5), // output wire [11 : 0] probe_out5 + .probe_out6(probe_out6), // output wire [0 : 0] probe_out6 + .probe_out7(probe_out7), // output wire [0 : 0] probe_out7 + .probe_out8(probe_out8) // output wire [0 : 0] probe_out8 ); // INST_TAG_END ------ End INSTANTIATION Template --------- -// You must compile the wrapper file vio_rf_test.v when simulating -// the core, vio_rf_test. When compiling the wrapper file, be sure to +// You must compile the wrapper file vio_RF_control.v when simulating +// the core, vio_RF_control. When compiling the wrapper file, be sure to // reference the Verilog simulation library. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.vho b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.vho similarity index 79% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.vho rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.vho index 37776596..ebb4dc98 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.vho +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.vho @@ -52,21 +52,18 @@ -- The following code must appear in the VHDL architecture header. ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT vio_rf_test +COMPONENT vio_RF_control PORT ( clk : IN STD_LOGIC; probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - probe_out2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - probe_out8 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - probe_out9 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - probe_out10 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ @@ -75,7 +72,7 @@ END COMPONENT; -- body. Substitute your own instance name and net names. ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : vio_rf_test +your_instance_name : vio_RF_control PORT MAP ( clk => clk, probe_out0 => probe_out0, @@ -86,14 +83,11 @@ your_instance_name : vio_rf_test probe_out5 => probe_out5, probe_out6 => probe_out6, probe_out7 => probe_out7, - probe_out8 => probe_out8, - probe_out9 => probe_out9, - probe_out10 => probe_out10, - probe_out11 => probe_out11 + probe_out8 => probe_out8 ); -- INST_TAG_END ------ End INSTANTIATION Template --------- --- You must compile the wrapper file vio_rf_test.vhd when simulating --- the core, vio_rf_test. When compiling the wrapper file, be sure to +-- You must compile the wrapper file vio_RF_control.vhd when simulating +-- the core, vio_RF_control. When compiling the wrapper file, be sure to -- reference the VHDL simulation library. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.v new file mode 100644 index 00000000..d2027514 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b9b77ac176e8ad7e093daf0c8fddbc4e9f9b57df2bec9eca440122e742975871 +size 346446 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.vhdl new file mode 100644 index 00000000..104bb3cf --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:363e7fd5368c994b30b8a7c879fab160cc73f2325814afb439ab825e5a209448 +size 624784 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.v similarity index 56% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.v index 374e48d6..2e62ebac 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.v @@ -1,11 +1,11 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Thu May 18 12:54:39 2023 +// Date : Tue Jun 27 16:05:58 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v -// Design : vio_rf_test +// /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/vio_RF_control_synth_1/vio_RF_control_stub.v +// Design : vio_RF_control // Purpose : Stub declaration of top-level module interface // Device : xc7z100ffg900-2 // -------------------------------------------------------------------------------- @@ -14,21 +14,17 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_rf_test(clk, probe_out0, probe_out1, probe_out2, - probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, - probe_out10, probe_out11) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]" */; +module vio_RF_control(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */; input clk; output [0:0]probe_out0; - output [7:0]probe_out1; - output [7:0]probe_out2; - output [31:0]probe_out3; - output [0:0]probe_out4; + output [1:0]probe_out1; + output [0:0]probe_out2; + output [7:0]probe_out3; + output [7:0]probe_out4; output [11:0]probe_out5; - output [11:0]probe_out6; - output [31:0]probe_out7; - output [31:0]probe_out8; - output [63:0]probe_out9; - output [4:0]probe_out10; - output [0:0]probe_out11; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.vhdl similarity index 50% rename from projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.vhdl index a80bc92f..adddb59d 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.vhdl @@ -1,46 +1,38 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Thu May 18 11:36:40 2023 +-- Date : Tue Jun 27 16:05:58 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl --- Design : vio_rf_control +-- /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl +-- Design : vio_RF_control -- Purpose : Stub declaration of top-level module interface -- Device : xc7z100ffg900-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -entity vio_rf_control is +entity vio_RF_control is Port ( clk : in STD_LOGIC; - probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 ); probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 ); - probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 7 downto 0 ); probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ) ); -end vio_rf_control; +end vio_RF_control; -architecture stub of vio_rf_control is +architecture stub of vio_RF_control is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.veo deleted file mode 100644 index 2f5a2d03..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.veo +++ /dev/null @@ -1,82 +0,0 @@ -// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:vio:3.0 -// IP Revision: 20 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -vio_rf_control your_instance_name ( - .clk(clk), // input wire clk - .probe_in0(probe_in0), // input wire [10 : 0] probe_in0 - .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 - .probe_out1(probe_out1), // output wire [1 : 0] probe_out1 - .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 - .probe_out3(probe_out3), // output wire [5 : 0] probe_out3 - .probe_out4(probe_out4), // output wire [5 : 0] probe_out4 - .probe_out5(probe_out5), // output wire [11 : 0] probe_out5 - .probe_out6(probe_out6), // output wire [0 : 0] probe_out6 - .probe_out7(probe_out7), // output wire [0 : 0] probe_out7 - .probe_out8(probe_out8), // output wire [0 : 0] probe_out8 - .probe_out9(probe_out9), // output wire [0 : 0] probe_out9 - .probe_out10(probe_out10), // output wire [0 : 0] probe_out10 - .probe_out11(probe_out11), // output wire [0 : 0] probe_out11 - .probe_out12(probe_out12), // output wire [0 : 0] probe_out12 - .probe_out13(probe_out13), // output wire [31 : 0] probe_out13 - .probe_out14(probe_out14), // output wire [0 : 0] probe_out14 - .probe_out15(probe_out15) // output wire [31 : 0] probe_out15 -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file vio_rf_control.v when simulating -// the core, vio_rf_control. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.vho b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.vho deleted file mode 100644 index 9934f43c..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.vho +++ /dev/null @@ -1,109 +0,0 @@ --- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:vio:3.0 --- IP Revision: 20 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT vio_rf_control - PORT ( - clk : IN STD_LOGIC; - probe_in0 : IN STD_LOGIC_VECTOR(10 DOWNTO 0); - probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out3 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - probe_out4 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out9 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out10 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out12 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out13 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out15 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : vio_rf_control - PORT MAP ( - clk => clk, - probe_in0 => probe_in0, - probe_out0 => probe_out0, - probe_out1 => probe_out1, - probe_out2 => probe_out2, - probe_out3 => probe_out3, - probe_out4 => probe_out4, - probe_out5 => probe_out5, - probe_out6 => probe_out6, - probe_out7 => probe_out7, - probe_out8 => probe_out8, - probe_out9 => probe_out9, - probe_out10 => probe_out10, - probe_out11 => probe_out11, - probe_out12 => probe_out12, - probe_out13 => probe_out13, - probe_out14 => probe_out14, - probe_out15 => probe_out15 - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file vio_rf_control.vhd when simulating --- the core, vio_rf_control. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.v deleted file mode 100644 index a82bf59b..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:61871bc56b34526261f6ee93952fb8c48de88deae16fa932900a16de7cd4b693 -size 418849 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.vhdl deleted file mode 100644 index 285e9cc8..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:7d4547a5ef5862f5cc376f41a5d671a805063b6777f0f60d9e8d278616fba128 -size 727945 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v deleted file mode 100644 index e5624f99..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v +++ /dev/null @@ -1,39 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Thu May 18 11:36:40 2023 -// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -// Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v -// Design : vio_rf_control -// Purpose : Stub declaration of top-level module interface -// Device : xc7z100ffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_rf_control(clk, probe_in0, probe_out0, probe_out1, - probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, - probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */; - input clk; - input [10:0]probe_in0; - output [0:0]probe_out0; - output [1:0]probe_out1; - output [0:0]probe_out2; - output [5:0]probe_out3; - output [5:0]probe_out4; - output [11:0]probe_out5; - output [0:0]probe_out6; - output [0:0]probe_out7; - output [0:0]probe_out8; - output [0:0]probe_out9; - output [0:0]probe_out10; - output [0:0]probe_out11; - output [0:0]probe_out12; - output [31:0]probe_out13; - output [0:0]probe_out14; - output [31:0]probe_out15; -endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl deleted file mode 100644 index a80bc92f..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl +++ /dev/null @@ -1,47 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Thu May 18 11:36:40 2023 --- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl --- Design : vio_rf_control --- Purpose : Stub declaration of top-level module interface --- Device : xc7z100ffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity vio_rf_control is - Port ( - clk : in STD_LOGIC; - probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 ); - probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); - probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 ); - probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 ); - probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - -end vio_rf_control; - -architecture stub of vio_rf_control is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]"; -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; -begin -end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/hdl/vio_v3_0_20_vio_include.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/hdl/vio_v3_0_20_vio_include.v deleted file mode 100644 index 0673f57f..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/hdl/vio_v3_0_20_vio_include.v +++ /dev/null @@ -1,283 +0,0 @@ -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) -`pragma protect key_block -GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx -XWe4lBDDrw== - -`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) -`pragma protect key_block -rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH -9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c -eVhT3XSIJDvufMyiJUc= - -`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit 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bytes = 256) -`pragma protect key_block -FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v -ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX -cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC -xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa -draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg== - -`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) -`pragma protect key_block -ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv -j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO -R19uHYIhWP+7IpmjTiQ= - -`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) 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index d9ec5846..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/sim/vio_rf_test.v +++ /dev/null @@ -1,82 +0,0 @@ -// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. -`timescale 1ns / 1ps -module vio_rf_test ( -clk, - -probe_out0, -probe_out1, -probe_out2, -probe_out3, -probe_out4, -probe_out5, -probe_out6, -probe_out7, -probe_out8, -probe_out9, -probe_out10, -probe_out11 -); - -input clk; - -output reg [0 : 0] probe_out0 = 'h0 ; -output reg [7 : 0] probe_out1 = 'h1f ; -output reg [7 : 0] probe_out2 = 'h1f ; -output reg [31 : 0] probe_out3 = 'h003A9800 ; -output reg [0 : 0] probe_out4 = 'h0 ; -output reg [11 : 0] probe_out5 = 'h3E8 ; -output reg [11 : 0] probe_out6 = 'h5DC ; -output reg [31 : 0] probe_out7 = 'h00004800 ; -output reg [31 : 0] probe_out8 = 'h000000C0 ; -output reg [63 : 0] probe_out9 = 'h0000000000009600 ; -output reg [4 : 0] probe_out10 = 'h10 ; -output reg [0 : 0] probe_out11 = 'h0 ; - - -endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.v deleted file mode 100644 index b0f9aad4..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:5c56114c4d1dbd4de738da259f25557427b35cb18dfeb59dda5bf2598412b05e -size 477028 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.vhdl deleted file mode 100644 index 0ffb41e3..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:0d14ce253bc7bd29c3d5ba48eb5bde1db77a4576966d51a7f7133d0cfa5da73e -size 802152 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.vhdl deleted file mode 100644 index 290eaedb..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.vhdl +++ /dev/null @@ -1,42 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Thu May 18 12:54:39 2023 --- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl --- Design : vio_rf_test --- Purpose : Stub declaration of top-level module interface --- Device : xc7z100ffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity vio_rf_test is - Port ( - clk : in STD_LOGIC; - probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); - probe_out2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out7 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out8 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out9 : out STD_LOGIC_VECTOR ( 63 downto 0 ); - probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 ); - probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - -end vio_rf_test; - -architecture stub of vio_rf_test is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]"; -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; -begin -end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/README.txt index 329d7e8b..2088b06e 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/compile.do index 93bccf0a..34a9ef3c 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/compile.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/compile.do @@ -8,11 +8,11 @@ vmap xil_defaultlib activehdl/xil_defaultlib vmap xpm activehdl/xpm vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ "../../../ip/ila_rf_test/sim/ila_rf_test.v" \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/file_info.txt index b42182bb..4aee3904 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/file_info.txt @@ -1,5 +1,5 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" -xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/ila_rf_test.sh index ef0405c1..adcf6ab8 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/ila_rf_test.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/ila_rf_test.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/README.txt index a417301d..88da984b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/file_info.txt index b42182bb..4aee3904 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/file_info.txt @@ -1,5 +1,5 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" -xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/ila_rf_test.sh index b28aaf5f..8ac2ca95 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/ila_rf_test.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/ila_rf_test.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/run.f index 858d1c03..174238dc 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/run.f +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/run.f @@ -1,9 +1,9 @@ -makelib ies_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib ies_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib ies_lib/xil_defaultlib \ "../../../ip/ila_rf_test/sim/ila_rf_test.v" \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/README.txt index 329d7e8b..2088b06e 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/compile.do index 9f6d2b3d..79e9fe53 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/compile.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/compile.do @@ -2,13 +2,21 @@ vlib modelsim_lib/work vlib modelsim_lib/msim vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ "../../../ip/ila_rf_test/sim/ila_rf_test.v" \ - vlog -work xil_defaultlib \ "glbl.v" diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/file_info.txt index bd70b315..4aee3904 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/file_info.txt @@ -1,2 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/ila_rf_test.sh index 74f64123..23372aa2 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/ila_rf_test.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/ila_rf_test.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -95,10 +95,11 @@ setup() copy_setup_file() { file="modelsim.ini" - if [[ ($1 != "") ]]; then + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then lib_map_path="$1" else - lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/simulate.do index fc7771fc..b350d998 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/simulate.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/simulate.do @@ -1,7 +1,7 @@ onbreak {quit -f} onerror {quit -f} -vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.ila_rf_test xil_defaultlib.glbl +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.ila_rf_test xil_defaultlib.glbl do {wave.do} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/README.txt index 329d7e8b..2088b06e 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/compile.do index 52ed87f9..04f4907b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/compile.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/compile.do @@ -8,11 +8,11 @@ vmap xil_defaultlib questa_lib/msim/xil_defaultlib vmap xpm questa_lib/msim/xpm vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ "../../../ip/ila_rf_test/sim/ila_rf_test.v" \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/file_info.txt index b42182bb..4aee3904 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/file_info.txt @@ -1,5 +1,5 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" -xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/ila_rf_test.sh index 6136d58d..208dbd46 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/ila_rf_test.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/ila_rf_test.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -102,10 +102,9 @@ setup() copy_setup_file() { file="modelsim.ini" + lib_map_path="" if [[ ($1 != "") ]]; then lib_map_path="$1" - else - lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/README.txt index 329d7e8b..2088b06e 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/compile.do index df3ecb23..c701178f 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/compile.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/compile.do @@ -8,11 +8,11 @@ vmap xil_defaultlib riviera/xil_defaultlib vmap xpm riviera/xpm vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ "../../../ip/ila_rf_test/sim/ila_rf_test.v" \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/file_info.txt index b42182bb..4aee3904 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/file_info.txt @@ -1,5 +1,5 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" -xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/ila_rf_test.sh index a7cb2d74..68545b4e 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/ila_rf_test.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/ila_rf_test.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -93,10 +93,9 @@ setup() map_setup_file() { file="library.cfg" + lib_map_path="" if [[ ($1 != "") ]]; then lib_map_path="$1" - else - lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/README.txt index 329d7e8b..2088b06e 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/file_info.txt index bd70b315..4aee3904 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/file_info.txt @@ -1,2 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/ila_rf_test.sh index 285de8ba..a4ad0676 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/ila_rf_test.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/ila_rf_test.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -48,7 +48,7 @@ vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" vcs_sim_opts="-ucli -licqueue -l simulate.log" # Design libraries -design_libs=(xil_defaultlib) +design_libs=(xil_defaultlib xpm) # Simulation root library directory sim_lib_dir="vcs_lib" @@ -70,6 +70,15 @@ run() compile() { # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/ila_rf_test/hdl/verilog" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_rf_test/hdl/verilog" \ "$ref_dir/../../../ip/ila_rf_test/sim/ila_rf_test.v" \ 2>&1 | tee -a vlogan.log @@ -138,10 +147,9 @@ create_lib_mappings() touch $file + lib_map_path="" if [[ ($1 != "") ]]; then lib_map_path="$1" - else - lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" fi for (( i=0; i<${#design_libs[*]}; i++ )); do diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/README.txt index a417301d..88da984b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/file_info.txt index b42182bb..4aee3904 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/file_info.txt @@ -1,5 +1,5 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" -xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/ila_rf_test.sh index 1008c3bc..e9cf5fce 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/ila_rf_test.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/ila_rf_test.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/run.f index 6e8625bd..c9e1eb1e 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/run.f +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/run.f @@ -1,9 +1,9 @@ -makelib xcelium_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib xcelium_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib xcelium_lib/xil_defaultlib \ "../../../ip/ila_rf_test/sim/ila_rf_test.v" \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/README.txt index 329d7e8b..2088b06e 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/ila_rf_test.sh index 69fb6008..3ba48e90 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/ila_rf_test.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/ila_rf_test.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -22,7 +22,7 @@ #********************************************************************************************************* # Command line options -xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0 xvlog_opts="--relax" @@ -92,7 +92,7 @@ setup() copy_setup_file() { file="xsim.ini" - lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim" if [[ ($1 != "") ]]; then lib_map_path="$1" fi diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/README.txt similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/README.txt rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/README.txt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/README.txt similarity index 87% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/README.txt rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/README.txt index cf9b236c..a4eb3478 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./vio_rf_control.sh +./vio_RF_control.sh This command will launch the 'compile', 'elaborate' and 'simulate' functions implemented in the script file for the 3-step flow. These functions are called @@ -26,16 +26,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_control.sh' script. +'-reset_run' switch to the './vio_RF_control.sh' script. -./vio_rf_control.sh -reset_run +./vio_RF_control.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./vio_rf_control.sh -noclean_files +./vio_RF_control.sh -noclean_files -For more information on the script, please type './vio_rf_control.sh -help'. +For more information on the script, please type './vio_RF_control.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/compile.do new file mode 100644 index 00000000..5eabe183 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \ +"../../../ip/vio_RF_control/sim/vio_RF_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/file_info.txt new file mode 100644 index 00000000..61c3b6eb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/glbl.v similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/glbl.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/simulate.do similarity index 59% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/simulate.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/simulate.do index ffcd11d6..3e367b3f 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/simulate.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/simulate.do @@ -1,14 +1,14 @@ onbreak {quit -force} onerror {quit -force} -asim -t 1ps +access +r +m+vio_rf_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_control xil_defaultlib.glbl +asim -t 1ps +access +r +m+vio_RF_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_RF_control xil_defaultlib.glbl do {wave.do} view wave view structure -do {vio_rf_control.udo} +do {vio_RF_control.udo} run -all diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/vio_RF_control.sh similarity index 85% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.sh rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/vio_RF_control.sh index 57722fc1..e2cb0877 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/vio_RF_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_rf_control.sh +# Filename : vio_RF_control.sh # Simulator : Aldec Active-HDL Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_rf_control.sh [-help] -# usage: vio_rf_control.sh [-lib_map_path] -# usage: vio_rf_control.sh [-noclean_files] -# usage: vio_rf_control.sh [-reset_run] +# usage: vio_RF_control.sh [-help] +# usage: vio_RF_control.sh [-lib_map_path] +# usage: vio_RF_control.sh [-noclean_files] +# usage: vio_RF_control.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# executing this script. Please type 'vio_RF_control.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -66,7 +66,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi map_setup_file $2 @@ -121,7 +121,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi @@ -133,10 +133,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_rf_control.sh [-help]\n\ -Usage: vio_rf_control.sh [-lib_map_path]\n\ -Usage: vio_rf_control.sh [-reset_run]\n\ -Usage: vio_rf_control.sh [-noclean_files]\n\n\ + msg="Usage: vio_RF_control.sh [-help]\n\ +Usage: vio_RF_control.sh [-lib_map_path]\n\ +Usage: vio_RF_control.sh [-reset_run]\n\ +Usage: vio_RF_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/vio_RF_control.udo similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.udo rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/vio_RF_control.udo diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/wave.do similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/wave.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/wave.do diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/README.txt similarity index 87% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/README.txt rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/README.txt index 5f27dcbd..aae61794 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./vio_rf_control.sh +./vio_RF_control.sh This command will launch the 'execute' function for the single-step flow. This function is called from the main 'run' function in the script file. @@ -25,16 +25,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_control.sh' script. +'-reset_run' switch to the './vio_RF_control.sh' script. -./vio_rf_control.sh -reset_run +./vio_RF_control.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./vio_rf_control.sh -noclean_files +./vio_RF_control.sh -noclean_files -For more information on the script, please type './vio_rf_control.sh -help'. +For more information on the script, please type './vio_RF_control.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/file_info.txt new file mode 100644 index 00000000..61c3b6eb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/glbl.v similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/glbl.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/run.f new file mode 100644 index 00000000..77ab7c15 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_RF_control/sim/vio_RF_control.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/vio_RF_control.sh similarity index 85% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/vio_rf_control.sh rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/vio_RF_control.sh index 58e0866d..751d965d 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/vio_rf_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/vio_RF_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_rf_control.sh +# Filename : vio_RF_control.sh # Simulator : Cadence Incisive Enterprise Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_rf_control.sh [-help] -# usage: vio_rf_control.sh [-lib_map_path] -# usage: vio_rf_control.sh [-noclean_files] -# usage: vio_rf_control.sh [-reset_run] +# usage: vio_RF_control.sh [-help] +# usage: vio_RF_control.sh [-lib_map_path] +# usage: vio_RF_control.sh [-noclean_files] +# usage: vio_RF_control.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# executing this script. Please type 'vio_RF_control.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm) sim_lib_dir="ies_lib" # Script info -echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,12 +73,12 @@ execute() -reflib "$ref_lib_dir/secureip:secureip" \ -reflib "$ref_lib_dir/unimacro:unimacro" \ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.vio_rf_control \ + -top xil_defaultlib.vio_RF_control \ -f run.f \ -top glbl \ glbl.v \ - +incdir+"../../../ip/vio_rf_control/hdl/verilog" \ - +incdir+"../../../ip/vio_rf_control/hdl" + +incdir+"../../../ip/vio_RF_control/hdl/verilog" \ + +incdir+"../../../ip/vio_RF_control/hdl" } # STEP: setup @@ -87,7 +87,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 else ref_lib_dir=$2 @@ -146,7 +146,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi @@ -158,10 +158,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_rf_control.sh [-help]\n\ -Usage: vio_rf_control.sh [-lib_map_path]\n\ -Usage: vio_rf_control.sh [-reset_run]\n\ -Usage: vio_rf_control.sh [-noclean_files]\n\n\ + msg="Usage: vio_RF_control.sh [-help]\n\ +Usage: vio_RF_control.sh [-lib_map_path]\n\ +Usage: vio_RF_control.sh [-reset_run]\n\ +Usage: vio_RF_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/README.txt similarity index 87% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/README.txt rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/README.txt index cf9b236c..a4eb3478 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./vio_rf_control.sh +./vio_RF_control.sh This command will launch the 'compile', 'elaborate' and 'simulate' functions implemented in the script file for the 3-step flow. These functions are called @@ -26,16 +26,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_control.sh' script. +'-reset_run' switch to the './vio_RF_control.sh' script. -./vio_rf_control.sh -reset_run +./vio_RF_control.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./vio_rf_control.sh -noclean_files +./vio_RF_control.sh -noclean_files -For more information on the script, please type './vio_rf_control.sh -help'. +For more information on the script, please type './vio_RF_control.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/compile.do similarity index 50% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/compile.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/compile.do index d2f17c3d..34b3265c 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/compile.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/compile.do @@ -5,8 +5,8 @@ vlib modelsim_lib/msim/xil_defaultlib vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib -vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ -"../../../ip/vio_rf_test/sim/vio_rf_test.v" \ +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \ +"../../../ip/vio_RF_control/sim/vio_RF_control.v" \ vlog -work xil_defaultlib \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/file_info.txt new file mode 100644 index 00000000..21f6b746 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/file_info.txt @@ -0,0 +1,2 @@ +vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/glbl.v similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/glbl.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/simulate.do similarity index 79% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/simulate.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/simulate.do index 476df0a8..e13f99d2 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/simulate.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/simulate.do @@ -1,7 +1,7 @@ onbreak {quit -f} onerror {quit -f} -vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_rf_test xil_defaultlib.glbl +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_RF_control xil_defaultlib.glbl do {wave.do} @@ -9,7 +9,7 @@ view wave view structure view signals -do {vio_rf_test.udo} +do {vio_RF_control.udo} run -all diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/vio_RF_control.sh similarity index 86% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.sh rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/vio_RF_control.sh index b1fbd79c..1e9ea471 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/vio_RF_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_rf_control.sh +# Filename : vio_RF_control.sh # Simulator : Mentor Graphics ModelSim Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_rf_control.sh [-help] -# usage: vio_rf_control.sh [-lib_map_path] -# usage: vio_rf_control.sh [-noclean_files] -# usage: vio_rf_control.sh [-reset_run] +# usage: vio_RF_control.sh [-help] +# usage: vio_RF_control.sh [-lib_map_path] +# usage: vio_RF_control.sh [-noclean_files] +# usage: vio_RF_control.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# executing this script. Please type 'vio_RF_control.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -66,7 +66,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi copy_setup_file $2 @@ -136,7 +136,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi @@ -148,10 +148,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_rf_control.sh [-help]\n\ -Usage: vio_rf_control.sh [-lib_map_path]\n\ -Usage: vio_rf_control.sh [-reset_run]\n\ -Usage: vio_rf_control.sh [-noclean_files]\n\n\ + msg="Usage: vio_RF_control.sh [-help]\n\ +Usage: vio_RF_control.sh [-lib_map_path]\n\ +Usage: vio_RF_control.sh [-reset_run]\n\ +Usage: vio_RF_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/vio_RF_control.udo similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.udo rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/vio_RF_control.udo diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/wave.do similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/wave.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/wave.do diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/README.txt similarity index 87% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/README.txt rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/README.txt index cf9b236c..a4eb3478 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./vio_rf_control.sh +./vio_RF_control.sh This command will launch the 'compile', 'elaborate' and 'simulate' functions implemented in the script file for the 3-step flow. These functions are called @@ -26,16 +26,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_control.sh' script. +'-reset_run' switch to the './vio_RF_control.sh' script. -./vio_rf_control.sh -reset_run +./vio_RF_control.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./vio_rf_control.sh -noclean_files +./vio_RF_control.sh -noclean_files -For more information on the script, please type './vio_rf_control.sh -help'. +For more information on the script, please type './vio_RF_control.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/compile.do new file mode 100644 index 00000000..2b64e932 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \ +"../../../ip/vio_RF_control/sim/vio_RF_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/elaborate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/elaborate.do similarity index 66% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/elaborate.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/elaborate.do index 904131c9..7d97b47a 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/elaborate.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/elaborate.do @@ -1 +1 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_rf_control xil_defaultlib.glbl -o vio_rf_control_opt +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_RF_control xil_defaultlib.glbl -o vio_RF_control_opt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/file_info.txt new file mode 100644 index 00000000..61c3b6eb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/glbl.v similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/glbl.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/simulate.do similarity index 60% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/simulate.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/simulate.do index 71d9432f..9f89099b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/simulate.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/simulate.do @@ -1,7 +1,7 @@ onbreak {quit -f} onerror {quit -f} -vsim -t 1ps -lib xil_defaultlib vio_rf_test_opt +vsim -t 1ps -lib xil_defaultlib vio_RF_control_opt do {wave.do} @@ -9,7 +9,7 @@ view wave view structure view signals -do {vio_rf_test.udo} +do {vio_RF_control.udo} run -all diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/vio_RF_control.sh similarity index 87% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.sh rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/vio_RF_control.sh index c459e240..2474d59a 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/vio_RF_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_rf_control.sh +# Filename : vio_RF_control.sh # Simulator : Mentor Graphics Questa Advanced Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_rf_control.sh [-help] -# usage: vio_rf_control.sh [-lib_map_path] -# usage: vio_rf_control.sh [-noclean_files] -# usage: vio_rf_control.sh [-reset_run] +# usage: vio_RF_control.sh [-help] +# usage: vio_RF_control.sh [-lib_map_path] +# usage: vio_RF_control.sh [-noclean_files] +# usage: vio_RF_control.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# executing this script. Please type 'vio_RF_control.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,7 +73,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi copy_setup_file $2 @@ -143,7 +143,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi @@ -155,10 +155,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_rf_control.sh [-help]\n\ -Usage: vio_rf_control.sh [-lib_map_path]\n\ -Usage: vio_rf_control.sh [-reset_run]\n\ -Usage: vio_rf_control.sh [-noclean_files]\n\n\ + msg="Usage: vio_RF_control.sh [-help]\n\ +Usage: vio_RF_control.sh [-lib_map_path]\n\ +Usage: vio_RF_control.sh [-reset_run]\n\ +Usage: vio_RF_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/vio_RF_control.udo similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.udo rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/vio_RF_control.udo diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/wave.do similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/wave.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/wave.do diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/README.txt similarity index 87% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/README.txt rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/README.txt index cf9b236c..a4eb3478 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./vio_rf_control.sh +./vio_RF_control.sh This command will launch the 'compile', 'elaborate' and 'simulate' functions implemented in the script file for the 3-step flow. These functions are called @@ -26,16 +26,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_control.sh' script. +'-reset_run' switch to the './vio_RF_control.sh' script. -./vio_rf_control.sh -reset_run +./vio_RF_control.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./vio_rf_control.sh -noclean_files +./vio_RF_control.sh -noclean_files -For more information on the script, please type './vio_rf_control.sh -help'. +For more information on the script, please type './vio_RF_control.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/compile.do new file mode 100644 index 00000000..7f2de32b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \ +"../../../ip/vio_RF_control/sim/vio_RF_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/file_info.txt new file mode 100644 index 00000000..61c3b6eb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/glbl.v similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/glbl.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/simulate.do similarity index 59% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/simulate.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/simulate.do index ffcd11d6..3e367b3f 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/simulate.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/simulate.do @@ -1,14 +1,14 @@ onbreak {quit -force} onerror {quit -force} -asim -t 1ps +access +r +m+vio_rf_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_control xil_defaultlib.glbl +asim -t 1ps +access +r +m+vio_RF_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_RF_control xil_defaultlib.glbl do {wave.do} view wave view structure -do {vio_rf_control.udo} +do {vio_RF_control.udo} run -all diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/vio_RF_control.sh similarity index 86% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.sh rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/vio_RF_control.sh index 48413816..3cdb9372 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/vio_RF_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_rf_control.sh +# Filename : vio_RF_control.sh # Simulator : Aldec Riviera-PRO Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_rf_control.sh [-help] -# usage: vio_rf_control.sh [-lib_map_path] -# usage: vio_rf_control.sh [-noclean_files] -# usage: vio_rf_control.sh [-reset_run] +# usage: vio_RF_control.sh [-help] +# usage: vio_RF_control.sh [-lib_map_path] +# usage: vio_RF_control.sh [-noclean_files] +# usage: vio_RF_control.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# executing this script. Please type 'vio_RF_control.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -66,7 +66,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi map_setup_file $2 @@ -122,7 +122,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi @@ -134,10 +134,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_rf_control.sh [-help]\n\ -Usage: vio_rf_control.sh [-lib_map_path]\n\ -Usage: vio_rf_control.sh [-reset_run]\n\ -Usage: vio_rf_control.sh [-noclean_files]\n\n\ + msg="Usage: vio_RF_control.sh [-help]\n\ +Usage: vio_RF_control.sh [-lib_map_path]\n\ +Usage: vio_RF_control.sh [-reset_run]\n\ +Usage: vio_RF_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/vio_RF_control.udo similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.udo rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/vio_RF_control.udo diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/wave.do similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/wave.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/wave.do diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/README.txt new file mode 100644 index 00000000..a4eb3478 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_RF_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_RF_control.sh' script. + +./vio_RF_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_RF_control.sh -noclean_files + +For more information on the script, please type './vio_RF_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/file_info.txt new file mode 100644 index 00000000..21f6b746 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/file_info.txt @@ -0,0 +1,2 @@ +vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/glbl.v similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/glbl.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/simulate.do similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/simulate.do rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/simulate.do diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/vio_RF_control.sh similarity index 83% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/vio_rf_control.sh rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/vio_RF_control.sh index d5e47f1b..49685cc8 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/vio_rf_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/vio_RF_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_rf_control.sh +# Filename : vio_RF_control.sh # Simulator : Synopsys Verilog Compiler Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_rf_control.sh [-help] -# usage: vio_rf_control.sh [-lib_map_path] -# usage: vio_rf_control.sh [-noclean_files] -# usage: vio_rf_control.sh [-reset_run] +# usage: vio_RF_control.sh [-help] +# usage: vio_RF_control.sh [-lib_map_path] +# usage: vio_RF_control.sh [-noclean_files] +# usage: vio_RF_control.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# executing this script. Please type 'vio_RF_control.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib) sim_lib_dir="vcs_lib" # Script info -echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -70,8 +70,8 @@ run() compile() { # Compile design files - vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl" \ - "$ref_dir/../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_RF_control/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_RF_control/hdl" \ + "$ref_dir/../../../ip/vio_RF_control/sim/vio_RF_control.v" \ 2>&1 | tee -a vlogan.log @@ -84,13 +84,13 @@ compile() # RUN_STEP: elaborate() { - vcs $vcs_elab_opts xil_defaultlib.vio_rf_control xil_defaultlib.glbl -o vio_rf_control_simv + vcs $vcs_elab_opts xil_defaultlib.vio_RF_control xil_defaultlib.glbl -o vio_RF_control_simv } # RUN_STEP: simulate() { - ./vio_rf_control_simv $vcs_sim_opts -do simulate.do + ./vio_RF_control_simv $vcs_sim_opts -do simulate.do } # STEP: setup @@ -99,7 +99,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi create_lib_mappings $2 @@ -175,7 +175,7 @@ create_lib_dir() # Delete generated data from the previous run reset_run() { - files_to_remove=(ucli.key vio_rf_control_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_rf_control_simv.daidir) + files_to_remove=(ucli.key vio_RF_control_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_RF_control_simv.daidir) for (( i=0; i<${#files_to_remove[*]}; i++ )); do file="${files_to_remove[i]}" if [[ -e $file ]]; then @@ -190,7 +190,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi @@ -202,10 +202,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_rf_control.sh [-help]\n\ -Usage: vio_rf_control.sh [-lib_map_path]\n\ -Usage: vio_rf_control.sh [-reset_run]\n\ -Usage: vio_rf_control.sh [-noclean_files]\n\n\ + msg="Usage: vio_RF_control.sh [-help]\n\ +Usage: vio_RF_control.sh [-lib_map_path]\n\ +Usage: vio_RF_control.sh [-reset_run]\n\ +Usage: vio_RF_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/README.txt similarity index 87% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/README.txt rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/README.txt index 5f27dcbd..aae61794 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./vio_rf_control.sh +./vio_RF_control.sh This command will launch the 'execute' function for the single-step flow. This function is called from the main 'run' function in the script file. @@ -25,16 +25,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_control.sh' script. +'-reset_run' switch to the './vio_RF_control.sh' script. -./vio_rf_control.sh -reset_run +./vio_RF_control.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./vio_rf_control.sh -noclean_files +./vio_RF_control.sh -noclean_files -For more information on the script, please type './vio_rf_control.sh -help'. +For more information on the script, please type './vio_RF_control.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/file_info.txt new file mode 100644 index 00000000..61c3b6eb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/glbl.v similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/glbl.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/run.f new file mode 100644 index 00000000..98294cbb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_RF_control/sim/vio_RF_control.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/vio_RF_control.sh similarity index 85% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/vio_rf_control.sh rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/vio_RF_control.sh index bc9d642d..b648b8b3 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/vio_rf_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/vio_RF_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_rf_control.sh +# Filename : vio_RF_control.sh # Simulator : Cadence Xcelium Parallel Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_rf_control.sh [-help] -# usage: vio_rf_control.sh [-lib_map_path] -# usage: vio_rf_control.sh [-noclean_files] -# usage: vio_rf_control.sh [-reset_run] +# usage: vio_RF_control.sh [-help] +# usage: vio_RF_control.sh [-lib_map_path] +# usage: vio_RF_control.sh [-noclean_files] +# usage: vio_RF_control.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# executing this script. Please type 'vio_RF_control.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm) sim_lib_dir="xcelium_lib" # Script info -echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,12 +73,12 @@ execute() -reflib "$ref_lib_dir/secureip:secureip" \ -reflib "$ref_lib_dir/unimacro:unimacro" \ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.vio_rf_control \ + -top xil_defaultlib.vio_RF_control \ -f run.f \ -top glbl \ glbl.v \ - +incdir+"../../../ip/vio_rf_control/hdl/verilog" \ - +incdir+"../../../ip/vio_rf_control/hdl" + +incdir+"../../../ip/vio_RF_control/hdl/verilog" \ + +incdir+"../../../ip/vio_RF_control/hdl" } # STEP: setup @@ -87,7 +87,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 else ref_lib_dir=$2 @@ -146,7 +146,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi @@ -158,10 +158,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_rf_control.sh [-help]\n\ -Usage: vio_rf_control.sh [-lib_map_path]\n\ -Usage: vio_rf_control.sh [-reset_run]\n\ -Usage: vio_rf_control.sh [-noclean_files]\n\n\ + msg="Usage: vio_RF_control.sh [-help]\n\ +Usage: vio_RF_control.sh [-lib_map_path]\n\ +Usage: vio_RF_control.sh [-reset_run]\n\ +Usage: vio_RF_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/README.txt new file mode 100644 index 00000000..a4eb3478 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_RF_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_RF_control.sh' script. + +./vio_RF_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_RF_control.sh -noclean_files + +For more information on the script, please type './vio_RF_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/cmd.tcl similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/cmd.tcl rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/cmd.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/file_info.txt new file mode 100644 index 00000000..21f6b746 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/glbl.v similarity index 100% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/glbl.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vio_RF_control.sh similarity index 84% rename from projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vio_rf_control.sh rename to projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vio_RF_control.sh index 4efab4f6..ca3e934e 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vio_rf_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vio_RF_control.sh @@ -2,32 +2,32 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_rf_control.sh +# Filename : vio_RF_control.sh # Simulator : Xilinx Vivado Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_rf_control.sh [-help] -# usage: vio_rf_control.sh [-lib_map_path] -# usage: vio_rf_control.sh [-noclean_files] -# usage: vio_rf_control.sh [-reset_run] +# usage: vio_RF_control.sh [-help] +# usage: vio_RF_control.sh [-lib_map_path] +# usage: vio_RF_control.sh [-noclean_files] +# usage: vio_RF_control.sh [-reset_run] # #********************************************************************************************************* # Command line options -xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0 xvlog_opts="--relax" # Script info -echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -50,13 +50,13 @@ compile() # RUN_STEP: elaborate() { - xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_rf_control xil_defaultlib.vio_rf_control xil_defaultlib.glbl -log elaborate.log + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_RF_control xil_defaultlib.vio_RF_control xil_defaultlib.glbl -log elaborate.log } # RUN_STEP: simulate() { - xsim vio_rf_control -key {Behavioral:sim_1:Functional:vio_rf_control} -tclbatch cmd.tcl -log simulate.log + xsim vio_RF_control -key {Behavioral:sim_1:Functional:vio_RF_control} -tclbatch cmd.tcl -log simulate.log } # STEP: setup @@ -65,7 +65,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi copy_setup_file $2 @@ -92,7 +92,7 @@ setup() copy_setup_file() { file="xsim.ini" - lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim" if [[ ($1 != "") ]]; then lib_map_path="$1" fi @@ -168,7 +168,7 @@ map_local_libs() # Delete generated data from the previous run reset_run() { - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_rf_control.wdb xsim.dir) + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_RF_control.wdb xsim.dir) for (( i=0; i<${#files_to_remove[*]}; i++ )); do file="${files_to_remove[i]}" if [[ -e $file ]]; then @@ -181,7 +181,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n" exit 1 fi @@ -193,10 +193,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_rf_control.sh [-help]\n\ -Usage: vio_rf_control.sh [-lib_map_path]\n\ -Usage: vio_rf_control.sh [-reset_run]\n\ -Usage: vio_rf_control.sh [-noclean_files]\n\n\ + msg="Usage: vio_RF_control.sh [-help]\n\ +Usage: vio_RF_control.sh [-lib_map_path]\n\ +Usage: vio_RF_control.sh [-reset_run]\n\ +Usage: vio_RF_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vlog.prj new file mode 100644 index 00000000..ec7db132 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_RF_control/hdl/verilog" --include "../../../ip/vio_RF_control/hdl" \ +"../../../ip/vio_RF_control/sim/vio_RF_control.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/compile.do deleted file mode 100644 index 192201b2..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/compile.do +++ /dev/null @@ -1,22 +0,0 @@ -vlib work -vlib activehdl - -vlib activehdl/xil_defaultlib -vlib activehdl/xpm - -vmap xil_defaultlib activehdl/xil_defaultlib -vmap xpm activehdl/xpm - -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ -"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/file_info.txt deleted file mode 100644 index 5d1c0b80..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/file_info.txt deleted file mode 100644 index 5d1c0b80..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/run.f deleted file mode 100644 index e4edaabe..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/run.f +++ /dev/null @@ -1,14 +0,0 @@ --makelib ies_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib ies_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - "../../../ip/vio_rf_control/sim/vio_rf_control.v" \ --endlib --makelib ies_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/compile.do deleted file mode 100644 index 747a39e2..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/compile.do +++ /dev/null @@ -1,14 +0,0 @@ -vlib modelsim_lib/work -vlib modelsim_lib/msim - -vlib modelsim_lib/msim/xil_defaultlib - -vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib - -vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ -"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ - - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/file_info.txt deleted file mode 100644 index 6afb6a11..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/simulate.do deleted file mode 100644 index a8dfaf75..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_rf_control xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure -view signals - -do {vio_rf_control.udo} - -run -all - -quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/compile.do deleted file mode 100644 index d50d8c8e..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/compile.do +++ /dev/null @@ -1,22 +0,0 @@ -vlib questa_lib/work -vlib questa_lib/msim - -vlib questa_lib/msim/xil_defaultlib -vlib questa_lib/msim/xpm - -vmap xil_defaultlib questa_lib/msim/xil_defaultlib -vmap xpm questa_lib/msim/xpm - -vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ -"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/file_info.txt deleted file mode 100644 index 5d1c0b80..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/simulate.do deleted file mode 100644 index 5aa3f82e..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -t 1ps -lib xil_defaultlib vio_rf_control_opt - -do {wave.do} - -view wave -view structure -view signals - -do {vio_rf_control.udo} - -run -all - -quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/compile.do deleted file mode 100644 index 72ffdcee..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/compile.do +++ /dev/null @@ -1,22 +0,0 @@ -vlib work -vlib riviera - -vlib riviera/xil_defaultlib -vlib riviera/xpm - -vmap xil_defaultlib riviera/xil_defaultlib -vmap xpm riviera/xpm - -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ -"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/file_info.txt deleted file mode 100644 index 5d1c0b80..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/README.txt deleted file mode 100644 index cf9b236c..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_rf_control.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_control.sh' script. - -./vio_rf_control.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_rf_control.sh -noclean_files - -For more information on the script, please type './vio_rf_control.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/file_info.txt deleted file mode 100644 index 6afb6a11..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/file_info.txt deleted file mode 100644 index 5d1c0b80..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/run.f deleted file mode 100644 index 60d4bd69..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/run.f +++ /dev/null @@ -1,14 +0,0 @@ --makelib xcelium_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib xcelium_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - "../../../ip/vio_rf_control/sim/vio_rf_control.v" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/README.txt deleted file mode 100644 index cf9b236c..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_rf_control.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_control.sh' script. - -./vio_rf_control.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_rf_control.sh -noclean_files - -For more information on the script, please type './vio_rf_control.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/file_info.txt deleted file mode 100644 index 6afb6a11..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vlog.prj deleted file mode 100644 index b28359a7..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vlog.prj +++ /dev/null @@ -1,6 +0,0 @@ -verilog xil_defaultlib --include "../../../ip/vio_rf_control/hdl/verilog" --include "../../../ip/vio_rf_control/hdl" \ -"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ - -verilog xil_defaultlib "glbl.v" - -nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/README.txt deleted file mode 100644 index f3d66c82..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/README.txt +++ /dev/null @@ -1,83 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required -# to simulate the design for a simulator, the directory structure -# and the generated exported files. -# -################################################################################ - -1. Simulate Design - -To simulate design, cd to the simulator directory and execute the script. - -For example:- - -% cd questa -% ./top.sh - -The export simulation flow requires the Xilinx pre-compiled simulation library -components for the target simulator. These components are referred using the -'-lib_map_path' switch. If this switch is specified, then the export simulation -will automatically set this library path in the generated script and update, -copy the simulator setup file(s) in the exported directory. - -If '-lib_map_path' is not specified, then the pre-compiled simulation library -information will not be included in the exported scripts and that may cause -simulation errors when running this script. Alternatively, you can provide the -library information using this switch while executing the generated script. - -For example:- - -% ./top.sh -lib_map_path /design/questa/clibs - -Please refer to the generated script header 'Prerequisite' section for more details. - -2. Directory Structure - -By default, if the -directory switch is not specified, export_simulation will -create the following directory structure:- - -/export_sim/ - -For example, if the current working directory is /tmp/test, export_simulation -will create the following directory path:- - -/tmp/test/export_sim/questa - -If -directory switch is specified, export_simulation will create a simulator -sub-directory under the specified directory path. - -For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' -command will create the following directory:- - -/tmp/test/my_test_area/func_sim/questa - -By default, if -simulator is not specified, export_simulation will create a -simulator sub-directory for each simulator and export the files for each simulator -in this sub-directory respectively. - -IMPORTANT: Please note that the simulation library path must be specified manually -in the generated script for the respective simulator. Please refer to the generated -script header 'Prerequisite' section for more details. - -3. Exported script and files - -Export simulation will create the driver shell script, setup files and copy the -design sources in the output directory path. - -By default, when the -script_name switch is not specified, export_simulation will -create the following script name:- - -.sh (Unix) -When exporting the files for an IP using the -of_objects switch, export_simulation -will create the following script name:- - -.sh (Unix) -Export simulation will create the setup files for the target simulator specified -with the -simulator switch. - -For example, if the target simulator is "ies", export_simulation will create the -'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' -file. - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/README.txt deleted file mode 100644 index 6760b784..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_rf_test.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_test.sh' script. - -./vio_rf_test.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_rf_test.sh -noclean_files - -For more information on the script, please type './vio_rf_test.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/compile.do deleted file mode 100644 index ccd5b864..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/compile.do +++ /dev/null @@ -1,22 +0,0 @@ -vlib work -vlib activehdl - -vlib activehdl/xil_defaultlib -vlib activehdl/xpm - -vmap xil_defaultlib activehdl/xil_defaultlib -vmap xpm activehdl/xpm - -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ -"../../../ip/vio_rf_test/sim/vio_rf_test.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/file_info.txt deleted file mode 100644 index 90af45a6..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/simulate.do deleted file mode 100644 index 19aa03d3..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+vio_rf_test -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_test xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {vio_rf_test.udo} - -run -all - -endsim - -quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/vio_rf_test.sh deleted file mode 100755 index 34dc2659..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/vio_rf_test.sh +++ /dev/null @@ -1,152 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_rf_test.sh -# Simulator : Aldec Active-HDL Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Thu May 18 12:54:23 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_rf_test.sh [-help] -# usage: vio_rf_test.sh [-lib_map_path] -# usage: vio_rf_test.sh [-noclean_files] -# usage: vio_rf_test.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_test.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - lib_map_path="" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_rf_test.sh [-help]\n\ -Usage: vio_rf_test.sh [-lib_map_path]\n\ -Usage: vio_rf_test.sh [-reset_run]\n\ -Usage: vio_rf_test.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/vio_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/vio_rf_test.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/README.txt deleted file mode 100644 index 467b8785..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_rf_test.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_test.sh' script. - -./vio_rf_test.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_rf_test.sh -noclean_files - -For more information on the script, please type './vio_rf_test.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/file_info.txt deleted file mode 100644 index 90af45a6..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/run.f deleted file mode 100644 index e85f930f..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/run.f +++ /dev/null @@ -1,14 +0,0 @@ --makelib ies_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib ies_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - "../../../ip/vio_rf_test/sim/vio_rf_test.v" \ --endlib --makelib ies_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/vio_rf_test.sh deleted file mode 100755 index 99e30094..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/vio_rf_test.sh +++ /dev/null @@ -1,177 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_rf_test.sh -# Simulator : Cadence Incisive Enterprise Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Thu May 18 12:54:23 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_rf_test.sh [-help] -# usage: vio_rf_test.sh [-lib_map_path] -# usage: vio_rf_test.sh [-noclean_files] -# usage: vio_rf_test.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_test.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm) - -# Simulation root library directory -sim_lib_dir="ies_lib" - -# Script info -echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - irun $irun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.vio_rf_test \ - -f run.f \ - -top glbl \ - glbl.v \ - +incdir+"../../../ip/vio_rf_test/hdl/verilog" \ - +incdir+"../../../ip/vio_rf_test/hdl" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_rf_test.sh [-help]\n\ -Usage: vio_rf_test.sh [-lib_map_path]\n\ -Usage: vio_rf_test.sh [-reset_run]\n\ -Usage: vio_rf_test.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/README.txt deleted file mode 100644 index 6760b784..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_rf_test.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_test.sh' script. - -./vio_rf_test.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_rf_test.sh -noclean_files - -For more information on the script, please type './vio_rf_test.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/file_info.txt deleted file mode 100644 index 7d0ff7cd..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/vio_rf_test.sh deleted file mode 100755 index 99640f03..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/vio_rf_test.sh +++ /dev/null @@ -1,167 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_rf_test.sh -# Simulator : Mentor Graphics ModelSim Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Thu May 18 12:54:23 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_rf_test.sh [-help] -# usage: vio_rf_test.sh [-lib_map_path] -# usage: vio_rf_test.sh [-noclean_files] -# usage: vio_rf_test.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_test.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="modelsim_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_rf_test.sh [-help]\n\ -Usage: vio_rf_test.sh [-lib_map_path]\n\ -Usage: vio_rf_test.sh [-reset_run]\n\ -Usage: vio_rf_test.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/vio_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/vio_rf_test.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/README.txt deleted file mode 100644 index 6760b784..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_rf_test.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_test.sh' script. - -./vio_rf_test.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_rf_test.sh -noclean_files - -For more information on the script, please type './vio_rf_test.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/compile.do deleted file mode 100644 index 208a8940..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/compile.do +++ /dev/null @@ -1,22 +0,0 @@ -vlib questa_lib/work -vlib questa_lib/msim - -vlib questa_lib/msim/xil_defaultlib -vlib questa_lib/msim/xpm - -vmap xil_defaultlib questa_lib/msim/xil_defaultlib -vmap xpm questa_lib/msim/xpm - -vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ -"../../../ip/vio_rf_test/sim/vio_rf_test.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/elaborate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/elaborate.do deleted file mode 100644 index a6051f2c..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/elaborate.do +++ /dev/null @@ -1 +0,0 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_rf_test xil_defaultlib.glbl -o vio_rf_test_opt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/file_info.txt deleted file mode 100644 index 90af45a6..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/vio_rf_test.sh deleted file mode 100755 index 784bd298..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/vio_rf_test.sh +++ /dev/null @@ -1,174 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_rf_test.sh -# Simulator : Mentor Graphics Questa Advanced Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Thu May 18 12:54:23 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_rf_test.sh [-help] -# usage: vio_rf_test.sh [-lib_map_path] -# usage: vio_rf_test.sh [-noclean_files] -# usage: vio_rf_test.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_test.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -elaborate() -{ - source elaborate.do 2>&1 | tee -a elaborate.log -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="questa_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_rf_test.sh [-help]\n\ -Usage: vio_rf_test.sh [-lib_map_path]\n\ -Usage: vio_rf_test.sh [-reset_run]\n\ -Usage: vio_rf_test.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/vio_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/vio_rf_test.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/README.txt deleted file mode 100644 index 6760b784..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_rf_test.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_test.sh' script. - -./vio_rf_test.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_rf_test.sh -noclean_files - -For more information on the script, please type './vio_rf_test.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/compile.do deleted file mode 100644 index 1516448e..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/compile.do +++ /dev/null @@ -1,22 +0,0 @@ -vlib work -vlib riviera - -vlib riviera/xil_defaultlib -vlib riviera/xpm - -vmap xil_defaultlib riviera/xil_defaultlib -vmap xpm riviera/xpm - -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ -"../../../ip/vio_rf_test/sim/vio_rf_test.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/file_info.txt deleted file mode 100644 index 90af45a6..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/simulate.do deleted file mode 100644 index 19aa03d3..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+vio_rf_test -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_test xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {vio_rf_test.udo} - -run -all - -endsim - -quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/vio_rf_test.sh deleted file mode 100755 index f6be4aaa..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/vio_rf_test.sh +++ /dev/null @@ -1,153 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_rf_test.sh -# Simulator : Aldec Riviera-PRO Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Thu May 18 12:54:23 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_rf_test.sh [-help] -# usage: vio_rf_test.sh [-lib_map_path] -# usage: vio_rf_test.sh [-noclean_files] -# usage: vio_rf_test.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_test.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_rf_test.sh [-help]\n\ -Usage: vio_rf_test.sh [-lib_map_path]\n\ -Usage: vio_rf_test.sh [-reset_run]\n\ -Usage: vio_rf_test.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/vio_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/vio_rf_test.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/README.txt deleted file mode 100644 index 6760b784..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_rf_test.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_test.sh' script. - -./vio_rf_test.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_rf_test.sh -noclean_files - -For more information on the script, please type './vio_rf_test.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/file_info.txt deleted file mode 100644 index 7d0ff7cd..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/simulate.do deleted file mode 100644 index 58afc787..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/simulate.do +++ /dev/null @@ -1,2 +0,0 @@ -run -quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/vio_rf_test.sh deleted file mode 100755 index eaa918ef..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/vio_rf_test.sh +++ /dev/null @@ -1,221 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_rf_test.sh -# Simulator : Synopsys Verilog Compiler Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Thu May 18 12:54:23 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_rf_test.sh [-help] -# usage: vio_rf_test.sh [-lib_map_path] -# usage: vio_rf_test.sh [-noclean_files] -# usage: vio_rf_test.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_test.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Command line options -vlogan_opts="-full64" -vhdlan_opts="-full64" -vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" -vcs_sim_opts="-ucli -licqueue -l simulate.log" - -# Design libraries -design_libs=(xil_defaultlib) - -# Simulation root library directory -sim_lib_dir="vcs_lib" - -# Script info -echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_rf_test/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_rf_test/hdl" \ - "$ref_dir/../../../ip/vio_rf_test/sim/vio_rf_test.v" \ - 2>&1 | tee -a vlogan.log - - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - glbl.v \ - 2>&1 | tee -a vlogan.log - -} - -# RUN_STEP: -elaborate() -{ - vcs $vcs_elab_opts xil_defaultlib.vio_rf_test xil_defaultlib.glbl -o vio_rf_test_simv -} - -# RUN_STEP: -simulate() -{ - ./vio_rf_test_simv $vcs_sim_opts -do simulate.do -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - create_lib_mappings $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - create_lib_mappings $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Define design library mappings -create_lib_mappings() -{ - file="synopsys_sim.setup" - if [[ -e $file ]]; then - if [[ ($1 == "") ]]; then - return - else - rm -rf $file - fi - fi - - touch $file - - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - mapping="$lib:$sim_lib_dir/$lib" - echo $mapping >> $file - done - - if [[ ($lib_map_path != "") ]]; then - incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" - echo $incl_ref >> $file - fi -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ucli.key vio_rf_test_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_rf_test_simv.daidir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_rf_test.sh [-help]\n\ -Usage: vio_rf_test.sh [-lib_map_path]\n\ -Usage: vio_rf_test.sh [-reset_run]\n\ -Usage: vio_rf_test.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/README.txt deleted file mode 100644 index 467b8785..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_rf_test.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_test.sh' script. - -./vio_rf_test.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_rf_test.sh -noclean_files - -For more information on the script, please type './vio_rf_test.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/file_info.txt deleted file mode 100644 index 90af45a6..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/run.f deleted file mode 100644 index 4ca48e89..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/run.f +++ /dev/null @@ -1,14 +0,0 @@ --makelib xcelium_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib xcelium_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - "../../../ip/vio_rf_test/sim/vio_rf_test.v" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/vio_rf_test.sh deleted file mode 100755 index eec41381..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/vio_rf_test.sh +++ /dev/null @@ -1,177 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_rf_test.sh -# Simulator : Cadence Xcelium Parallel Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Thu May 18 12:54:23 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_rf_test.sh [-help] -# usage: vio_rf_test.sh [-lib_map_path] -# usage: vio_rf_test.sh [-noclean_files] -# usage: vio_rf_test.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_rf_test.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm) - -# Simulation root library directory -sim_lib_dir="xcelium_lib" - -# Script info -echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - xrun $xrun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.vio_rf_test \ - -f run.f \ - -top glbl \ - glbl.v \ - +incdir+"../../../ip/vio_rf_test/hdl/verilog" \ - +incdir+"../../../ip/vio_rf_test/hdl" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_rf_test.sh [-help]\n\ -Usage: vio_rf_test.sh [-lib_map_path]\n\ -Usage: vio_rf_test.sh [-reset_run]\n\ -Usage: vio_rf_test.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/README.txt deleted file mode 100644 index 6760b784..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_rf_test.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_rf_test.sh' script. - -./vio_rf_test.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_rf_test.sh -noclean_files - -For more information on the script, please type './vio_rf_test.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/cmd.tcl deleted file mode 100644 index eef7a0f0..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/cmd.tcl +++ /dev/null @@ -1,12 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run -all -quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/file_info.txt deleted file mode 100644 index 7d0ff7cd..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vio_rf_test.sh deleted file mode 100755 index 12529a4f..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vio_rf_test.sh +++ /dev/null @@ -1,212 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_rf_test.sh -# Simulator : Xilinx Vivado Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Thu May 18 12:54:23 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_rf_test.sh [-help] -# usage: vio_rf_test.sh [-lib_map_path] -# usage: vio_rf_test.sh [-noclean_files] -# usage: vio_rf_test.sh [-reset_run] -# -#********************************************************************************************************* - -# Command line options -xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 -xvlog_opts="--relax" - - -# Script info -echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log - -} - -# RUN_STEP: -elaborate() -{ - xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_rf_test xil_defaultlib.vio_rf_test xil_defaultlib.glbl -log elaborate.log -} - -# RUN_STEP: -simulate() -{ - xsim vio_rf_test -key {Behavioral:sim_1:Functional:vio_rf_test} -tclbatch cmd.tcl -log simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Copy xsim.ini file -copy_setup_file() -{ - file="xsim.ini" - lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - cp $src_file . - fi - - # Map local design libraries to xsim.ini - map_local_libs - - fi -} - -# Map local design libraries -map_local_libs() -{ - updated_mappings=() - local_mappings=() - - # Local design libraries - local_libs=() - - if [[ 0 == ${#local_libs[@]} ]]; then - return - fi - - file="xsim.ini" - file_backup="xsim.ini.bak" - - if [[ -e $file ]]; then - rm -f $file_backup - # Create a backup copy of the xsim.ini file - cp $file $file_backup - # Read libraries from backup file and search in local library collection - while read -r line - do - IN=$line - # Split mapping entry with '=' delimiter to fetch library name and mapping - read lib_name mapping <<<$(IFS="="; echo $IN) - # If local library found, then construct the local mapping and add to local mapping collection - if `echo ${local_libs[@]} | grep -wq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - local_mappings+=("$lib_name") - fi - # Add to updated library mapping collection - updated_mappings+=("$line") - done < "$file_backup" - # Append local libraries not found originally from xsim.ini - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - updated_mappings+=("$line") - fi - done - # Write updated mappings in xsim.ini - rm -f $file - for (( i=0; i<${#updated_mappings[*]}; i++ )); do - lib_name="${updated_mappings[i]}" - echo $lib_name >> $file - done - else - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - mapping="$lib_name=xsim.dir/$lib_name" - echo $mapping >> $file - done - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_rf_test.wdb xsim.dir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_rf_test.sh [-help]\n\ -Usage: vio_rf_test.sh [-lib_map_path]\n\ -Usage: vio_rf_test.sh [-reset_run]\n\ -Usage: vio_rf_test.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vlog.prj deleted file mode 100644 index 4d5e02ee..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vlog.prj +++ /dev/null @@ -1,6 +0,0 @@ -verilog xil_defaultlib --include "../../../ip/vio_rf_test/hdl/verilog" --include "../../../ip/vio_rf_test/hdl" \ -"../../../ip/vio_rf_test/sim/vio_rf_test.v" \ - -verilog xil_defaultlib "glbl.v" - -nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index c0228156..c9f87a9b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,11 +1,11 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3231:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3234:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e6d656e755f72657365745f616e645f67656e65726174655f6f75747075745f70726f6475637473:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3631:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3638:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686a66696c6563686f6f73657268656c706572735f6a756d705f746f5f726563656e745f70726f6a6563745f6469726563746f7279:33:00:00 @@ -21,17 +21,17 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f696e666f726d6174696f6e5f6d65737361676573:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e6577697070726f6a65637477697a6172645f69705f6c6f636174696f6e:31:00:00 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--git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf index 88b59d6e..5a44be7b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -1,10 +1,10 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:37:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:38:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:35:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:32:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:36:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:37:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:32:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:38:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3131:00:00 -eof:4015402791 +eof:2683708577 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc index 4e6ebcf8..24316b6b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:10 +6d6f64655f636f756e7465727c4755494d6f6465:11 eof: diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index 5e476161..a8d96beb 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,23 +17,23 @@ This means code written to parse this file will need to be revisited each subseq - + - - + + - + - + - - - + + + @@ -49,24 +49,24 @@ This means code written to parse this file will need to be revisited each subseq - + - - + + - - + + - + - + - +
diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.vivado.begin.rst deleted file mode 100644 index 276b0a90..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.js deleted file mode 100755 index 3e83de11..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.sh deleted file mode 100755 index f679f2e8..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc deleted file mode 100644 index b0ee3d71..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc +++ /dev/null @@ -1,32 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci -# IP: The module: 'ila_rf_test' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila_impl.xdc -# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila.xdc -# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# IP: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci -# IP: The module: 'ila_rf_test' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila_impl.xdc -# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila.xdc -# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/gen_run.xml deleted file mode 100644 index edd4ab0b..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/gen_run.xml +++ /dev/null @@ -1,64 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/htr.txt deleted file mode 100644 index e6ad1c38..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -# -# Vivado(TM) -# htr.txt: a Vivado-generated description of how-to-repeat the -# the basic steps of a run. Note that runme.bat/sh needs -# to be invoked for Vivado to track run status. -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -vivado -log ila_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_test.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp deleted file mode 100644 index 4fb538ac..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:48cb571da4d59aee5fa06a02e4b28dec6359bb3021537818e7565b5a09633ff6 -size 752324 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.tcl deleted file mode 100644 index 5864a4fd..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.tcl +++ /dev/null @@ -1,159 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin -set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7z100ffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci -set_property used_in_synthesis false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila_impl.xdc] -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila_impl.xdc] -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila.xdc] -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test_ooc.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1 -new_name ila_rf_test -ip [get_ips ila_rf_test]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top ila_rf_test -part xc7z100ffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix ila_rf_test_ ila_rf_test.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_test_stub.v - lappend ipCachedFiles ila_rf_test_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_test_stub.vhdl - lappend ipCachedFiles ila_rf_test_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_test_sim_netlist.v - lappend ipCachedFiles ila_rf_test_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_test_sim_netlist.vhdl - lappend ipCachedFiles ila_rf_test_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp ila_rf_test.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips ila_rf_test] -} - -rename_ref -prefix_all ila_rf_test_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef ila_rf_test.dcp -create_report "ila_rf_test_synth_1_synth_report_utilization_0" "report_utilization -file ila_rf_test_utilization_synth.rpt -pb ila_rf_test_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci] - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.vds b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.vds deleted file mode 100644 index 6d2a9a3c..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.vds +++ /dev/null @@ -1,1430 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu May 18 12:54:22 2023 -# Process ID: 520461 -# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1 -# Command line: vivado -log ila_rf_test.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_test.tcl -# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.vds -# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/vivado.jou -#----------------------------------------------------------- -source ila_rf_test.tcl -notrace -Command: synth_design -top ila_rf_test -part xc7z100ffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' -INFO: [Device 21-403] Loading part xc7z100ffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 520729 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1882.547 ; gain = 161.719 ; free physical = 558 ; free virtual = 47853 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'ila_rf_test' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/synth/ila_rf_test.v:84] -INFO: [Synth 8-6157] synthesizing module 'CFGLUT5' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] -INFO: [Synth 8-6155] done synthesizing module 'CFGLUT5' (8#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] -INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] -INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (9#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] -INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] -INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (19#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] -INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] -INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (21#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] -INFO: [Synth 8-6157] synthesizing module 'SRLC16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] -INFO: [Synth 8-6155] done synthesizing module 'SRLC16E' (23#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] -INFO: [Synth 8-6157] synthesizing module 'FDRE' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] -INFO: [Synth 8-6155] done synthesizing module 'FDRE' (28#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] -WARNING: [Synth 8-7023] instance 'inst' of module 'ila_v6_2_9_ila' has 1033 connections declared, but only 1027 given [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/synth/ila_rf_test.v:3227] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity ila_rf_test does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/synth/ila_rf_test.v:116] -INFO: [Synth 8-6155] done synthesizing module 'ila_rf_test' (46#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/synth/ila_rf_test.v:84] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port REGCEA -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port WEB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[4] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port REGCEA -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port WEB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[4] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port REGCEA -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port WEB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[4] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port REGCEA -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port WEB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[4] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port RSTA[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEA[3] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEA[2] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEA[1] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port RSTB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[32] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[31] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[30] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[29] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[28] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[27] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[26] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[25] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[24] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[23] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[22] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[21] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[20] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[19] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[18] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[17] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[16] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[15] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[14] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[13] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[12] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 2233.242 ; gain = 512.414 ; free physical = 1624 ; free virtual = 48717 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 2233.242 ; gain = 512.414 ; free physical = 1639 ; free virtual = 48731 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 2233.242 ; gain = 512.414 ; free physical = 1639 ; free virtual = 48731 ---------------------------------------------------------------------------------- -INFO: [Netlist 29-17] Analyzing 132 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test_ooc.xdc] for cell 'inst' -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test_ooc.xdc] for cell 'inst' -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila.xdc] for cell 'inst' -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila.xdc] for cell 'inst' -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2329.086 ; gain = 0.000 ; free physical = 1573 ; free virtual = 48668 -INFO: [Project 1-111] Unisim Transformation Summary: - A total of 94 instances were transformed. - CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 80 instances - CFGLUT5 => SRLC32E: 14 instances - -Constraint Validation Runtime : Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2329.086 ; gain = 0.000 ; free physical = 1572 ; free virtual = 48667 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:38 ; elapsed = 00:00:49 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1676 ; free virtual = 48772 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7z100ffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:38 ; elapsed = 00:00:49 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1676 ; free virtual = 48772 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for inst. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:49 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1676 ; free virtual = 48772 ---------------------------------------------------------------------------------- -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1672 ; free virtual = 48769 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Adders : - 2 Input 12 Bit Adders := 1 - 2 Input 9 Bit Adders := 1 - 2 Input 7 Bit Adders := 2 - 2 Input 6 Bit Adders := 1 - 2 Input 4 Bit Adders := 12 - 2 Input 2 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 26 - 2 Input 1 Bit XORs := 4 -+---Registers : - 1024 Bit Registers := 2 - 128 Bit Registers := 1 - 48 Bit Registers := 1 - 33 Bit Registers := 2 - 32 Bit Registers := 9 - 17 Bit Registers := 2 - 16 Bit Registers := 109 - 12 Bit Registers := 11 - 10 Bit Registers := 1 - 9 Bit Registers := 1 - 7 Bit Registers := 3 - 6 Bit Registers := 2 - 4 Bit Registers := 14 - 2 Bit Registers := 6 - 1 Bit Registers := 159 -+---Muxes : - 2 Input 32 Bit Muxes := 1 - 2 Input 16 Bit Muxes := 21 - 4 Input 16 Bit Muxes := 1 - 3 Input 16 Bit Muxes := 2 - 8 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 12 - 3 Input 15 Bit Muxes := 1 - 8 Input 12 Bit Muxes := 1 - 3 Input 7 Bit Muxes := 1 - 8 Input 7 Bit Muxes := 1 - 2 Input 6 Bit Muxes := 4 - 2 Input 5 Bit Muxes := 2 - 5 Input 4 Bit Muxes := 12 - 2 Input 4 Bit Muxes := 37 - 2 Input 3 Bit Muxes := 12 - 10 Input 3 Bit Muxes := 1 - 2 Input 2 Bit Muxes := 5 - 8 Input 2 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 95 - 3 Input 1 Bit Muxes := 12 - 9 Input 1 Bit Muxes := 1 - 4 Input 1 Bit Muxes := 1 - 8 Input 1 Bit Muxes := 5 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module xsdbs_v1_0_2_xsdbs -Detailed RTL Component Info : -+---Registers : - 128 Bit Registers := 1 - 17 Bit Registers := 1 - 16 Bit Registers := 4 - 1 Bit Registers := 4 -+---Muxes : - 2 Input 16 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_stat -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_ctl -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized29 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__parameterized0 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized30 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized44 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized45 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized46 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized47 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized48 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__parameterized1 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized49 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized50 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized51 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized52 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized53 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized54 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized55 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized10 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_stream -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_p2s -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized0 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized1 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized2 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized3 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized4 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized5 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized6 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized7 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized8 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized9 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module ila_v6_2_9_ila_register -Detailed RTL Component Info : -+---Adders : - 2 Input 9 Bit Adders := 1 - 2 Input 7 Bit Adders := 2 - 2 Input 6 Bit Adders := 1 -+---Registers : - 1024 Bit Registers := 2 - 17 Bit Registers := 1 - 16 Bit Registers := 12 - 9 Bit Registers := 1 - 7 Bit Registers := 2 - 6 Bit Registers := 1 - 1 Bit Registers := 31 -+---Muxes : - 2 Input 16 Bit Muxes := 8 - 4 Input 16 Bit Muxes := 1 - 3 Input 16 Bit Muxes := 1 - 8 Input 16 Bit Muxes := 1 - 3 Input 15 Bit Muxes := 1 - 2 Input 6 Bit Muxes := 4 - 2 Input 5 Bit Muxes := 2 - 10 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 13 - 9 Input 1 Bit Muxes := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0 -Detailed RTL Component Info : -+---Registers : - 12 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA -Detailed RTL Component Info : -+---Registers : - 10 Bit Registers := 1 -Module ltlib_v1_0_0_match -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ila_v6_2_9_ila_trigger -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 3 -Module ltlib_v1_0_0_async_edge_xfer -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 1 -+---Registers : - 1 Bit Registers := 5 -Module ltlib_v1_0_0_rising_edge_detection -Detailed RTL Component Info : -+---Registers : - 2 Bit Registers := 1 - 1 Bit Registers := 1 -+---Muxes : - 2 Input 2 Bit Muxes := 2 -Module ila_v6_2_9_ila_reset_ctrl -Detailed RTL Component Info : -+---Registers : - 6 Bit Registers := 1 - 1 Bit Registers := 2 -Module ltlib_v1_0_0_cfglut7 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 3 -Module ltlib_v1_0_0_cfglut6 -Detailed RTL Component Info : -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module ltlib_v1_0_0_allx_typeA_nodelay -Detailed RTL Component Info : -+---Registers : - 12 Bit Registers := 1 -Module ila_v6_2_9_ila_cap_addrgen -Detailed RTL Component Info : -+---Registers : - 33 Bit Registers := 2 - 16 Bit Registers := 1 - 12 Bit Registers := 3 - 1 Bit Registers := 2 -+---Muxes : - 2 Input 1 Bit Muxes := 12 -Module ltlib_v1_0_0_cfglut6__parameterized0 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module ila_v6_2_9_ila_cap_ctrl_legacy -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 3 -+---Muxes : - 2 Input 1 Bit Muxes := 1 - 4 Input 1 Bit Muxes := 1 -Module ltlib_v1_0_0_generic_mux -Detailed RTL Component Info : -+---Muxes : - 3 Input 16 Bit Muxes := 1 -Module ltlib_v1_0_0_generic_memrd -Detailed RTL Component Info : -+---Adders : - 2 Input 12 Bit Adders := 1 - 2 Input 2 Bit Adders := 1 -+---Registers : - 48 Bit Registers := 1 - 12 Bit Registers := 1 - 7 Bit Registers := 1 - 4 Bit Registers := 2 - 2 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 8 Input 12 Bit Muxes := 1 - 3 Input 7 Bit Muxes := 1 - 8 Input 7 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 1 - 2 Input 2 Bit Muxes := 1 - 8 Input 2 Bit Muxes := 1 - 8 Input 1 Bit Muxes := 5 -Module ila_v6_2_9_ila_core -Detailed RTL Component Info : -+---Registers : - 32 Bit Registers := 9 - 16 Bit Registers := 2 - 2 Bit Registers := 3 - 1 Bit Registers := 5 -+---Muxes : - 2 Input 32 Bit Muxes := 1 -Module ila_v6_2_9_ila -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 6 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 2020 (col length:140) -BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1008] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1008] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1009] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1009] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1010] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1010] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1011] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1011] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1012] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1012] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1013] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1013] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1014] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1014] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1015] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1015] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1016] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1016] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1017] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1017] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1018] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1018] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1019] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1019] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1020] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1020] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1021] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1021] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1022] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1022] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1023] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1023] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_trig/shift_cap_strg_qual_reg ) -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_trig/CAP_QUAL_STRG_reg' (FD) to 'inst/ila_core_inst/u_trig/shift_cap_strg_qual_reg' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[0]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[5]' -INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[0] ) -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_892/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[7].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[5].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[3].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[2].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[1]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[1] ) -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_892/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[7].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[5].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[3].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[2].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[2]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[2] ) -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_892/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[7].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[5].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[3].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[2].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[3]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[3] ) -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_892/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[7].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[5].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[3].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[2].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[8] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[9] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[10] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[11] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[12] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[12] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[13] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[14] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[14] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[2] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[3] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[8] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[9] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[10] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[11] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[12] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[13] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[14] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_trig/shift_cap_strg_qual_reg ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[8] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[9] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[10] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[11] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[12] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[13] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[14] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[15] ) ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1635 ; free virtual = 48744 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1517 ; free virtual = 48631 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1511 ; free virtual = 48624 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1508 ; free virtual = 48621 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- -INFO: [Synth 8-3295] tying undriven pin dummy_inferred:in0 to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:trig_in to constant 0 -INFO: [Synth 8-3295] tying undriven pin inst:trig_out_ack to constant 0 ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:47 ; elapsed = 00:00:57 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1497 ; free virtual = 48611 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:47 ; elapsed = 00:00:57 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1497 ; free virtual = 48611 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1498 ; free virtual = 48612 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1498 ; free virtual = 48612 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1498 ; free virtual = 48612 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1498 ; free virtual = 48612 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start ROM, RAM, DSP and Shift Register Reporting ---------------------------------------------------------------------------------- - -Static Shift Register Report: -+---------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ -|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | -+---------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ -|ila_v6_2_9_ila | ila_core_inst/u_ila_regs/adv_rb_drdy4_reg | 5 | 1 | NO | NO | YES | 1 | 0 | -|ila_v6_2_9_ila | ila_core_inst/shifted_data_in_reg[8][31] | 9 | 32 | NO | NO | YES | 32 | 0 | -|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[3] | 3 | 1 | NO | NO | YES | 1 | 0 | -|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[3] | 3 | 1 | NO | NO | YES | 1 | 0 | -+---------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ - ---------------------------------------------------------------------------------- -Finished ROM, RAM, DSP and Shift Register Reporting ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+---------+------+ -| |Cell |Count | -+------+---------+------+ -|1 |CARRY4 | 43| -|2 |CFGLUT5 | 94| -|3 |LUT1 | 39| -|4 |LUT2 | 49| -|5 |LUT3 | 117| -|6 |LUT4 | 172| -|7 |LUT5 | 42| -|8 |LUT6 | 544| -|9 |MUXF7 | 4| -|10 |RAMB36E1 | 4| -|11 |SRL16E | 36| -|12 |SRLC16E | 2| -|13 |SRLC32E | 17| -|14 |FDRE | 1620| -|15 |FDSE | 9| -+------+---------+------+ - -Report Instance Areas: -+------+------------------------------------------------------------------------+------------------------------------------------------------+------+ -| |Instance |Module |Cells | -+------+------------------------------------------------------------------------+------------------------------------------------------------+------+ -|1 |top | | 2792| -|2 | inst |ila_v6_2_9_ila | 2792| -|3 | ila_core_inst |ila_v6_2_9_ila_core | 2785| -|4 | ila_trace_memory_inst |ila_v6_2_9_ila_trace_memory | 4| -|5 | \SUBCORE_RAM_BLK_MEM_1.trace_block_memory |blk_mem_gen_v8_4_3 | 4| -|6 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 4| -|7 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_v8_4_3_blk_mem_gen_top | 4| -|8 | \valid.cstr |blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr | 4| -|9 | \ramloop[0].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width | 1| -|10 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper | 1| -|11 | \ramloop[1].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized0 | 1| -|12 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 | 1| -|13 | \ramloop[2].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized1 | 1| -|14 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 | 1| -|15 | \ramloop[3].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized2 | 1| -|16 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 | 1| -|17 | u_ila_cap_ctrl |ila_v6_2_9_ila_cap_ctrl_legacy | 279| -|18 | U_CDONE |ltlib_v1_0_0_cfglut6__parameterized0 | 5| -|19 | U_NS0 |ltlib_v1_0_0_cfglut7 | 6| -|20 | U_NS1 |ltlib_v1_0_0_cfglut7_58 | 6| -|21 | u_cap_addrgen |ila_v6_2_9_ila_cap_addrgen | 257| -|22 | U_CMPRESET |ltlib_v1_0_0_cfglut6 | 3| -|23 | u_cap_sample_counter |ila_v6_2_9_ila_cap_sample_counter | 48| -|24 | U_SCE |ltlib_v1_0_0_cfglut4_65 | 1| -|25 | U_SCMPCE |ltlib_v1_0_0_cfglut5_66 | 1| -|26 | U_SCRST |ltlib_v1_0_0_cfglut6_67 | 5| -|27 | u_scnt_cmp |ltlib_v1_0_0_match_nodelay_68 | 24| -|28 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_69 | 24| -|29 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_70 | 12| -|30 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_71 | 5| -|31 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_72 | 5| -|32 | u_cap_window_counter |ila_v6_2_9_ila_cap_window_counter | 57| -|33 | U_WCE |ltlib_v1_0_0_cfglut4 | 1| -|34 | U_WHCMPCE |ltlib_v1_0_0_cfglut5 | 1| -|35 | U_WLCMPCE |ltlib_v1_0_0_cfglut5_59 | 1| -|36 | u_wcnt_hcmp |ltlib_v1_0_0_match_nodelay | 12| -|37 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_61 | 12| -|38 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_62 | 12| -|39 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_63 | 5| -|40 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_64 | 5| -|41 | u_wcnt_lcmp |ltlib_v1_0_0_match_nodelay_60 | 24| -|42 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay | 24| -|43 | DUT |ltlib_v1_0_0_all_typeA__parameterized1 | 12| -|44 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1 | 5| -|45 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2 | 5| -|46 | u_ila_regs |ila_v6_2_9_ila_register | 2019| -|47 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 302| -|48 | reg_890 |xsdbs_v1_0_2_reg__parameterized62 | 16| -|49 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_57 | 16| -|50 | \MU_SRL[0].mu_srl_reg |xsdbs_v1_0_2_reg_p2s | 73| -|51 | \MU_SRL[1].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized0 | 89| -|52 | \MU_SRL[2].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized1 | 73| -|53 | \MU_SRL[3].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized2 | 73| -|54 | \MU_SRL[4].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized3 | 73| -|55 | \MU_SRL[5].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized4 | 105| -|56 | \MU_SRL[6].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized5 | 73| -|57 | \MU_SRL[7].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized6 | 73| -|58 | \MU_SRL[8].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized7 | 75| -|59 | \MU_SRL[9].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized8 | 73| -|60 | \TC_SRL[0].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized9 | 76| -|61 | reg_15 |xsdbs_v1_0_2_reg__parameterized44 | 20| -|62 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_56 | 20| -|63 | reg_16 |xsdbs_v1_0_2_reg__parameterized45 | 20| -|64 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_55 | 20| -|65 | reg_17 |xsdbs_v1_0_2_reg__parameterized46 | 30| -|66 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_54 | 30| -|67 | reg_18 |xsdbs_v1_0_2_reg__parameterized47 | 19| -|68 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_53 | 19| -|69 | reg_19 |xsdbs_v1_0_2_reg__parameterized48 | 31| -|70 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_52 | 31| -|71 | reg_1a |xsdbs_v1_0_2_reg__parameterized49 | 17| -|72 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1_51 | 17| -|73 | reg_6 |xsdbs_v1_0_2_reg__parameterized29 | 31| -|74 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_50 | 31| -|75 | reg_7 |xsdbs_v1_0_2_reg__parameterized30 | 30| -|76 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized0 | 30| -|77 | reg_8 |xsdbs_v1_0_2_reg__parameterized31 | 5| -|78 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_49 | 5| -|79 | reg_80 |xsdbs_v1_0_2_reg__parameterized50 | 20| -|80 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1_48 | 20| -|81 | reg_81 |xsdbs_v1_0_2_reg__parameterized51 | 61| -|82 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_47 | 61| -|83 | reg_82 |xsdbs_v1_0_2_reg__parameterized52 | 17| -|84 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1 | 17| -|85 | reg_83 |xsdbs_v1_0_2_reg__parameterized53 | 17| -|86 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_46 | 17| -|87 | reg_84 |xsdbs_v1_0_2_reg__parameterized54 | 17| -|88 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_45 | 17| -|89 | reg_85 |xsdbs_v1_0_2_reg__parameterized55 | 17| -|90 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_44 | 17| -|91 | reg_887 |xsdbs_v1_0_2_reg__parameterized57 | 3| -|92 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_43 | 3| -|93 | reg_88d |xsdbs_v1_0_2_reg__parameterized59 | 6| -|94 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_42 | 6| -|95 | reg_9 |xsdbs_v1_0_2_reg__parameterized32 | 25| -|96 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_41 | 25| -|97 | reg_srl_fff |xsdbs_v1_0_2_reg_p2s__parameterized10 | 95| -|98 | reg_stream_ffd |xsdbs_v1_0_2_reg_stream | 28| -|99 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl | 28| -|100 | reg_stream_ffe |xsdbs_v1_0_2_reg_stream__parameterized0 | 24| -|101 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat | 24| -|102 | u_ila_reset_ctrl |ila_v6_2_9_ila_reset_ctrl | 46| -|103 | arm_detection_inst |ltlib_v1_0_0_rising_edge_detection | 5| -|104 | \asyncrounous_transfer.arm_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer | 7| -|105 | \asyncrounous_transfer.arm_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_37 | 6| -|106 | \asyncrounous_transfer.halt_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer_38 | 7| -|107 | \asyncrounous_transfer.halt_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_39 | 6| -|108 | halt_detection_inst |ltlib_v1_0_0_rising_edge_detection_40 | 5| -|109 | u_trig |ila_v6_2_9_ila_trigger | 190| -|110 | \N_DDR_TC.N_DDR_TC_INST[0].U_TC |ltlib_v1_0_0_match | 25| -|111 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA | 23| -|112 | DUT |ltlib_v1_0_0_all_typeA_34 | 13| -|113 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_35 | 5| -|114 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_36 | 6| -|115 | U_TM |ila_v6_2_9_ila_trig_match | 164| -|116 | \N_DDR_MODE.G_NMU[0].U_M |ltlib_v1_0_0_match__parameterized0 | 38| -|117 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_30 | 37| -|118 | DUT |ltlib_v1_0_0_all_typeA_31 | 13| -|119 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_32 | 5| -|120 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 6| -|121 | \N_DDR_MODE.G_NMU[1].U_M |ltlib_v1_0_0_match__parameterized1 | 11| -|122 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_27 | 10| -|123 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_28 | 8| -|124 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_29 | 6| -|125 | \N_DDR_MODE.G_NMU[2].U_M |ltlib_v1_0_0_match__parameterized1_0 | 11| -|126 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_24 | 10| -|127 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_25 | 8| -|128 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_26 | 6| -|129 | \N_DDR_MODE.G_NMU[3].U_M |ltlib_v1_0_0_match__parameterized1_1 | 11| -|130 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_21 | 10| -|131 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_22 | 8| -|132 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_23 | 6| -|133 | \N_DDR_MODE.G_NMU[4].U_M |ltlib_v1_0_0_match__parameterized1_2 | 11| -|134 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_18 | 10| -|135 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_19 | 8| -|136 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 6| -|137 | \N_DDR_MODE.G_NMU[5].U_M |ltlib_v1_0_0_match__parameterized1_3 | 11| -|138 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_15 | 10| -|139 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_16 | 8| -|140 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 6| -|141 | \N_DDR_MODE.G_NMU[6].U_M |ltlib_v1_0_0_match__parameterized1_4 | 11| -|142 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_12 | 10| -|143 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_13 | 8| -|144 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 6| -|145 | \N_DDR_MODE.G_NMU[7].U_M |ltlib_v1_0_0_match__parameterized1_5 | 11| -|146 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_9 | 10| -|147 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_10 | 8| -|148 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 6| -|149 | \N_DDR_MODE.G_NMU[8].U_M |ltlib_v1_0_0_match__parameterized1_6 | 11| -|150 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1 | 10| -|151 | DUT |ltlib_v1_0_0_all_typeA__parameterized0 | 8| -|152 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_8 | 6| -|153 | \N_DDR_MODE.G_NMU[9].U_M |ltlib_v1_0_0_match__parameterized0_7 | 38| -|154 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0 | 37| -|155 | DUT |ltlib_v1_0_0_all_typeA | 13| -|156 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice | 5| -|157 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0 | 6| -|158 | xsdb_memory_read_inst |ltlib_v1_0_0_generic_memrd | 124| -+------+------------------------------------------------------------------------+------------------------------------------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1498 ; free virtual = 48612 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1163 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2329.086 ; gain = 512.414 ; free physical = 1553 ; free virtual = 48667 -Synthesis Optimization Complete : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1566 ; free virtual = 48680 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 145 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2329.086 ; gain = 0.000 ; free physical = 1503 ; free virtual = 48619 -INFO: [Project 1-111] Unisim Transformation Summary: - A total of 94 instances were transformed. - CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 80 instances - CFGLUT5 => SRLC32E: 14 instances - -INFO: [Common 17-83] Releasing license: Synthesis -274 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:50 ; elapsed = 00:01:01 . Memory (MB): peak = 2329.086 ; gain = 918.160 ; free physical = 1601 ; free virtual = 48716 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2329.086 ; gain = 0.000 ; free physical = 1601 ; free virtual = 48716 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ila_rf_test, cache-ID = 2d405617321a842f -INFO: [Coretcl 2-1174] Renamed 157 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2353.098 ; gain = 0.000 ; free physical = 1585 ; free virtual = 48709 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file ila_rf_test_utilization_synth.rpt -pb ila_rf_test_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Thu May 18 12:55:29 2023... diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v deleted file mode 100644 index cbf75d90..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:19d8ad4109babf969bdfe516c397a62b469ce49220b24c8d85e150a3319d7151 -size 1824426 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl deleted file mode 100644 index 680381a6..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:449f65ac341f50fe588c835e11213443114b29b0fa40133ee2f5f46c10dbcd55 -size 3440051 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v deleted file mode 100644 index be350621..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v +++ /dev/null @@ -1,31 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Thu May 18 12:55:28 2023 -// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -// Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v -// Design : ila_rf_test -// Purpose : Stub declaration of top-level module interface -// Device : xc7z100ffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) -module ila_rf_test(clk, probe0, probe1, probe2, probe3, probe4, probe5, - probe6, probe7, probe8, probe9) -/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]" */; - input clk; - input [11:0]probe0; - input [0:0]probe1; - input [0:0]probe2; - input [0:0]probe3; - input [0:0]probe4; - input [0:0]probe5; - input [0:0]probe6; - input [0:0]probe7; - input [0:0]probe8; - input [11:0]probe9; -endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl deleted file mode 100644 index ae79d844..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl +++ /dev/null @@ -1,40 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Thu May 18 12:55:28 2023 --- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl --- Design : ila_rf_test --- Purpose : Stub declaration of top-level module interface --- Device : xc7z100ffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity ila_rf_test is - Port ( - clk : in STD_LOGIC; - probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); - probe1 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe2 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe3 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe4 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe5 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe6 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe7 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe8 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 ) - ); - -end ila_rf_test; - -architecture stub of ila_rf_test is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]"; -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; -begin -end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.pb deleted file mode 100644 index 77c679d5..00000000 Binary files a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.pb and /dev/null differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.rpt deleted file mode 100644 index 8270de28..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.rpt +++ /dev/null @@ -1,190 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Thu May 18 12:55:28 2023 -| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_utilization -file ila_rf_test_utilization_synth.rpt -pb ila_rf_test_utilization_synth.pb -| Design : ila_rf_test -| Device : 7z100ffg900-2 -| Design State : Synthesized ------------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 1013 | 0 | 277400 | 0.37 | -| LUT as Logic | 864 | 0 | 277400 | 0.31 | -| LUT as Memory | 149 | 0 | 108200 | 0.14 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 149 | 0 | | | -| Slice Registers | 1629 | 0 | 554800 | 0.29 | -| Register as Flip Flop | 1629 | 0 | 554800 | 0.29 | -| Register as Latch | 0 | 0 | 554800 | 0.00 | -| F7 Muxes | 4 | 0 | 138700 | <0.01 | -| F8 Muxes | 0 | 0 | 69350 | 0.00 | -+----------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 9 | Yes | Set | - | -| 1620 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+-------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 4 | 0 | 755 | 0.53 | -| RAMB36/FIFO* | 4 | 0 | 755 | 0.53 | -| RAMB36E1 only | 4 | | | | -| RAMB18 | 0 | 0 | 1510 | 0.00 | -+-------------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 2020 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 362 | 0.00 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| Bonded IOPADs | 0 | 0 | 130 | 0.00 | -| PHY_CONTROL | 0 | 0 | 8 | 0.00 | -| PHASER_REF | 0 | 0 | 8 | 0.00 | -| OUT_FIFO | 0 | 0 | 32 | 0.00 | -| IN_FIFO | 0 | 0 | 32 | 0.00 | -| IDELAYCTRL | 0 | 0 | 8 | 0.00 | -| IBUFDS | 0 | 0 | 348 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 362 | 0.00 | -| OLOGIC | 0 | 0 | 362 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 32 | 0.00 | -| MMCME2_ADV | 0 | 0 | 8 | 0.00 | -| PLLE2_ADV | 0 | 0 | 8 | 0.00 | -| BUFMRCE | 0 | 0 | 16 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 32 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 1620 | Flop & Latch | -| LUT6 | 544 | LUT | -| LUT4 | 172 | LUT | -| LUT3 | 117 | LUT | -| SRL16E | 116 | Distributed Memory | -| SRLC32E | 111 | Distributed Memory | -| LUT2 | 49 | LUT | -| CARRY4 | 43 | CarryLogic | -| LUT5 | 42 | LUT | -| LUT1 | 39 | LUT | -| FDSE | 9 | Flop & Latch | -| RAMB36E1 | 4 | Block Memory | -| MUXF7 | 4 | MuxFx | -| SRLC16E | 2 | Distributed Memory | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/project.wdf deleted file mode 100644 index b7d95384..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/project.wdf +++ /dev/null @@ -1,39 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/rundef.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/rundef.js deleted file mode 100644 index e293d0ce..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/rundef.js +++ /dev/null @@ -1,40 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -echo "This script was generated under a different operating system." -echo "Please update the PATH variable below, before executing this script" -exit - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log ila_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_test.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.bat deleted file mode 100644 index ba55218d..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.bat +++ /dev/null @@ -1,11 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -set PATH=%SYSTEMROOT%\system32;%PATH% -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.sh deleted file mode 100755 index c70e213c..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.sh +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -if [ -z "$PATH" ]; then - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin -else - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log ila_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_test.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/vivado.pb deleted file mode 100644 index ca725632..00000000 Binary files a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/vivado.pb and /dev/null differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml index 6cf8268b..da0b2271 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.vivado.begin.rst deleted file mode 100644 index d6d135b3..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.js deleted file mode 100755 index 3e83de11..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.sh deleted file mode 100755 index f679f2e8..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/gen_run.xml deleted file mode 100644 index 07b201fe..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/gen_run.xml +++ /dev/null @@ -1,59 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/htr.txt deleted file mode 100644 index e1d888e9..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -# -# Vivado(TM) -# htr.txt: a Vivado-generated description of how-to-repeat the -# the basic steps of a run. Note that runme.bat/sh needs -# to be invoked for Vivado to track run status. -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -vivado -log vio_rf_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/project.wdf deleted file mode 100644 index de5d35f9..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/project.wdf +++ /dev/null @@ -1,37 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:34:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:34:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3133:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3133:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3665393633363431666561663437633339616462383862306139303537636232:506172656e742050412070726f6a656374204944:00 -eof:298239738 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/rundef.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/rundef.js deleted file mode 100644 index 775d1146..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/rundef.js +++ /dev/null @@ -1,40 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -echo "This script was generated under a different operating system." -echo "Please update the PATH variable below, before executing this script" -exit - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log vio_rf_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.bat deleted file mode 100644 index ba55218d..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.bat +++ /dev/null @@ -1,11 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -set PATH=%SYSTEMROOT%\system32;%PATH% -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.sh deleted file mode 100755 index 441e08aa..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.sh +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -if [ -z "$PATH" ]; then - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin -else - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log vio_rf_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp deleted file mode 100644 index ebbfd5d4..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:403a566a4d857f7eecb54e66d0e2af879bf1bdebaffa20b5c0ba1e8f0c117e3f -size 187108 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.tcl deleted file mode 100644 index 80a9ecdf..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.tcl +++ /dev/null @@ -1,155 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin -set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7z100ffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xdc] -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control_ooc.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1 -new_name vio_rf_control -ip [get_ips vio_rf_control]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top vio_rf_control -part xc7z100ffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix vio_rf_control_ vio_rf_control.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.v - lappend ipCachedFiles vio_rf_control_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.vhdl - lappend ipCachedFiles vio_rf_control_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_sim_netlist.v - lappend ipCachedFiles vio_rf_control_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_sim_netlist.vhdl - lappend ipCachedFiles vio_rf_control_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp vio_rf_control.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_rf_control] -} - -rename_ref -prefix_all vio_rf_control_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef vio_rf_control.dcp -create_report "vio_rf_control_synth_1_synth_report_utilization_0" "report_utilization -file vio_rf_control_utilization_synth.rpt -pb vio_rf_control_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci] - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.vds b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.vds deleted file mode 100644 index 125d4363..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.vds +++ /dev/null @@ -1,665 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu May 18 11:36:23 2023 -# Process ID: 437325 -# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1 -# Command line: vivado -log vio_rf_control.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl -# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.vds -# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vivado.jou -#----------------------------------------------------------- -source vio_rf_control.tcl -notrace -Command: synth_design -top vio_rf_control -part xc7z100ffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' -INFO: [Device 21-403] Loading part xc7z100ffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 437390 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.445 ; gain = 150.688 ; free physical = 453 ; free virtual = 49921 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'vio_rf_control' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/synth/vio_rf_control.v:59] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rf_control does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/synth/vio_rf_control.v:102] -INFO: [Synth 8-6155] done synthesizing module 'vio_rf_control' (8#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/synth/vio_rf_control.v:59] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[11] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[10] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[9] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[8] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[7] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[6] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[11] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[10] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[9] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[8] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[7] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[6] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[4] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[3] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_in_one has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1922.133 ; gain = 212.375 ; free physical = 546 ; free virtual = 49951 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.102 ; gain = 215.344 ; free physical = 543 ; free virtual = 49950 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.102 ; gain = 215.344 ; free physical = 543 ; free virtual = 49950 ---------------------------------------------------------------------------------- -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control_ooc.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control_ooc.xdc] -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.789 ; gain = 0.000 ; free physical = 425 ; free virtual = 49861 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2113.727 ; gain = 7.938 ; free physical = 424 ; free virtual = 49860 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 489 ; free virtual = 49938 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7z100ffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 489 ; free virtual = 49938 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 489 ; free virtual = 49939 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 474 ; free virtual = 49928 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Adders : - 2 Input 3 Bit Adders := 1 - 2 Input 2 Bit Adders := 2 -+---Registers : - 128 Bit Registers := 1 - 32 Bit Registers := 2 - 16 Bit Registers := 26 - 13 Bit Registers := 1 - 12 Bit Registers := 1 - 11 Bit Registers := 4 - 7 Bit Registers := 1 - 6 Bit Registers := 2 - 5 Bit Registers := 1 - 4 Bit Registers := 1 - 3 Bit Registers := 3 - 2 Bit Registers := 3 - 1 Bit Registers := 40 -+---Muxes : - 2 Input 16 Bit Muxes := 4 - 8 Input 13 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 21 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module vio_v3_0_20_probe_in_one -Detailed RTL Component Info : -+---Registers : - 11 Bit Registers := 4 - 1 Bit Registers := 2 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 1 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized0 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 2 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized1 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 6 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized2 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 6 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized3 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 12 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized4 -Detailed RTL Component Info : -+---Adders : - 2 Input 2 Bit Adders := 1 -+---Registers : - 32 Bit Registers := 1 - 16 Bit Registers := 3 - 2 Bit Registers := 1 -+---Muxes : - 2 Input 16 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_all -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 4 Bit Registers := 1 - 1 Bit Registers := 18 -+---Muxes : - 2 Input 1 Bit Muxes := 2 -Module vio_v3_0_20_probe_width -Detailed RTL Component Info : -+---Adders : - 2 Input 3 Bit Adders := 1 -+---Registers : - 13 Bit Registers := 1 - 3 Bit Registers := 1 -+---Muxes : - 8 Input 13 Bit Muxes := 1 -Module xsdbs_v1_0_2_xsdbs -Detailed RTL Component Info : -+---Registers : - 128 Bit Registers := 1 - 16 Bit Registers := 2 - 1 Bit Registers := 1 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_decoder -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 2 - 7 Bit Registers := 1 - 5 Bit Registers := 1 - 3 Bit Registers := 2 - 1 Bit Registers := 9 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 3 -Module vio_v3_0_20_vio -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 2020 (col length:140) -BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 516 ; free virtual = 49925 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 457 ; free virtual = 49815 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 456 ; free virtual = 49814 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 449 ; free virtual = 49809 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+------+------+ -| |Cell |Count | -+------+------+------+ -|1 |LUT1 | 1| -|2 |LUT2 | 14| -|3 |LUT3 | 80| -|4 |LUT4 | 9| -|5 |LUT5 | 28| -|6 |LUT6 | 100| -|7 |MUXF7 | 7| -|8 |MUXF8 | 1| -|9 |FDRE | 532| -|10 |FDSE | 20| -+------+------+------+ - -Report Instance Areas: -+------+----------------------------------------+--------------------------------------------+------+ -| |Instance |Module |Cells | -+------+----------------------------------------+--------------------------------------------+------+ -|1 |top | | 792| -|2 | inst |vio_v3_0_20_vio | 792| -|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| -|4 | DECODER_INST |vio_v3_0_20_decoder | 86| -|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 58| -|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 368| -|7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| -|8 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| -|9 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3| -|10 | \G_PROBE_OUT[12].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3| -|11 | \G_PROBE_OUT[13].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 101| -|12 | \G_PROBE_OUT[14].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_3 | 3| -|13 | \G_PROBE_OUT[15].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_4 | 106| -|14 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 6| -|15 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_5 | 3| -|16 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 12| -|17 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 12| -|18 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 24| -|19 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_6 | 3| -|20 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_7 | 3| -|21 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_8 | 3| -|22 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_9 | 3| -|23 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 16| -+------+----------------------------------------+--------------------------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 292 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2113.727 ; gain = 215.344 ; free physical = 499 ; free virtual = 49862 -Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 512 ; free virtual = 49876 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2113.727 ; gain = 0.000 ; free physical = 440 ; free virtual = 49737 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -130 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2113.727 ; gain = 714.809 ; free physical = 539 ; free virtual = 49831 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2113.727 ; gain = 0.000 ; free physical = 539 ; free virtual = 49831 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rf_control, cache-ID = caeedda65f3825d9 -INFO: [Coretcl 2-1174] Renamed 22 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2137.738 ; gain = 0.000 ; free physical = 503 ; free virtual = 49794 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file vio_rf_control_utilization_synth.rpt -pb vio_rf_control_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Thu May 18 11:36:41 2023... diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v deleted file mode 100644 index a82bf59b..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:61871bc56b34526261f6ee93952fb8c48de88deae16fa932900a16de7cd4b693 -size 418849 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl deleted file mode 100644 index 285e9cc8..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:7d4547a5ef5862f5cc376f41a5d671a805063b6777f0f60d9e8d278616fba128 -size 727945 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v deleted file mode 100644 index e5624f99..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v +++ /dev/null @@ -1,39 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Thu May 18 11:36:40 2023 -// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -// Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v -// Design : vio_rf_control -// Purpose : Stub declaration of top-level module interface -// Device : xc7z100ffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_rf_control(clk, probe_in0, probe_out0, probe_out1, - probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, - probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */; - input clk; - input [10:0]probe_in0; - output [0:0]probe_out0; - output [1:0]probe_out1; - output [0:0]probe_out2; - output [5:0]probe_out3; - output [5:0]probe_out4; - output [11:0]probe_out5; - output [0:0]probe_out6; - output [0:0]probe_out7; - output [0:0]probe_out8; - output [0:0]probe_out9; - output [0:0]probe_out10; - output [0:0]probe_out11; - output [0:0]probe_out12; - output [31:0]probe_out13; - output [0:0]probe_out14; - output [31:0]probe_out15; -endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.pb deleted file mode 100644 index 760ddc80..00000000 Binary files a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.pb and /dev/null differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.rpt deleted file mode 100644 index 69768854..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.rpt +++ /dev/null @@ -1,183 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Thu May 18 11:36:40 2023 -| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_utilization -file vio_rf_control_utilization_synth.rpt -pb vio_rf_control_utilization_synth.pb -| Design : vio_rf_control -| Device : 7z100ffg900-2 -| Design State : Synthesized ------------------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 189 | 0 | 277400 | 0.07 | -| LUT as Logic | 189 | 0 | 277400 | 0.07 | -| LUT as Memory | 0 | 0 | 108200 | 0.00 | -| Slice Registers | 552 | 0 | 554800 | 0.10 | -| Register as Flip Flop | 552 | 0 | 554800 | 0.10 | -| Register as Latch | 0 | 0 | 554800 | 0.00 | -| F7 Muxes | 7 | 0 | 138700 | <0.01 | -| F8 Muxes | 1 | 0 | 69350 | <0.01 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 20 | Yes | Set | - | -| 532 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 755 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | -| RAMB18 | 0 | 0 | 1510 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 2020 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 362 | 0.00 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| Bonded IOPADs | 0 | 0 | 130 | 0.00 | -| PHY_CONTROL | 0 | 0 | 8 | 0.00 | -| PHASER_REF | 0 | 0 | 8 | 0.00 | -| OUT_FIFO | 0 | 0 | 32 | 0.00 | -| IN_FIFO | 0 | 0 | 32 | 0.00 | -| IDELAYCTRL | 0 | 0 | 8 | 0.00 | -| IBUFDS | 0 | 0 | 348 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 362 | 0.00 | -| OLOGIC | 0 | 0 | 362 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 32 | 0.00 | -| MMCME2_ADV | 0 | 0 | 8 | 0.00 | -| PLLE2_ADV | 0 | 0 | 8 | 0.00 | -| BUFMRCE | 0 | 0 | 16 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 32 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 532 | Flop & Latch | -| LUT6 | 100 | LUT | -| LUT3 | 80 | LUT | -| LUT5 | 28 | LUT | -| FDSE | 20 | Flop & Latch | -| LUT2 | 14 | LUT | -| LUT4 | 9 | LUT | -| MUXF7 | 7 | MuxFx | -| MUXF8 | 1 | MuxFx | -| LUT1 | 1 | LUT | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vivado.pb deleted file mode 100644 index e166a01e..00000000 Binary files a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vivado.pb and /dev/null differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.vivado.begin.rst deleted file mode 100644 index c61ffe5b..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.js deleted file mode 100755 index 3e83de11..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.sh deleted file mode 100755 index f679f2e8..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/gen_run.xml deleted file mode 100644 index 35b57724..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/gen_run.xml +++ /dev/null @@ -1,64 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/htr.txt deleted file mode 100644 index fb099950..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -# -# Vivado(TM) -# htr.txt: a Vivado-generated description of how-to-repeat the -# the basic steps of a run. Note that runme.bat/sh needs -# to be invoked for Vivado to track run status. -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -vivado -log vio_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_test.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/project.wdf deleted file mode 100644 index b7d95384..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/project.wdf +++ /dev/null @@ -1,39 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/rundef.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/rundef.js deleted file mode 100644 index 4e5aae25..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/rundef.js +++ /dev/null @@ -1,40 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -echo "This script was generated under a different operating system." -echo "Please update the PATH variable below, before executing this script" -exit - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log vio_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_test.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.bat deleted file mode 100644 index ba55218d..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.bat +++ /dev/null @@ -1,11 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -set PATH=%SYSTEMROOT%\system32;%PATH% -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.sh deleted file mode 100755 index c30677cd..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.sh +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -if [ -z "$PATH" ]; then - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin -else - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log vio_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_test.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp deleted file mode 100644 index f890da71..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:24264de632f3c11f0b2d857dbfcbc618aa7cefc401ff56a7bf2779bd9fb40439 -size 217220 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.tcl deleted file mode 100644 index c31353c5..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.tcl +++ /dev/null @@ -1,155 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin -set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7z100ffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xdc] -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test_ooc.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1 -new_name vio_rf_test -ip [get_ips vio_rf_test]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top vio_rf_test -part xc7z100ffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix vio_rf_test_ vio_rf_test.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_test_stub.v - lappend ipCachedFiles vio_rf_test_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_test_stub.vhdl - lappend ipCachedFiles vio_rf_test_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_test_sim_netlist.v - lappend ipCachedFiles vio_rf_test_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_test_sim_netlist.vhdl - lappend ipCachedFiles vio_rf_test_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp vio_rf_test.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_rf_test] -} - -rename_ref -prefix_all vio_rf_test_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef vio_rf_test.dcp -create_report "vio_rf_test_synth_1_synth_report_utilization_0" "report_utilization -file vio_rf_test_utilization_synth.rpt -pb vio_rf_test_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci] - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.vds b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.vds deleted file mode 100644 index 68837bf2..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.vds +++ /dev/null @@ -1,653 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu May 18 12:54:22 2023 -# Process ID: 520460 -# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1 -# Command line: vivado -log vio_rf_test.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_test.tcl -# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.vds -# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vivado.jou -#----------------------------------------------------------- -source vio_rf_test.tcl -notrace -Command: synth_design -top vio_rf_test -part xc7z100ffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' -INFO: [Device 21-403] Loading part xc7z100ffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 520694 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.508 ; gain = 153.719 ; free physical = 488 ; free virtual = 48108 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'vio_rf_test' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/synth/vio_rf_test.v:59] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rf_test does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/synth/vio_rf_test.v:93] -INFO: [Synth 8-6155] done synthesizing module 'vio_rf_test' (7#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/synth/vio_rf_test.v:59] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[11] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[10] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[9] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[8] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[7] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[6] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[5] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized6 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in0[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in36[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in37[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in38[0] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1922.195 ; gain = 215.406 ; free physical = 474 ; free virtual = 48095 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.164 ; gain = 218.375 ; free physical = 473 ; free virtual = 48095 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.164 ; gain = 218.375 ; free physical = 473 ; free virtual = 48095 ---------------------------------------------------------------------------------- -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test_ooc.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test_ooc.xdc] -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2106.820 ; gain = 0.000 ; free physical = 465 ; free virtual = 47975 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2114.758 ; gain = 7.938 ; free physical = 465 ; free virtual = 47975 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 513 ; free virtual = 47799 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7z100ffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 513 ; free virtual = 47799 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 513 ; free virtual = 47800 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 507 ; free virtual = 47794 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Adders : - 2 Input 3 Bit Adders := 2 - 2 Input 2 Bit Adders := 3 -+---Registers : - 128 Bit Registers := 1 - 64 Bit Registers := 1 - 32 Bit Registers := 3 - 16 Bit Registers := 28 - 14 Bit Registers := 1 - 12 Bit Registers := 2 - 8 Bit Registers := 2 - 7 Bit Registers := 1 - 5 Bit Registers := 2 - 4 Bit Registers := 1 - 3 Bit Registers := 4 - 2 Bit Registers := 3 - 1 Bit Registers := 27 -+---Muxes : - 2 Input 16 Bit Muxes := 5 - 4 Input 16 Bit Muxes := 1 - 6 Input 14 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 14 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module vio_v3_0_20_probe_out_one -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 1 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized0 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 8 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized1 -Detailed RTL Component Info : -+---Adders : - 2 Input 2 Bit Adders := 1 -+---Registers : - 32 Bit Registers := 1 - 16 Bit Registers := 3 - 2 Bit Registers := 1 -+---Muxes : - 2 Input 16 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized2 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 12 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized3 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 12 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized4 -Detailed RTL Component Info : -+---Adders : - 2 Input 2 Bit Adders := 1 -+---Registers : - 32 Bit Registers := 1 - 16 Bit Registers := 3 - 2 Bit Registers := 1 -+---Muxes : - 2 Input 16 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized5 -Detailed RTL Component Info : -+---Adders : - 2 Input 2 Bit Adders := 1 -+---Registers : - 32 Bit Registers := 1 - 16 Bit Registers := 3 - 2 Bit Registers := 1 -+---Muxes : - 2 Input 16 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized6 -Detailed RTL Component Info : -+---Adders : - 2 Input 3 Bit Adders := 1 -+---Registers : - 64 Bit Registers := 1 - 16 Bit Registers := 5 - 3 Bit Registers := 1 -+---Muxes : - 4 Input 16 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_one__parameterized7 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 5 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_all -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 4 Bit Registers := 1 - 1 Bit Registers := 14 -+---Muxes : - 2 Input 1 Bit Muxes := 2 -Module vio_v3_0_20_probe_width -Detailed RTL Component Info : -+---Adders : - 2 Input 3 Bit Adders := 1 -+---Registers : - 14 Bit Registers := 1 - 3 Bit Registers := 1 -+---Muxes : - 6 Input 14 Bit Muxes := 1 -Module xsdbs_v1_0_2_xsdbs -Detailed RTL Component Info : -+---Registers : - 128 Bit Registers := 1 - 16 Bit Registers := 2 - 1 Bit Registers := 1 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_decoder -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 2 - 7 Bit Registers := 1 - 5 Bit Registers := 1 - 3 Bit Registers := 2 - 1 Bit Registers := 9 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 3 -Module vio_v3_0_20_vio -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 2020 (col length:140) -BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[1]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[2]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 490 ; free virtual = 47781 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 427 ; free virtual = 47708 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 427 ; free virtual = 47708 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 423 ; free virtual = 47705 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 573 ; free virtual = 47825 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 573 ; free virtual = 47825 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 575 ; free virtual = 47828 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 575 ; free virtual = 47828 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 575 ; free virtual = 47828 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 575 ; free virtual = 47828 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-----+------+ -| |Cell |Count | -+------+-----+------+ -|1 |LUT2 | 13| -|2 |LUT3 | 85| -|3 |LUT4 | 7| -|4 |LUT5 | 35| -|5 |LUT6 | 143| -|6 |FDRE | 678| -|7 |FDSE | 78| -+------+-----+------+ - -Report Instance Areas: -+------+----------------------------------------+--------------------------------------------+------+ -| |Instance |Module |Cells | -+------+----------------------------------------+--------------------------------------------+------+ -|1 |top | | 1039| -|2 | inst |vio_v3_0_20_vio | 1039| -|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| -|4 | DECODER_INST |vio_v3_0_20_decoder | 79| -|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 676| -|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| -|7 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized7 | 10| -|8 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| -|9 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 16| -|10 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_1 | 16| -|11 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 100| -|12 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3| -|13 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 24| -|14 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 24| -|15 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 105| -|16 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized5 | 104| -|17 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized6 | 171| -|18 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 20| -+------+----------------------------------------+--------------------------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 575 ; free virtual = 47828 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 293 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.758 ; gain = 218.375 ; free physical = 607 ; free virtual = 47881 -Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 621 ; free virtual = 47890 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2114.758 ; gain = 0.000 ; free physical = 535 ; free virtual = 47811 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -102 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2114.758 ; gain = 715.840 ; free physical = 607 ; free virtual = 47894 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2114.758 ; gain = 0.000 ; free physical = 604 ; free virtual = 47893 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rf_test, cache-ID = 06d53c7bf3a5a806 -INFO: [Coretcl 2-1174] Renamed 17 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2138.770 ; gain = 0.000 ; free physical = 553 ; free virtual = 47840 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file vio_rf_test_utilization_synth.rpt -pb vio_rf_test_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Thu May 18 12:54:40 2023... diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v deleted file mode 100644 index b0f9aad4..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:5c56114c4d1dbd4de738da259f25557427b35cb18dfeb59dda5bf2598412b05e -size 477028 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl deleted file mode 100644 index 0ffb41e3..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:0d14ce253bc7bd29c3d5ba48eb5bde1db77a4576966d51a7f7133d0cfa5da73e -size 802152 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v deleted file mode 100644 index 374e48d6..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v +++ /dev/null @@ -1,34 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Thu May 18 12:54:39 2023 -// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -// Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v -// Design : vio_rf_test -// Purpose : Stub declaration of top-level module interface -// Device : xc7z100ffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_rf_test(clk, probe_out0, probe_out1, probe_out2, - probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, - probe_out10, probe_out11) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]" */; - input clk; - output [0:0]probe_out0; - output [7:0]probe_out1; - output [7:0]probe_out2; - output [31:0]probe_out3; - output [0:0]probe_out4; - output [11:0]probe_out5; - output [11:0]probe_out6; - output [31:0]probe_out7; - output [31:0]probe_out8; - output [63:0]probe_out9; - output [4:0]probe_out10; - output [0:0]probe_out11; -endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl deleted file mode 100644 index 290eaedb..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl +++ /dev/null @@ -1,42 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Thu May 18 12:54:39 2023 --- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl --- Design : vio_rf_test --- Purpose : Stub declaration of top-level module interface --- Device : xc7z100ffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity vio_rf_test is - Port ( - clk : in STD_LOGIC; - probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); - probe_out2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out7 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out8 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out9 : out STD_LOGIC_VECTOR ( 63 downto 0 ); - probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 ); - probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - -end vio_rf_test; - -architecture stub of vio_rf_test is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]"; -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; -begin -end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.pb deleted file mode 100644 index 7a0dd59b..00000000 Binary files a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.pb and /dev/null differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.rpt deleted file mode 100644 index e51bb4dc..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.rpt +++ /dev/null @@ -1,180 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Thu May 18 12:54:39 2023 -| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_utilization -file vio_rf_test_utilization_synth.rpt -pb vio_rf_test_utilization_synth.pb -| Design : vio_rf_test -| Device : 7z100ffg900-2 -| Design State : Synthesized ------------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 236 | 0 | 277400 | 0.09 | -| LUT as Logic | 236 | 0 | 277400 | 0.09 | -| LUT as Memory | 0 | 0 | 108200 | 0.00 | -| Slice Registers | 756 | 0 | 554800 | 0.14 | -| Register as Flip Flop | 756 | 0 | 554800 | 0.14 | -| Register as Latch | 0 | 0 | 554800 | 0.00 | -| F7 Muxes | 0 | 0 | 138700 | 0.00 | -| F8 Muxes | 0 | 0 | 69350 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 78 | Yes | Set | - | -| 678 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 755 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | -| RAMB18 | 0 | 0 | 1510 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 2020 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 362 | 0.00 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| Bonded IOPADs | 0 | 0 | 130 | 0.00 | -| PHY_CONTROL | 0 | 0 | 8 | 0.00 | -| PHASER_REF | 0 | 0 | 8 | 0.00 | -| OUT_FIFO | 0 | 0 | 32 | 0.00 | -| IN_FIFO | 0 | 0 | 32 | 0.00 | -| IDELAYCTRL | 0 | 0 | 8 | 0.00 | -| IBUFDS | 0 | 0 | 348 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 362 | 0.00 | -| OLOGIC | 0 | 0 | 362 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 32 | 0.00 | -| MMCME2_ADV | 0 | 0 | 8 | 0.00 | -| PLLE2_ADV | 0 | 0 | 8 | 0.00 | -| BUFMRCE | 0 | 0 | 16 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 32 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 678 | Flop & Latch | -| LUT6 | 143 | LUT | -| LUT3 | 85 | LUT | -| FDSE | 78 | Flop & Latch | -| LUT5 | 35 | LUT | -| LUT2 | 13 | LUT | -| LUT4 | 7 | LUT | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vivado.pb deleted file mode 100644 index ee19ad8e..00000000 Binary files a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vivado.pb and /dev/null differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr index 5df05218..7c2fc2cf 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -278,37 +246,6 @@ - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - - - - - - - - Vivado Synthesis Defaults - - - - - - - @@ -341,58 +278,6 @@ - - - - - - - - - - - - - - - - - - - - Default settings for Implementation. - - - - - - - - - - - - - - - - - - Default settings for Implementation. - - - - - - - - - - - - - - diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/sig_clk_gen.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/sig_clk_gen.xcix index 156f8841..f7944b02 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/sig_clk_gen.xcix +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/sig_clk_gen.xcix @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:533644b17a1cbea30e65b69b38c4f370aa16211eb5185c4805b874678c030e2c -size 93062 +oid sha256:b18fd5cfc84965ad9f098d337da5ef2adef769ba47a6258e42fbb3697b3c5daf +size 95265 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control.xcix new file mode 100644 index 00000000..4637e451 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b54cf031cbee0d69af400dd9711af02e62ed3bb5a7e8cc76fd93edce598c0871 +size 712909 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control.xcix deleted file mode 100644 index 81013c3b..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control.xcix +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:74e7166d8bda8c3824a8ab80ef948f950fabd3f401c14a10bbd6e0bb92b13a42 -size 777513 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test.xcix deleted file mode 100644 index 2806cf80..00000000 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test.xcix +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:8cf2a0a93c53f8015dc532e9053c8d45d71205773e5dd65d3813ecdb9b892583 -size 817412 diff --git a/projects/dl814_dj/dl814_dj_new_48m/project.tcl b/projects/dl814_dj/dl814_dj_new_48m/project.tcl index 84143cd6..a9d91a75 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/project.tcl +++ b/projects/dl814_dj/dl814_dj_new_48m/project.tcl @@ -3,7 +3,7 @@ # # project.tcl: Tcl script for re-creating project 'project' # -# Generated by Vivado on Fri May 12 10:01:28 CST 2023 +# Generated by Vivado on Sun Jul 09 14:59:13 CST 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -27,8 +27,9 @@ # # 3. The following remote source files that were added to the original project:- # -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xci" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ip/basic_driver/ila_ctrl_signal/ila_ctrl_signal.xci" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ip/basic_driver/ila_4x16x131072/ila_4x16x131072.xci" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ip/basic_driver/ila_2x16x131072/ila_2x16x131072.xci" @@ -36,24 +37,24 @@ # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/lpf_125k/lpf_125k.xci" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/lpf_125k/lpf_125k.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.xci" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ipi-bd/basic_driver_bd/system_bd.bd" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/sig_clk_gen/sig_clk_gen.xci" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/rtl/rf_auto_switch_freq.v" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/rtl/rf_control.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/rtl/tx_control.v" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/rtl/tx_pn_seq_6mcps.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_control.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_pn_seq_6mcps.v" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/rtl/system_top.v" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/coe/lpf_125k.coe" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/coe/lpf_125k.coe" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/coe/sweep_freq.coe" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/coe/freq_word.coe" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word.xci" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/constraints/z7100_ad9528_ad9371.xdc" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/testbenches/tb_tx_pn_seq.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/sig_clk_gen/sig_clk_gen.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/testbenches/tb_tx_pn_seq.v" # #***************************************************************************************** @@ -158,13 +159,13 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj set_property -name "target_simulator" -value "IES" -objects $obj -set_property -name "webtalk.activehdl_export_sim" -value "36" -objects $obj -set_property -name "webtalk.ies_export_sim" -value "36" -objects $obj -set_property -name "webtalk.modelsim_export_sim" -value "36" -objects $obj -set_property -name "webtalk.questa_export_sim" -value "36" -objects $obj -set_property -name "webtalk.riviera_export_sim" -value "36" -objects $obj -set_property -name "webtalk.vcs_export_sim" -value "36" -objects $obj -set_property -name "webtalk.xsim_export_sim" -value "36" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "42" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "42" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "42" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "42" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "42" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "42" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "42" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj # Create 'sources_1' fileset (if not found) @@ -175,7 +176,8 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ - [file normalize "${origin_dir}/ip/vio_rf_control/vio_rf_control.xci"] \ + [file normalize "${origin_dir}/ip/ila_rf_test/ila_rf_test.xci"] \ + [file normalize "${origin_dir}/ip/vio_RF_control/vio_RF_control.xci"] \ [file normalize "${origin_dir}/ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \ [file normalize "${origin_dir}/../common_ip/basic_driver/ila_ctrl_signal/ila_ctrl_signal.xci"] \ [file normalize "${origin_dir}/../common_ip/basic_driver/ila_4x16x131072/ila_4x16x131072.xci"] \ @@ -187,14 +189,14 @@ set files [list \ [file normalize "${origin_dir}/ip/lpf_125k/lpf_125k.xci"] \ [file normalize "${origin_dir}/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.xci"] \ [file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/system_bd.bd"] \ - [file normalize "${origin_dir}/ip/sig_clk_gen/sig_clk_gen.xci"] \ - [file normalize "${origin_dir}/rtl/rf_auto_switch_freq.v"] \ [file normalize "${origin_dir}/rtl/rf_control.v"] \ [file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v"] \ [file normalize "${origin_dir}/rtl/tx_control.v"] \ [file normalize "${origin_dir}/rtl/tx_pn_seq_6mcps.v"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \ [file normalize "${origin_dir}/rtl/system_top.v"] \ + [file normalize "${origin_dir}/ip/rom_freq_word/rom_freq_word.xci"] \ + [file normalize "${origin_dir}/rtl/rf_auto_switch_freq.v"] \ [file normalize "${origin_dir}/ip/coe/lpf_125k.coe"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \ @@ -203,7 +205,16 @@ set files [list \ add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/ip/vio_rf_control/vio_rf_control.xci" +set file "$origin_dir/ip/ila_rf_test/ila_rf_test.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/vio_RF_control/vio_RF_control.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -307,7 +318,7 @@ set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "registered_with_manager" -value "1" -objects $file_obj -set file "$origin_dir/ip/sig_clk_gen/sig_clk_gen.xci" +set file "$origin_dir/ip/rom_freq_word/rom_freq_word.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -328,12 +339,12 @@ set_property -name "top_auto_set" -value "0" -objects $obj # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ - [file normalize "${origin_dir}/ip/rom_freq_word/rom_freq_word.xci"] \ + [file normalize "${origin_dir}/ip/sig_clk_gen/sig_clk_gen.xci"] \ ] add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/ip/rom_freq_word/rom_freq_word.xci" +set file "$origin_dir/ip/sig_clk_gen/sig_clk_gen.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.hw/project.lpr b/projects/dl814_dj/dl814_dj_new_48m/project/project.hw/project.lpr index 29d8123e..c82f75e0 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/project/project.hw/project.lpr +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.hw/project.lpr @@ -3,4 +3,6 @@ - + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx index 4351693b..c6cf2cfb 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx @@ -11,11 +11,11 @@ "type": "XSDB_V3", "name": "dbg_hub", "spec": "labtools_xsdbm_v3", - "clk_input_freq_hz": "122880320" + "clk_input_freq_hz": "192000507" }, { "type": "ILA_V3", - "name": "ila_rf_test", + "name": "u_ila_ctrl_signal", "spec": "labtools_ila_v6", "ipName": "ila", "core_location": { @@ -23,13 +23,123 @@ "slave_index": 0, "bscan_switch_index": 0 }, - "uuid": "C3E203EDC3EB51B199EEE872BD8D49EB", + "uuid": "46B6B100E72A58A8A2087FA72DC35D0B", "pins": [ { "name": "probe0", "id": 0, "type": "DATA_TRIGGER", "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 0, + "nets": [ + { + "name": "jesd_reset", + "isBus": false + } + ] + }, + { + "name": "probe1", + "id": 1, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "rx_sync", + "isBus": false + } + ] + }, + { + "name": "probe2", + "id": 2, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 2, + "nets": [ + { + "name": "rx_rstn", + "isBus": false + } + ] + }, + { + "name": "probe3", + "id": 3, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 3, + "nets": [ + { + "name": "tx_sync", + "isBus": false + } + ] + }, + { + "name": "probe4", + "id": 4, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 4, + "nets": [ + { + "name": "tx_rstn", + "isBus": false + } + ] + }, + { + "name": "probe5", + "id": 5, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 5, + "nets": [ + { + "name": "sysref", + "isBus": false + } + ] + } + ] + }, + { + "type": "ILA_V3", + "name": "u_ila_rf_test", + "spec": "labtools_ila_v6", + "ipName": "ila", + "core_location": { + "user_chain": 1, + "slave_index": 1, + "bscan_switch_index": 0 + }, + "uuid": "E5E249F0F463550991043737009BC5E0", + "pins": [ + { + "name": "probe0", + "id": 6, + "type": "DATA_TRIGGER", + "direction": "IN", "isVector": true, "leftIndex": 0, "rightIndex": 11, @@ -81,13 +191,78 @@ }, { "name": "probe1", - "id": 1, + "id": 7, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, "leftIndex": 0, "rightIndex": 0, "portIndex": 1, + "nets": [ + { + "name": "rf_spi_attn_clk_OBUF", + "isBus": false, + "parentNetId": 18 + } + ] + }, + { + "name": "probe2", + "id": 8, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 2, + "nets": [ + { + "name": "rf_spi_attn_csn_OBUF", + "isBus": false + } + ] + }, + { + "name": "probe3", + "id": 9, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 3, + "nets": [ + { + "name": "rf_spi_attn_mosi_OBUF", + "isBus": false + } + ] + }, + { + "name": "probe4", + "id": 10, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 4, + "nets": [ + { + "name": "rf_spi_attn_miso_IBUF", + "isBus": false + } + ] + }, + { + "name": "probe5", + "id": 11, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 5, "nets": [ { "name": "tx_gain_on_OBUF", @@ -95,73 +270,9 @@ } ] }, - { - "name": "probe2", - "id": 2, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 2, - "nets": [ - { - "name": "rx_gain_IBUF", - "isBus": false - } - ] - }, - { - "name": "probe3", - "id": 3, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 3, - "nets": [ - { - "name": "rx_gain_on_OBUF", - "isBus": false - } - ] - }, - { - "name": "probe4", - "id": 4, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 4, - "nets": [ - { - "name": "tx_gain_OBUF", - "isBus": false - } - ] - }, - { - "name": "probe5", - "id": 5, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 5, - "nets": [ - { - "name": "hop_words_valid_OBUF", - "isBus": false - } - ] - }, { "name": "probe6", - "id": 6, + "id": 12, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, @@ -170,14 +281,14 @@ "portIndex": 6, "nets": [ { - "name": "freq_hop_switch_OBUF", + "name": "rx_gain_on_OBUF", "isBus": false } ] }, { "name": "probe7", - "id": 7, + "id": 13, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, @@ -186,15 +297,14 @@ "portIndex": 7, "nets": [ { - "name": "clk_12M_OBUF", - "isBus": false, - "parentNetId": 18 + "name": "hop_words_valid_OBUF", + "isBus": false } ] }, { "name": "probe8", - "id": 8, + "id": 14, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, @@ -203,171 +313,7 @@ "portIndex": 8, "nets": [ { - "name": "CS_rf_OBUF", - "isBus": false - } - ] - }, - { - "name": "probe9", - "id": 9, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 11, - "portIndex": 9, - "nets": [ - { - "name": "freq_hop_words_sweep", - "isBus": true, - "subnets": [ - { - "name": "freq_hop_words_sweep[11]" - }, - { - "name": "freq_hop_words_sweep[10]" - }, - { - "name": "freq_hop_words_sweep[9]" - }, - { - "name": "freq_hop_words_sweep[8]" - }, - { - "name": "freq_hop_words_sweep[7]" - }, - { - "name": "freq_hop_words_sweep[6]" - }, - { - "name": "freq_hop_words_sweep[5]" - }, - { - "name": "freq_hop_words_sweep[4]" - }, - { - "name": "freq_hop_words_sweep[3]" - }, - { - "name": "freq_hop_words_sweep[2]" - }, - { - "name": "freq_hop_words_sweep[1]" - }, - { - "name": "freq_hop_words_sweep[0]" - } - ] - } - ] - } - ] - }, - { - "type": "ILA_V3", - "name": "u_ila_ctrl_signal", - "spec": "labtools_ila_v6", - "ipName": "ila", - "core_location": { - "user_chain": 1, - "slave_index": 1, - "bscan_switch_index": 0 - }, - "uuid": "46B6B100E72A58A8A2087FA72DC35D0B", - "pins": [ - { - "name": "probe0", - "id": 10, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 0, - "nets": [ - { - "name": "jesd_reset", - "isBus": false - } - ] - }, - { - "name": "probe1", - "id": 11, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 1, - "nets": [ - { - "name": "rx_sync", - "isBus": false - } - ] - }, - { - "name": "probe2", - "id": 12, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 2, - "nets": [ - { - "name": "rx_rstn", - "isBus": false - } - ] - }, - { - "name": "probe3", - "id": 13, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 3, - "nets": [ - { - "name": "tx_sync", - "isBus": false - } - ] - }, - { - "name": "probe4", - "id": 14, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 4, - "nets": [ - { - "name": "tx_rstn", - "isBus": false - } - ] - }, - { - "name": "probe5", - "id": 15, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 5, - "nets": [ - { - "name": "sysref", + "name": "freq_hop_switch_OBUF", "isBus": false } ] @@ -388,7 +334,7 @@ "pins": [ { "name": "probe0", - "id": 16, + "id": 15, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -454,7 +400,7 @@ }, { "name": "probe1", - "id": 17, + "id": 16, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -520,7 +466,7 @@ }, { "name": "probe2", - "id": 18, + "id": 17, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -586,7 +532,7 @@ }, { "name": "probe3", - "id": 19, + "id": 18, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -666,7 +612,7 @@ "pins": [ { "name": "probe0", - "id": 20, + "id": 19, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -732,7 +678,7 @@ }, { "name": "probe1", - "id": 21, + "id": 20, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -800,7 +746,7 @@ }, { "type": "VIO_V2", - "name": "u_rf_control/vio_rf_test", + "name": "u_vio_manual_ctrl", "spec": "labtools_vio_v3", "ipName": "vio", "core_location": { @@ -808,850 +754,11 @@ "slave_index": 4, "bscan_switch_index": 0 }, - "uuid": "8F1E87AA41105143AA018CE9B35278A7", - "pins": [ - { - "name": "probe_out0", - "id": 22, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 0, - "nets": [ - { - "name": "u_rf_control/CS_rf_flag", - "isBus": false - } - ] - }, - { - "name": "probe_out1", - "id": 23, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 7, - "portIndex": 1, - "nets": [ - { - "name": "u_rf_control/MOSI_tx_atte", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/MOSI_tx_atte[7]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[6]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[5]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[4]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[3]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[2]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[1]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[0]" - } - ] - } - ] - }, - { - "name": "probe_out2", - "id": 24, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 7, - "portIndex": 2, - "nets": [ - { - "name": "u_rf_control/MOSI_rx_atte", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/MOSI_rx_atte[7]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[6]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[5]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[4]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[3]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[2]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[1]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[0]" - } - ] - } - ] - }, - { - "name": "probe_out3", - "id": 25, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 3, - "nets": [ - { - "name": "u_rf_control/cnt_frechange_top", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/cnt_frechange_top[31]" - }, - { - "name": "u_rf_control/cnt_frechange_top[30]" - }, - { - "name": "u_rf_control/cnt_frechange_top[29]" - }, - { - "name": "u_rf_control/cnt_frechange_top[28]" - }, - { - "name": "u_rf_control/cnt_frechange_top[27]" - }, - { - "name": "u_rf_control/cnt_frechange_top[26]" - }, - { - "name": "u_rf_control/cnt_frechange_top[25]" - }, - { - "name": "u_rf_control/cnt_frechange_top[24]" - }, - { - "name": "u_rf_control/cnt_frechange_top[23]" - }, - { - "name": "u_rf_control/cnt_frechange_top[22]" - }, - { - "name": "u_rf_control/cnt_frechange_top[21]" - }, - { - "name": "u_rf_control/cnt_frechange_top[20]" - }, - { - "name": "u_rf_control/cnt_frechange_top[19]" - }, - { - "name": "u_rf_control/cnt_frechange_top[18]" - }, - { - "name": "u_rf_control/cnt_frechange_top[17]" - }, - { - "name": "u_rf_control/cnt_frechange_top[16]" - }, - { - "name": "u_rf_control/cnt_frechange_top[15]" - }, - { - "name": "u_rf_control/cnt_frechange_top[14]" - }, - { - "name": "u_rf_control/cnt_frechange_top[13]" - }, - { - "name": "u_rf_control/cnt_frechange_top[12]" - }, - { - "name": "u_rf_control/cnt_frechange_top[11]" - }, - { - "name": "u_rf_control/cnt_frechange_top[10]" - }, - { - "name": "u_rf_control/cnt_frechange_top[9]" - }, - { - "name": "u_rf_control/cnt_frechange_top[8]" - }, - { - "name": "u_rf_control/cnt_frechange_top[7]" - }, - { - "name": "u_rf_control/cnt_frechange_top[6]" - }, - { - "name": "u_rf_control/cnt_frechange_top[5]" - }, - { - "name": "u_rf_control/cnt_frechange_top[4]" - }, - { - "name": "u_rf_control/cnt_frechange_top[3]" - }, - { - "name": "u_rf_control/cnt_frechange_top[2]" - }, - { - "name": "u_rf_control/cnt_frechange_top[1]" - }, - { - "name": "u_rf_control/cnt_frechange_top[0]" - } - ] - } - ] - }, - { - "name": "probe_out4", - "id": 26, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 4, - "nets": [ - { - "name": "u_rf_control/freq_hop_change", - "isBus": false - } - ] - }, - { - "name": "probe_out5", - "id": 27, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 11, - "portIndex": 5, - "nets": [ - { - "name": "u_rf_control/freq_hop_words_vio1", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/freq_hop_words_vio1[11]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[10]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[9]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[8]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[7]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[6]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[5]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[4]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[3]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[2]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[1]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[0]" - } - ] - } - ] - }, - { - "name": "probe_out6", - "id": 28, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 11, - "portIndex": 6, - "nets": [ - { - "name": "u_rf_control/freq_hop_words_vio2", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/freq_hop_words_vio2[11]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[10]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[9]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[8]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[7]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[6]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[5]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[4]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[3]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[2]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[1]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[0]" - } - ] - } - ] - }, - { - "name": "probe_out7", - "id": 29, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 7, - "nets": [ - { - "name": "u_rf_control/switch_delay_time", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/switch_delay_time[31]" - }, - { - "name": "u_rf_control/switch_delay_time[30]" - }, - { - "name": "u_rf_control/switch_delay_time[29]" - }, - { - "name": "u_rf_control/switch_delay_time[28]" - }, - { - "name": "u_rf_control/switch_delay_time[27]" - }, - { - "name": "u_rf_control/switch_delay_time[26]" - }, - { - "name": "u_rf_control/switch_delay_time[25]" - }, - { - "name": "u_rf_control/switch_delay_time[24]" - }, - { - "name": "u_rf_control/switch_delay_time[23]" - }, - { - "name": "u_rf_control/switch_delay_time[22]" - }, - { - "name": "u_rf_control/switch_delay_time[21]" - }, - { - "name": "u_rf_control/switch_delay_time[20]" - }, - { - "name": "u_rf_control/switch_delay_time[19]" - }, - { - "name": "u_rf_control/switch_delay_time[18]" - }, - { - "name": "u_rf_control/switch_delay_time[17]" - }, - { - "name": "u_rf_control/switch_delay_time[16]" - }, - { - "name": "u_rf_control/switch_delay_time[15]" - }, - { - "name": "u_rf_control/switch_delay_time[14]" - }, - { - "name": "u_rf_control/switch_delay_time[13]" - }, - { - "name": "u_rf_control/switch_delay_time[12]" - }, - { - "name": "u_rf_control/switch_delay_time[11]" - }, - { - "name": "u_rf_control/switch_delay_time[10]" - }, - { - "name": "u_rf_control/switch_delay_time[9]" - }, - { - "name": "u_rf_control/switch_delay_time[8]" - }, - { - "name": "u_rf_control/switch_delay_time[7]" - }, - { - "name": "u_rf_control/switch_delay_time[6]" - }, - { - "name": "u_rf_control/switch_delay_time[5]" - }, - { - "name": "u_rf_control/switch_delay_time[4]" - }, - { - "name": "u_rf_control/switch_delay_time[3]" - }, - { - "name": "u_rf_control/switch_delay_time[2]" - }, - { - "name": "u_rf_control/switch_delay_time[1]" - }, - { - "name": "u_rf_control/switch_delay_time[0]" - } - ] - } - ] - }, - { - "name": "probe_out8", - "id": 30, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 8, - "nets": [ - { - "name": "u_rf_control/valid_delay_time_max", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/valid_delay_time_max[31]" - }, - { - "name": "u_rf_control/valid_delay_time_max[30]" - }, - { - "name": "u_rf_control/valid_delay_time_max[29]" - }, - { - "name": "u_rf_control/valid_delay_time_max[28]" - }, - { - "name": "u_rf_control/valid_delay_time_max[27]" - }, - { - "name": "u_rf_control/valid_delay_time_max[26]" - }, - { - "name": "u_rf_control/valid_delay_time_max[25]" - }, - { - "name": "u_rf_control/valid_delay_time_max[24]" - }, - { - "name": "u_rf_control/valid_delay_time_max[23]" - }, - { - "name": "u_rf_control/valid_delay_time_max[22]" - }, - { - "name": "u_rf_control/valid_delay_time_max[21]" - }, - { - "name": "u_rf_control/valid_delay_time_max[20]" - }, - { - "name": "u_rf_control/valid_delay_time_max[19]" - }, - { - "name": "u_rf_control/valid_delay_time_max[18]" - }, - { - "name": "u_rf_control/valid_delay_time_max[17]" - }, - { - "name": "u_rf_control/valid_delay_time_max[16]" - }, - { - "name": "u_rf_control/valid_delay_time_max[15]" - }, - { - "name": "u_rf_control/valid_delay_time_max[14]" - }, - { - "name": "u_rf_control/valid_delay_time_max[13]" - }, - { - "name": "u_rf_control/valid_delay_time_max[12]" - }, - { - "name": "u_rf_control/valid_delay_time_max[11]" - }, - { - "name": "u_rf_control/valid_delay_time_max[10]" - }, - { - "name": "u_rf_control/valid_delay_time_max[9]" - }, - { - "name": "u_rf_control/valid_delay_time_max[8]" - }, - { - "name": "u_rf_control/valid_delay_time_max[7]" - }, - { - "name": "u_rf_control/valid_delay_time_max[6]" - }, - { - "name": "u_rf_control/valid_delay_time_max[5]" - }, - { - "name": "u_rf_control/valid_delay_time_max[4]" - }, - { - "name": "u_rf_control/valid_delay_time_max[3]" - }, - { - "name": "u_rf_control/valid_delay_time_max[2]" - }, - { - "name": "u_rf_control/valid_delay_time_max[1]" - }, - { - "name": "u_rf_control/valid_delay_time_max[0]" - } - ] - } - ] - }, - { - "name": "probe_out9", - "id": 31, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 63, - "portIndex": 9, - "nets": [ - { - "name": "u_rf_control/slot_vio_time", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/slot_vio_time[63]" - }, - { - "name": "u_rf_control/slot_vio_time[62]" - }, - { - "name": "u_rf_control/slot_vio_time[61]" - }, - { - "name": "u_rf_control/slot_vio_time[60]" - }, - { - "name": "u_rf_control/slot_vio_time[59]" - }, - { - "name": "u_rf_control/slot_vio_time[58]" - }, - { - "name": "u_rf_control/slot_vio_time[57]" - }, - { - "name": "u_rf_control/slot_vio_time[56]" - }, - { - "name": "u_rf_control/slot_vio_time[55]" - }, - { - "name": "u_rf_control/slot_vio_time[54]" - }, - { - "name": "u_rf_control/slot_vio_time[53]" - }, - { - "name": "u_rf_control/slot_vio_time[52]" - }, - { - "name": "u_rf_control/slot_vio_time[51]" - }, - { - "name": "u_rf_control/slot_vio_time[50]" - }, - { - "name": "u_rf_control/slot_vio_time[49]" - }, - { - "name": "u_rf_control/slot_vio_time[48]" - }, - { - "name": "u_rf_control/slot_vio_time[47]" - }, - { - "name": "u_rf_control/slot_vio_time[46]" - }, - { - "name": "u_rf_control/slot_vio_time[45]" - }, - { - "name": "u_rf_control/slot_vio_time[44]" - }, - { - "name": "u_rf_control/slot_vio_time[43]" - }, - { - "name": "u_rf_control/slot_vio_time[42]" - }, - { - "name": "u_rf_control/slot_vio_time[41]" - }, - { - "name": "u_rf_control/slot_vio_time[40]" - }, - { - "name": "u_rf_control/slot_vio_time[39]" - }, - { - "name": "u_rf_control/slot_vio_time[38]" - }, - { - "name": "u_rf_control/slot_vio_time[37]" - }, - { - "name": "u_rf_control/slot_vio_time[36]" - }, - { - "name": "u_rf_control/slot_vio_time[35]" - }, - { - "name": "u_rf_control/slot_vio_time[34]" - }, - { - "name": "u_rf_control/slot_vio_time[33]" - }, - { - "name": "u_rf_control/slot_vio_time[32]" - }, - { - "name": "u_rf_control/slot_vio_time[31]" - }, - { - "name": "u_rf_control/slot_vio_time[30]" - }, - { - "name": "u_rf_control/slot_vio_time[29]" - }, - { - "name": "u_rf_control/slot_vio_time[28]" - }, - { - "name": "u_rf_control/slot_vio_time[27]" - }, - { - "name": "u_rf_control/slot_vio_time[26]" - }, - { - "name": "u_rf_control/slot_vio_time[25]" - }, - { - "name": "u_rf_control/slot_vio_time[24]" - }, - { - "name": "u_rf_control/slot_vio_time[23]" - }, - { - "name": "u_rf_control/slot_vio_time[22]" - }, - { - "name": "u_rf_control/slot_vio_time[21]" - }, - { - "name": "u_rf_control/slot_vio_time[20]" - }, - { - "name": "u_rf_control/slot_vio_time[19]" - }, - { - "name": "u_rf_control/slot_vio_time[18]" - }, - { - "name": "u_rf_control/slot_vio_time[17]" - }, - { - "name": "u_rf_control/slot_vio_time[16]" - }, - { - "name": "u_rf_control/slot_vio_time[15]" - }, - { - "name": "u_rf_control/slot_vio_time[14]" - }, - { - "name": "u_rf_control/slot_vio_time[13]" - }, - { - "name": "u_rf_control/slot_vio_time[12]" - }, - { - "name": "u_rf_control/slot_vio_time[11]" - }, - { - "name": "u_rf_control/slot_vio_time[10]" - }, - { - "name": "u_rf_control/slot_vio_time[9]" - }, - { - "name": "u_rf_control/slot_vio_time[8]" - }, - { - "name": "u_rf_control/slot_vio_time[7]" - }, - { - "name": "u_rf_control/slot_vio_time[6]" - }, - { - "name": "u_rf_control/slot_vio_time[5]" - }, - { - "name": "u_rf_control/slot_vio_time[4]" - }, - { - "name": "u_rf_control/slot_vio_time[3]" - }, - { - "name": "u_rf_control/slot_vio_time[2]" - }, - { - "name": "u_rf_control/slot_vio_time[1]" - }, - { - "name": "u_rf_control/slot_vio_time[0]" - } - ] - } - ] - }, - { - "name": "probe_out10", - "id": 32, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 4, - "portIndex": 10, - "nets": [ - { - "name": "u_rf_control/cnt_slot_max", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/cnt_slot_max[4]" - }, - { - "name": "u_rf_control/cnt_slot_max[3]" - }, - { - "name": "u_rf_control/cnt_slot_max[2]" - }, - { - "name": "u_rf_control/cnt_slot_max[1]" - }, - { - "name": "u_rf_control/cnt_slot_max[0]" - } - ] - } - ] - }, - { - "name": "probe_out11", - "id": 33, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 11, - "nets": [ - { - "name": "u_rf_control/freq_swicth_start", - "isBus": false - } - ] - } - ] - }, - { - "type": "VIO_V2", - "name": "u_vio_manual_ctrl", - "spec": "labtools_vio_v3", - "ipName": "vio", - "core_location": { - "user_chain": 1, - "slave_index": 5, - "bscan_switch_index": 0 - }, "uuid": "6DFBBD640CB857419C054C66C7EA7B27", "pins": [ { "name": "probe_out0", - "id": 34, + "id": 21, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1678,7 +785,7 @@ }, { "name": "probe_out1", - "id": 35, + "id": 22, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1694,7 +801,7 @@ }, { "name": "probe_out2", - "id": 36, + "id": 23, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1808,7 +915,7 @@ }, { "name": "probe_out3", - "id": 37, + "id": 24, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1832,7 +939,7 @@ }, { "name": "probe_out4", - "id": 38, + "id": 25, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1869,65 +976,14 @@ "ipName": "vio", "core_location": { "user_chain": 1, - "slave_index": 6, + "slave_index": 5, "bscan_switch_index": 0 }, "uuid": "364BEEA5FFA15F6D870138E33BF7A4F4", "pins": [ - { - "name": "probe_in0", - "id": 39, - "type": "DATA", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 10, - "portIndex": 0, - "nets": [ - { - "name": "freq_hop_words_auto", - "isBus": true, - "subnets": [ - { - "name": "freq_hop_words_auto[10]" - }, - { - "name": "freq_hop_words_auto[9]" - }, - { - "name": "freq_hop_words_auto[8]" - }, - { - "name": "freq_hop_words_auto[7]" - }, - { - "name": "freq_hop_words_auto[6]" - }, - { - "name": "freq_hop_words_auto[5]" - }, - { - "name": "freq_hop_words_auto[4]" - }, - { - "name": "freq_hop_words_auto[3]" - }, - { - "name": "freq_hop_words_auto[2]" - }, - { - "name": "freq_hop_words_auto[1]" - }, - { - "name": "freq_hop_words_auto[0]" - } - ] - } - ] - }, { "name": "probe_out0", - "id": 40, + "id": 26, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1936,14 +992,14 @@ "portIndex": 0, "nets": [ { - "name": "gain_on_vio", + "name": "vio_set_trx", "isBus": false } ] }, { "name": "probe_out1", - "id": 41, + "id": 27, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1967,7 +1023,7 @@ }, { "name": "probe_out2", - "id": 42, + "id": 28, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1976,25 +1032,31 @@ "portIndex": 2, "nets": [ { - "name": "rf_vio_set", + "name": "vio_set_freq", "isBus": false } ] }, { "name": "probe_out3", - "id": 43, + "id": 29, "type": "DATA", "direction": "OUT", "isVector": true, "leftIndex": 0, - "rightIndex": 5, + "rightIndex": 7, "portIndex": 3, "nets": [ { "name": "tx_gain_manual", "isBus": true, "subnets": [ + { + "name": "tx_gain_manual[7]" + }, + { + "name": "tx_gain_manual[6]" + }, { "name": "tx_gain_manual[5]" }, @@ -2019,18 +1081,24 @@ }, { "name": "probe_out4", - "id": 44, + "id": 30, "type": "DATA", "direction": "OUT", "isVector": true, "leftIndex": 0, - "rightIndex": 5, + "rightIndex": 7, "portIndex": 4, "nets": [ { "name": "rx_gain_manual", "isBus": true, "subnets": [ + { + "name": "rx_gain_manual[7]" + }, + { + "name": "rx_gain_manual[6]" + }, { "name": "rx_gain_manual[5]" }, @@ -2055,7 +1123,7 @@ }, { "name": "probe_out5", - "id": 45, + "id": 31, "type": "DATA", "direction": "OUT", "isVector": true, @@ -2109,7 +1177,7 @@ }, { "name": "probe_out6", - "id": 46, + "id": 32, "type": "DATA", "direction": "OUT", "isVector": false, @@ -2125,7 +1193,7 @@ }, { "name": "probe_out7", - "id": 47, + "id": 33, "type": "DATA", "direction": "OUT", "isVector": false, @@ -2141,7 +1209,7 @@ }, { "name": "probe_out8", - "id": 48, + "id": 34, "type": "DATA", "direction": "OUT", "isVector": false, @@ -2150,318 +1218,10 @@ "portIndex": 8, "nets": [ { - "name": "self_check_dout", + "name": "rf_config_valid", "isBus": false } ] - }, - { - "name": "probe_out9", - "id": 49, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 9, - "nets": [ - { - "name": "rf_auto_start_vio", - "isBus": false - } - ] - }, - { - "name": "probe_out10", - "id": 50, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 10, - "nets": [ - { - "name": "rf_ctrl_mode_vio", - "isBus": false - } - ] - }, - { - "name": "probe_out11", - "id": 51, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 11, - "nets": [ - { - "name": "switch_next_freq_vio", - "isBus": false - } - ] - }, - { - "name": "probe_out12", - "id": 52, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 12, - "nets": [ - { - "name": "switch_last_freq_vio", - "isBus": false - } - ] - }, - { - "name": "probe_out13", - "id": 53, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 13, - "nets": [ - { - "name": "cnt_valid_to_switch_vio", - "isBus": true, - "subnets": [ - { - "name": "cnt_valid_to_switch_vio[31]" - }, - { - "name": "cnt_valid_to_switch_vio[30]" - }, - { - "name": "cnt_valid_to_switch_vio[29]" - }, - { - "name": "cnt_valid_to_switch_vio[28]" - }, - { - "name": "cnt_valid_to_switch_vio[27]" - }, - { - "name": "cnt_valid_to_switch_vio[26]" - }, - { - "name": "cnt_valid_to_switch_vio[25]" - }, - { - "name": "cnt_valid_to_switch_vio[24]" - }, - { - "name": "cnt_valid_to_switch_vio[23]" - }, - { - "name": "cnt_valid_to_switch_vio[22]" - }, - { - "name": "cnt_valid_to_switch_vio[21]" - }, - { - "name": "cnt_valid_to_switch_vio[20]" - }, - { - "name": "cnt_valid_to_switch_vio[19]" - }, - { - "name": "cnt_valid_to_switch_vio[18]" - }, - { - "name": "cnt_valid_to_switch_vio[17]" - }, - { - "name": "cnt_valid_to_switch_vio[16]" - }, - { - "name": "cnt_valid_to_switch_vio[15]" - }, - { - "name": "cnt_valid_to_switch_vio[14]" - }, - { - "name": "cnt_valid_to_switch_vio[13]" - }, - { - "name": "cnt_valid_to_switch_vio[12]" - }, - { - "name": "cnt_valid_to_switch_vio[11]" - }, - { - "name": "cnt_valid_to_switch_vio[10]" - }, - { - "name": "cnt_valid_to_switch_vio[9]" - }, - { - "name": "cnt_valid_to_switch_vio[8]" - }, - { - "name": "cnt_valid_to_switch_vio[7]" - }, - { - "name": "cnt_valid_to_switch_vio[6]" - }, - { - "name": "cnt_valid_to_switch_vio[5]" - }, - { - "name": "cnt_valid_to_switch_vio[4]" - }, - { - "name": "cnt_valid_to_switch_vio[3]" - }, - { - "name": "cnt_valid_to_switch_vio[2]" - }, - { - "name": "cnt_valid_to_switch_vio[1]" - }, - { - "name": "cnt_valid_to_switch_vio[0]" - } - ] - } - ] - }, - { - "name": "probe_out14", - "id": 54, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 14, - "nets": [ - { - "name": "auto_test_enable_vio", - "isBus": false - } - ] - }, - { - "name": "probe_out15", - "id": 55, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 15, - "nets": [ - { - "name": "test_slot_length_vio", - "isBus": true, - "subnets": [ - { - "name": "test_slot_length_vio[31]" - }, - { - "name": "test_slot_length_vio[30]" - }, - { - "name": "test_slot_length_vio[29]" - }, - { - "name": "test_slot_length_vio[28]" - }, - { - "name": "test_slot_length_vio[27]" - }, - { - "name": "test_slot_length_vio[26]" - }, - { - "name": "test_slot_length_vio[25]" - }, - { - "name": "test_slot_length_vio[24]" - }, - { - "name": "test_slot_length_vio[23]" - }, - { - "name": "test_slot_length_vio[22]" - }, - { - "name": "test_slot_length_vio[21]" - }, - { - "name": "test_slot_length_vio[20]" - }, - { - "name": "test_slot_length_vio[19]" - }, - { - "name": "test_slot_length_vio[18]" - }, - { - "name": "test_slot_length_vio[17]" - }, - { - "name": "test_slot_length_vio[16]" - }, - { - "name": "test_slot_length_vio[15]" - }, - { - "name": "test_slot_length_vio[14]" - }, - { - "name": "test_slot_length_vio[13]" - }, - { - "name": "test_slot_length_vio[12]" - }, - { - "name": "test_slot_length_vio[11]" - }, - { - "name": "test_slot_length_vio[10]" - }, - { - "name": "test_slot_length_vio[9]" - }, - { - "name": "test_slot_length_vio[8]" - }, - { - "name": "test_slot_length_vio[7]" - }, - { - "name": "test_slot_length_vio[6]" - }, - { - "name": "test_slot_length_vio[5]" - }, - { - "name": "test_slot_length_vio[4]" - }, - { - "name": "test_slot_length_vio[3]" - }, - { - "name": "test_slot_length_vio[2]" - }, - { - "name": "test_slot_length_vio[1]" - }, - { - "name": "test_slot_length_vio[0]" - } - ] - } - ] } ] } @@ -2469,7 +1229,7 @@ "parent_nets": [ { "id": 18, - "name": "u_rf_control/clk_12M", + "name": "u_rf_control/spi_attn_clk", "state_reg": [ { "name": "u_rf_control/FSM_sequential_state_MOSI_reg[0]", diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.bit b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.bit index 48ffee4d..a7162a1e 100644 Binary files a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.bit and b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.bit differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.ltx b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.ltx index 4351693b..c6cf2cfb 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.ltx +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.ltx @@ -11,11 +11,11 @@ "type": "XSDB_V3", "name": "dbg_hub", "spec": "labtools_xsdbm_v3", - "clk_input_freq_hz": "122880320" + "clk_input_freq_hz": "192000507" }, { "type": "ILA_V3", - "name": "ila_rf_test", + "name": "u_ila_ctrl_signal", "spec": "labtools_ila_v6", "ipName": "ila", "core_location": { @@ -23,13 +23,123 @@ "slave_index": 0, "bscan_switch_index": 0 }, - "uuid": "C3E203EDC3EB51B199EEE872BD8D49EB", + "uuid": "46B6B100E72A58A8A2087FA72DC35D0B", "pins": [ { "name": "probe0", "id": 0, "type": "DATA_TRIGGER", "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 0, + "nets": [ + { + "name": "jesd_reset", + "isBus": false + } + ] + }, + { + "name": "probe1", + "id": 1, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "rx_sync", + "isBus": false + } + ] + }, + { + "name": "probe2", + "id": 2, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 2, + "nets": [ + { + "name": "rx_rstn", + "isBus": false + } + ] + }, + { + "name": "probe3", + "id": 3, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 3, + "nets": [ + { + "name": "tx_sync", + "isBus": false + } + ] + }, + { + "name": "probe4", + "id": 4, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 4, + "nets": [ + { + "name": "tx_rstn", + "isBus": false + } + ] + }, + { + "name": "probe5", + "id": 5, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 5, + "nets": [ + { + "name": "sysref", + "isBus": false + } + ] + } + ] + }, + { + "type": "ILA_V3", + "name": "u_ila_rf_test", + "spec": "labtools_ila_v6", + "ipName": "ila", + "core_location": { + "user_chain": 1, + "slave_index": 1, + "bscan_switch_index": 0 + }, + "uuid": "E5E249F0F463550991043737009BC5E0", + "pins": [ + { + "name": "probe0", + "id": 6, + "type": "DATA_TRIGGER", + "direction": "IN", "isVector": true, "leftIndex": 0, "rightIndex": 11, @@ -81,13 +191,78 @@ }, { "name": "probe1", - "id": 1, + "id": 7, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, "leftIndex": 0, "rightIndex": 0, "portIndex": 1, + "nets": [ + { + "name": "rf_spi_attn_clk_OBUF", + "isBus": false, + "parentNetId": 18 + } + ] + }, + { + "name": "probe2", + "id": 8, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 2, + "nets": [ + { + "name": "rf_spi_attn_csn_OBUF", + "isBus": false + } + ] + }, + { + "name": "probe3", + "id": 9, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 3, + "nets": [ + { + "name": "rf_spi_attn_mosi_OBUF", + "isBus": false + } + ] + }, + { + "name": "probe4", + "id": 10, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 4, + "nets": [ + { + "name": "rf_spi_attn_miso_IBUF", + "isBus": false + } + ] + }, + { + "name": "probe5", + "id": 11, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 5, "nets": [ { "name": "tx_gain_on_OBUF", @@ -95,73 +270,9 @@ } ] }, - { - "name": "probe2", - "id": 2, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 2, - "nets": [ - { - "name": "rx_gain_IBUF", - "isBus": false - } - ] - }, - { - "name": "probe3", - "id": 3, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 3, - "nets": [ - { - "name": "rx_gain_on_OBUF", - "isBus": false - } - ] - }, - { - "name": "probe4", - "id": 4, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 4, - "nets": [ - { - "name": "tx_gain_OBUF", - "isBus": false - } - ] - }, - { - "name": "probe5", - "id": 5, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 5, - "nets": [ - { - "name": "hop_words_valid_OBUF", - "isBus": false - } - ] - }, { "name": "probe6", - "id": 6, + "id": 12, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, @@ -170,14 +281,14 @@ "portIndex": 6, "nets": [ { - "name": "freq_hop_switch_OBUF", + "name": "rx_gain_on_OBUF", "isBus": false } ] }, { "name": "probe7", - "id": 7, + "id": 13, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, @@ -186,15 +297,14 @@ "portIndex": 7, "nets": [ { - "name": "clk_12M_OBUF", - "isBus": false, - "parentNetId": 18 + "name": "hop_words_valid_OBUF", + "isBus": false } ] }, { "name": "probe8", - "id": 8, + "id": 14, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, @@ -203,171 +313,7 @@ "portIndex": 8, "nets": [ { - "name": "CS_rf_OBUF", - "isBus": false - } - ] - }, - { - "name": "probe9", - "id": 9, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 11, - "portIndex": 9, - "nets": [ - { - "name": "freq_hop_words_sweep", - "isBus": true, - "subnets": [ - { - "name": "freq_hop_words_sweep[11]" - }, - { - "name": "freq_hop_words_sweep[10]" - }, - { - "name": "freq_hop_words_sweep[9]" - }, - { - "name": "freq_hop_words_sweep[8]" - }, - { - "name": "freq_hop_words_sweep[7]" - }, - { - "name": "freq_hop_words_sweep[6]" - }, - { - "name": "freq_hop_words_sweep[5]" - }, - { - "name": "freq_hop_words_sweep[4]" - }, - { - "name": "freq_hop_words_sweep[3]" - }, - { - "name": "freq_hop_words_sweep[2]" - }, - { - "name": "freq_hop_words_sweep[1]" - }, - { - "name": "freq_hop_words_sweep[0]" - } - ] - } - ] - } - ] - }, - { - "type": "ILA_V3", - "name": "u_ila_ctrl_signal", - "spec": "labtools_ila_v6", - "ipName": "ila", - "core_location": { - "user_chain": 1, - "slave_index": 1, - "bscan_switch_index": 0 - }, - "uuid": "46B6B100E72A58A8A2087FA72DC35D0B", - "pins": [ - { - "name": "probe0", - "id": 10, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 0, - "nets": [ - { - "name": "jesd_reset", - "isBus": false - } - ] - }, - { - "name": "probe1", - "id": 11, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 1, - "nets": [ - { - "name": "rx_sync", - "isBus": false - } - ] - }, - { - "name": "probe2", - "id": 12, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 2, - "nets": [ - { - "name": "rx_rstn", - "isBus": false - } - ] - }, - { - "name": "probe3", - "id": 13, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 3, - "nets": [ - { - "name": "tx_sync", - "isBus": false - } - ] - }, - { - "name": "probe4", - "id": 14, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 4, - "nets": [ - { - "name": "tx_rstn", - "isBus": false - } - ] - }, - { - "name": "probe5", - "id": 15, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 5, - "nets": [ - { - "name": "sysref", + "name": "freq_hop_switch_OBUF", "isBus": false } ] @@ -388,7 +334,7 @@ "pins": [ { "name": "probe0", - "id": 16, + "id": 15, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -454,7 +400,7 @@ }, { "name": "probe1", - "id": 17, + "id": 16, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -520,7 +466,7 @@ }, { "name": "probe2", - "id": 18, + "id": 17, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -586,7 +532,7 @@ }, { "name": "probe3", - "id": 19, + "id": 18, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -666,7 +612,7 @@ "pins": [ { "name": "probe0", - "id": 20, + "id": 19, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -732,7 +678,7 @@ }, { "name": "probe1", - "id": 21, + "id": 20, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -800,7 +746,7 @@ }, { "type": "VIO_V2", - "name": "u_rf_control/vio_rf_test", + "name": "u_vio_manual_ctrl", "spec": "labtools_vio_v3", "ipName": "vio", "core_location": { @@ -808,850 +754,11 @@ "slave_index": 4, "bscan_switch_index": 0 }, - "uuid": "8F1E87AA41105143AA018CE9B35278A7", - "pins": [ - { - "name": "probe_out0", - "id": 22, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 0, - "nets": [ - { - "name": "u_rf_control/CS_rf_flag", - "isBus": false - } - ] - }, - { - "name": "probe_out1", - "id": 23, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 7, - "portIndex": 1, - "nets": [ - { - "name": "u_rf_control/MOSI_tx_atte", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/MOSI_tx_atte[7]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[6]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[5]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[4]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[3]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[2]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[1]" - }, - { - "name": "u_rf_control/MOSI_tx_atte[0]" - } - ] - } - ] - }, - { - "name": "probe_out2", - "id": 24, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 7, - "portIndex": 2, - "nets": [ - { - "name": "u_rf_control/MOSI_rx_atte", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/MOSI_rx_atte[7]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[6]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[5]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[4]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[3]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[2]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[1]" - }, - { - "name": "u_rf_control/MOSI_rx_atte[0]" - } - ] - } - ] - }, - { - "name": "probe_out3", - "id": 25, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 3, - "nets": [ - { - "name": "u_rf_control/cnt_frechange_top", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/cnt_frechange_top[31]" - }, - { - "name": "u_rf_control/cnt_frechange_top[30]" - }, - { - "name": "u_rf_control/cnt_frechange_top[29]" - }, - { - "name": "u_rf_control/cnt_frechange_top[28]" - }, - { - "name": "u_rf_control/cnt_frechange_top[27]" - }, - { - "name": "u_rf_control/cnt_frechange_top[26]" - }, - { - "name": "u_rf_control/cnt_frechange_top[25]" - }, - { - "name": "u_rf_control/cnt_frechange_top[24]" - }, - { - "name": "u_rf_control/cnt_frechange_top[23]" - }, - { - "name": "u_rf_control/cnt_frechange_top[22]" - }, - { - "name": "u_rf_control/cnt_frechange_top[21]" - }, - { - "name": "u_rf_control/cnt_frechange_top[20]" - }, - { - "name": "u_rf_control/cnt_frechange_top[19]" - }, - { - "name": "u_rf_control/cnt_frechange_top[18]" - }, - { - "name": "u_rf_control/cnt_frechange_top[17]" - }, - { - "name": "u_rf_control/cnt_frechange_top[16]" - }, - { - "name": "u_rf_control/cnt_frechange_top[15]" - }, - { - "name": "u_rf_control/cnt_frechange_top[14]" - }, - { - "name": "u_rf_control/cnt_frechange_top[13]" - }, - { - "name": "u_rf_control/cnt_frechange_top[12]" - }, - { - "name": "u_rf_control/cnt_frechange_top[11]" - }, - { - "name": "u_rf_control/cnt_frechange_top[10]" - }, - { - "name": "u_rf_control/cnt_frechange_top[9]" - }, - { - "name": "u_rf_control/cnt_frechange_top[8]" - }, - { - "name": "u_rf_control/cnt_frechange_top[7]" - }, - { - "name": "u_rf_control/cnt_frechange_top[6]" - }, - { - "name": "u_rf_control/cnt_frechange_top[5]" - }, - { - "name": "u_rf_control/cnt_frechange_top[4]" - }, - { - "name": "u_rf_control/cnt_frechange_top[3]" - }, - { - "name": "u_rf_control/cnt_frechange_top[2]" - }, - { - "name": "u_rf_control/cnt_frechange_top[1]" - }, - { - "name": "u_rf_control/cnt_frechange_top[0]" - } - ] - } - ] - }, - { - "name": "probe_out4", - "id": 26, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 4, - "nets": [ - { - "name": "u_rf_control/freq_hop_change", - "isBus": false - } - ] - }, - { - "name": "probe_out5", - "id": 27, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 11, - "portIndex": 5, - "nets": [ - { - "name": "u_rf_control/freq_hop_words_vio1", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/freq_hop_words_vio1[11]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[10]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[9]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[8]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[7]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[6]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[5]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[4]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[3]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[2]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[1]" - }, - { - "name": "u_rf_control/freq_hop_words_vio1[0]" - } - ] - } - ] - }, - { - "name": "probe_out6", - "id": 28, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 11, - "portIndex": 6, - "nets": [ - { - "name": "u_rf_control/freq_hop_words_vio2", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/freq_hop_words_vio2[11]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[10]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[9]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[8]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[7]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[6]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[5]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[4]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[3]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[2]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[1]" - }, - { - "name": "u_rf_control/freq_hop_words_vio2[0]" - } - ] - } - ] - }, - { - "name": "probe_out7", - "id": 29, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 7, - "nets": [ - { - "name": "u_rf_control/switch_delay_time", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/switch_delay_time[31]" - }, - { - "name": "u_rf_control/switch_delay_time[30]" - }, - { - "name": "u_rf_control/switch_delay_time[29]" - }, - { - "name": "u_rf_control/switch_delay_time[28]" - }, - { - "name": "u_rf_control/switch_delay_time[27]" - }, - { - "name": "u_rf_control/switch_delay_time[26]" - }, - { - "name": "u_rf_control/switch_delay_time[25]" - }, - { - "name": "u_rf_control/switch_delay_time[24]" - }, - { - "name": "u_rf_control/switch_delay_time[23]" - }, - { - "name": "u_rf_control/switch_delay_time[22]" - }, - { - "name": "u_rf_control/switch_delay_time[21]" - }, - { - "name": "u_rf_control/switch_delay_time[20]" - }, - { - "name": "u_rf_control/switch_delay_time[19]" - }, - { - "name": "u_rf_control/switch_delay_time[18]" - }, - { - "name": "u_rf_control/switch_delay_time[17]" - }, - { - "name": "u_rf_control/switch_delay_time[16]" - }, - { - "name": "u_rf_control/switch_delay_time[15]" - }, - { - "name": "u_rf_control/switch_delay_time[14]" - }, - { - "name": "u_rf_control/switch_delay_time[13]" - }, - { - "name": "u_rf_control/switch_delay_time[12]" - }, - { - "name": "u_rf_control/switch_delay_time[11]" - }, - { - "name": "u_rf_control/switch_delay_time[10]" - }, - { - "name": "u_rf_control/switch_delay_time[9]" - }, - { - "name": "u_rf_control/switch_delay_time[8]" - }, - { - "name": "u_rf_control/switch_delay_time[7]" - }, - { - "name": "u_rf_control/switch_delay_time[6]" - }, - { - "name": "u_rf_control/switch_delay_time[5]" - }, - { - "name": "u_rf_control/switch_delay_time[4]" - }, - { - "name": "u_rf_control/switch_delay_time[3]" - }, - { - "name": "u_rf_control/switch_delay_time[2]" - }, - { - "name": "u_rf_control/switch_delay_time[1]" - }, - { - "name": "u_rf_control/switch_delay_time[0]" - } - ] - } - ] - }, - { - "name": "probe_out8", - "id": 30, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 8, - "nets": [ - { - "name": "u_rf_control/valid_delay_time_max", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/valid_delay_time_max[31]" - }, - { - "name": "u_rf_control/valid_delay_time_max[30]" - }, - { - "name": "u_rf_control/valid_delay_time_max[29]" - }, - { - "name": "u_rf_control/valid_delay_time_max[28]" - }, - { - "name": "u_rf_control/valid_delay_time_max[27]" - }, - { - "name": "u_rf_control/valid_delay_time_max[26]" - }, - { - "name": "u_rf_control/valid_delay_time_max[25]" - }, - { - "name": "u_rf_control/valid_delay_time_max[24]" - }, - { - "name": "u_rf_control/valid_delay_time_max[23]" - }, - { - "name": "u_rf_control/valid_delay_time_max[22]" - }, - { - "name": "u_rf_control/valid_delay_time_max[21]" - }, - { - "name": "u_rf_control/valid_delay_time_max[20]" - }, - { - "name": "u_rf_control/valid_delay_time_max[19]" - }, - { - "name": "u_rf_control/valid_delay_time_max[18]" - }, - { - "name": "u_rf_control/valid_delay_time_max[17]" - }, - { - "name": "u_rf_control/valid_delay_time_max[16]" - }, - { - "name": "u_rf_control/valid_delay_time_max[15]" - }, - { - "name": "u_rf_control/valid_delay_time_max[14]" - }, - { - "name": "u_rf_control/valid_delay_time_max[13]" - }, - { - "name": "u_rf_control/valid_delay_time_max[12]" - }, - { - "name": "u_rf_control/valid_delay_time_max[11]" - }, - { - "name": "u_rf_control/valid_delay_time_max[10]" - }, - { - "name": "u_rf_control/valid_delay_time_max[9]" - }, - { - "name": "u_rf_control/valid_delay_time_max[8]" - }, - { - "name": "u_rf_control/valid_delay_time_max[7]" - }, - { - "name": "u_rf_control/valid_delay_time_max[6]" - }, - { - "name": "u_rf_control/valid_delay_time_max[5]" - }, - { - "name": "u_rf_control/valid_delay_time_max[4]" - }, - { - "name": "u_rf_control/valid_delay_time_max[3]" - }, - { - "name": "u_rf_control/valid_delay_time_max[2]" - }, - { - "name": "u_rf_control/valid_delay_time_max[1]" - }, - { - "name": "u_rf_control/valid_delay_time_max[0]" - } - ] - } - ] - }, - { - "name": "probe_out9", - "id": 31, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 63, - "portIndex": 9, - "nets": [ - { - "name": "u_rf_control/slot_vio_time", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/slot_vio_time[63]" - }, - { - "name": "u_rf_control/slot_vio_time[62]" - }, - { - "name": "u_rf_control/slot_vio_time[61]" - }, - { - "name": "u_rf_control/slot_vio_time[60]" - }, - { - "name": "u_rf_control/slot_vio_time[59]" - }, - { - "name": "u_rf_control/slot_vio_time[58]" - }, - { - "name": "u_rf_control/slot_vio_time[57]" - }, - { - "name": "u_rf_control/slot_vio_time[56]" - }, - { - "name": "u_rf_control/slot_vio_time[55]" - }, - { - "name": "u_rf_control/slot_vio_time[54]" - }, - { - "name": "u_rf_control/slot_vio_time[53]" - }, - { - "name": "u_rf_control/slot_vio_time[52]" - }, - { - "name": "u_rf_control/slot_vio_time[51]" - }, - { - "name": "u_rf_control/slot_vio_time[50]" - }, - { - "name": "u_rf_control/slot_vio_time[49]" - }, - { - "name": "u_rf_control/slot_vio_time[48]" - }, - { - "name": "u_rf_control/slot_vio_time[47]" - }, - { - "name": "u_rf_control/slot_vio_time[46]" - }, - { - "name": "u_rf_control/slot_vio_time[45]" - }, - { - "name": "u_rf_control/slot_vio_time[44]" - }, - { - "name": "u_rf_control/slot_vio_time[43]" - }, - { - "name": "u_rf_control/slot_vio_time[42]" - }, - { - "name": "u_rf_control/slot_vio_time[41]" - }, - { - "name": "u_rf_control/slot_vio_time[40]" - }, - { - "name": "u_rf_control/slot_vio_time[39]" - }, - { - "name": "u_rf_control/slot_vio_time[38]" - }, - { - "name": "u_rf_control/slot_vio_time[37]" - }, - { - "name": "u_rf_control/slot_vio_time[36]" - }, - { - "name": "u_rf_control/slot_vio_time[35]" - }, - { - "name": "u_rf_control/slot_vio_time[34]" - }, - { - "name": "u_rf_control/slot_vio_time[33]" - }, - { - "name": "u_rf_control/slot_vio_time[32]" - }, - { - "name": "u_rf_control/slot_vio_time[31]" - }, - { - "name": "u_rf_control/slot_vio_time[30]" - }, - { - "name": "u_rf_control/slot_vio_time[29]" - }, - { - "name": "u_rf_control/slot_vio_time[28]" - }, - { - "name": "u_rf_control/slot_vio_time[27]" - }, - { - "name": "u_rf_control/slot_vio_time[26]" - }, - { - "name": "u_rf_control/slot_vio_time[25]" - }, - { - "name": "u_rf_control/slot_vio_time[24]" - }, - { - "name": "u_rf_control/slot_vio_time[23]" - }, - { - "name": "u_rf_control/slot_vio_time[22]" - }, - { - "name": "u_rf_control/slot_vio_time[21]" - }, - { - "name": "u_rf_control/slot_vio_time[20]" - }, - { - "name": "u_rf_control/slot_vio_time[19]" - }, - { - "name": "u_rf_control/slot_vio_time[18]" - }, - { - "name": "u_rf_control/slot_vio_time[17]" - }, - { - "name": "u_rf_control/slot_vio_time[16]" - }, - { - "name": "u_rf_control/slot_vio_time[15]" - }, - { - "name": "u_rf_control/slot_vio_time[14]" - }, - { - "name": "u_rf_control/slot_vio_time[13]" - }, - { - "name": "u_rf_control/slot_vio_time[12]" - }, - { - "name": "u_rf_control/slot_vio_time[11]" - }, - { - "name": "u_rf_control/slot_vio_time[10]" - }, - { - "name": "u_rf_control/slot_vio_time[9]" - }, - { - "name": "u_rf_control/slot_vio_time[8]" - }, - { - "name": "u_rf_control/slot_vio_time[7]" - }, - { - "name": "u_rf_control/slot_vio_time[6]" - }, - { - "name": "u_rf_control/slot_vio_time[5]" - }, - { - "name": "u_rf_control/slot_vio_time[4]" - }, - { - "name": "u_rf_control/slot_vio_time[3]" - }, - { - "name": "u_rf_control/slot_vio_time[2]" - }, - { - "name": "u_rf_control/slot_vio_time[1]" - }, - { - "name": "u_rf_control/slot_vio_time[0]" - } - ] - } - ] - }, - { - "name": "probe_out10", - "id": 32, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 4, - "portIndex": 10, - "nets": [ - { - "name": "u_rf_control/cnt_slot_max", - "isBus": true, - "subnets": [ - { - "name": "u_rf_control/cnt_slot_max[4]" - }, - { - "name": "u_rf_control/cnt_slot_max[3]" - }, - { - "name": "u_rf_control/cnt_slot_max[2]" - }, - { - "name": "u_rf_control/cnt_slot_max[1]" - }, - { - "name": "u_rf_control/cnt_slot_max[0]" - } - ] - } - ] - }, - { - "name": "probe_out11", - "id": 33, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 11, - "nets": [ - { - "name": "u_rf_control/freq_swicth_start", - "isBus": false - } - ] - } - ] - }, - { - "type": "VIO_V2", - "name": "u_vio_manual_ctrl", - "spec": "labtools_vio_v3", - "ipName": "vio", - "core_location": { - "user_chain": 1, - "slave_index": 5, - "bscan_switch_index": 0 - }, "uuid": "6DFBBD640CB857419C054C66C7EA7B27", "pins": [ { "name": "probe_out0", - "id": 34, + "id": 21, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1678,7 +785,7 @@ }, { "name": "probe_out1", - "id": 35, + "id": 22, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1694,7 +801,7 @@ }, { "name": "probe_out2", - "id": 36, + "id": 23, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1808,7 +915,7 @@ }, { "name": "probe_out3", - "id": 37, + "id": 24, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1832,7 +939,7 @@ }, { "name": "probe_out4", - "id": 38, + "id": 25, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1869,65 +976,14 @@ "ipName": "vio", "core_location": { "user_chain": 1, - "slave_index": 6, + "slave_index": 5, "bscan_switch_index": 0 }, "uuid": "364BEEA5FFA15F6D870138E33BF7A4F4", "pins": [ - { - "name": "probe_in0", - "id": 39, - "type": "DATA", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 10, - "portIndex": 0, - "nets": [ - { - "name": "freq_hop_words_auto", - "isBus": true, - "subnets": [ - { - "name": "freq_hop_words_auto[10]" - }, - { - "name": "freq_hop_words_auto[9]" - }, - { - "name": "freq_hop_words_auto[8]" - }, - { - "name": "freq_hop_words_auto[7]" - }, - { - "name": "freq_hop_words_auto[6]" - }, - { - "name": "freq_hop_words_auto[5]" - }, - { - "name": "freq_hop_words_auto[4]" - }, - { - "name": "freq_hop_words_auto[3]" - }, - { - "name": "freq_hop_words_auto[2]" - }, - { - "name": "freq_hop_words_auto[1]" - }, - { - "name": "freq_hop_words_auto[0]" - } - ] - } - ] - }, { "name": "probe_out0", - "id": 40, + "id": 26, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1936,14 +992,14 @@ "portIndex": 0, "nets": [ { - "name": "gain_on_vio", + "name": "vio_set_trx", "isBus": false } ] }, { "name": "probe_out1", - "id": 41, + "id": 27, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1967,7 +1023,7 @@ }, { "name": "probe_out2", - "id": 42, + "id": 28, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1976,25 +1032,31 @@ "portIndex": 2, "nets": [ { - "name": "rf_vio_set", + "name": "vio_set_freq", "isBus": false } ] }, { "name": "probe_out3", - "id": 43, + "id": 29, "type": "DATA", "direction": "OUT", "isVector": true, "leftIndex": 0, - "rightIndex": 5, + "rightIndex": 7, "portIndex": 3, "nets": [ { "name": "tx_gain_manual", "isBus": true, "subnets": [ + { + "name": "tx_gain_manual[7]" + }, + { + "name": "tx_gain_manual[6]" + }, { "name": "tx_gain_manual[5]" }, @@ -2019,18 +1081,24 @@ }, { "name": "probe_out4", - "id": 44, + "id": 30, "type": "DATA", "direction": "OUT", "isVector": true, "leftIndex": 0, - "rightIndex": 5, + "rightIndex": 7, "portIndex": 4, "nets": [ { "name": "rx_gain_manual", "isBus": true, "subnets": [ + { + "name": "rx_gain_manual[7]" + }, + { + "name": "rx_gain_manual[6]" + }, { "name": "rx_gain_manual[5]" }, @@ -2055,7 +1123,7 @@ }, { "name": "probe_out5", - "id": 45, + "id": 31, "type": "DATA", "direction": "OUT", "isVector": true, @@ -2109,7 +1177,7 @@ }, { "name": "probe_out6", - "id": 46, + "id": 32, "type": "DATA", "direction": "OUT", "isVector": false, @@ -2125,7 +1193,7 @@ }, { "name": "probe_out7", - "id": 47, + "id": 33, "type": "DATA", "direction": "OUT", "isVector": false, @@ -2141,7 +1209,7 @@ }, { "name": "probe_out8", - "id": 48, + "id": 34, "type": "DATA", "direction": "OUT", "isVector": false, @@ -2150,318 +1218,10 @@ "portIndex": 8, "nets": [ { - "name": "self_check_dout", + "name": "rf_config_valid", "isBus": false } ] - }, - { - "name": "probe_out9", - "id": 49, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 9, - "nets": [ - { - "name": "rf_auto_start_vio", - "isBus": false - } - ] - }, - { - "name": "probe_out10", - "id": 50, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 10, - "nets": [ - { - "name": "rf_ctrl_mode_vio", - "isBus": false - } - ] - }, - { - "name": "probe_out11", - "id": 51, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 11, - "nets": [ - { - "name": "switch_next_freq_vio", - "isBus": false - } - ] - }, - { - "name": "probe_out12", - "id": 52, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 12, - "nets": [ - { - "name": "switch_last_freq_vio", - "isBus": false - } - ] - }, - { - "name": "probe_out13", - "id": 53, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 13, - "nets": [ - { - "name": "cnt_valid_to_switch_vio", - "isBus": true, - "subnets": [ - { - "name": "cnt_valid_to_switch_vio[31]" - }, - { - "name": "cnt_valid_to_switch_vio[30]" - }, - { - "name": "cnt_valid_to_switch_vio[29]" - }, - { - "name": "cnt_valid_to_switch_vio[28]" - }, - { - "name": "cnt_valid_to_switch_vio[27]" - }, - { - "name": "cnt_valid_to_switch_vio[26]" - }, - { - "name": "cnt_valid_to_switch_vio[25]" - }, - { - "name": "cnt_valid_to_switch_vio[24]" - }, - { - "name": "cnt_valid_to_switch_vio[23]" - }, - { - "name": "cnt_valid_to_switch_vio[22]" - }, - { - "name": "cnt_valid_to_switch_vio[21]" - }, - { - "name": "cnt_valid_to_switch_vio[20]" - }, - { - "name": "cnt_valid_to_switch_vio[19]" - }, - { - "name": "cnt_valid_to_switch_vio[18]" - }, - { - "name": "cnt_valid_to_switch_vio[17]" - }, - { - "name": "cnt_valid_to_switch_vio[16]" - }, - { - "name": "cnt_valid_to_switch_vio[15]" - }, - { - "name": "cnt_valid_to_switch_vio[14]" - }, - { - "name": "cnt_valid_to_switch_vio[13]" - }, - { - "name": "cnt_valid_to_switch_vio[12]" - }, - { - "name": "cnt_valid_to_switch_vio[11]" - }, - { - "name": "cnt_valid_to_switch_vio[10]" - }, - { - "name": "cnt_valid_to_switch_vio[9]" - }, - { - "name": "cnt_valid_to_switch_vio[8]" - }, - { - "name": "cnt_valid_to_switch_vio[7]" - }, - { - "name": "cnt_valid_to_switch_vio[6]" - }, - { - "name": "cnt_valid_to_switch_vio[5]" - }, - { - "name": "cnt_valid_to_switch_vio[4]" - }, - { - "name": "cnt_valid_to_switch_vio[3]" - }, - { - "name": "cnt_valid_to_switch_vio[2]" - }, - { - "name": "cnt_valid_to_switch_vio[1]" - }, - { - "name": "cnt_valid_to_switch_vio[0]" - } - ] - } - ] - }, - { - "name": "probe_out14", - "id": 54, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 14, - "nets": [ - { - "name": "auto_test_enable_vio", - "isBus": false - } - ] - }, - { - "name": "probe_out15", - "id": 55, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 15, - "nets": [ - { - "name": "test_slot_length_vio", - "isBus": true, - "subnets": [ - { - "name": "test_slot_length_vio[31]" - }, - { - "name": "test_slot_length_vio[30]" - }, - { - "name": "test_slot_length_vio[29]" - }, - { - "name": "test_slot_length_vio[28]" - }, - { - "name": "test_slot_length_vio[27]" - }, - { - "name": "test_slot_length_vio[26]" - }, - { - "name": "test_slot_length_vio[25]" - }, - { - "name": "test_slot_length_vio[24]" - }, - { - "name": "test_slot_length_vio[23]" - }, - { - "name": "test_slot_length_vio[22]" - }, - { - "name": "test_slot_length_vio[21]" - }, - { - "name": "test_slot_length_vio[20]" - }, - { - "name": "test_slot_length_vio[19]" - }, - { - "name": "test_slot_length_vio[18]" - }, - { - "name": "test_slot_length_vio[17]" - }, - { - "name": "test_slot_length_vio[16]" - }, - { - "name": "test_slot_length_vio[15]" - }, - { - "name": "test_slot_length_vio[14]" - }, - { - "name": "test_slot_length_vio[13]" - }, - { - "name": "test_slot_length_vio[12]" - }, - { - "name": "test_slot_length_vio[11]" - }, - { - "name": "test_slot_length_vio[10]" - }, - { - "name": "test_slot_length_vio[9]" - }, - { - "name": "test_slot_length_vio[8]" - }, - { - "name": "test_slot_length_vio[7]" - }, - { - "name": "test_slot_length_vio[6]" - }, - { - "name": "test_slot_length_vio[5]" - }, - { - "name": "test_slot_length_vio[4]" - }, - { - "name": "test_slot_length_vio[3]" - }, - { - "name": "test_slot_length_vio[2]" - }, - { - "name": "test_slot_length_vio[1]" - }, - { - "name": "test_slot_length_vio[0]" - } - ] - } - ] } ] } @@ -2469,7 +1229,7 @@ "parent_nets": [ { "id": 18, - "name": "u_rf_control/clk_12M", + "name": "u_rf_control/spi_attn_clk", "state_reg": [ { "name": "u_rf_control/FSM_sequential_state_MOSI_reg[0]", diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf index e7fcd8a0..4c456da9 100644 Binary files a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf and b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v b/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v index 3344198b..0fa74719 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v +++ b/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v @@ -19,439 +19,232 @@ // ////////////////////////////////////////////////////////////////////////////////// -module rf_control( - input clk , //192Mclk - input rst , +module rf_control +( + // clock & reset + input clk , // 192M clk + input rst , - input [5:0] tx_gain_manual , //发射增益输入 - input [5:0] rx_gain_manual , //接收增益输入 + // net tx/rx control + input [ 1:0] rf_txrx_net , // 网络层控制收发，1发2收 - input gain_on_vio , //vio设置参数or自动切换 - input [1:0] rf_txrx_vio , //发射通道或者接收通道 - input [1:0] rf_txrx_net , //受网络层控制 + // net freq control + input [11:0] tx_freq_hop_words , // tx跳频频率控制字 + input tx_hop_words_valid , // tx跳频频率控制字有效脉冲 + input tx_freq_hop_switch , // tx频点切换脉冲 - input rf_vio_set , //vio设置参数or自动切换 + input [11:0] rx_freq_hop_words , // rx跳频频率控制字 + input rx_hop_words_valid , // rx跳频频率控制字有效脉冲 + input rx_freq_hop_switch , // rx频点切换脉冲 - input [11:0] tx_freq_hop_words , //tx跳频频率控制字 - input tx_hop_words_valid , //tx跳频频率控制字有效脉冲 - input tx_freq_hop_switch , //tx频点切换脉冲 + // vio tx/rx control + input [ 1:0] rf_txrx_vio , // vio控制收发，1发2收 - input [11:0] rx_freq_hop_words , //rx跳频频率控制字 - input rx_hop_words_valid , //rx跳频频率控制字有效脉冲 - input rx_freq_hop_switch , //rx频点切换脉冲 + // vio freq control + input [11:0] freq_hop_words_vio , // vio设置跳频频率控制字 + input hop_words_valid_vio , // vio设置跳频频率控制字有效脉冲 + input freq_hop_switch_vio , // vio设置频点切换脉冲 - input [11:0] freq_hop_words_vio , //vio设置跳频频率控制字 - input hop_words_valid_vio , //vio设置跳频频率控制字有效脉冲 - input freq_hop_switch_vio , //vio设置频点切换脉冲 + // manual configuration + input vio_set_trx , // 0: 网络层控制收发，1: vio控制收发 + input vio_set_freq , // 0: 网络层控制频点，1: vio控制频点 + input rf_config_valid , // 衰减切换脉冲 + input [ 7:0] tx_gain , // 发射通道衰减，可调范围0~60dB，1dB步进 + input [ 7:0] rx_gain , // 接收通道衰减，可调范围0~60dB，1dB步进 - // 新增4个引脚 - output reg clk_12M = 1'd0 , // 串行输入时钟 - output reg CS_rf = 1'd1 , // 发送使能输入CS - output reg tx_gain = 1'd0 , //发射通道增益 - input rx_gain , + // rf attenuation spi interface + output reg spi_attn_clk = 1'd0 , + output reg spi_attn_csn = 1'd1 , + output reg spi_attn_mosi = 1'd0 , + input spi_attn_miso , - output reg tx_gain_on = 1'd0 , //发射通道开关 - // output reg rx_gain = 1'd0 , //接收通道增益 - output reg rx_gain_on = 1'd0 , //发射通道开关 + // rf tx/rx control + output reg tx_gain_on = 1'd0 , // 发射通道开关 + output reg rx_gain_on = 1'd0 , // 发射通道开关 - output reg [11:0] freq_hop_words = 12'd0 , //跳频频率控制字 - output reg hop_words_valid = 1'd0 , //跳频频率控制字有效脉冲 - output reg freq_hop_switch = 1'd0 , //频点切换脉冲 - output reg freq_hop_switch_out = 1'd0 , - - output reg [11:0] freq_hop_words_sweep = 12'd0 - ); - - reg rst_D1_1 = 1'd0; - reg rst_D1_2 = 1'd0; - reg rst_D1_3 = 1'd0; - always @(posedge clk) begin - rst_D1_1 <= rst ; - rst_D1_2 <= rst ; - rst_D1_3 <= rst ; - - end - -//-------------------------------------------------------------------------------------------------- - -//发射通道增益、开关设置 - always @(posedge clk) begin - if(rst_D1_1) - tx_gain_on <= 1'b0 ; - else if(gain_on_vio) - tx_gain_on <= (rf_txrx_vio[1:0] == 2'd1) ? 1'd1 :1'd0 ; - else - tx_gain_on <= (rf_txrx_net[1:0] == 2'd1) ? 1'd1 :1'd0 ; - end - -//-------------------------------------------------------------------------------------------------- -//接收通道增益、开关设置 - reg [5:0] rx_gain_div2 = 5'd0; - always @(posedge clk) begin - if(rst_D1_2) - rx_gain_on <= 1'b0 ; - else if(gain_on_vio) - rx_gain_on <= (rf_txrx_vio[1:0] == 2'd2) ? 1'd1 :1'd0 ; - else - rx_gain_on <= (rf_txrx_net[1:0] == 2'd2) ? 1'd1 :1'd0 ; - end -//-------------------------------------------------------------------------------------------------- -//跳频设置vio控制or网络层设置 - reg [11:0] freq_hop_words_net = 12'd0 ; - reg hop_words_valid_net = 1'd0 ; - reg freq_hop_switch_net = 1'd0 ; - - - always @(posedge clk) begin - if(rst_D1_3)begin - freq_hop_words_net [11:0] <= 12'd0 ; - hop_words_valid_net <= 1'd0 ; - freq_hop_switch_net <= 1'd0 ; - end - else if(rf_txrx_net[1:0] == 2'd1)begin - freq_hop_words_net [11:0] <= tx_freq_hop_words[11:0] ; - hop_words_valid_net <= tx_hop_words_valid ; - freq_hop_switch_net <= tx_freq_hop_switch ; - end - else if(rf_txrx_net[1:0] == 2'd2)begin - freq_hop_words_net [11:0] <= rx_freq_hop_words[11:0] ; - hop_words_valid_net <= rx_hop_words_valid ; - freq_hop_switch_net <= rx_freq_hop_switch ; - end - else begin - freq_hop_words_net [11:0] <= freq_hop_words_net [11:0] ; - hop_words_valid_net <= 1'd0 ; - freq_hop_switch_net <= 1'd0 ; - end - - end - - // reg [11:0] freq_hop_words_sweep = 12'd0; - reg hop_words_valid_sweep = 1'd0; - reg freq_hop_switch_sweep = 1'd0; - - reg hop_words_valid_manual = 1'd0; - reg freq_hop_switch_manual = 1'd0; - - reg [11:0] freq_hop_words_manual = 12'd0 ; - - wire freq_swicth_start; - always @(posedge clk) begin - if(rst_D1_3)begin - freq_hop_words [11:0] <= 12'd0 ; - hop_words_valid <= 1'd0 ; - freq_hop_switch <= 1'd0 ; - freq_hop_switch_out <= 1'd0 ; - end - else if(rf_vio_set)begin // rf_vio_set为1频率控制字控 - freq_hop_words [11:0] <= freq_hop_words_vio[11:0] ; - hop_words_valid <= hop_words_valid_vio ; - freq_hop_switch <= freq_hop_switch_vio ; - freq_hop_switch_out <= freq_hop_switch_vio ; - end - else if(freq_swicth_start)begin - freq_hop_words [11:0] <= freq_hop_words_sweep[11:0] ; - hop_words_valid <= hop_words_valid_sweep ; - freq_hop_switch <= freq_hop_switch_sweep ; - freq_hop_switch_out <= freq_hop_switch_sweep ; - end - else begin - freq_hop_words [11:0] <= freq_hop_words_manual[11:0] ; - hop_words_valid <= hop_words_valid_manual ; - freq_hop_switch <= freq_hop_switch_manual ; - freq_hop_switch_out <= freq_hop_switch_manual ; - end - end - - - - // 12M时钟生成 - // reg clk_12M = 1'd0 ; - reg [2:0] cnt_8 = 3'd0 ; - reg clk_switch = 1'd0 ; - // 8位计数器 - always@(posedge clk) begin - if(rst_D1_1) begin - cnt_8 <= 3'd0 ; - clk_switch <= 1'd0 ; - end - else if(cnt_8 == 3'd7)begin - cnt_8 <= 3'd0 ; - clk_switch <= 1'd1 ; - end - else begin - cnt_8 <= cnt_8 + 3'd1 ; - clk_switch <= 1'd0 ; - end - end - - always@(posedge clk) begin // 产生12M时钟 - if(clk_switch == 1'd1)begin - clk_12M <= ~clk_12M ; - end - else begin - clk_12M <= clk_12M ; - end - end - - // 发送使能输入 - // reg CS_rf = 1'd1; - wire CS_rf_flag; - reg CS_rf_flag_D1 = 1'd0; - wire [31:0] cnt_frechange_top ; - wire [31:0] switch_delay_time ; - wire freq_hop_change ; - - wire [11:0] freq_hop_words_vio1 ; - wire [11:0] freq_hop_words_vio2 ; - wire [31:0] valid_delay_time_max ; - wire [63:0] slot_vio_time ; - wire [4:0] cnt_slot_max ; - wire [7:0] MOSI_tx_atte ; - wire [7:0] MOSI_rx_atte ; - // 发送使能输入vio_rftx_en -vio_rf_test vio_rf_test ( - .clk(clk), // input wire clk - .probe_out0(CS_rf_flag), // output wire [0 : 0] probe_out0 - .probe_out1(MOSI_tx_atte), // output wire [0 : 0] probe_out0 - .probe_out2(MOSI_rx_atte), // output wire [0 : 0] probe_out0 - .probe_out3(cnt_frechange_top), - .probe_out4(freq_hop_change), // 切换频率开始 - .probe_out5(freq_hop_words_vio1[11:0]), - .probe_out6(freq_hop_words_vio2[11:0]), - .probe_out7(switch_delay_time[31:0]), // valid和switch之间的时间 - .probe_out8(valid_delay_time_max[31:0]), // valid和switch的切换时间 - .probe_out9(slot_vio_time[63:0]), // 一个频点的时间 - .probe_out10(cnt_slot_max[4:0]), - .probe_out11(freq_swicth_start) + // rf freq control + output reg [11:0] freq_hop_words = 11'd0 , // 跳频频率控制字 + output reg hop_words_valid = 1'd0 , // 跳频频率控制字有效脉冲 + output reg freq_hop_switch = 1'd0 // 频点切换脉冲 ); -always@(posedge clk_12M)begin - CS_rf_flag_D1 <= CS_rf_flag; +reg rst_D1_1 = 1'd0; +reg rst_D1_2 = 1'd0; +reg rst_D1_3 = 1'd0; + +always @(posedge clk) begin + rst_D1_1 <= rst ; + rst_D1_2 <= rst ; + rst_D1_3 <= rst ; end - // 中频-射频数据输出MOSI - reg MOSI = 1'd0 ; - wire [31:0] MOSI_data; - reg [7:0] MOSI_head = 8'h5A; - // wire [7:0] MOSI_tx_atte ; - // wire [7:0] MOSI_rx_atte ; - reg [7:0] MOSI_recv = 8'hA5; +//------------------------------------------------------------------------------ +//发射通道增益、开关设置 - assign MOSI_data = {MOSI_head,MOSI_tx_atte,MOSI_rx_atte,MOSI_recv}; +always @(posedge clk) begin + if(rst_D1_1) + tx_gain_on <= 1'b0 ; + else if(vio_set_trx) + tx_gain_on <= (rf_txrx_vio[1:0] == 2'd1) ? 1'd1 :1'd0 ; + else + tx_gain_on <= (rf_txrx_net[1:0] == 2'd1) ? 1'd1 :1'd0 ; +end + +//------------------------------------------------------------------------------ +//接收通道增益、开关设置 + +always @(posedge clk) begin + if(rst_D1_2) + rx_gain_on <= 1'b0 ; + else if(vio_set_trx) + rx_gain_on <= (rf_txrx_vio[1:0] == 2'd2) ? 1'd1 :1'd0 ; + else + rx_gain_on <= (rf_txrx_net[1:0] == 2'd2) ? 1'd1 :1'd0 ; +end + +//------------------------------------------------------------------------------ +//跳频设置vio控制or网络层设置 + +reg [11:0] freq_hop_words_net = 'b0; +reg hop_words_valid_net = 'b0; +reg freq_hop_switch_net = 'b0; + +always @(posedge clk) begin + if(rst_D1_3)begin + freq_hop_words_net[11:0] <= 'b0; + hop_words_valid_net <= 'b0; + freq_hop_switch_net <= 'b0; + end + else if(rf_txrx_net[1:0] == 2'd1)begin + freq_hop_words_net[11:0] <= tx_freq_hop_words[11:0]; + hop_words_valid_net <= tx_hop_words_valid ; + freq_hop_switch_net <= tx_freq_hop_switch ; + end + else if(rf_txrx_net[1:0] == 2'd2)begin + freq_hop_words_net[11:0] <= rx_freq_hop_words[11:0]; + hop_words_valid_net <= rx_hop_words_valid ; + freq_hop_switch_net <= rx_freq_hop_switch ; + end + else begin + freq_hop_words_net[11:0] <= freq_hop_words_net[11:0]; + hop_words_valid_net <= 1'd0 ; + freq_hop_switch_net <= 1'd0 ; + end +end + +always @(posedge clk) begin + if(rst_D1_3)begin + freq_hop_words[11:0] <= 'b0; + hop_words_valid <= 'b0; + freq_hop_switch <= 'b0; + end + else if(vio_set_freq)begin + freq_hop_words[11:0] <= freq_hop_words_vio[11:0]; + hop_words_valid <= hop_words_valid_vio ; + freq_hop_switch <= freq_hop_switch_vio ; + end + else begin + freq_hop_words[11:0] <= freq_hop_words_net[11:0]; + hop_words_valid <= hop_words_valid_net ; + freq_hop_switch <= freq_hop_switch_net ; + end +end + +// 12M时钟生成 +// reg spi_attn_clk = 1'd0; +reg [2:0] cnt_8 = 3'd0; +reg clk_switch = 1'd0; + +// 8位计数器 +always@(posedge clk) begin + if(rst_D1_1) begin + cnt_8 <= 3'd0; + clk_switch <= 1'd0; + end + else if(cnt_8 == 3'd7)begin + cnt_8 <= 3'd0; + clk_switch <= 1'd1; + end + else begin + cnt_8 <= cnt_8 + 3'd1; + clk_switch <= 1'd0 ; + end +end + +always@(posedge clk) begin // 产生12M时钟 + if (clk_switch == 1'd1)begin + spi_attn_clk <= ~spi_attn_clk; + end + else begin + spi_attn_clk <= spi_attn_clk; + end +end + +// 发送使能输入 +reg CS_rf_flag = 'b0; +reg CS_rf_flag_D1 = 'b0; +reg CS_rf_flag_D2 = 'b0; +reg CS_rf_flag_D3 = 'b0; + +// 中频-射频数据输出MOSI +reg MOSI = 1'd0 ; +wire [31:0] MOSI_data ; +reg [ 7:0] MOSI_head = 8'h5A; +wire [ 7:0] MOSI_tx_attn ; +wire [ 7:0] MOSI_rx_attn ; +reg [ 7:0] MOSI_recv = 8'hA5; + +assign MOSI_tx_attn = tx_gain; +assign MOSI_rx_attn = rx_gain; + +always@(posedge spi_attn_clk)begin + CS_rf_flag_D1 <= rf_config_valid; + CS_rf_flag_D2 <= CS_rf_flag_D1; + CS_rf_flag_D3 <= CS_rf_flag_D2; +end + +assign MOSI_data = {MOSI_head,MOSI_tx_attn,MOSI_rx_attn,MOSI_recv}; reg [3:0] state_MOSI = 4'd0; -reg [7:0] cnt_64 = 8'd0; +reg [7:0] cnt_64 = 8'd0; -always@(posedge clk_12M) begin - if(rst_D1_1) begin - state_MOSI <= 4'd0; - cnt_64 <= 8'd0; - end - else begin - case(state_MOSI) - 4'd0:begin // 等待发送指令 - if(CS_rf_flag && !CS_rf_flag_D1)begin - state_MOSI <= 4'd1; - end - else begin - state_MOSI <= 4'd0; - end - end +always@(posedge spi_attn_clk) begin + if(rst_D1_1) begin + state_MOSI <= 4'd0; + cnt_64 <= 8'd0; + end + else begin + case(state_MOSI) + 4'd0:begin // 等待发送指令 + if(CS_rf_flag_D2 && !CS_rf_flag_D3)begin + state_MOSI <= 4'd1; + end + else begin + state_MOSI <= 4'd0; + end + end - 4'd1:begin // 发送数据 - CS_rf <= 1'd0; - if(cnt_64 == 8'd31)begin - cnt_64 <= 8'd0; - tx_gain <= MOSI_data[0]; - state_MOSI <= 4'd2; - end - else begin - cnt_64 <= cnt_64 + 8'd1; - tx_gain <= MOSI_data[31 - cnt_64]; - state_MOSI <= 4'd1; - end - end + 4'd1:begin // 发送数据 + spi_attn_csn <= 1'd0; + if(cnt_64 == 8'd31)begin + cnt_64 <= 8'd0; + spi_attn_mosi <= MOSI_data[0]; + state_MOSI <= 4'd2; + end + else begin + cnt_64 <= cnt_64 + 8'd1; + spi_attn_mosi <= MOSI_data[31 - cnt_64]; + state_MOSI <= 4'd1; + end + end - 4'd2:begin - CS_rf <= 1'd1; - state_MOSI <= 4'd0; - tx_gain <= 1'd0; - end - endcase - end -end - - -// 扫频信号 -// 通过vio选择控制频点的方式 - -reg [31:0] cnt_frechange; - -always@(posedge clk) begin - if(rst_D1_1)begin - cnt_frechange <= 32'd0; - end - else begin - if(cnt_frechange == cnt_frechange_top) begin - cnt_frechange <= 32'd0; - end - else begin - cnt_frechange <= cnt_frechange + 32'd1; - end - end -end - - -always@(posedge clk) begin - if(rst_D1_2)begin - freq_hop_words_sweep <= 12'd0; - hop_words_valid_sweep <= 1'd0; - freq_hop_switch_sweep <= 1'd0; - end - else if(cnt_frechange == cnt_frechange_top) begin - if(freq_hop_words_sweep == 12'd3500) begin - freq_hop_words_sweep <= 12'd0; - end - else begin - freq_hop_words_sweep <= freq_hop_words_sweep + 12'd1; - end - hop_words_valid_sweep <= 1'd0; - freq_hop_switch_sweep <= 1'd1; - end - else if(cnt_frechange == cnt_frechange_top - 32'd1920000) begin - freq_hop_words_sweep <= freq_hop_words_sweep; - hop_words_valid_sweep <= 1'd1; - freq_hop_switch_sweep <= 1'd0; - end - else begin - freq_hop_words_sweep <= freq_hop_words_sweep; - hop_words_valid_sweep <= 1'd0; - freq_hop_switch_sweep <= 1'd0; - end -end - -// 控制时隙长短 -reg [31:0] delay_time = 32'd0; -reg hop_words_valid_manual_long = 1'd0; -reg [31:0] valid_delay_time = 32'd0; -reg [31:0] freq_hop_switch_delay_time = 32'd0; -reg [63:0] slot_time_cnt = 64'd0; - - -reg [4:0] state_vio_time = 5'd0; -reg [4:0] cnt_slot = 5'd0; - -reg freq_hop_change_D1 = 1'd0; -reg freq_hop_change_D2 = 1'd0; -reg freq_hop_change_D3 = 1'd0; - -always@(posedge clk) begin - freq_hop_change_D1 <= freq_hop_change; - freq_hop_change_D2 <= freq_hop_change_D1; - freq_hop_change_D3 <= freq_hop_change_D2; -end - -always@(posedge clk) begin - if(rst_D1_1) begin - state_vio_time <= 5'd0; - freq_hop_words_manual <= freq_hop_words_vio1; - end - else begin - case(state_vio_time) - 5'd0:begin // 等待切换频率开始 - if(!freq_hop_change_D1 && freq_hop_change)begin - state_vio_time <= 5'd1; - slot_time_cnt <= 64'd1 + slot_time_cnt; - - if(freq_hop_words_manual == freq_hop_words_vio1) begin - freq_hop_words_manual <= freq_hop_words_vio2; - end - else if(freq_hop_words_manual == freq_hop_words_vio2) begin - freq_hop_words_manual <= freq_hop_words_vio1; - end - else begin - freq_hop_words_manual <= freq_hop_words_vio1; - end - end - else begin - state_vio_time <= 5'd0; - freq_hop_words_manual <= freq_hop_words_manual; - end - end - - 5'd1:begin // 等待valid信号拉高完毕 - if(valid_delay_time == valid_delay_time_max) begin - hop_words_valid_manual <= 1'd0; - valid_delay_time <= 32'd0; - state_vio_time <= 5'd2; - end - else begin - hop_words_valid_manual <= 1'd1; - valid_delay_time <= valid_delay_time + 32'd1; - state_vio_time <= 5'd1; - end - slot_time_cnt <= 64'd1 + slot_time_cnt; - end - - 5'd2:begin // 等待switch信号 - if(delay_time == switch_delay_time) begin - freq_hop_switch_manual <= 1'd1; - delay_time <= 32'd0; - state_vio_time <= 5'd3; - end - else begin - freq_hop_switch_manual <= 1'd0; - delay_time <= 32'd1 + delay_time; - state_vio_time <= 5'd2; - end - slot_time_cnt <= 64'd1 + slot_time_cnt; - end - - 5'd3:begin // 等待switch信号拉高完毕 - if(freq_hop_switch_delay_time == valid_delay_time_max) begin - freq_hop_switch_manual <= 1'd0; - freq_hop_switch_delay_time <= 32'd0; - state_vio_time <= 5'd4; - end - else begin - freq_hop_switch_manual <= 1'd1; - freq_hop_switch_delay_time <= freq_hop_switch_delay_time + 32'd1; - state_vio_time <= 5'd3; - end - slot_time_cnt <= 64'd1 + slot_time_cnt; - end - - 5'd4:begin // 等待时隙结束 - if(slot_time_cnt == slot_vio_time)begin - if(cnt_slot == cnt_slot_max - 5'd1) begin - cnt_slot <= 5'd0; - state_vio_time <= 5'd0; - slot_time_cnt <= 64'd0; - end - else begin - state_vio_time <= 5'd1; - slot_time_cnt <= 64'd0; - cnt_slot <= cnt_slot + 5'd1; - end - end - else begin - state_vio_time <= 5'd4; - slot_time_cnt <= 64'd1 + slot_time_cnt; - cnt_slot <= cnt_slot; - end - end - default:begin - if(!freq_hop_change_D1 && freq_hop_change)begin - state_vio_time <= 5'd1; - end - else begin - state_vio_time <= 5'd0; - end - end - - endcase - end + 4'd2:begin + spi_attn_csn <= 1'd1; + state_MOSI <= 4'd0; + spi_attn_mosi <= 1'd0; + end + endcase + end end endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v b/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v index a670cfd4..93cedf34 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v +++ b/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v @@ -71,10 +71,10 @@ module system_top // ************************************************************************* // ****************************** RF Control ******************************* // ************************************************************************* - output tx_gain , - input rx_gain , - output clk_12M , - output CS_rf , + output rf_spi_attn_clk , + output rf_spi_attn_csn , + output rf_spi_attn_mosi , + input rf_spi_attn_miso , output tx_gain_on , output rx_gain_on , @@ -107,12 +107,7 @@ module system_top inout [53:0] fixed_io_mio , inout fixed_io_ps_clk , inout fixed_io_ps_porb , - inout fixed_io_ps_srstb , - // ************************************************************************* - // ************************* Sync Signal *********************************** - // ************************************************************************* - output sync_signal_out , - output reg sync_gnd = 1'b0 + inout fixed_io_ps_srstb ); @@ -125,7 +120,10 @@ wire sys_clk_2x ; // 245.76mhz wire sys_rst ; // optional siganl clock, can be changed to whatever frequency you want -wire sig_clk ; // 245.76mhz +wire sig_clk ; // 48MHz +wire sig_clk_2x ; // 96MHz +wire sig_clk_3x ; // 144MHz +wire sig_clk_4x ; // 192MHz wire sig_clk_ld ; wire sig_rst ; @@ -135,6 +133,9 @@ sig_clk_gen u_sig_clk_gen ( // Clock out ports .clk_out1 (sig_clk ), // output clk_out1 + .clk_out2 (sig_clk_2x ), // output clk_out2 + .clk_out3 (sig_clk_3x ), // output clk_out3 + .clk_out4 (sig_clk_4x ), // output clk_out4 // Status and control signals .reset (sys_rst ), // input reset .locked (sig_clk_ld ), // output locked @@ -257,102 +258,65 @@ system_bd_wrapper u_system_bd //////////////////////////////////////////////////////////////////////////////// //////////////////////////// RF Control Interface ////////////////////////////// //////////////////////////////////////////////////////////////////////////////// -wire gain_on_vio ; -wire [1:0] rf_txrx_vio ; -wire rf_vio_set ; +wire vio_set_trx ; +wire vio_set_freq ; +wire rf_config_valid ; -wire [5:0] tx_gain_manual ; -wire [5:0] rx_gain_manual ; +wire [1:0] rf_txrx_vio ; +wire [7:0] tx_gain_manual ; +wire [7:0] rx_gain_manual ; -wire [11:0] freq_hop_words_vio ; -wire hop_words_valid_vio ; -wire freq_hop_switch_vio ; - -wire freq_hop_switch_out ; -wire [11:0] freq_hop_words_sweep; - -// rf auto switch frequency function -wire auto_test_enable_vio; -wire rf_auto_start_vio ; -wire rf_ctrl_mode_vio ; -wire switch_next_freq_vio; -wire switch_last_freq_vio; -wire [31:0] cnt_valid_to_switch_vio; -wire [31:0] test_slot_length_vio; - -wire [11:0] freq_hop_words_auto ; -wire hop_words_valid_auto; -wire freq_hop_switch_auto; - -rf_auto_switch_freq u_rf_auto_switch_freq -( - .clk (sys_clk ), - .rst (sys_rst ), - - // vio control - .start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first - .auto_test_enable (auto_test_enable_vio ), // rise-edge active - .rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch - .switch_next_freq (switch_next_freq_vio ), // rise-edge active - .switch_last_freq (switch_last_freq_vio ), // rise-edge active - .cnt_valid_to_switch (cnt_valid_to_switch_vio ), // the clock number from valid to switch - .test_slot_length (test_slot_length_vio[31:0] ), - - // input - .freq_hop_words_vio (freq_hop_words_vio[11:0] ), - .hop_words_valid_vio (hop_words_valid_vio ), - .freq_hop_switch_vio (freq_hop_switch_vio ), - - // output - .freq_hop_words_auto (freq_hop_words_auto[11:0] ), - .hop_words_valid_auto (hop_words_valid_auto ), - .freq_hop_switch_auto (freq_hop_switch_auto ), - .sync_signal (sync_signal_out ) -); +wire [11:0] freq_hop_words_vio ; +wire hop_words_valid_vio; +wire freq_hop_switch_vio; rf_control u_rf_control ( - .clk (sys_clk ), - .rst (sys_rst ), + // clock & reset + .clk (sig_clk_4x ), // 192M clk + .rst (sig_rst ), - //input - .gain_on_vio (gain_on_vio ), - .rf_txrx_vio (rf_txrx_vio[1:0] ), - .rf_txrx_net (2'd0 ), - .tx_gain_manual (tx_gain_manual[5:0] ), - .rx_gain_manual (rx_gain_manual[5:0] ), + // net tx/rx control + .rf_txrx_net ('b0 ), // 网络层控制收发，1发2收 - //0:net->control 1:vio->control - .rf_vio_set (rf_vio_set ), + // net freq control + .tx_freq_hop_words ('b0 ), // tx跳频频率控制字 + .tx_hop_words_valid ('b0 ), // tx跳频频率控制字有效脉冲 + .tx_freq_hop_switch ('b0 ), // tx频点切换脉冲 - //vio hop control - .freq_hop_words_vio (freq_hop_words_auto[10:0] ), - .hop_words_valid_vio (hop_words_valid_auto ), - .freq_hop_switch_vio (freq_hop_switch_auto ), + .rx_freq_hop_words ('b0 ), // rx跳频频率控制字 + .rx_hop_words_valid ('b0 ), // rx跳频频率控制字有效脉冲 + .rx_freq_hop_switch ('b0 ), // rx频点切换脉冲 - //tx hop control - .tx_freq_hop_words (11'b0 ), - .tx_hop_words_valid (1'b0 ), - .tx_freq_hop_switch (1'b0 ), + // vio tx/rx control + .rf_txrx_vio (rf_txrx_vio[1:0] ), // vio控制收发，1发2收 - //rx hop control - .rx_freq_hop_words (11'b0 ), - .rx_hop_words_valid (1'b0 ), - .rx_freq_hop_switch (1'b0 ), + // vio freq control + .freq_hop_words_vio (freq_hop_words_vio[11:0] ), // vio设置跳频频率控制字 + .hop_words_valid_vio (hop_words_valid_vio ), // vio设置跳频频率控制字有效脉冲 + .freq_hop_switch_vio (freq_hop_switch_vio ), // vio设置频点切换脉冲 - //output - .clk_12M (clk_12M ), - .CS_rf (CS_rf ), - .tx_gain (tx_gain ), - .tx_gain_on (tx_gain_on ), - .rx_gain (rx_gain ), - .rx_gain_on (rx_gain_on ), + // manual configuration + .vio_set_trx (vio_set_trx ), // 0: 网络层控制收发，1: vio控制收发 + .vio_set_freq (vio_set_freq ), // 0: 网络层控制频点，1: vio控制频点 + .rf_config_valid (rf_config_valid ), // 衰减切换脉冲 + .tx_gain (tx_gain_manual[7:0] ), // 发射通道衰减，可调范围0~60dB，1dB步进 + .rx_gain (rx_gain_manual[7:0] ), // 接收通道衰减，可调范围0~60dB，1dB步进 - .freq_hop_words (freq_hop_words[11:0] ), - .hop_words_valid (hop_words_valid ), - .freq_hop_switch (freq_hop_switch ), - .freq_hop_switch_out (freq_hop_switch_out ), - .freq_hop_words_sweep (freq_hop_words_sweep ) + // rf attenuation spi interface + .spi_attn_clk (rf_spi_attn_clk ), + .spi_attn_csn (rf_spi_attn_csn ), + .spi_attn_mosi (rf_spi_attn_mosi ), + .spi_attn_miso (rf_spi_attn_miso ), + + // rf tx/rx control + .tx_gain_on (tx_gain_on ), // 发射通道开关 + .rx_gain_on (rx_gain_on ), // 发射通道开关 + + // rf freq control + .freq_hop_words (freq_hop_words[11:0] ), // 跳频频率控制字 + .hop_words_valid (hop_words_valid ), // 跳频频率控制字有效脉冲 + .freq_hop_switch (freq_hop_switch ) // 频点切换脉冲 ); @@ -465,41 +429,32 @@ vio_manual_ctrl u_vio_manual_ctrl .probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4 ); -vio_rf_control u_vio_rf_control +vio_RF_control u_vio_rf_control ( - .clk (sys_clk ), // input wire clk - .probe_out0 (gain_on_vio ), // output wire [0 : 0] probe_out0 - .probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1 - .probe_out2 (rf_vio_set ), // output wire [0 : 0] probe_out2 - .probe_out3 (tx_gain_manual[5:0] ), // output wire [5 : 0] probe_out3 - .probe_out4 (rx_gain_manual[5:0] ), // output wire [5 : 0] probe_out4 - .probe_out5 (freq_hop_words_vio[11:0] ), // output wire [10 : 0] probe_out5 - .probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6 - .probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7 - .probe_out8 (self_check_dout ), // output wire [0 : 0] probe_out8 - .probe_out9 (rf_auto_start_vio ), // output wire [0 : 0] probe_out9 - .probe_out10 (rf_ctrl_mode_vio ), // output wire [0 : 0] probe_out10 - .probe_out11 (switch_next_freq_vio ), // output wire [0 : 0] probe_out11 - .probe_out12 (switch_last_freq_vio ), // output wire [0 : 0] probe_out12 - .probe_out13 (cnt_valid_to_switch_vio[31:0] ), // output wire [31: 0] probe_out13 - .probe_out14 (auto_test_enable_vio ), // output wire [0 : 0] probe_out14 - .probe_out15 (test_slot_length_vio[31:0] ), // output wire [31: 0] probe_out15 - .probe_in0 (freq_hop_words_auto[10:0] ) // input wire [10: 0] probe_in0 + .clk (sig_clk_4x ), // input wire clk + .probe_out0 (vio_set_trx ), // output wire [0 : 0] probe_out0 + .probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1 + .probe_out2 (vio_set_freq ), // output wire [0 : 0] probe_out2 + .probe_out3 (tx_gain_manual[7:0] ), // output wire [5 : 0] probe_out3 + .probe_out4 (rx_gain_manual[7:0] ), // output wire [5 : 0] probe_out4 + .probe_out5 (freq_hop_words_vio[11:0] ), // output wire [10 : 0] probe_out5 + .probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6 + .probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7 + .probe_out8 (rf_config_valid ) // output wire [0 : 0] probe_out8 ); -ila_rf_test ila_rf_test +ila_rf_test u_ila_rf_test ( - .clk (sys_clk ), // input wire clk + .clk (sig_clk_4x ), // input wire clk .probe0 (freq_hop_words[11:0] ), // input wire [11:0] probe0 - .probe1 (tx_gain_on ), // input wire [0:0] probe1 - .probe2 (rx_gain ), // input wire [0:0] probe2 - .probe3 (rx_gain_on ), // input wire [0:0] probe3 - .probe4 (tx_gain ), // input wire [0:0] probe4 - .probe5 (hop_words_valid ), // input wire [0:0] probe5 - .probe6 (freq_hop_switch ), // input wire [0:0] probe6 - .probe7 (clk_12M ), // input wire [0:0] probe7 - .probe8 (CS_rf ), // input wire [0:0] probe8 - .probe9 (freq_hop_words_sweep ) // input wire [11:0] probe9 + .probe1 (rf_spi_attn_clk ), // input wire [0:0] probe1 + .probe2 (rf_spi_attn_csn ), // input wire [0:0] probe2 + .probe3 (rf_spi_attn_mosi ), // input wire [0:0] probe3 + .probe4 (rf_spi_attn_miso ), // input wire [0:0] probe4 + .probe5 (tx_gain_on ), // input wire [0:0] probe5 + .probe6 (rx_gain_on ), // input wire [0:0] probe6 + .probe7 (hop_words_valid ), // input wire [0:0] probe7 + .probe8 (freq_hop_switch ) // input wire [0:0] probe8 ); endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/project.tcl b/projects/dl814_k7/dl814_k7_cal_coarse/project.tcl index 0ee9e8d4..c8892be3 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/project.tcl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/project.tcl @@ -3,7 +3,7 @@ # # project.tcl: Tcl script for re-creating project 'project' # -# Generated by Vivado on Thu Jun 15 18:37:56 CST 2023 +# Generated by Vivado on Sun Jul 09 14:58:03 CST 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -194,7 +194,7 @@ set proj_dir [get_property directory [current_project]] # Set project properties set obj [current_project] -set_property -name "compxlib.modelsim_compiled_library_dir" -value "/home/josh/Mentor/CompLib/2019.1.3" -objects $obj +set_property -name "compxlib.modelsim_compiled_library_dir" -value "/home/josh/Software/Xilinx/CompLib/Model/2019.1" -objects $obj set_property -name "compxlib.vcs_compiled_library_dir" -value "/home/josh/Software/Xilinx/CompLib/VCS/2019.1" -objects $obj set_property -name "corecontainer.enable" -value "1" -objects $obj set_property -name "default_lib" -value "xil_defaultlib" -objects $obj @@ -229,7 +229,7 @@ set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj set_property -name "webtalk.questa_export_sim" -value "92" -objects $obj set_property -name "webtalk.riviera_export_sim" -value "92" -objects $obj set_property -name "webtalk.vcs_export_sim" -value "92" -objects $obj -set_property -name "webtalk.vcs_launch_sim" -value "69" -objects $obj +set_property -name "webtalk.vcs_launch_sim" -value "77" -objects $obj set_property -name "webtalk.xsim_export_sim" -value "92" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj @@ -706,6 +706,7 @@ add_files -norecurse -fileset $obj $files # Set 'sim_1' fileset properties set obj [get_filesets sim_1] +set_property -name "sim_mode" -value "post-implementation" -objects $obj set_property -name "top" -value "tb_rx_pre_test" -objects $obj set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre_test.v b/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre_test.v index 953d5e58..a91aa3dd 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre_test.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre_test.v @@ -113,12 +113,24 @@ initial begin wait(ad9361_cal_valid); #1000 hop_trigger = 1'b1; - #100 + + #(192*200*10) // after 200us, trig again hop_trigger = 1'b0; - #(19600*40-100) // after a long time, trig again + + #(192*200*10) // after 200us, trig again hop_trigger = 1'b1; - #100 + + #(192*200*10) // after 200us, trig again hop_trigger = 1'b0; + + #(192*200*10) // after 200us, trig again + hop_trigger = 1'b1; + + #(192*200*10) // after 200us, trig again + hop_trigger = 1'b0; + + #(192*200*10) // after 200us, trig again + hop_trigger = 1'b1; end always @(posedge sys_clk) begin @@ -192,7 +204,8 @@ assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt]; //////////////////////////////////////////////////////////////////////////////// rx_pre_process #( - .OUTPUT_DATA_WIDTH (30 ) + .OUTPUT_DATA_WIDTH (30 ), + .SNAPSHOT_NUM (256 ) ) u_rx_pre_process ( // clock & reset @@ -210,6 +223,11 @@ rx_pre_process #( .rx_ch3_q (rx_ch3_q ), .rx_ch4_i (rx_ch4_i ), .rx_ch4_q (rx_ch4_q ), + // input channel phase + .phase_ch1 ('b0 ), + .phase_ch2 ('b0 ), + .phase_ch3 ('b0 ), + .phase_ch4 ('b0 ), // ad9361 calibration interface .ad9361_1_cal_start (ad9361_1_cal_start ), .ad9361_1_cal_done (ad9361_1_cal_done ),