diff --git a/projects/duifei/duifei_online_acq_par/ip/cmpy_12_12.xcix b/projects/duifei/duifei_online_acq_par/ip/cmpy_12_12.xcix new file mode 100755 index 00000000..78f16269 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/cmpy_12_12.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:a362ab4cd06eec867133af828280afc1887c76184d0470657b23a273c1f589a0 +size 3257593 diff --git a/projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep2.coe b/projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep2.coe new file mode 100644 index 00000000..083d32ca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep2.coe @@ -0,0 +1,258 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2.xcix b/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2.xcix index bf04bd4d..05545222 100644 --- a/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2.xcix +++ b/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2.xcix @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d3489db55b49758e586385420457a7c7af12d8771ec73e1e9bfffb367046283e -size 11923889 +oid sha256:f0cb03546d22de9043dce6dccf9354e8c76c4f044977989713442a3a9e77b351 +size 11915714 diff --git a/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt.xcix b/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt.xcix index 0625d02f..90220963 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt.xcix +++ b/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt.xcix @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c46708958268824938bb31727e17fe245b40135cf1d66a47a7278eb8f7c6bf07 -size 30660234 +oid sha256:5622d1046d474978e1b03b5adaf6ae84ca6fc7550bab748e5570fbf59c78db37 +size 31317654 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12.veo new file mode 100644 index 00000000..86d6c16a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12.veo @@ -0,0 +1,71 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:cmpy:6.0 +// IP Revision: 17 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +cmpy_12_12 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid + .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid + .s_axis_b_tdata(s_axis_b_tdata), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file cmpy_12_12.v when simulating +// the core, cmpy_12_12. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12.vho new file mode 100644 index 00000000..3e45d748 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12.vho @@ -0,0 +1,87 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:cmpy:6.0 +-- IP Revision: 17 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT cmpy_12_12 + PORT ( + aclk : IN STD_LOGIC; + s_axis_a_tvalid : IN STD_LOGIC; + s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_b_tvalid : IN STD_LOGIC; + s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_dout_tvalid : OUT STD_LOGIC; + m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : cmpy_12_12 + PORT MAP ( + aclk => aclk, + s_axis_a_tvalid => s_axis_a_tvalid, + s_axis_a_tdata => s_axis_a_tdata, + s_axis_b_tvalid => s_axis_b_tvalid, + s_axis_b_tdata => s_axis_b_tdata, + m_axis_dout_tvalid => m_axis_dout_tvalid, + m_axis_dout_tdata => m_axis_dout_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file cmpy_12_12.vhd when simulating +-- the core, cmpy_12_12. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_sim_netlist.v new file mode 100644 index 00000000..aecc407d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:a852ea914f1fae3bdd9dac48f971893ca60e0e4a8049bd5cc95816e592e09beb +size 128245 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_sim_netlist.vhdl new file mode 100644 index 00000000..b3d27d12 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:87b0810ff4c92090e9d6d519f754ae766fca7a6b091140b36e4943a1bf33cc61 +size 173647 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_stub.v new file mode 100644 index 00000000..2aa28b3f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Tue May 16 02:16:23 2023 +// Host : DESKTOP-3AAKI0I running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// E:/DF/df_datalink_v0/df_datalink_v0.runs/cmpy_12_12_synth_1/cmpy_12_12_stub.v +// Design : cmpy_12_12 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1" *) +module cmpy_12_12(aclk, s_axis_a_tvalid, s_axis_a_tdata, + s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata) +/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]" */; + input aclk; + input s_axis_a_tvalid; + input [31:0]s_axis_a_tdata; + input s_axis_b_tvalid; + input [31:0]s_axis_b_tdata; + output m_axis_dout_tvalid; + output [63:0]m_axis_dout_tdata; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_stub.vhdl new file mode 100644 index 00000000..b80e5c4e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/cmpy_12_12_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Tue May 16 02:16:23 2023 +-- Host : DESKTOP-3AAKI0I running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- E:/DF/df_datalink_v0/df_datalink_v0.runs/cmpy_12_12_synth_1/cmpy_12_12_stub.vhdl +-- Design : cmpy_12_12 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity cmpy_12_12 is + Port ( + aclk : in STD_LOGIC; + s_axis_a_tvalid : in STD_LOGIC; + s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axis_b_tvalid : in STD_LOGIC; + s_axis_b_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_dout_tvalid : out STD_LOGIC; + m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end cmpy_12_12; + +architecture stub of cmpy_12_12 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/demo_tb/tb_cmpy_12_12.vhd b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/demo_tb/tb_cmpy_12_12.vhd new file mode 100644 index 00000000..a7efcdea --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/demo_tb/tb_cmpy_12_12.vhd @@ -0,0 +1,389 @@ +-------------------------------------------------------------------------------- +-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- Description: +-- This is an example testbench for the Complex Multiplier IP core. +-- The testbench has been generated by Vivado to accompany the IP core +-- instance you have generated. +-- +-- This testbench is for demonstration purposes only. See note below for +-- instructions on how to use it with your core. +-- +-- See the Complex Multiplier product guide for further information +-- about this core. +-- +-------------------------------------------------------------------------------- +-- Using this testbench +-- +-- This testbench instantiates your generated Complex Multiplier core +-- instance named "cmpy_12_12". +-- +-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado +-- documentation for details. +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity tb_cmpy_12_12 is +end tb_cmpy_12_12; + +architecture tb of tb_cmpy_12_12 is + + ----------------------------------------------------------------------- + -- Timing constants + ----------------------------------------------------------------------- + constant CLOCK_PERIOD : time := 100 ns; + constant T_HOLD : time := 10 ns; + constant T_STROBE : time := CLOCK_PERIOD - (1 ns); + constant TEST_CYCLES : integer := 3000; + constant PHASE_CYCLES : integer := 1000; + + ----------------------------------------------------------------------- + -- DUT input signals + ----------------------------------------------------------------------- + + -- General inputs + signal aclk : std_logic := '0'; -- the master clock + + -- Slave channel A inputs + signal s_axis_a_tvalid : std_logic := '0'; -- TVALID for channel A + signal s_axis_a_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- TDATA for channel A + + -- Slave channel B inputs + signal s_axis_b_tvalid : std_logic := '0'; -- TVALID for channel B + signal s_axis_b_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- TDATA for channel B + + ----------------------------------------------------------------------- + -- DUT output signals + ----------------------------------------------------------------------- + + -- Master channel DOUT outputs + signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel DOUT + signal m_axis_dout_tdata : std_logic_vector(63 downto 0) := (others => '0'); -- TDATA for channel DOUT + + ----------------------------------------------------------------------- + -- Aliases for AXI channel TDATA fields + -- These are a convenience for viewing data in a simulator waveform viewer. + -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command + -- to prevent the simulator optimizing away these signals. + ----------------------------------------------------------------------- + signal s_axis_a_tdata_real : std_logic_vector(11 downto 0) := (others => '0'); + signal s_axis_a_tdata_imag : std_logic_vector(11 downto 0) := (others => '0'); + signal s_axis_b_tdata_real : std_logic_vector(11 downto 0) := (others => '0'); + signal s_axis_b_tdata_imag : std_logic_vector(11 downto 0) := (others => '0'); + signal m_axis_dout_tdata_real : std_logic_vector(24 downto 0) := (others => '0'); + signal m_axis_dout_tdata_imag : std_logic_vector(24 downto 0) := (others => '0'); + + ----------------------------------------------------------------------- + -- Testbench signals + ----------------------------------------------------------------------- + + signal cycles : integer := 0; -- Clock cycle counter + + ----------------------------------------------------------------------- + -- Constants, types and functions to create input data + -- Treat the complex multiplier as a mixer that is combining two + -- sinusoids exp(+/-jwt) of different frequencies and amplitudes: + -- channel A: exp(+jwt), frequency = clock / 30, amplitude = fullscale >> 3 + -- channel B: exp(-jwt), frequency = clock / 32, amplitude = fullscale + -- The output of the complex multiplier is a sinusoid with a frequency + -- equal to the difference between the input frequencies. + ----------------------------------------------------------------------- + + constant IP_A_DEPTH : integer := 30; + constant IP_A_WIDTH : integer := 12; + constant IP_A_SHIFT : integer := 3; -- bit shift for amplitude + constant IP_B_DEPTH : integer := 32; + constant IP_B_WIDTH : integer := 12; + constant IP_B_SHIFT : integer := 0; -- no bit shift, max amplitude + type T_IP_INT_ENTRY is record + re : integer; + im : integer; + end record; + type T_IP_A_ENTRY is record + re : std_logic_vector(IP_A_WIDTH-1 downto 0); + im : std_logic_vector(IP_A_WIDTH-1 downto 0); + end record; + type T_IP_B_ENTRY is record + re : std_logic_vector(IP_B_WIDTH-1 downto 0); + im : std_logic_vector(IP_B_WIDTH-1 downto 0); + end record; + type T_IP_A_TABLE is array (0 to IP_A_DEPTH-1) of T_IP_A_ENTRY; + type T_IP_B_TABLE is array (0 to IP_B_DEPTH-1) of T_IP_B_ENTRY; + + -- Common function to calculate sine and cosine values + function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is + variable result : T_IP_INT_ENTRY; + variable theta : real; + variable limited_width : integer := width - 2; + begin + if limited_width > 30 then + limited_width := 30; + end if; + theta := real(index) / real(depth) * 2.0 * MATH_PI; + result.re := integer(round(cos(theta) * real(2**limited_width-1))); + result.im := integer(round(sin(theta) * real(2**limited_width-1))); + return result; + end function create_ip_entry; + + -- Use separate functions to calculate channel A and B sinusoids as they return different types + function create_ip_a_table return T_IP_A_TABLE is + variable result : T_IP_A_TABLE; + variable entry_int : T_IP_INT_ENTRY; + begin + for i in 0 to IP_A_DEPTH-1 loop + entry_int := create_ip_entry(i, IP_A_DEPTH, IP_A_WIDTH - IP_A_SHIFT); + result(i).re := std_logic_vector(to_signed(entry_int.re, IP_A_WIDTH)); + result(i).im := std_logic_vector(to_signed(entry_int.im, IP_A_WIDTH)); + end loop; + return result; + end function create_ip_a_table; + + function create_ip_b_table return T_IP_B_TABLE is + variable result : T_IP_B_TABLE; + variable entry_int : T_IP_INT_ENTRY; + begin + for i in 0 to IP_B_DEPTH-1 loop + entry_int := create_ip_entry(IP_B_DEPTH-1-i, IP_B_DEPTH, IP_B_WIDTH - IP_B_SHIFT); -- note rotation direction + result(i).re := std_logic_vector(to_signed(entry_int.re, IP_B_WIDTH)); + result(i).im := std_logic_vector(to_signed(entry_int.im, IP_B_WIDTH)); + end loop; + return result; + end function create_ip_b_table; + + -- Call the functions to create the data + constant IP_A_DATA : T_IP_A_TABLE := create_ip_a_table; + constant IP_B_DATA : T_IP_B_TABLE := create_ip_b_table; + + +begin + + ----------------------------------------------------------------------- + -- Instantiate the DUT + ----------------------------------------------------------------------- + + dut : entity work.cmpy_12_12 + port map ( + aclk => aclk, + s_axis_a_tvalid => s_axis_a_tvalid, + s_axis_a_tdata => s_axis_a_tdata, + s_axis_b_tvalid => s_axis_b_tvalid, + s_axis_b_tdata => s_axis_b_tdata, + m_axis_dout_tvalid => m_axis_dout_tvalid, + m_axis_dout_tdata => m_axis_dout_tdata + ); + + ----------------------------------------------------------------------- + -- Generate clock + ----------------------------------------------------------------------- + + clock_gen : process + begin + aclk <= '0'; + wait for CLOCK_PERIOD; + loop + cycles <= cycles + 1; + aclk <= '0'; + wait for CLOCK_PERIOD/2; + aclk <= '1'; + wait for CLOCK_PERIOD/2; + if cycles >= TEST_CYCLES then + report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; + wait; + end if; + end loop; + end process clock_gen; + + ----------------------------------------------------------------------- + -- Generate inputs + ----------------------------------------------------------------------- + + stimuli : process + variable ip_a_index : integer := 0; + variable ip_b_index : integer := 0; + variable a_tvalid_nxt : std_logic := '0'; + variable b_tvalid_nxt : std_logic := '0'; + variable phase2_cycles : integer := 1; + variable phase2_count : integer := 0; + constant PHASE2_LIMIT : integer := 30; + begin + + -- Test is stopped in clock_gen process, use endless loop here + loop + + -- Drive inputs T_HOLD time after rising edge of clock + wait until rising_edge(aclk); + wait for T_HOLD; + + -- Drive AXI TVALID signals to demonstrate different types of operation + case cycles is -- do different types of operation at different phases of the test + when 0 to PHASE_CYCLES * 1 - 1 => + -- Phase 1: inputs always valid, no missing input data + a_tvalid_nxt := '1'; + b_tvalid_nxt := '1'; + when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 => + -- Phase 2: deprive channel A of valid transactions at an increasing rate + b_tvalid_nxt := '1'; + if phase2_count < phase2_cycles then + a_tvalid_nxt := '0'; + else + a_tvalid_nxt := '1'; + end if; + phase2_count := phase2_count + 1; + if phase2_count >= PHASE2_LIMIT then + phase2_count := 0; + phase2_cycles := phase2_cycles + 1; + end if; + when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 => + -- Phase 3: deprive channel A of 1 out of 2 transactions, and channel B of 1 out of 3 transactions + if cycles mod 2 = 0 then + a_tvalid_nxt := '0'; + else + a_tvalid_nxt := '1'; + end if; + if cycles mod 3 = 0 then + b_tvalid_nxt := '0'; + else + b_tvalid_nxt := '1'; + end if; + when others => + -- Test will stop imminently - do nothing + null; + end case; + + -- Drive handshake signals with local variable values + s_axis_a_tvalid <= a_tvalid_nxt; + s_axis_b_tvalid <= b_tvalid_nxt; + + -- Drive AXI slave channel A payload + -- Drive '0's on payload signals when not valid + if a_tvalid_nxt /= '1' then + s_axis_a_tdata <= (others => '0'); + else + -- TDATA: Real and imaginary components are each 12 bits wide and byte-aligned at their LSBs + s_axis_a_tdata(11 downto 0) <= IP_A_DATA(ip_a_index).re; + s_axis_a_tdata(15 downto 12) <= (others => IP_A_DATA(ip_a_index).re(11)); -- sign-extend; + s_axis_a_tdata(27 downto 16) <= IP_A_DATA(ip_a_index).im; + s_axis_a_tdata(31 downto 28) <= (others => IP_A_DATA(ip_a_index).im(11)); -- sign-extend; + end if; + + -- Drive AXI slave channel B payload + -- Drive '0's on payload signals when not valid + if b_tvalid_nxt /= '1' then + s_axis_b_tdata <= (others => '0'); + else + -- TDATA: Real and imaginary components are each 12 bits wide and byte-aligned at their LSBs + s_axis_b_tdata(11 downto 0) <= IP_B_DATA(ip_b_index).re; + s_axis_b_tdata(15 downto 12) <= (others => IP_B_DATA(ip_b_index).re(11)); -- sign-extend + s_axis_b_tdata(27 downto 16) <= IP_B_DATA(ip_b_index).im; + s_axis_b_tdata(31 downto 28) <= (others => IP_B_DATA(ip_b_index).im(11)); -- sign-extend + end if; + + -- Increment input data indices + if a_tvalid_nxt = '1' then + ip_a_index := ip_a_index + 1; + if ip_a_index = IP_A_DEPTH then + ip_a_index := 0; + end if; + end if; + if b_tvalid_nxt = '1' then + ip_b_index := ip_b_index + 1; + if ip_b_index = IP_B_DEPTH then + ip_b_index := 0; + end if; + end if; + + end loop; + + end process stimuli; + + ----------------------------------------------------------------------- + -- Check outputs + ----------------------------------------------------------------------- + + check_outputs : process + variable check_ok : boolean := true; + begin + + -- Check outputs T_STROBE time after rising edge of clock + wait until rising_edge(aclk); + wait for T_STROBE; + + -- Do not check the output payload values, as this requires the behavioral model + -- which would make this demonstration testbench unwieldy. + -- Instead, check the protocol of the DOUT channel: + -- check that the payload is valid (not X) when TVALID is high + + if m_axis_dout_tvalid = '1' then + if is_x(m_axis_dout_tdata) then + report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error; + check_ok := false; + end if; + + end if; + + assert check_ok + report "ERROR: terminating test with failures." severity failure; + + end process check_outputs; + + ----------------------------------------------------------------------- + -- Assign TDATA fields to aliases, for easy simulator waveform viewing + ----------------------------------------------------------------------- + + s_axis_a_tdata_real <= s_axis_a_tdata(11 downto 0); + s_axis_a_tdata_imag <= s_axis_a_tdata(27 downto 16); + s_axis_b_tdata_real <= s_axis_b_tdata(11 downto 0); + s_axis_b_tdata_imag <= s_axis_b_tdata(27 downto 16); + m_axis_dout_tdata_real <= m_axis_dout_tdata(24 downto 0); + m_axis_dout_tdata_imag <= m_axis_dout_tdata(56 downto 32); + +end tb; + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/sim/cmpy_12_12.vhd b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/sim/cmpy_12_12.vhd new file mode 100644 index 00000000..caa806f8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/cmpy_12_12/sim/cmpy_12_12.vhd @@ -0,0 +1,202 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:cmpy:6.0 +-- IP Revision: 17 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY cmpy_v6_0_17; +USE cmpy_v6_0_17.cmpy_v6_0_17; + +ENTITY cmpy_12_12 IS + PORT ( + aclk : IN STD_LOGIC; + s_axis_a_tvalid : IN STD_LOGIC; + s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_b_tvalid : IN STD_LOGIC; + s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_dout_tvalid : OUT STD_LOGIC; + m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END cmpy_12_12; + +ARCHITECTURE cmpy_12_12_arch OF cmpy_12_12 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF cmpy_12_12_arch: ARCHITECTURE IS "yes"; + COMPONENT cmpy_v6_0_17 IS + GENERIC ( + C_VERBOSITY : INTEGER; + C_XDEVICEFAMILY : STRING; + C_XDEVICE : STRING; + C_A_WIDTH : INTEGER; + C_B_WIDTH : INTEGER; + C_OUT_WIDTH : INTEGER; + C_LATENCY : INTEGER; + C_MULT_TYPE : INTEGER; + C_OPTIMIZE_GOAL : INTEGER; + HAS_NEGATE : INTEGER; + SINGLE_OUTPUT : INTEGER; + ROUND : INTEGER; + USE_DSP_CASCADES : INTEGER; + C_THROTTLE_SCHEME : INTEGER; + C_HAS_ACLKEN : INTEGER; + C_HAS_ARESETN : INTEGER; + C_HAS_S_AXIS_A_TUSER : INTEGER; + C_HAS_S_AXIS_A_TLAST : INTEGER; + C_HAS_S_AXIS_B_TUSER : INTEGER; + C_HAS_S_AXIS_B_TLAST : INTEGER; + C_HAS_S_AXIS_CTRL_TUSER : INTEGER; + C_HAS_S_AXIS_CTRL_TLAST : INTEGER; + C_TLAST_RESOLUTION : INTEGER; + C_S_AXIS_A_TDATA_WIDTH : INTEGER; + C_S_AXIS_A_TUSER_WIDTH : INTEGER; + C_S_AXIS_B_TDATA_WIDTH : INTEGER; + C_S_AXIS_B_TUSER_WIDTH : INTEGER; + C_S_AXIS_CTRL_TDATA_WIDTH : INTEGER; + C_S_AXIS_CTRL_TUSER_WIDTH : INTEGER; + C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER; + C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER + ); + PORT ( + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_a_tvalid : IN STD_LOGIC; + s_axis_a_tready : OUT STD_LOGIC; + s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_a_tlast : IN STD_LOGIC; + s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_b_tvalid : IN STD_LOGIC; + s_axis_b_tready : OUT STD_LOGIC; + s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_b_tlast : IN STD_LOGIC; + s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_ctrl_tvalid : IN STD_LOGIC; + s_axis_ctrl_tready : OUT STD_LOGIC; + s_axis_ctrl_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_ctrl_tlast : IN STD_LOGIC; + s_axis_ctrl_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + m_axis_dout_tvalid : OUT STD_LOGIC; + m_axis_dout_tready : IN STD_LOGIC; + m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_dout_tlast : OUT STD_LOGIC; + m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); + END COMPONENT cmpy_v6_0_17; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; +BEGIN + U0 : cmpy_v6_0_17 + GENERIC MAP ( + C_VERBOSITY => 0, + C_XDEVICEFAMILY => "zynq", + C_XDEVICE => "xc7z100", + C_A_WIDTH => 12, + C_B_WIDTH => 12, + C_OUT_WIDTH => 25, + C_LATENCY => 6, + C_MULT_TYPE => 1, + C_OPTIMIZE_GOAL => 0, + HAS_NEGATE => 0, + SINGLE_OUTPUT => 0, + ROUND => 0, + USE_DSP_CASCADES => 1, + C_THROTTLE_SCHEME => 3, + C_HAS_ACLKEN => 0, + C_HAS_ARESETN => 0, + C_HAS_S_AXIS_A_TUSER => 0, + C_HAS_S_AXIS_A_TLAST => 0, + C_HAS_S_AXIS_B_TUSER => 0, + C_HAS_S_AXIS_B_TLAST => 0, + C_HAS_S_AXIS_CTRL_TUSER => 0, + C_HAS_S_AXIS_CTRL_TLAST => 0, + C_TLAST_RESOLUTION => 0, + C_S_AXIS_A_TDATA_WIDTH => 32, + C_S_AXIS_A_TUSER_WIDTH => 1, + C_S_AXIS_B_TDATA_WIDTH => 32, + C_S_AXIS_B_TUSER_WIDTH => 1, + C_S_AXIS_CTRL_TDATA_WIDTH => 8, + C_S_AXIS_CTRL_TUSER_WIDTH => 1, + C_M_AXIS_DOUT_TDATA_WIDTH => 64, + C_M_AXIS_DOUT_TUSER_WIDTH => 1 + ) + PORT MAP ( + aclk => aclk, + aclken => '1', + aresetn => '1', + s_axis_a_tvalid => s_axis_a_tvalid, + s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_a_tlast => '0', + s_axis_a_tdata => s_axis_a_tdata, + s_axis_b_tvalid => s_axis_b_tvalid, + s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_b_tlast => '0', + s_axis_b_tdata => s_axis_b_tdata, + s_axis_ctrl_tvalid => '0', + s_axis_ctrl_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_ctrl_tlast => '0', + s_axis_ctrl_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), + m_axis_dout_tvalid => m_axis_dout_tvalid, + m_axis_dout_tready => '0', + m_axis_dout_tdata => m_axis_dout_tdata + ); +END cmpy_12_12_arch; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.v index d3f1af42..ebfae4d1 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.v +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1443d4bafada7dc1e0c863ea91378c74e51dc722fffc7f31975ed98b8b2156e2 -size 3097268 +oid sha256:4457b319e5020edbb4bc195eedb43c9884c9d55c51bc5a7f7fc7e4e99842a06a +size 3096708 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.vhdl index 4c1fdd72..2c269a41 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:95dd57d9721f3b42d8a90e06529d75215410975e1f142885dbff239c1e3814b9 -size 4406730 +oid sha256:9ca930ab93262dfe23764251a7800e1c2266d5ea0dc0d4bd74d54277f707d802 +size 4405013 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.v index 68b03a4e..79c5f858 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.v +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 19:43:16 2023 +// Date : Mon May 8 19:43:15 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -// Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v +// Command : write_verilog -force -mode synth_stub -rename_top fir_prbs7_invert_rep2 -prefix +// fir_prbs7_invert_rep2_ fir_prbs7_invert_rep2_stub.v // Design : fir_prbs7_invert_rep2 // Purpose : Stub declaration of top-level module interface // Device : xc7z100ffg900-2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.vhdl index 558f6ff5..697ecb8d 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 19:43:16 2023 +-- Date : Mon May 8 19:43:15 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl +-- Command : write_vhdl -force -mode synth_stub -rename_top fir_prbs7_invert_rep2 -prefix +-- fir_prbs7_invert_rep2_ fir_prbs7_invert_rep2_stub.vhdl -- Design : fir_prbs7_invert_rep2 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z100ffg900-2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo index f2bdb947..cad4b747 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo @@ -66,7 +66,9 @@ ila_rx_data_cnt your_instance_name ( .probe6(probe6), // input wire [11:0] probe6 .probe7(probe7), // input wire [11:0] probe7 .probe8(probe8), // input wire [11:0] probe8 - .probe9(probe9) // input wire [12:0] probe9 + .probe9(probe9), // input wire [12:0] probe9 + .probe10(probe10), // input wire [15:0] probe10 + .probe11(probe11) // input wire [15:0] probe11 ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.v index fb313b71..4ecb89b9 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.v +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:58fe8062145bd2d6b613764a172659ba526a33aed3a141d3deff1768e66ca912 -size 9313139 +oid sha256:e3d21e4075a7c3018ed37d668e390b9c0c0c95d8520271d9d365486e3b8f6305 +size 11127106 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.vhdl index 9fae400f..18a1fef2 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3b8c280982b4ebec4e143f0808389c05ec04ca3442de015f049e1b5ac5bfb1e9 -size 11855995 +oid sha256:b3b3d36e9b714a32cf40e2e7a2e08a8c6688d30d5ee593a9a7217bd3c8fa4486 +size 13855799 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v index 361f5c14..fb77bcdd 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Fri May 12 10:13:05 2023 +// Date : Tue May 16 20:23:18 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v @@ -15,8 +15,8 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "ila,Vivado 2019.1.3" *) module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, - probe6, probe7, probe8, probe9) -/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]" */; + probe6, probe7, probe8, probe9, probe10, probe11) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0],probe10[15:0],probe11[15:0]" */; input clk; input [11:0]probe0; input [11:0]probe1; @@ -28,4 +28,6 @@ module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, input [11:0]probe7; input [11:0]probe8; input [12:0]probe9; + input [15:0]probe10; + input [15:0]probe11; endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl index 33c61727..1b0b11d2 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Fri May 12 10:13:05 2023 +-- Date : Tue May 16 20:23:18 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl @@ -24,7 +24,9 @@ entity ila_rx_data_cnt is probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 ); probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 ); probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 ); - probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 ) + probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); end ila_rx_data_cnt; @@ -33,7 +35,7 @@ architecture stub of ila_rx_data_cnt is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0],probe10[15:0],probe11[15:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; begin diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v index 8cf8464f..38e2cbc4 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v @@ -59,7 +59,9 @@ probe5, probe6, probe7, probe8, -probe9 +probe9, +probe10, +probe11 ); input clk; @@ -75,6 +77,8 @@ input [11 : 0] probe6; input [11 : 0] probe7; input [11 : 0] probe8; input [12 : 0] probe9; +input [15 : 0] probe10; +input [15 : 0] probe11; endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/hdl/vio_v3_0_20_vio_include.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/hdl/vio_v3_0_20_vio_include.v new file mode 100644 index 00000000..0673f57f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/hdl/vio_v3_0_20_vio_include.v @@ -0,0 +1,283 @@ +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "XILINX" +`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`pragma protect key_block +GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx +XWe4lBDDrw== + +`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH +9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c +eVhT3XSIJDvufMyiJUc= + +`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit +pNc3Ov7QvW8kjTq3JHFuCf7SmCYRrmElQv0XobTk6mnMb4khaXw9wTP8YMS0XAqk3Bksal+aKfvX +LL/afyM4UwBfiIb04ZgvhdOlp/dkCqWqZyDL2qVScyGrZcDCW3CCZTVQO29hqMLZP5S82keXpBv3 +5J7nHHbQ3n4dxsRykYtJtwg7JDyqGHiwhj1HDtjhG+LX9ry1wy5YgvxrzSfKoouAeHCKXcG7TY0a +sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ== + +`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +ItrqCM44kZl0WwWeSAjetSYD0fPwYZdVjFp5cRl5XZyoYOMWKCVEXncinM06x/MDVlkYiXgz2Xqn +6ui7jR7RwOKALvqoqdehIoXZUA/5yPMntFpxPcFIY1DonBI4CuMjhqCuB2RkxKNIco5Z7/QxCk49 +MCUlvIFRd2MXM+zvhCRdja7e9blnwJEUETukq+EKuAwuR3+VN3uzCXsNtgBqMZa2CyM6Z60fStuc +v1eiDP/hxOimuSfsS7evakl5WMjgZuj4Jld1+y5hTOuPvw4+s3KIb2ejIH2r/I7ui7sWUZTah36a +4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A== + +`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v +ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX +cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC +xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa +draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg== + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv +j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO +R19uHYIhWP+7IpmjTiQ= + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM +kLLATubglrp6DudyaIY943skTmlH+as6fKaHODrTcy4CDIP4kKrok/7y1rBI6+YAfN3ZIW+45MiV +cHuhXHXxxXblzCT6obAZK5QUCP2qZKgO0jjI1RD7ZEJuS/mX5wkIAvOe8L1HBkyUsRq6Cu30W6u9 +7VI3LOy7TZqb6Nix6Ok85ylO82KP12tdXY2IRivakKu4fdWQ6vc3ARiefSR0+RDmE/eZzhzQbt26 +mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q== + +`pragma protect data_method = "AES128-CBC" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464) +`pragma protect data_block +vLDJJUgjrlRfGtI6e1+Byt5lDBB9Oezy8FH9Uy/Lem9icZpnVjts8rEqPHcw31BJ5u3y4ePWkCUm +QQfQ8vh3WaO2dCX+QhbDMTmPaIe/t8nHJKefrbW5OY3eRKkptlVSIFCFITpJlzyfpSe0CsF+dWLc +F4J0aJzlQEKkTcCFk2ey1erWcvHgIf6eCwkGouO/COjRPomcaMzJt3ty3PwhKodmumGUICNXKjG/ +lH5VI4pSkr0hpeNp/WZhHstrrYJB7GSwMCqfL0IH36wCF3R29Yjp7ouoogJ4+imS5vnMJpU2Czmi +PFyY3LiBeZ4VP5b8Iv0AK4XoJtM3XG9iTBAC/oslCJUtBhINFPia8EueAVn178qtq+htmZXlEAbM +O43w6xZ55fggub8NiHe8M4qAhDC0nwv3LBVndn8xEKF+13iwSiqhLjU1Cya8z+0j0TUExIeVQyri +OXh0d9oxCJ2lfPtNjHZ3LkjbMLvzdJG8pBuDtx5952IJrwkJIaT76aOEs7XK8O+cfrtfhh1fPpY1 +XTzoMx95+Qp7Ay2J8NObIZHBuUKX2ORE3b7zSBW5FPRjaxTibHQ2blQzoAbo5y5f30hxOHsi0+Xe +D4bwHKzoBpsdKAyvlKom17BBx5Q5KccIElz3z9ulgthM6zwAWmMVPzQnJAhmz3Hl3t0m7+YNA4Ia +cg/H8tiXcV6CEnRuaFRr8dvkZAlT16o4u+tEwi85XgpkoApFQ7EytG673+LigwZbb2C7khwEoIiw +1LN4Eh9i2WsLPaEipn3q58x1rH4/MEzwsGw7loWE4BkCf+n5QAWYc/nk4xfSwFTBvxs6sPejsrRX +qbtO8ZOnKuVTT2ZLwEtvGrf+Ii1Xymt1JsQt7Z0QBWTykLt0ZhWTrPnMg/zcRxyRCDNYWVJx8JKC +Fjg1XzSDYIYff4HaLPjmiu5sPEXaKTQJvaZa52Dq87oKwWI0A3g0ymKK7UVXrmX/odtLOlHIxuhy +JnruUntWueD34KJMT2lBO7AP0g/OmHDI6v72Q/2Tk66QaWfnnDJl6qRN2WDuGyNuwSflbEGQiK02 +vyM4a6K9KN70ev9aLX4d2m7Uo9n4GFbdvjakrlHDS/K+TRs6XmOa+y8ErWxn9Pfy9UyRrFg1TdQb +Zk69XUdoQZ6CNWoKazZHaJ5p5+6nk/G0nm8LR039U2sqH+B1hJMuvFvsx4NzEoYpE1jNsiy4B9Ta +ArVNSpGuZCA4Juifia1UC8m+mMYsLBACf9YX/Uua3EeOfU2CEi5koPuBzR/QKb/1oRa3x2oux2Cf ++p+HcJdQfSOpF6AkpWZLChsoTMd2F24Ztmjz3/vNIapPf4rcObfDEJwayu7hSrsslcCIcoXdojo4 +VXLn2QFVUYMgSq3pYGFywvmQTA5x/JAfOcWO8IBKdixvS3F6xSTwH8JaKocC0735inh65PwNjS9F +2KIwvgHQvLpCxNny+0NvSQ7ETTouC6xXj+EUv4bGpml7J3HNjixHtTPfYXf7cl0mqQmUDJu0wLkp +WuvXFDvCxpwSZ5qw+1H5MPeue3MeB1Z6Ibu51Fs1EwnAe/g9C0Mo1XDCD6LfVjvpZYE62HzlzF/K +IJoLfeJT0O0VhjqhC3+M3TGXHNYm6chuUtfNR31cC7WgG/QiHYOVySvp3zljDZWrxsgHO+JwhbQC +n8ALL+g50X6+uS5w/HkFBsxwCIocmViJb0ojg1j2ncsUjwwEqkDBprVPYFh6Zimk5SJ9f3RO6pQj +saDd3hitIgpMf1ha8rpCYBkwqBTogxXfwijLMplBdGWVGSSSnnp6jTnWb0sV2VPA1l2X6Iq+pomM +jilYYfQ2dBuXFEMpQpwDC3/8N4YxpDZWX3gtyK2XV+2BcRONvrl/naflTsXxuXAhSxOBqggJw7pL +HvsOGKk0ng6uKC5yQPc6Q0SbWwwT54D9vLM4U1OiRKPpL9S1YXak+W8ZCXqdHkQNlUlm21ssL4dl +Et7q9IF5Vil/wnUjm0nJxVZ4QJU/uN7icrtnrvAf1gVLwK3fpC0ed6ku9s7Lq1KvNb7NEPDrOu3Q +hg+xhyl9MJTquidnbUsYlHdTvVzxIkI4q/1kx5mkbEjiIWG0R+haIwSqhTCdxpxxTgm+LGAtWJ4W +lEuCQ2VEu3cyamx3PWNKPt+CE1VayIkgGqEBXIaGpwkymL0y6hkgrA+q+2msQq245iR7XC83U26E +yb3da4UnYxL7g5WjJCSfCdNVOkKS1Yl9VZ6XSW5RFwWIdURQyewZxfPKaJWsDAGfpRftpZ2mOfIl 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b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/sim/vio_phase_comp.v @@ -0,0 +1,77 @@ +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module vio_phase_comp ( +clk, +probe_in0, +probe_out0, +probe_out1, +probe_out2, +probe_out3, +probe_out4, +probe_out5, +probe_out6, +probe_out7, +probe_out8 +); + +input clk; +input [0 : 0] probe_in0; + +output reg [11 : 0] probe_out0 = 'h000 ; +output reg [11 : 0] probe_out1 = 'h000 ; +output reg [11 : 0] probe_out2 = 'h000 ; +output reg [11 : 0] probe_out3 = 'h000 ; +output reg [11 : 0] probe_out4 = 'h000 ; +output reg [11 : 0] probe_out5 = 'h000 ; +output reg [11 : 0] probe_out6 = 'h000 ; +output reg [11 : 0] probe_out7 = 'h000 ; +output reg [4 : 0] probe_out8 = 'h00 ; + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo new file mode 100644 index 00000000..668c01ac --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo @@ -0,0 +1,75 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:vio:3.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +vio_phase_comp your_instance_name ( + .clk(clk), // input wire clk + .probe_in0(probe_in0), // input wire [0 : 0] probe_in0 + .probe_out0(probe_out0), // output wire [11 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [11 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [11 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [11 : 0] probe_out3 + .probe_out4(probe_out4), // output wire [11 : 0] probe_out4 + .probe_out5(probe_out5), // output wire [11 : 0] probe_out5 + .probe_out6(probe_out6), // output wire [11 : 0] probe_out6 + .probe_out7(probe_out7), // output wire [11 : 0] probe_out7 + .probe_out8(probe_out8) // output wire [4 : 0] probe_out8 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file vio_phase_comp.v when simulating +// the core, vio_phase_comp. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho new file mode 100644 index 00000000..fcc7fd2e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho @@ -0,0 +1,95 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:vio:3.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT vio_phase_comp + PORT ( + clk : IN STD_LOGIC; + probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out7 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out8 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : vio_phase_comp + PORT MAP ( + clk => clk, + probe_in0 => probe_in0, + probe_out0 => probe_out0, + probe_out1 => probe_out1, + probe_out2 => probe_out2, + probe_out3 => probe_out3, + probe_out4 => probe_out4, + probe_out5 => probe_out5, + probe_out6 => probe_out6, + probe_out7 => probe_out7, + probe_out8 => probe_out8 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file vio_phase_comp.vhd when simulating +-- the core, vio_phase_comp. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v new file mode 100644 index 00000000..2b9397b2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8a728b012261b1286ce2ddcfedc2eecde9e96f716da1a2094500d54e679c5dd3 +size 380163 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl new file mode 100644 index 00000000..ad53fde5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:62b0acda5c13e66909336af54eb0f6e79069e5c29116db14c7adc72123650fd9 +size 674599 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v similarity index 54% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v rename to projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v index 68b03a4e..0ed89469 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v @@ -1,11 +1,11 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 19:43:16 2023 +// Date : Tue May 16 20:22:24 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v -// Design : fir_prbs7_invert_rep2 +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v +// Design : vio_phase_comp // Purpose : Stub declaration of top-level module interface // Device : xc7z100ffg900-2 // -------------------------------------------------------------------------------- @@ -13,15 +13,19 @@ // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) -module fir_prbs7_invert_rep2(aresetn, aclk, s_axis_data_tvalid, - s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) -/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */; - input aresetn; - input aclk; - input s_axis_data_tvalid; - output s_axis_data_tready; - input [15:0]s_axis_data_tdata; - output m_axis_data_tvalid; - output [23:0]m_axis_data_tdata; +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_phase_comp(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[11:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[4:0]" */; + input clk; + input [0:0]probe_in0; + output [11:0]probe_out0; + output [11:0]probe_out1; + output [11:0]probe_out2; + output [11:0]probe_out3; + output [11:0]probe_out4; + output [11:0]probe_out5; + output [11:0]probe_out6; + output [11:0]probe_out7; + output [4:0]probe_out8; endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl new file mode 100644 index 00000000..f86dcd1a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Tue May 16 20:22:24 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl +-- Design : vio_phase_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_phase_comp is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + +end vio_phase_comp; + +architecture stub of vio_phase_comp is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[11:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[4:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/README.txt new file mode 100644 index 00000000..bb7f501a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:15:18 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12_12.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12_12.sh' script. + +./cmpy_12_12.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12_12.sh -noclean_files + +For more information on the script, please type './cmpy_12_12.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/cmpy_12_12.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/cmpy_12_12.sh new file mode 100755 index 00000000..40a50fca --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/cmpy_12_12.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12_12.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:15:18 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12_12.sh [-help] +# usage: cmpy_12_12.sh [-lib_map_path] +# usage: cmpy_12_12.sh [-noclean_files] +# usage: cmpy_12_12.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12_12.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12_12.sh [-help]\n\ +Usage: cmpy_12_12.sh [-lib_map_path]\n\ +Usage: cmpy_12_12.sh [-reset_run]\n\ +Usage: cmpy_12_12.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/cmpy_12_12.udo similarity index 100% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.Vivado_Synthesis.queue.rst rename to projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/cmpy_12_12.udo diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/compile.do new file mode 100644 index 00000000..3d667cda --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/compile.do @@ -0,0 +1,52 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/xbip_utils_v3_0_10 +vlib activehdl/axi_utils_v2_0_6 +vlib activehdl/xbip_pipe_v3_0_6 +vlib activehdl/xbip_bram18k_v3_0_6 +vlib activehdl/mult_gen_v12_0_15 +vlib activehdl/cmpy_v6_0_17 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6 +vmap xbip_pipe_v3_0_6 activehdl/xbip_pipe_v3_0_6 +vmap xbip_bram18k_v3_0_6 activehdl/xbip_bram18k_v3_0_6 +vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15 +vmap cmpy_v6_0_17 activehdl/cmpy_v6_0_17 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work xbip_pipe_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_bram18k_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + +vcom -work mult_gen_v12_0_15 -93 \ +"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + +vcom -work cmpy_v6_0_17 -93 \ +"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/file_info.txt new file mode 100644 index 00000000..23e28370 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/simulate.do new file mode 100644 index 00000000..2f53d734 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+cmpy_12_12 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {cmpy_12_12.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/README.txt new file mode 100644 index 00000000..7dd7c7e4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:15:18 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12_12.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12_12.sh' script. + +./cmpy_12_12.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12_12.sh -noclean_files + +For more information on the script, please type './cmpy_12_12.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/cmpy_12_12.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/cmpy_12_12.sh new file mode 100755 index 00000000..470e1909 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/cmpy_12_12.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12_12.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:15:18 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12_12.sh [-help] +# usage: cmpy_12_12.sh [-lib_map_path] +# usage: cmpy_12_12.sh [-noclean_files] +# usage: cmpy_12_12.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12_12.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.cmpy_12_12 \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12_12.sh [-help]\n\ +Usage: cmpy_12_12.sh [-lib_map_path]\n\ +Usage: cmpy_12_12.sh [-reset_run]\n\ +Usage: cmpy_12_12.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/file_info.txt new file mode 100644 index 00000000..23e28370 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/run.f new file mode 100644 index 00000000..c5e20897 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/ies/run.f @@ -0,0 +1,32 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xbip_utils_v3_0_10 \ + "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/axi_utils_v2_0_6 \ + "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xbip_pipe_v3_0_6 \ + "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xbip_bram18k_v3_0_6 \ + "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/mult_gen_v12_0_15 \ + "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/cmpy_v6_0_17 \ + "../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/README.txt new file mode 100644 index 00000000..bb7f501a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:15:18 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12_12.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12_12.sh' script. + +./cmpy_12_12.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12_12.sh -noclean_files + +For more information on the script, please type './cmpy_12_12.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/cmpy_12_12.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/cmpy_12_12.sh new file mode 100755 index 00000000..4daa0f73 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/cmpy_12_12.sh @@ -0,0 +1,168 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12_12.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:15:18 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12_12.sh [-help] +# usage: cmpy_12_12.sh [-lib_map_path] +# usage: cmpy_12_12.sh [-noclean_files] +# usage: cmpy_12_12.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12_12.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12_12.sh [-help]\n\ +Usage: cmpy_12_12.sh [-lib_map_path]\n\ +Usage: cmpy_12_12.sh [-reset_run]\n\ +Usage: cmpy_12_12.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/cmpy_12_12.udo similarity index 100% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.vivado.end.rst rename to projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/cmpy_12_12.udo diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/compile.do new file mode 100644 index 00000000..f4aacf88 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/compile.do @@ -0,0 +1,52 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/xbip_utils_v3_0_10 +vlib modelsim_lib/msim/axi_utils_v2_0_6 +vlib modelsim_lib/msim/xbip_pipe_v3_0_6 +vlib modelsim_lib/msim/xbip_bram18k_v3_0_6 +vlib modelsim_lib/msim/mult_gen_v12_0_15 +vlib modelsim_lib/msim/cmpy_v6_0_17 + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm +vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6 +vmap xbip_pipe_v3_0_6 modelsim_lib/msim/xbip_pipe_v3_0_6 +vmap xbip_bram18k_v3_0_6 modelsim_lib/msim/xbip_bram18k_v3_0_6 +vmap mult_gen_v12_0_15 modelsim_lib/msim/mult_gen_v12_0_15 +vmap cmpy_v6_0_17 modelsim_lib/msim/cmpy_v6_0_17 + +vlog -work xil_defaultlib -64 -incr -sv \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -64 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -64 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work xbip_pipe_v3_0_6 -64 -93 \ +"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_bram18k_v3_0_6 -64 -93 \ +"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + +vcom -work mult_gen_v12_0_15 -64 -93 \ +"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + +vcom -work cmpy_v6_0_17 -64 -93 \ +"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/file_info.txt new file mode 100644 index 00000000..23e28370 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/simulate.do new file mode 100644 index 00000000..0f058507 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {cmpy_12_12.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/README.txt new file mode 100644 index 00000000..bb7f501a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:15:18 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12_12.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12_12.sh' script. + +./cmpy_12_12.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12_12.sh -noclean_files + +For more information on the script, please type './cmpy_12_12.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/cmpy_12_12.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/cmpy_12_12.sh new file mode 100755 index 00000000..b1252c5b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/cmpy_12_12.sh @@ -0,0 +1,173 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12_12.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:15:18 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12_12.sh [-help] +# usage: cmpy_12_12.sh [-lib_map_path] +# usage: cmpy_12_12.sh [-noclean_files] +# usage: cmpy_12_12.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12_12.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12_12.sh [-help]\n\ +Usage: cmpy_12_12.sh [-lib_map_path]\n\ +Usage: cmpy_12_12.sh [-reset_run]\n\ +Usage: cmpy_12_12.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/cmpy_12_12.udo similarity index 100% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/__synthesis_is_complete__ rename to projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/cmpy_12_12.udo diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/compile.do new file mode 100644 index 00000000..3e9b3337 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/compile.do @@ -0,0 +1,52 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/xbip_utils_v3_0_10 +vlib questa_lib/msim/axi_utils_v2_0_6 +vlib questa_lib/msim/xbip_pipe_v3_0_6 +vlib questa_lib/msim/xbip_bram18k_v3_0_6 +vlib questa_lib/msim/mult_gen_v12_0_15 +vlib questa_lib/msim/cmpy_v6_0_17 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6 +vmap xbip_pipe_v3_0_6 questa_lib/msim/xbip_pipe_v3_0_6 +vmap xbip_bram18k_v3_0_6 questa_lib/msim/xbip_bram18k_v3_0_6 +vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15 +vmap cmpy_v6_0_17 questa_lib/msim/cmpy_v6_0_17 + +vlog -work xil_defaultlib -64 -sv \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -64 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -64 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work xbip_pipe_v3_0_6 -64 -93 \ +"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_bram18k_v3_0_6 -64 -93 \ +"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + +vcom -work mult_gen_v12_0_15 -64 -93 \ +"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + +vcom -work cmpy_v6_0_17 -64 -93 \ +"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/elaborate.do new file mode 100644 index 00000000..ad89ee5f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl -o cmpy_12_12_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/file_info.txt new file mode 100644 index 00000000..23e28370 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/simulate.do new file mode 100644 index 00000000..86bbddc6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib cmpy_12_12_opt + +do {wave.do} + +view wave +view structure +view signals + +do {cmpy_12_12.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/README.txt new file mode 100644 index 00000000..bb7f501a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:15:18 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12_12.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12_12.sh' script. + +./cmpy_12_12.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12_12.sh -noclean_files + +For more information on the script, please type './cmpy_12_12.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/cmpy_12_12.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/cmpy_12_12.sh new file mode 100755 index 00000000..24c9a8fd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/cmpy_12_12.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12_12.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:15:18 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12_12.sh [-help] +# usage: cmpy_12_12.sh [-lib_map_path] +# usage: cmpy_12_12.sh [-noclean_files] +# usage: cmpy_12_12.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12_12.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12_12.sh [-help]\n\ +Usage: cmpy_12_12.sh [-lib_map_path]\n\ +Usage: cmpy_12_12.sh [-reset_run]\n\ +Usage: cmpy_12_12.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/cmpy_12_12.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/cmpy_12_12.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/compile.do new file mode 100644 index 00000000..007b008f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/compile.do @@ -0,0 +1,52 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/xbip_utils_v3_0_10 +vlib riviera/axi_utils_v2_0_6 +vlib riviera/xbip_pipe_v3_0_6 +vlib riviera/xbip_bram18k_v3_0_6 +vlib riviera/mult_gen_v12_0_15 +vlib riviera/cmpy_v6_0_17 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6 +vmap xbip_pipe_v3_0_6 riviera/xbip_pipe_v3_0_6 +vmap xbip_bram18k_v3_0_6 riviera/xbip_bram18k_v3_0_6 +vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15 +vmap cmpy_v6_0_17 riviera/cmpy_v6_0_17 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work xbip_pipe_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + +vcom -work xbip_bram18k_v3_0_6 -93 \ +"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + +vcom -work mult_gen_v12_0_15 -93 \ +"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + +vcom -work cmpy_v6_0_17 -93 \ +"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/file_info.txt new file mode 100644 index 00000000..23e28370 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/simulate.do new file mode 100644 index 00000000..2f53d734 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+cmpy_12_12 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {cmpy_12_12.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/README.txt new file mode 100644 index 00000000..bb7f501a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:15:18 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12_12.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12_12.sh' script. + +./cmpy_12_12.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12_12.sh -noclean_files + +For more information on the script, please type './cmpy_12_12.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/cmpy_12_12.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/cmpy_12_12.sh new file mode 100755 index 00000000..6b7a081d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/cmpy_12_12.sh @@ -0,0 +1,253 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12_12.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:15:18 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12_12.sh [-help] +# usage: cmpy_12_12.sh [-lib_map_path] +# usage: cmpy_12_12.sh [-noclean_files] +# usage: cmpy_12_12.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12_12.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work axi_utils_v2_0_6 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xbip_pipe_v3_0_6 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xbip_bram18k_v3_0_6 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work mult_gen_v12_0_15 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work cmpy_v6_0_17 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \ + 2>&1 | tee -a vhdlan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl -o cmpy_12_12_simv +} + +# RUN_STEP: +simulate() +{ + ./cmpy_12_12_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key cmpy_12_12_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc cmpy_12_12_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12_12.sh [-help]\n\ +Usage: cmpy_12_12.sh [-lib_map_path]\n\ +Usage: cmpy_12_12.sh [-reset_run]\n\ +Usage: cmpy_12_12.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/file_info.txt new file mode 100644 index 00000000..23e28370 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/README.txt new file mode 100644 index 00000000..7dd7c7e4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:15:18 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12_12.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12_12.sh' script. + +./cmpy_12_12.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12_12.sh -noclean_files + +For more information on the script, please type './cmpy_12_12.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/cmpy_12_12.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/cmpy_12_12.sh new file mode 100755 index 00000000..02759dec --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/cmpy_12_12.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12_12.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:15:18 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12_12.sh [-help] +# usage: cmpy_12_12.sh [-lib_map_path] +# usage: cmpy_12_12.sh [-noclean_files] +# usage: cmpy_12_12.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'cmpy_12_12.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.cmpy_12_12 \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12_12.sh [-help]\n\ +Usage: cmpy_12_12.sh [-lib_map_path]\n\ +Usage: cmpy_12_12.sh [-reset_run]\n\ +Usage: cmpy_12_12.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/file_info.txt new file mode 100644 index 00000000..23e28370 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, +xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, +xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, +mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, +cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd, +cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/run.f new file mode 100644 index 00000000..d85fe821 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xcelium/run.f @@ -0,0 +1,32 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xbip_utils_v3_0_10 \ + "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/axi_utils_v2_0_6 \ + "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xbip_pipe_v3_0_6 \ + "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xbip_bram18k_v3_0_6 \ + "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/mult_gen_v12_0_15 \ + "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/cmpy_v6_0_17 \ + "../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/README.txt new file mode 100644 index 00000000..bb7f501a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:15:18 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./cmpy_12_12.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './cmpy_12_12.sh' script. + +./cmpy_12_12.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./cmpy_12_12.sh -noclean_files + +For more information on the script, please type './cmpy_12_12.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/cmpy_12_12.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/cmpy_12_12.sh new file mode 100755 index 00000000..b5deffc4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/cmpy_12_12.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : cmpy_12_12.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:15:18 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: cmpy_12_12.sh [-help] +# usage: cmpy_12_12.sh [-lib_map_path] +# usage: cmpy_12_12.sh [-noclean_files] +# usage: cmpy_12_12.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" +xvhdl_opts="--relax" + + +# Script info +echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot cmpy_12_12 xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim cmpy_12_12 -key {Behavioral:sim_1:Functional:cmpy_12_12} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb cmpy_12_12.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: cmpy_12_12.sh [-help]\n\ +Usage: cmpy_12_12.sh [-lib_map_path]\n\ +Usage: cmpy_12_12.sh [-reset_run]\n\ +Usage: cmpy_12_12.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/file_info.txt new file mode 100644 index 00000000..48623266 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/file_info.txt @@ -0,0 +1,2 @@ +cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/vhdl.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/vhdl.prj new file mode 100644 index 00000000..42232dcf --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/vhdl.prj @@ -0,0 +1,4 @@ +vhdl xil_defaultlib \ +"../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \ + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/vlog.prj new file mode 100644 index 00000000..35119d5b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/cmpy_12_12/xsim/vlog.prj @@ -0,0 +1,4 @@ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/README.txt index 040622af..870eebd1 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# Generated by export_simulation on Tue May 16 20:24:34 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.sh index 4f5b0b38..e1d35f79 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/activehdl/fir_prbs7_invert_rep2.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# Generated by Vivado on Tue May 16 20:24:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/README.txt index 0435eb8b..08d4961b 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# Generated by export_simulation on Tue May 16 20:24:34 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/fir_prbs7_invert_rep2.sh index a5f4219a..a0c23dcd 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/fir_prbs7_invert_rep2.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/ies/fir_prbs7_invert_rep2.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# Generated by Vivado on Tue May 16 20:24:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/README.txt index 040622af..870eebd1 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# Generated by export_simulation on Tue May 16 20:24:34 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.sh index 0771f27b..5476904b 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/modelsim/fir_prbs7_invert_rep2.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# Generated by Vivado on Tue May 16 20:24:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/README.txt index 040622af..870eebd1 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# Generated by export_simulation on Tue May 16 20:24:34 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.sh index 2fdee444..b5c19760 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/questa/fir_prbs7_invert_rep2.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# Generated by Vivado on Tue May 16 20:24:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/README.txt index 040622af..870eebd1 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# Generated by export_simulation on Tue May 16 20:24:34 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.sh index d1b2b808..bf781042 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/riviera/fir_prbs7_invert_rep2.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# Generated by Vivado on Tue May 16 20:24:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/README.txt index 040622af..870eebd1 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# Generated by export_simulation on Tue May 16 20:24:34 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/fir_prbs7_invert_rep2.sh index 02d748e9..07230100 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/fir_prbs7_invert_rep2.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/vcs/fir_prbs7_invert_rep2.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# Generated by Vivado on Tue May 16 20:24:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/README.txt index 0435eb8b..08d4961b 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# Generated by export_simulation on Tue May 16 20:24:34 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/fir_prbs7_invert_rep2.sh index 440bf721..7f787690 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/fir_prbs7_invert_rep2.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xcelium/fir_prbs7_invert_rep2.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# Generated by Vivado on Tue May 16 20:24:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/README.txt index 040622af..870eebd1 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 19:42:46 CST 2023 +# Generated by export_simulation on Tue May 16 20:24:34 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/fir_prbs7_invert_rep2.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/fir_prbs7_invert_rep2.sh index 8285dd81..930e2228 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/fir_prbs7_invert_rep2.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep2/xsim/fir_prbs7_invert_rep2.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 19:42:46 CST 2023 +# Generated by Vivado on Tue May 16 20:24:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/README.txt index 7b595ceb..4fa3fac0 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Fri May 12 10:10:58 CST 2023 +# Generated by export_simulation on Tue May 16 20:20:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.sh index 8e7209b3..9219ab57 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Fri May 12 10:10:58 CST 2023 +# Generated by Vivado on Tue May 16 20:20:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/README.txt index 00744917..4ea017cc 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Fri May 12 10:10:58 CST 2023 +# Generated by export_simulation on Tue May 16 20:20:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/ila_rx_data_cnt.sh index 6559ba6e..f05f9107 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/ila_rx_data_cnt.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/ila_rx_data_cnt.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Fri May 12 10:10:58 CST 2023 +# Generated by Vivado on Tue May 16 20:20:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/README.txt index 7b595ceb..4fa3fac0 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Fri May 12 10:10:58 CST 2023 +# Generated by export_simulation on Tue May 16 20:20:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.sh index 6cc8afb6..d3b6173a 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Fri May 12 10:10:58 CST 2023 +# Generated by Vivado on Tue May 16 20:20:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/README.txt index 7b595ceb..4fa3fac0 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Fri May 12 10:10:58 CST 2023 +# Generated by export_simulation on Tue May 16 20:20:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.sh index 4d0dd0f3..dfd84624 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Fri May 12 10:10:58 CST 2023 +# Generated by Vivado on Tue May 16 20:20:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/README.txt index 7b595ceb..4fa3fac0 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Fri May 12 10:10:58 CST 2023 +# Generated by export_simulation on Tue May 16 20:20:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.sh index 4f1bb1f1..15cc4104 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Fri May 12 10:10:58 CST 2023 +# Generated by Vivado on Tue May 16 20:20:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/README.txt index 7b595ceb..4fa3fac0 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Fri May 12 10:10:58 CST 2023 +# Generated by export_simulation on Tue May 16 20:20:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/ila_rx_data_cnt.sh index 0aa022db..046b47b6 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/ila_rx_data_cnt.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/ila_rx_data_cnt.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Fri May 12 10:10:58 CST 2023 +# Generated by Vivado on Tue May 16 20:20:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/README.txt index 00744917..4ea017cc 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Fri May 12 10:10:58 CST 2023 +# Generated by export_simulation on Tue May 16 20:20:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/ila_rx_data_cnt.sh index ad25db8d..b9330763 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/ila_rx_data_cnt.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/ila_rx_data_cnt.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Fri May 12 10:10:58 CST 2023 +# Generated by Vivado on Tue May 16 20:20:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/README.txt index 7b595ceb..4fa3fac0 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Fri May 12 10:10:58 CST 2023 +# Generated by export_simulation on Tue May 16 20:20:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/ila_rx_data_cnt.sh index 8724775a..5213dcfc 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/ila_rx_data_cnt.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/ila_rx_data_cnt.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Fri May 12 10:10:58 CST 2023 +# Generated by Vivado on Tue May 16 20:20:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt new file mode 100644 index 00000000..0c519bc5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:22:06 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_phase_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_phase_comp.sh' script. + +./vio_phase_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_phase_comp.sh -noclean_files + +For more information on the script, please type './vio_phase_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/compile.do new file mode 100644 index 00000000..da938526 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \ +"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/file_info.txt new file mode 100644 index 00000000..65344b7e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/simulate.do new file mode 100644 index 00000000..f374ee9b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_phase_comp -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_phase_comp xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_phase_comp.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh new file mode 100755 index 00000000..7db631db --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_phase_comp.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:22:06 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_phase_comp.sh [-help] +# usage: vio_phase_comp.sh [-lib_map_path] +# usage: vio_phase_comp.sh [-noclean_files] +# usage: vio_phase_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_phase_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_phase_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_phase_comp.sh [-help]\n\ +Usage: vio_phase_comp.sh [-lib_map_path]\n\ +Usage: vio_phase_comp.sh [-reset_run]\n\ +Usage: vio_phase_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt new file mode 100644 index 00000000..4a25ed7e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:22:06 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_phase_comp.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_phase_comp.sh' script. + +./vio_phase_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_phase_comp.sh -noclean_files + +For more information on the script, please type './vio_phase_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/file_info.txt new file mode 100644 index 00000000..65344b7e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/run.f new file mode 100644 index 00000000..7a543bd3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh new file mode 100755 index 00000000..b91f767f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_phase_comp.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:22:06 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_phase_comp.sh [-help] +# usage: vio_phase_comp.sh [-lib_map_path] +# usage: vio_phase_comp.sh [-noclean_files] +# usage: vio_phase_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_phase_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "vio_phase_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_phase_comp \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_phase_comp/hdl/verilog" \ + +incdir+"../../../ip/vio_phase_comp/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_phase_comp.sh [-help]\n\ +Usage: vio_phase_comp.sh [-lib_map_path]\n\ +Usage: vio_phase_comp.sh [-reset_run]\n\ +Usage: vio_phase_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt new file mode 100644 index 00000000..0c519bc5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:22:06 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_phase_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_phase_comp.sh' script. + +./vio_phase_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_phase_comp.sh -noclean_files + +For more information on the script, please type './vio_phase_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/compile.do new file mode 100644 index 00000000..0d981915 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \ +"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/file_info.txt new file mode 100644 index 00000000..90cc7c08 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/file_info.txt @@ -0,0 +1,2 @@ +vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/simulate.do new file mode 100644 index 00000000..3edc5467 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_phase_comp xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {vio_phase_comp.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh new file mode 100755 index 00000000..f7b0d673 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_phase_comp.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:22:06 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_phase_comp.sh [-help] +# usage: vio_phase_comp.sh [-lib_map_path] +# usage: vio_phase_comp.sh [-noclean_files] +# usage: vio_phase_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_phase_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_phase_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_phase_comp.sh [-help]\n\ +Usage: vio_phase_comp.sh [-lib_map_path]\n\ +Usage: vio_phase_comp.sh [-reset_run]\n\ +Usage: vio_phase_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt new file mode 100644 index 00000000..0c519bc5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:22:06 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_phase_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_phase_comp.sh' script. + +./vio_phase_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_phase_comp.sh -noclean_files + +For more information on the script, please type './vio_phase_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/compile.do new file mode 100644 index 00000000..d35ff983 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \ +"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/elaborate.do new file mode 100644 index 00000000..5b02ef35 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_phase_comp xil_defaultlib.glbl -o vio_phase_comp_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/file_info.txt new file mode 100644 index 00000000..65344b7e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/simulate.do new file mode 100644 index 00000000..8e9e0706 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib vio_phase_comp_opt + +do {wave.do} + +view wave +view structure +view signals + +do {vio_phase_comp.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh new file mode 100755 index 00000000..19a44f70 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_phase_comp.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:22:06 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_phase_comp.sh [-help] +# usage: vio_phase_comp.sh [-lib_map_path] +# usage: vio_phase_comp.sh [-noclean_files] +# usage: vio_phase_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_phase_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_phase_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_phase_comp.sh [-help]\n\ +Usage: vio_phase_comp.sh [-lib_map_path]\n\ +Usage: vio_phase_comp.sh [-reset_run]\n\ +Usage: vio_phase_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt new file mode 100644 index 00000000..0c519bc5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:22:06 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_phase_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_phase_comp.sh' script. + +./vio_phase_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_phase_comp.sh -noclean_files + +For more information on the script, please type './vio_phase_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/compile.do new file mode 100644 index 00000000..d966d500 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \ +"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/file_info.txt new file mode 100644 index 00000000..65344b7e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/simulate.do new file mode 100644 index 00000000..f374ee9b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_phase_comp -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_phase_comp xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_phase_comp.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh new file mode 100755 index 00000000..70994cb3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_phase_comp.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:22:06 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_phase_comp.sh [-help] +# usage: vio_phase_comp.sh [-lib_map_path] +# usage: vio_phase_comp.sh [-noclean_files] +# usage: vio_phase_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_phase_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_phase_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_phase_comp.sh [-help]\n\ +Usage: vio_phase_comp.sh [-lib_map_path]\n\ +Usage: vio_phase_comp.sh [-reset_run]\n\ +Usage: vio_phase_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt new file mode 100644 index 00000000..0c519bc5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:22:06 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_phase_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_phase_comp.sh' script. + +./vio_phase_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_phase_comp.sh -noclean_files + +For more information on the script, please type './vio_phase_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/file_info.txt new file mode 100644 index 00000000..90cc7c08 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/file_info.txt @@ -0,0 +1,2 @@ +vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh new file mode 100755 index 00000000..b31af7e6 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_phase_comp.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:22:06 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_phase_comp.sh [-help] +# usage: vio_phase_comp.sh [-lib_map_path] +# usage: vio_phase_comp.sh [-noclean_files] +# usage: vio_phase_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_phase_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "vio_phase_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl" \ + "$ref_dir/../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.vio_phase_comp xil_defaultlib.glbl -o vio_phase_comp_simv +} + +# RUN_STEP: +simulate() +{ + ./vio_phase_comp_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key vio_phase_comp_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_phase_comp_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_phase_comp.sh [-help]\n\ +Usage: vio_phase_comp.sh [-lib_map_path]\n\ +Usage: vio_phase_comp.sh [-reset_run]\n\ +Usage: vio_phase_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt new file mode 100644 index 00000000..4a25ed7e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:22:06 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_phase_comp.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_phase_comp.sh' script. + +./vio_phase_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_phase_comp.sh -noclean_files + +For more information on the script, please type './vio_phase_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/file_info.txt new file mode 100644 index 00000000..65344b7e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/run.f new file mode 100644 index 00000000..b90994fd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh new file mode 100755 index 00000000..77f145fe --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_phase_comp.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:22:06 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_phase_comp.sh [-help] +# usage: vio_phase_comp.sh [-lib_map_path] +# usage: vio_phase_comp.sh [-noclean_files] +# usage: vio_phase_comp.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_phase_comp.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "vio_phase_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_phase_comp \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_phase_comp/hdl/verilog" \ + +incdir+"../../../ip/vio_phase_comp/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_phase_comp.sh [-help]\n\ +Usage: vio_phase_comp.sh [-lib_map_path]\n\ +Usage: vio_phase_comp.sh [-reset_run]\n\ +Usage: vio_phase_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt new file mode 100644 index 00000000..0c519bc5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue May 16 20:22:06 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_phase_comp.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_phase_comp.sh' script. + +./vio_phase_comp.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_phase_comp.sh -noclean_files + +For more information on the script, please type './vio_phase_comp.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/file_info.txt new file mode 100644 index 00000000..90cc7c08 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh new file mode 100755 index 00000000..adeb9fdb --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_phase_comp.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue May 16 20:22:06 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_phase_comp.sh [-help] +# usage: vio_phase_comp.sh [-lib_map_path] +# usage: vio_phase_comp.sh [-noclean_files] +# usage: vio_phase_comp.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "vio_phase_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_phase_comp xil_defaultlib.vio_phase_comp xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim vio_phase_comp -key {Behavioral:sim_1:Functional:vio_phase_comp} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_phase_comp.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_phase_comp.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_phase_comp.sh [-help]\n\ +Usage: vio_phase_comp.sh [-lib_map_path]\n\ +Usage: vio_phase_comp.sh [-reset_run]\n\ +Usage: vio_phase_comp.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vlog.prj new file mode 100644 index 00000000..67b92e02 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_phase_comp/hdl/verilog" --include "../../../ip/vio_phase_comp/hdl" \ +"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/01859ea3ec989a3b.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/01859ea3ec989a3b.xci new file mode 100644 index 00000000..3db0c801 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/01859ea3ec989a3b.xci @@ -0,0 +1,3147 @@ + + + xilinx.com + ipcache + 01859ea3ec989a3b + 0 + + + ila_rx_data_cnt + + + 100000000 + TRUE + 2 + true + 10 + 10 + 200 + 5 + 65536 + FALSE + 3 + FALSE + FALSE + 1 + 0 + 2000000 + 0 + Native + 1 + 12 + 2 + 0 + 12 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 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a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_sim_netlist.v new file mode 100755 index 00000000..fedcc268 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cfb4ebb4bf66b07fbbf27e7e616dbf74daab4ba92c232aa37d9628032c22f8e2 +size 11178736 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_sim_netlist.vhdl new file mode 100755 index 00000000..8d458b42 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:467b6129770966febd219ae6272184fb8f030ed77d89fbfa6071e81d9417c2bc +size 14225548 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_stub.v new file mode 100755 index 00000000..3d4dfdcb --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_stub.v @@ -0,0 +1,33 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Tue May 16 20:23:15 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_stub.v +// Design : ila_rx_data_cnt +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9, probe10, probe11) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0],probe10[15:0],probe11[15:0]" */; + input clk; + input [11:0]probe0; + input [11:0]probe1; + input [11:0]probe2; + input [11:0]probe3; + input [11:0]probe4; + input [11:0]probe5; + input [11:0]probe6; + input [11:0]probe7; + input [11:0]probe8; + input [12:0]probe9; + input [15:0]probe10; + input [15:0]probe11; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_stub.vhdl new file mode 100755 index 00000000..9ced98be --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/01859ea3ec989a3b/ila_rx_data_cnt_stub.vhdl @@ -0,0 +1,42 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Tue May 16 20:23:15 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_stub.vhdl +-- Design : ila_rx_data_cnt +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0],probe10[15:0],probe11[15:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/stats.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/stats.txt new file mode 100644 index 00000000..aab82a9b --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/803b8df098fcb9e4/stats.txt @@ -0,0 +1,2 @@ +NumberHits:1 +Timestamp: Tue May 16 12:24:34 UTC 2023 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/dbab88f54d36bef1.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/dbab88f54d36bef1.xci new file mode 100644 index 00000000..b5b73e1e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/dbab88f54d36bef1.xci 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a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp.dcp new file mode 100644 index 00000000..5ec74fba --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ff50080316e138e3fa2faf0fe278dcf62faa194ee7befc5334fbf657fc0a756a +size 161543 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_sim_netlist.v new file mode 100755 index 00000000..4c9b41c5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:edddff249f7b1b05665fa6497d40214860a3fce2debe7c90155504b8c695aa82 +size 380636 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_sim_netlist.vhdl new file mode 100755 index 00000000..5be98dd3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:55c41508fc4f38fa6a37150aaee2b0ca9a92af229530b5e6c275a5796b16a420 +size 711442 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_stub.v new file mode 100755 index 00000000..84624fdc --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Tue May 16 20:22:23 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v +// Design : vio_phase_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[11:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[4:0]" */; + input clk; + input [0:0]probe_in0; + output [11:0]probe_out0; + output [11:0]probe_out1; + output [11:0]probe_out2; + output [11:0]probe_out3; + output [11:0]probe_out4; + output [11:0]probe_out5; + output [11:0]probe_out6; + output [11:0]probe_out7; + output [4:0]probe_out8; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_stub.vhdl new file mode 100755 index 00000000..b7b82bbe --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/dbab88f54d36bef1/vio_phase_comp_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Tue May 16 20:22:23 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl +-- Design : vio_phase_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[11:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[4:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index 48cc66e2..3423e038 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,16 +1,18 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3134:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3332:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3136:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3335:00:00 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a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -1,15 +1,15 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:36:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f7079697068616e646c6572:32:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:32:00:00 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4e6ebcf8..94ba00c0 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:10 +6d6f64655f636f756e7465727c4755494d6f6465:12 eof: diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf index c7d3c06f..73b12f76 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a343373:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323434302e3030304d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313032312e3630354d42:00:00 -eof:62189081 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a353773:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323436312e3832304d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313034332e3432364d42:00:00 +eof:443330095 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index a0f21200..7f6690af 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,33 +17,35 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - - + + - - + + - - - + + + + + @@ -51,36 +53,36 @@ This means code written to parse this file will need to be revisited each subseq - - - + + + - + - + - + - - - - - + + + + + - + - +
diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_20.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_20.xml new file mode 100644 index 00000000..dda7de74 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_21.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_21.xml new file mode 100644 index 00000000..7f15b224 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/gen_run.xml index 15653a90..d9a982d4 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/gen_run.xml @@ -1,9 +1,9 @@ + - diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc deleted file mode 100644 index e1729df2..00000000 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc +++ /dev/null @@ -1,24 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci -# IP: The module: 'fir_prbs7_invert_rep2' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/constraints/fir_compiler_v7_2.xdc -# XDC: The top module name and the constraint reference have the same name: 'fir_prbs7_invert_rep2'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'fir_prbs7_invert_rep2'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci -# IP: The module: 'fir_prbs7_invert_rep2' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/constraints/fir_compiler_v7_2.xdc -# XDC: The top module name and the constraint reference have the same name: 'fir_prbs7_invert_rep2'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'fir_prbs7_invert_rep2'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp deleted file mode 100644 index 49759195..00000000 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:9a726f8146fa94c962f939f929f726098df42cf331d3c8797ae07fba83eccc5e -size 1390882 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.vds deleted file mode 100644 index 993ad85a..00000000 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.vds +++ /dev/null @@ -1,746 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Mon May 8 19:42:47 2023 -# Process ID: 2699758 -# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1 -# Command line: vivado -log fir_prbs7_invert_rep2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs7_invert_rep2.tcl -# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.vds -# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/vivado.jou -#----------------------------------------------------------- -source fir_prbs7_invert_rep2.tcl -notrace -Command: synth_design -top fir_prbs7_invert_rep2 -part xc7z100ffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' -INFO: [Device 21-403] Loading part xc7z100ffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 2699833 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1855.598 ; gain = 152.719 ; free physical = 780 ; free virtual = 47398 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'fir_prbs7_invert_rep2' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/synth/fir_prbs7_invert_rep2.vhd:71] - Parameter C_XDEVICEFAMILY bound to: zynq - type: string - Parameter C_ELABORATION_DIR bound to: ./ - type: string - Parameter C_COMPONENT_NAME bound to: fir_prbs7_invert_rep2 - type: string - Parameter C_COEF_FILE bound to: fir_prbs7_invert_rep2.mif - type: string - Parameter C_COEF_FILE_LINES bound to: 256 - type: integer - Parameter C_FILTER_TYPE bound to: 0 - type: integer - Parameter C_INTERP_RATE bound to: 1 - type: integer - Parameter C_DECIM_RATE bound to: 1 - type: integer - Parameter C_ZERO_PACKING_FACTOR bound to: 1 - type: integer - Parameter C_SYMMETRY bound to: 0 - type: integer - Parameter C_NUM_FILTS bound to: 1 - type: integer - Parameter C_NUM_TAPS bound to: 256 - type: integer - Parameter C_NUM_CHANNELS bound to: 1 - type: integer - Parameter C_CHANNEL_PATTERN bound to: fixed - type: string - Parameter C_ROUND_MODE bound to: 0 - type: integer - Parameter C_COEF_RELOAD bound to: 0 - type: integer - Parameter C_NUM_RELOAD_SLOTS bound to: 1 - type: integer - Parameter C_COL_MODE bound to: 1 - type: integer - Parameter C_COL_PIPE_LEN bound to: 4 - type: integer - Parameter C_COL_CONFIG bound to: 64 - type: string - Parameter C_OPTIMIZATION bound to: 0 - type: integer - Parameter C_DATA_PATH_WIDTHS bound to: 12 - type: string - Parameter C_DATA_IP_PATH_WIDTHS bound to: 12 - type: string - Parameter C_DATA_PX_PATH_WIDTHS bound to: 12 - type: string - Parameter C_DATA_WIDTH bound to: 12 - type: integer - Parameter C_COEF_PATH_WIDTHS bound to: 8 - type: string - Parameter C_COEF_WIDTH bound to: 8 - type: integer - Parameter C_DATA_PATH_SRC bound to: 0 - type: string - Parameter C_COEF_PATH_SRC bound to: 0 - type: string - Parameter C_PX_PATH_SRC bound to: 0 - type: string - Parameter C_DATA_PATH_SIGN bound to: 0 - type: string - Parameter C_COEF_PATH_SIGN bound to: 0 - type: string - Parameter C_ACCUM_PATH_WIDTHS bound to: 20 - type: string - Parameter C_OUTPUT_WIDTH bound to: 20 - type: integer - Parameter C_OUTPUT_PATH_WIDTHS bound to: 20 - type: string - Parameter C_ACCUM_OP_PATH_WIDTHS bound to: 20 - type: string - Parameter C_EXT_MULT_CNFG bound to: none - type: string - Parameter C_DATA_PATH_PSAMP_SRC bound to: 0 - type: string - Parameter C_OP_PATH_PSAMP_SRC bound to: 0 - type: string - Parameter C_NUM_MADDS bound to: 64 - type: integer - Parameter C_OPT_MADDS bound to: none - type: string - Parameter C_OVERSAMPLING_RATE bound to: 4 - type: integer - Parameter C_INPUT_RATE bound to: 4 - type: integer - Parameter C_OUTPUT_RATE bound to: 4 - type: integer - Parameter C_DATA_MEMTYPE bound to: 0 - type: integer - Parameter C_COEF_MEMTYPE bound to: 2 - type: integer - Parameter C_IPBUFF_MEMTYPE bound to: 0 - type: integer - Parameter C_OPBUFF_MEMTYPE bound to: 0 - type: integer - Parameter C_DATAPATH_MEMTYPE bound to: 0 - type: integer - Parameter C_MEM_ARRANGEMENT bound to: 0 - type: integer - Parameter C_DATA_MEM_PACKING bound to: 0 - type: integer - Parameter C_COEF_MEM_PACKING bound to: 0 - type: integer - Parameter C_FILTS_PACKED bound to: 0 - type: integer - Parameter C_LATENCY bound to: 75 - type: integer - Parameter C_HAS_ARESETn bound to: 1 - type: integer - Parameter C_HAS_ACLKEN bound to: 0 - type: integer - Parameter C_DATA_HAS_TLAST bound to: 0 - type: integer - Parameter C_S_DATA_HAS_FIFO bound to: 0 - type: integer - Parameter C_S_DATA_HAS_TUSER bound to: 0 - type: integer - Parameter C_S_DATA_TDATA_WIDTH bound to: 16 - type: integer - Parameter C_S_DATA_TUSER_WIDTH bound to: 1 - type: integer - Parameter C_M_DATA_HAS_TREADY bound to: 0 - type: integer - Parameter C_M_DATA_HAS_TUSER bound to: 0 - type: integer - Parameter C_M_DATA_TDATA_WIDTH bound to: 24 - type: integer - Parameter C_M_DATA_TUSER_WIDTH bound to: 1 - type: integer - Parameter C_HAS_CONFIG_CHANNEL bound to: 0 - type: integer - Parameter C_CONFIG_SYNC_MODE bound to: 0 - type: integer - Parameter C_CONFIG_PACKET_SIZE bound to: 0 - type: integer - Parameter C_CONFIG_TDATA_WIDTH bound to: 1 - type: integer - Parameter C_RELOAD_TDATA_WIDTH bound to: 1 - type: integer -INFO: [Synth 8-3491] module 'fir_compiler_v7_2_12' declared at '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/hdl/fir_compiler_v7_2_vh_rfs.vhd:61264' bound to instance 'U0' of component 'fir_compiler_v7_2_12' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/synth/fir_prbs7_invert_rep2.vhd:201] -WARNING: [Synth 8-5858] RAM p_path_out_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers -INFO: [Synth 8-256] done synthesizing module 'fir_prbs7_invert_rep2' (12#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/synth/fir_prbs7_invert_rep2.vhd:71] -WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port WE -WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port CE -WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port CLK -WARNING: [Synth 8-3331] design cntrl_delay__parameterized0 has unconnected port CE -WARNING: [Synth 8-3331] design cntrl_delay__parameterized0 has unconnected port SCLR -WARNING: [Synth 8-3331] design cntrl_delay__parameterized0 has unconnected port CLK -WARNING: [Synth 8-3331] design delay__parameterized7 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design buff has unconnected port RE -WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port WE -WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port CE -WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port CLK -WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port WE -WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port CE -WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port CLK -WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port PRE_ADDSUB -WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port PRE_ADD_BYPASS -WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port CED -WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port WE -WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port CE -WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port CLK -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][57] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][56] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][55] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][54] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][53] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][52] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][51] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][50] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][49] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][48] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][62] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][61] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][60] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][59] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][58] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][57] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][56] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][55] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][54] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][53] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][52] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][51] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][50] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][49] -WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][48] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][57] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][56] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][55] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][54] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][53] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][52] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][51] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][50] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][49] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][48] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][47] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][46] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][45] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][44] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][43] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][42] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][41] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][40] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][39] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][38] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][37] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][36] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][35] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][34] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][33] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][32] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][31] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][30] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][29] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][28] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][27] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][26] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][25] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][24] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][23] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][22] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][21] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][20] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][19] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][18] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][17] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][16] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][15] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][14] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][13] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][12] -WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][11] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2009.316 ; gain = 306.438 ; free physical = 902 ; free virtual = 47301 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2009.316 ; gain = 306.438 ; free physical = 930 ; free virtual = 47329 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2009.316 ; gain = 306.438 ; free physical = 930 ; free virtual = 47329 ---------------------------------------------------------------------------------- -INFO: [Netlist 29-17] Analyzing 65 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_ooc.xdc] for cell 'U0' -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_ooc.xdc] for cell 'U0' -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/constraints/fir_compiler_v7_2.xdc] for cell 'U0' -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/constraints/fir_compiler_v7_2.xdc] for cell 'U0' -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2168.098 ; gain = 0.000 ; free physical = 797 ; free virtual = 47202 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2168.098 ; gain = 0.000 ; free physical = 793 ; free virtual = 47199 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 757 ; free virtual = 47106 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7z100ffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 757 ; free virtual = 47106 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 757 ; free virtual = 47106 ---------------------------------------------------------------------------------- -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 796 ; free virtual = 47144 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 2020 (col length:140) -BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Common 17-14] Message 'Synth 8-5542' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_cntrl_signals[4].i_delay/gen_dly.gen_regs.delay_bus_reg[0][0]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.i_cntrl_cntrl_mem_we/gen_reg.d_reg_reg[0]' -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.sclr_cntrl_algn_reg[0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[0].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[2].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[4].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[5].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[8].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[11].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[13].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[16].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[25].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[26].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[29].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[32].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[42].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[51].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[53].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[61].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_mem_array[62].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[3] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[8] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[9] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[2] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.chan_max_early_reg ) -INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[19]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[23]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[20]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[23]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[21]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[23]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[22]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[23]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tlast_int_reg ) -INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.base_max_cntrl_reg' (FDR) to 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.base_max_reg' ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 782 ; free virtual = 47132 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 688 ; free virtual = 46938 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 687 ; free virtual = 46925 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. -WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. -INFO: [Common 17-14] Message 'Synth 8-5591' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 705 ; free virtual = 46931 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 704 ; free virtual = 46927 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 704 ; free virtual = 46927 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 711 ; free virtual = 46936 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 711 ; free virtual = 46936 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 710 ; free virtual = 46935 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 710 ; free virtual = 46935 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+----------+------+ -| |Cell |Count | -+------+----------+------+ -|1 |DSP48E1 | 64| -|2 |DSP48E1_1 | 1| -|3 |LUT1 | 21| -|4 |LUT2 | 10| -|5 |LUT3 | 14| -|6 |LUT4 | 4| -|7 |LUT5 | 6| -|8 |LUT6 | 7| -|9 |SRL16E | 782| -|10 |SRLC32E | 9| -|11 |FDRE | 2796| -|12 |FDSE | 6| -+------+----------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 710 ; free virtual = 46935 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2256 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2168.098 ; gain = 306.438 ; free physical = 780 ; free virtual = 47005 -Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2168.098 ; gain = 465.219 ; free physical = 780 ; free virtual = 47005 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 65 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2168.098 ; gain = 0.000 ; free physical = 811 ; free virtual = 47036 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -218 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2168.098 ; gain = 772.121 ; free physical = 916 ; free virtual = 47141 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2168.098 ; gain = 0.000 ; free physical = 916 ; free virtual = 47141 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP fir_prbs7_invert_rep2, cache-ID = 803b8df098fcb9e4 -INFO: [Coretcl 2-1174] Renamed 462 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2192.109 ; gain = 0.000 ; free physical = 913 ; free virtual = 47152 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file fir_prbs7_invert_rep2_utilization_synth.rpt -pb fir_prbs7_invert_rep2_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Mon May 8 19:43:17 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v deleted file mode 100644 index d3f1af42..00000000 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:1443d4bafada7dc1e0c863ea91378c74e51dc722fffc7f31975ed98b8b2156e2 -size 3097268 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl deleted file mode 100644 index 4c1fdd72..00000000 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:95dd57d9721f3b42d8a90e06529d75215410975e1f142885dbff239c1e3814b9 -size 4406730 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl deleted file mode 100644 index 558f6ff5..00000000 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl +++ /dev/null @@ -1,36 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 19:43:16 2023 --- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl --- Design : fir_prbs7_invert_rep2 --- Purpose : Stub declaration of top-level module interface --- Device : xc7z100ffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity fir_prbs7_invert_rep2 is - Port ( - aresetn : in STD_LOGIC; - aclk : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ) - ); - -end fir_prbs7_invert_rep2; - -architecture stub of fir_prbs7_invert_rep2 is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; -begin -end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.pb deleted file mode 100644 index 230a6d70..00000000 Binary files a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.pb and /dev/null differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/vivado.pb deleted file mode 100644 index 4f304037..00000000 Binary files a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/vivado.pb and /dev/null differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml index b49500c2..7ef45142 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml @@ -1,9 +1,9 @@ + - diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.begin.rst index 2a5479a3..df76322f 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.begin.rst +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/gen_run.xml index be1417d1..cffcf935 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp index 76603bb2..902e3e03 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:977bfdf4f6a67e6132f8c7dd204955797d92313831d277c854ce4ab17950246f -size 3456077 +oid sha256:8f8451898e58ce9220bdb79106fb72c2ebf2ce124713a2611cc9248c725b52ec +size 4033214 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds index c4bed609..ed5e095f 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds @@ -2,8 +2,8 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Fri May 12 10:10:59 2023 -# Process ID: 1324838 +# Start of session at: Tue May 16 20:20:56 2023 +# Process ID: 834113 # Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1 # Command line: vivado -log ila_rx_data_cnt.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rx_data_cnt.tcl # Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds @@ -16,9 +16,9 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' INFO: [Device 21-403] Loading part xc7z100ffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 1324944 +INFO: Helper process launched with PID 834206 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1882.984 ; gain = 157.688 ; free physical = 448 ; free virtual = 47886 +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1883.016 ; gain = 157.719 ; free physical = 754 ; free virtual = 57223 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'ila_rx_data_cnt' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:84] INFO: [Synth 8-6157] synthesizing module 'CFGLUT5' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] @@ -33,8 +33,8 @@ INFO: [Synth 8-6157] synthesizing module 'SRLC16E' [/tools/Xilinx/Vivado/2019.1/ INFO: [Synth 8-6155] done synthesizing module 'SRLC16E' (27#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] INFO: [Synth 8-6157] synthesizing module 'FDRE' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] INFO: [Synth 8-6155] done synthesizing module 'FDRE' (32#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] -WARNING: [Synth 8-7023] instance 'inst' of module 'ila_v6_2_9_ila' has 1033 connections declared, but only 1027 given [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:3227] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity ila_rx_data_cnt does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:116] +WARNING: [Synth 8-7023] instance 'inst' of module 'ila_v6_2_9_ila' has 1033 connections declared, but only 1027 given [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:3231] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity ila_rx_data_cnt does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:120] INFO: [Synth 8-6155] done synthesizing module 'ila_rx_data_cnt' (52#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:84] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MUX_RST[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MEM_LAT_RST @@ -56,89 +56,89 @@ WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1951] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1950] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1949] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1948] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1947] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1946] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1945] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1944] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1943] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1942] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1941] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1940] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1939] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1938] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1937] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1936] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1935] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1934] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1933] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1932] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1931] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1930] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1929] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1928] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1927] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1926] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1925] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1924] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1923] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1922] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1921] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1920] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1919] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1918] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1917] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1916] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1915] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1914] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1913] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1912] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1911] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1910] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1909] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1908] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1907] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1906] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1905] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1904] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1903] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1902] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1901] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1900] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1899] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1898] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1897] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1896] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1895] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1894] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1893] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1892] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1891] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1890] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1889] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1888] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1887] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1886] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1885] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1884] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1883] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1882] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1881] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1880] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1879] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1878] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1877] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1876] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1875] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1874] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1873] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1872] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2463] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2462] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2461] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2460] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2459] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2458] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2457] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2456] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2455] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2454] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2453] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2452] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2451] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2450] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2449] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2448] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2447] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2446] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2445] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2444] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2443] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2442] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2441] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2440] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2439] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2438] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2437] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2436] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2435] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2434] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2433] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2432] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2431] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2430] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2429] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2428] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2427] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2426] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2425] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2424] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2423] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2422] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2421] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2420] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2419] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2418] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2417] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2416] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2415] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2414] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2413] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2412] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2411] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2410] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2409] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2408] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2407] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2406] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2405] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2404] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2403] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2402] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2401] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2400] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2399] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2398] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2397] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2396] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2395] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2394] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2393] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2392] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2391] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2390] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2389] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2388] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2387] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2386] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2385] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2384] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:01:18 ; elapsed = 00:01:28 . Memory (MB): peak = 2347.156 ; gain = 621.859 ; free physical = 707 ; free virtual = 47616 +Finished RTL Elaboration : Time (s): cpu = 00:01:30 ; elapsed = 00:01:40 . Memory (MB): peak = 2382.945 ; gain = 657.648 ; free physical = 1628 ; free virtual = 56734 --------------------------------------------------------------------------------- Report Check Netlist: @@ -151,12 +151,12 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:01:19 ; elapsed = 00:01:29 . Memory (MB): peak = 2347.156 ; gain = 621.859 ; free physical = 729 ; free virtual = 47646 +Finished Handling Custom Attributes : Time (s): cpu = 00:01:31 ; elapsed = 00:01:41 . Memory (MB): peak = 2382.945 ; gain = 657.648 ; free physical = 1697 ; free virtual = 56804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:19 ; elapsed = 00:01:29 . Memory (MB): peak = 2347.156 ; gain = 621.859 ; free physical = 729 ; free virtual = 47646 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:31 ; elapsed = 00:01:41 . Memory (MB): peak = 2382.945 ; gain = 657.648 ; free physical = 1697 ; free virtual = 56804 --------------------------------------------------------------------------------- -INFO: [Netlist 29-17] Analyzing 1055 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 1159 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization @@ -170,32 +170,32 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_ Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2440.000 ; gain = 0.000 ; free physical = 534 ; free virtual = 47475 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2461.820 ; gain = 0.000 ; free physical = 1432 ; free virtual = 56541 INFO: [Project 1-111] Unisim Transformation Summary: - A total of 636 instances were transformed. - CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 580 instances - CFGLUT5 => SRLC32E: 56 instances + A total of 672 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 612 instances + CFGLUT5 => SRLC32E: 60 instances -Constraint Validation Runtime : Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2440.000 ; gain = 0.000 ; free physical = 502 ; free virtual = 47444 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2461.820 ; gain = 0.000 ; free physical = 1469 ; free virtual = 56577 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:01:24 ; elapsed = 00:01:35 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 666 ; free virtual = 47624 +Finished Constraint Validation : Time (s): cpu = 00:01:37 ; elapsed = 00:01:47 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1551 ; free virtual = 56657 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z100ffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:01:24 ; elapsed = 00:01:35 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 666 ; free virtual = 47624 +Finished Loading Part and Timing Information : Time (s): cpu = 00:01:37 ; elapsed = 00:01:47 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1551 ; free virtual = 56657 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for inst. (constraint file /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:25 ; elapsed = 00:01:35 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 660 ; free virtual = 47618 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:37 ; elapsed = 00:01:47 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1550 ; free virtual = 56656 --------------------------------------------------------------------------------- -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized55' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized56' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized59' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized60' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' @@ -252,6 +252,10 @@ INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in modul INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized52' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized53' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized54' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized55' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized56' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized57' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized58' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- @@ -261,7 +265,7 @@ INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in modul P2S | 0100 | 0100 S2P | 1000 | 1000 --------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized55' +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized59' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- @@ -271,7 +275,7 @@ INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in m P2S | 0100 | 0100 S2P | 1000 | 1000 --------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized56' +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized60' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- @@ -832,8 +836,48 @@ INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in m S2P | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized54' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized55' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized56' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized57' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized58' --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:27 ; elapsed = 00:01:39 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 626 ; free virtual = 47596 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:40 ; elapsed = 00:01:51 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1633 ; free virtual = 56746 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -851,52 +895,50 @@ Detailed RTL Component Info : 2 Input 9 Bit Adders := 1 2 Input 7 Bit Adders := 4 2 Input 6 Bit Adders := 1 - 2 Input 4 Bit Adders := 58 - 2 Input 3 Bit Adders := 1 + 2 Input 4 Bit Adders := 63 +---XORs : - 2 Input 13 Bit XORs := 72 + 2 Input 13 Bit XORs := 76 2 Input 1 Bit XORs := 4 +---Registers : 1024 Bit Registers := 2 - 128 Bit Registers := 2 - 121 Bit Registers := 9 + 160 Bit Registers := 1 + 153 Bit Registers := 9 + 128 Bit Registers := 1 33 Bit Registers := 2 32 Bit Registers := 9 - 24 Bit Registers := 1 - 20 Bit Registers := 33 + 24 Bit Registers := 34 17 Bit Registers := 2 - 16 Bit Registers := 225 + 16 Bit Registers := 247 13 Bit Registers := 4 12 Bit Registers := 36 9 Bit Registers := 1 8 Bit Registers := 1 7 Bit Registers := 5 6 Bit Registers := 2 - 4 Bit Registers := 65 - 3 Bit Registers := 1 + 4 Bit Registers := 70 2 Bit Registers := 6 - 1 Bit Registers := 377 + 1 Bit Registers := 397 +---Muxes : - 2 Input 121 Bit Muxes := 1 + 2 Input 153 Bit Muxes := 1 2 Input 32 Bit Muxes := 12 - 2 Input 16 Bit Muxes := 72 + 2 Input 16 Bit Muxes := 76 4 Input 16 Bit Muxes := 2 3 Input 16 Bit Muxes := 1 8 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 58 + 2 Input 15 Bit Muxes := 62 3 Input 15 Bit Muxes := 1 3 Input 7 Bit Muxes := 1 8 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 4 2 Input 5 Bit Muxes := 2 - 2 Input 4 Bit Muxes := 176 - 5 Input 4 Bit Muxes := 58 - 2 Input 3 Bit Muxes := 58 - 8 Input 3 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 188 + 5 Input 4 Bit Muxes := 62 + 8 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 62 2 Input 2 Bit Muxes := 6 - 2 Input 1 Bit Muxes := 380 + 2 Input 1 Bit Muxes := 400 4 Input 1 Bit Muxes := 2 - 3 Input 1 Bit Muxes := 58 + 3 Input 1 Bit Muxes := 62 9 Input 1 Bit Muxes := 1 8 Input 1 Bit Muxes := 5 --------------------------------------------------------------------------------- @@ -940,7 +982,7 @@ Detailed RTL Component Info : 1 Bit Registers := 2 +---Muxes : 2 Input 16 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized55 +Module xsdbs_v1_0_2_reg_p2s__parameterized59 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 @@ -979,7 +1021,7 @@ Detailed RTL Component Info : 1 Bit Registers := 4 +---Muxes : 2 Input 16 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg__parameterized39 +Module xsdbs_v1_0_2_reg__parameterized45 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 @@ -987,42 +1029,10 @@ Module xsdbs_v1_0_2_reg_ctl__parameterized0 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized40 +Module xsdbs_v1_0_2_reg__parameterized46 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized54 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized55 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized56 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized57 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg__parameterized58 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__parameterized1 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized59 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__parameterized2 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 Module xsdbs_v1_0_2_reg__parameterized60 Detailed RTL Component Info : +---XORs : @@ -1043,11 +1053,43 @@ Module xsdbs_v1_0_2_reg__parameterized64 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 Module xsdbs_v1_0_2_reg__parameterized65 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized56 +Module xsdbs_v1_0_2_reg_ctl__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized66 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized67 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized68 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized69 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized70 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized71 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized60 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 @@ -2061,6 +2103,78 @@ Detailed RTL Component Info : 3 Input 1 Bit Muxes := 1 Module xsdbs_v1_0_2_reg_p2s__parameterized54 Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized55 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized56 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized57 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized58 +Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---XORs : @@ -2107,7 +2221,7 @@ Detailed RTL Component Info : Module ltlib_v1_0_0_allx_typeA Detailed RTL Component Info : +---Registers : - 20 Bit Registers := 1 + 24 Bit Registers := 1 Module ltlib_v1_0_0_match Detailed RTL Component Info : +---Registers : @@ -2126,6 +2240,14 @@ Detailed RTL Component Info : 13 Bit Registers := 2 Module ltlib_v1_0_0_match__parameterized1 Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized2 +Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module ila_v6_2_9_ila_trigger @@ -2208,31 +2330,30 @@ Module ltlib_v1_0_0_generic_memrd Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 1 - 2 Input 3 Bit Adders := 1 + 2 Input 4 Bit Adders := 1 +---Registers : - 128 Bit Registers := 1 + 160 Bit Registers := 1 16 Bit Registers := 1 7 Bit Registers := 1 - 4 Bit Registers := 2 - 3 Bit Registers := 1 + 4 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 8 Input 16 Bit Muxes := 1 3 Input 7 Bit Muxes := 1 8 Input 7 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 - 8 Input 3 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 8 Input 1 Bit Muxes := 5 Module ila_v6_2_9_ila_core Detailed RTL Component Info : +---Registers : - 121 Bit Registers := 9 + 153 Bit Registers := 9 16 Bit Registers := 2 2 Bit Registers := 3 1 Bit Registers := 5 +---Muxes : - 2 Input 121 Bit Muxes := 1 + 2 Input 153 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module ila_v6_2_9_ila Detailed RTL Component Info : @@ -2290,16 +2411,19 @@ INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[0] ) INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[10].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' @@ -2320,16 +2444,19 @@ INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[1] ) INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[10].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' @@ -2351,16 +2478,19 @@ INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[10].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' @@ -2373,7 +2503,7 @@ INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_ INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' @@ -2381,21 +2511,12 @@ INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[3] ) INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[6] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[7] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[10] ) @@ -2406,7 +2527,6 @@ INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[7] ) @@ -2419,7 +2539,7 @@ INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[15] ) --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:34 ; elapsed = 00:01:47 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 498 ; free virtual = 47591 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:48 ; elapsed = 00:02:00 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1386 ; free virtual = 56530 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting @@ -2446,13 +2566,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:38 ; elapsed = 00:01:50 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 466 ; free virtual = 47484 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:52 ; elapsed = 00:02:04 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1260 ; free virtual = 56412 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:01:39 ; elapsed = 00:01:51 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 449 ; free virtual = 47472 +Finished Timing Optimization : Time (s): cpu = 00:01:52 ; elapsed = 00:02:05 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1231 ; free virtual = 56402 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting @@ -2478,7 +2598,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:01:40 ; elapsed = 00:01:52 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 477 ; free virtual = 47486 +Finished Technology Mapping : Time (s): cpu = 00:01:54 ; elapsed = 00:02:06 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1185 ; free virtual = 56403 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -2498,9 +2618,15 @@ Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- -INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [9] is driving 218 big block pins (URAM, BRAM and DSP loads). Created 22 replicas of its driver. -INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [10] is driving 218 big block pins (URAM, BRAM and DSP loads). Created 22 replicas of its driver. -INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_en is driving 228 big block pins (URAM, BRAM and DSP loads). Created 23 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [1] is driving 274 big block pins (URAM, BRAM and DSP loads). Created 28 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [2] is driving 274 big block pins (URAM, BRAM and DSP loads). Created 28 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [4] is driving 274 big block pins (URAM, BRAM and DSP loads). Created 28 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [5] is driving 274 big block pins (URAM, BRAM and DSP loads). Created 28 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [6] is driving 274 big block pins (URAM, BRAM and DSP loads). Created 28 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [8] is driving 274 big block pins (URAM, BRAM and DSP loads). Created 28 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [9] is driving 274 big block pins (URAM, BRAM and DSP loads). Created 28 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [10] is driving 274 big block pins (URAM, BRAM and DSP loads). Created 28 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_en is driving 276 big block pins (URAM, BRAM and DSP loads). Created 28 replicas of its driver. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- @@ -2545,7 +2671,7 @@ INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 INFO: [Synth 8-3295] tying undriven pin inst:trig_in to constant 0 INFO: [Synth 8-3295] tying undriven pin inst:trig_out_ack to constant 0 --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:01:41 ; elapsed = 00:01:53 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 474 ; free virtual = 47483 +Finished IO Insertion : Time (s): cpu = 00:01:54 ; elapsed = 00:02:07 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1543 ; free virtual = 56762 --------------------------------------------------------------------------------- Report Check Netlist: @@ -2558,7 +2684,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:01:41 ; elapsed = 00:01:53 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 474 ; free virtual = 47483 +Finished Renaming Generated Instances : Time (s): cpu = 00:01:54 ; elapsed = 00:02:07 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1543 ; free virtual = 56762 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -2570,25 +2696,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:41 ; elapsed = 00:01:53 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 471 ; free virtual = 47484 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:55 ; elapsed = 00:02:08 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1550 ; free virtual = 56771 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:01:41 ; elapsed = 00:01:54 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 471 ; free virtual = 47484 +Finished Renaming Generated Ports : Time (s): cpu = 00:01:55 ; elapsed = 00:02:08 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1550 ; free virtual = 56774 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:01:41 ; elapsed = 00:01:54 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 469 ; free virtual = 47484 +Finished Handling Custom Attributes : Time (s): cpu = 00:01:55 ; elapsed = 00:02:08 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1565 ; free virtual = 56775 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:01:41 ; elapsed = 00:01:54 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 468 ; free virtual = 47484 +Finished Renaming Generated Nets : Time (s): cpu = 00:01:55 ; elapsed = 00:02:08 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1565 ; free virtual = 56775 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting @@ -2600,9 +2726,9 @@ Static Shift Register Report: +---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |ila_v6_2_9_generic_counter | counter_load_i_reg[16] | 16 | 4 | NO | NO | YES | 4 | 0 | |ila_v6_2_9_ila | ila_core_inst/u_ila_regs/adv_rb_drdy4_reg | 3 | 1 | NO | NO | YES | 1 | 0 | -|ila_v6_2_9_ila | ila_core_inst/shifted_data_in_reg[8][120] | 9 | 121 | NO | NO | YES | 121 | 0 | |ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | |ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/shifted_data_in_reg[8][152] | 9 | 153 | NO | NO | YES | 153 | 0 | +---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- @@ -2622,24 +2748,24 @@ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ -|1 |CARRY4 | 229| -|2 |CFGLUT5 | 636| -|3 |LUT1 | 90| -|4 |LUT2 | 130| -|5 |LUT3 | 420| -|6 |LUT4 | 569| +|1 |CARRY4 | 241| +|2 |CFGLUT5 | 672| +|3 |LUT1 | 93| +|4 |LUT2 | 172| +|5 |LUT3 | 262| +|6 |LUT4 | 596| |7 |LUT5 | 267| -|8 |LUT6 | 2079| -|9 |MUXF7 | 369| -|10 |MUXF8 | 119| +|8 |LUT6 | 2662| +|9 |MUXF7 | 449| +|10 |MUXF8 | 155| |11 |RAM64M | 32| -|12 |RAMB36E1 | 208| -|13 |RAMB36E1_1 | 5| -|14 |RAMB36E1_2 | 5| -|15 |SRL16E | 129| +|12 |RAMB36E1 | 272| +|13 |RAMB36E1_1 | 1| +|14 |RAMB36E1_2 | 1| +|15 |SRL16E | 161| |16 |SRLC16E | 2| |17 |SRLC32E | 17| -|18 |FDRE | 4627| +|18 |FDRE | 5078| |19 |FDSE | 9| +------+-----------+------+ @@ -2647,9 +2773,9 @@ Report Instance Areas: +------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ | |Instance |Module |Cells | +------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ -|1 |top | | 9942| -|2 | inst |ila_v6_2_9_ila | 9942| -|3 | ila_core_inst |ila_v6_2_9_ila_core | 9935| +|1 |top | | 11142| +|2 | inst |ila_v6_2_9_ila | 11142| +|3 | ila_core_inst |ila_v6_2_9_ila_core | 11135| |4 | \ADV_TRIG.u_adv_trig |ila_v6_2_9_ila_adv_trigger_sequencer | 185| |5 | \ADV_TRIG_MEM_READ.u_fsm_memory_read_inst |ila_v6_2_9_ila_fsm_memory_read | 52| |6 | \COUNTER.u_count |ila_v6_2_9_ila_counter | 232| @@ -2657,13 +2783,13 @@ Report Instance Areas: |8 | \G_COUNTER[1].U_COUNTER |ila_v6_2_9_generic_counter__2 | 58| |9 | \G_COUNTER[2].U_COUNTER |ila_v6_2_9_generic_counter__3 | 58| |10 | \G_COUNTER[3].U_COUNTER |ila_v6_2_9_generic_counter | 58| -|11 | ila_trace_memory_inst |ila_v6_2_9_ila_trace_memory | 1067| -|12 | \SUBCORE_RAM_BLK_MEM_1.trace_block_memory |blk_mem_gen_v8_4_3 | 1067| -|13 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 1067| -|14 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_v8_4_3_blk_mem_gen_top | 1067| -|15 | \valid.cstr |blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr | 1067| -|16 | \bindec_a.bindec_inst_a |blk_mem_gen_v8_4_3_bindec | 15| -|17 | \has_mux_b.B |blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 | 834| +|11 | ila_trace_memory_inst |ila_v6_2_9_ila_trace_memory | 1374| +|12 | \SUBCORE_RAM_BLK_MEM_1.trace_block_memory |blk_mem_gen_v8_4_3 | 1374| +|13 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 1374| +|14 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_v8_4_3_blk_mem_gen_top | 1374| +|15 | \valid.cstr |blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr | 1374| +|16 | \bindec_a.bindec_inst_a |blk_mem_gen_v8_4_3_bindec | 13| +|17 | \has_mux_b.B |blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 | 1087| |18 | \ramloop[0].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width | 1| |19 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper | 1| |20 | \ramloop[100].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized99 | 1| @@ -2904,672 +3030,816 @@ Report Instance Areas: |255 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized205 | 1| |256 | \ramloop[207].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized206 | 1| |257 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized206 | 1| -|258 | \ramloop[208].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized207 | 2| -|259 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized207 | 2| -|260 | \ramloop[209].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized208 | 2| -|261 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized208 | 2| +|258 | \ramloop[208].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized207 | 1| +|259 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized207 | 1| +|260 | \ramloop[209].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized208 | 1| +|261 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized208 | 1| |262 | \ramloop[20].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized19 | 1| |263 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized19 | 1| -|264 | \ramloop[210].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized209 | 2| -|265 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized209 | 2| -|266 | \ramloop[211].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized210 | 2| -|267 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized210 | 2| -|268 | \ramloop[212].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized211 | 2| -|269 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized211 | 2| -|270 | \ramloop[21].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized20 | 1| -|271 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized20 | 1| -|272 | \ramloop[22].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized21 | 1| -|273 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized21 | 1| -|274 | \ramloop[23].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized22 | 1| -|275 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized22 | 1| -|276 | \ramloop[24].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized23 | 1| -|277 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized23 | 1| -|278 | \ramloop[25].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized24 | 1| -|279 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized24 | 1| -|280 | \ramloop[26].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized25 | 1| -|281 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized25 | 1| -|282 | \ramloop[27].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized26 | 1| -|283 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized26 | 1| -|284 | \ramloop[28].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized27 | 1| -|285 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized27 | 1| -|286 | \ramloop[29].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized28 | 1| -|287 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized28 | 1| -|288 | \ramloop[2].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized1 | 1| -|289 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 | 1| -|290 | \ramloop[30].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized29 | 1| -|291 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized29 | 1| -|292 | \ramloop[31].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized30 | 1| -|293 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized30 | 1| -|294 | \ramloop[32].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized31 | 1| -|295 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized31 | 1| -|296 | \ramloop[33].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized32 | 1| -|297 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized32 | 1| -|298 | \ramloop[34].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized33 | 1| -|299 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized33 | 1| -|300 | \ramloop[35].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized34 | 1| -|301 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized34 | 1| -|302 | \ramloop[36].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized35 | 1| -|303 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized35 | 1| -|304 | \ramloop[37].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized36 | 1| -|305 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized36 | 1| -|306 | \ramloop[38].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized37 | 1| -|307 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized37 | 1| -|308 | \ramloop[39].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized38 | 1| -|309 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized38 | 1| -|310 | \ramloop[3].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized2 | 1| -|311 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 | 1| -|312 | \ramloop[40].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized39 | 1| -|313 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized39 | 1| -|314 | \ramloop[41].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized40 | 1| -|315 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized40 | 1| -|316 | \ramloop[42].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized41 | 1| -|317 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized41 | 1| -|318 | \ramloop[43].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized42 | 1| -|319 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized42 | 1| -|320 | \ramloop[44].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized43 | 1| -|321 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized43 | 1| -|322 | \ramloop[45].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized44 | 1| -|323 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized44 | 1| -|324 | \ramloop[46].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized45 | 1| -|325 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized45 | 1| -|326 | \ramloop[47].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized46 | 1| -|327 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized46 | 1| -|328 | \ramloop[48].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized47 | 1| -|329 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized47 | 1| -|330 | \ramloop[49].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized48 | 1| -|331 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized48 | 1| -|332 | \ramloop[4].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized3 | 1| -|333 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized3 | 1| -|334 | \ramloop[50].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized49 | 1| -|335 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized49 | 1| -|336 | \ramloop[51].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized50 | 1| -|337 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized50 | 1| -|338 | \ramloop[52].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized51 | 1| -|339 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized51 | 1| -|340 | \ramloop[53].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized52 | 1| -|341 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized52 | 1| -|342 | \ramloop[54].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized53 | 1| -|343 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized53 | 1| -|344 | \ramloop[55].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized54 | 1| -|345 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized54 | 1| -|346 | \ramloop[56].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized55 | 1| -|347 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized55 | 1| -|348 | \ramloop[57].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized56 | 1| -|349 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized56 | 1| -|350 | \ramloop[58].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized57 | 1| -|351 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized57 | 1| -|352 | \ramloop[59].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized58 | 1| -|353 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized58 | 1| -|354 | \ramloop[5].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized4 | 1| -|355 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized4 | 1| -|356 | \ramloop[60].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized59 | 1| -|357 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized59 | 1| -|358 | \ramloop[61].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized60 | 1| -|359 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized60 | 1| -|360 | \ramloop[62].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized61 | 1| -|361 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized61 | 1| -|362 | \ramloop[63].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized62 | 1| -|363 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized62 | 1| -|364 | \ramloop[64].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized63 | 1| -|365 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized63 | 1| -|366 | \ramloop[65].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized64 | 1| -|367 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized64 | 1| -|368 | \ramloop[66].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized65 | 1| -|369 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized65 | 1| -|370 | \ramloop[67].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized66 | 1| -|371 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized66 | 1| -|372 | \ramloop[68].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized67 | 1| -|373 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized67 | 1| -|374 | \ramloop[69].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized68 | 1| -|375 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized68 | 1| -|376 | \ramloop[6].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized5 | 1| -|377 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized5 | 1| -|378 | \ramloop[70].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized69 | 1| -|379 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized69 | 1| -|380 | \ramloop[71].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized70 | 1| -|381 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized70 | 1| -|382 | \ramloop[72].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized71 | 1| -|383 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized71 | 1| -|384 | \ramloop[73].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized72 | 1| -|385 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized72 | 1| -|386 | \ramloop[74].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized73 | 1| -|387 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized73 | 1| -|388 | \ramloop[75].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized74 | 1| -|389 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized74 | 1| -|390 | \ramloop[76].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized75 | 1| -|391 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized75 | 1| -|392 | \ramloop[77].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized76 | 1| -|393 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized76 | 1| -|394 | \ramloop[78].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized77 | 1| -|395 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized77 | 1| -|396 | \ramloop[79].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized78 | 1| -|397 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized78 | 1| -|398 | \ramloop[7].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized6 | 1| -|399 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized6 | 1| -|400 | \ramloop[80].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized79 | 1| -|401 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized79 | 1| -|402 | \ramloop[81].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized80 | 1| -|403 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized80 | 1| -|404 | \ramloop[82].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized81 | 1| -|405 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized81 | 1| -|406 | \ramloop[83].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized82 | 1| -|407 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized82 | 1| -|408 | \ramloop[84].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized83 | 1| -|409 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized83 | 1| -|410 | \ramloop[85].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized84 | 1| -|411 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized84 | 1| -|412 | \ramloop[86].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized85 | 1| -|413 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized85 | 1| -|414 | \ramloop[87].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized86 | 1| -|415 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized86 | 1| -|416 | \ramloop[88].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized87 | 1| -|417 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized87 | 1| -|418 | \ramloop[89].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized88 | 1| -|419 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized88 | 1| -|420 | \ramloop[8].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized7 | 1| -|421 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized7 | 1| -|422 | \ramloop[90].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized89 | 1| -|423 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized89 | 1| -|424 | \ramloop[91].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized90 | 1| -|425 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized90 | 1| -|426 | \ramloop[92].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized91 | 1| -|427 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized91 | 1| -|428 | \ramloop[93].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized92 | 1| -|429 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized92 | 1| -|430 | \ramloop[94].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized93 | 1| -|431 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized93 | 1| -|432 | \ramloop[95].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized94 | 1| -|433 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized94 | 1| -|434 | \ramloop[96].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized95 | 1| -|435 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized95 | 1| -|436 | \ramloop[97].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized96 | 1| -|437 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized96 | 1| -|438 | \ramloop[98].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized97 | 1| -|439 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized97 | 1| -|440 | \ramloop[99].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized98 | 1| -|441 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized98 | 1| -|442 | \ramloop[9].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized8 | 1| -|443 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized8 | 1| -|444 | u_ila_cap_ctrl |ila_v6_2_9_ila_cap_ctrl_legacy | 318| -|445 | U_CDONE |ltlib_v1_0_0_cfglut6__parameterized0 | 5| -|446 | U_NS0 |ltlib_v1_0_0_cfglut7 | 8| -|447 | U_NS1 |ltlib_v1_0_0_cfglut7_312 | 10| -|448 | u_cap_addrgen |ila_v6_2_9_ila_cap_addrgen | 290| -|449 | U_CMPRESET |ltlib_v1_0_0_cfglut6 | 3| -|450 | u_cap_sample_counter |ila_v6_2_9_ila_cap_sample_counter | 71| -|451 | U_SCE |ltlib_v1_0_0_cfglut4_319 | 1| -|452 | U_SCMPCE |ltlib_v1_0_0_cfglut5_320 | 1| -|453 | U_SCRST |ltlib_v1_0_0_cfglut6_321 | 3| -|454 | u_scnt_cmp |ltlib_v1_0_0_match_nodelay_322 | 28| -|455 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_323 | 28| -|456 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_324 | 12| -|457 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_325 | 5| -|458 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_326 | 5| -|459 | u_cap_window_counter |ila_v6_2_9_ila_cap_window_counter | 66| -|460 | U_WCE |ltlib_v1_0_0_cfglut4 | 1| -|461 | U_WHCMPCE |ltlib_v1_0_0_cfglut5 | 1| -|462 | U_WLCMPCE |ltlib_v1_0_0_cfglut5_313 | 1| -|463 | u_wcnt_hcmp |ltlib_v1_0_0_match_nodelay | 12| -|464 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_315 | 12| -|465 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_316 | 12| -|466 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_317 | 5| -|467 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_318 | 5| -|468 | u_wcnt_lcmp |ltlib_v1_0_0_match_nodelay_314 | 28| -|469 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay | 28| -|470 | DUT |ltlib_v1_0_0_all_typeA__parameterized1 | 12| -|471 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1 | 5| -|472 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2 | 5| -|473 | u_ila_regs |ila_v6_2_9_ila_register | 5891| -|474 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 302| -|475 | reg_890 |xsdbs_v1_0_2_reg__parameterized72 | 16| -|476 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_311 | 16| -|477 | \ADV_TRIG_STREAM.reg_stream_ffc |xsdbs_v1_0_2_reg_stream__parameterized0 | 25| -|478 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_310 | 22| -|479 | \ADV_TRIG_STREAM_READBACK.reg_stream_ffb |xsdbs_v1_0_2_reg_stream | 27| -|480 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_309 | 27| -|481 | \CNT.CNT_SRL[0].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized51 | 75| -|482 | \CNT.CNT_SRL[1].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized52 | 74| -|483 | \CNT.CNT_SRL[2].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized53 | 88| -|484 | \CNT.CNT_SRL[3].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized54 | 86| -|485 | \MU_SRL[0].mu_srl_reg |xsdbs_v1_0_2_reg_p2s | 74| -|486 | \MU_SRL[10].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized9 | 74| -|487 | \MU_SRL[11].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized10 | 106| -|488 | \MU_SRL[12].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized11 | 74| -|489 | \MU_SRL[13].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized12 | 74| -|490 | \MU_SRL[14].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized13 | 74| -|491 | \MU_SRL[15].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized14 | 90| -|492 | \MU_SRL[16].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized15 | 74| -|493 | \MU_SRL[17].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized16 | 74| -|494 | \MU_SRL[18].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized17 | 74| -|495 | \MU_SRL[19].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized18 | 106| -|496 | \MU_SRL[1].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized0 | 74| -|497 | \MU_SRL[2].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized1 | 74| -|498 | \MU_SRL[3].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized2 | 106| -|499 | \MU_SRL[4].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized3 | 74| -|500 | \MU_SRL[5].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized4 | 74| -|501 | \MU_SRL[6].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized5 | 74| -|502 | \MU_SRL[7].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized6 | 90| -|503 | \MU_SRL[8].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized7 | 74| -|504 | \MU_SRL[9].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized8 | 74| -|505 | \STRG_QUAL.qual_strg_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized55 | 81| -|506 | \TC_SRL[0].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized19 | 74| -|507 | \TC_SRL[10].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized29 | 74| -|508 | \TC_SRL[11].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized30 | 106| -|509 | \TC_SRL[12].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized31 | 74| -|510 | \TC_SRL[13].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized32 | 74| -|511 | \TC_SRL[14].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized33 | 74| -|512 | \TC_SRL[15].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized34 | 90| -|513 | \TC_SRL[16].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized35 | 74| -|514 | \TC_SRL[17].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized36 | 74| -|515 | \TC_SRL[18].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized37 | 74| -|516 | \TC_SRL[19].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized38 | 106| -|517 | \TC_SRL[1].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized20 | 74| -|518 | \TC_SRL[20].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized39 | 74| -|519 | \TC_SRL[21].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized40 | 74| -|520 | \TC_SRL[22].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized41 | 74| -|521 | \TC_SRL[23].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized42 | 90| -|522 | \TC_SRL[24].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized43 | 74| -|523 | \TC_SRL[25].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized44 | 74| -|524 | \TC_SRL[26].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized45 | 74| -|525 | \TC_SRL[27].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized46 | 122| -|526 | \TC_SRL[28].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized47 | 74| -|527 | \TC_SRL[29].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized48 | 74| -|528 | \TC_SRL[2].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized21 | 74| -|529 | \TC_SRL[30].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized49 | 74| -|530 | \TC_SRL[31].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized50 | 90| -|531 | \TC_SRL[3].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized22 | 106| -|532 | \TC_SRL[4].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized23 | 74| -|533 | \TC_SRL[5].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized24 | 74| -|534 | \TC_SRL[6].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized25 | 74| -|535 | \TC_SRL[7].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized26 | 90| -|536 | \TC_SRL[8].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized27 | 74| -|537 | \TC_SRL[9].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized28 | 74| -|538 | reg_15 |xsdbs_v1_0_2_reg__parameterized54 | 29| -|539 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_308 | 29| -|540 | reg_16 |xsdbs_v1_0_2_reg__parameterized55 | 17| -|541 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_307 | 17| -|542 | reg_17 |xsdbs_v1_0_2_reg__parameterized56 | 26| -|543 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_306 | 26| -|544 | reg_18 |xsdbs_v1_0_2_reg__parameterized57 | 31| -|545 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_305 | 31| -|546 | reg_19 |xsdbs_v1_0_2_reg__parameterized58 | 20| -|547 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_304 | 20| -|548 | reg_1a |xsdbs_v1_0_2_reg__parameterized59 | 33| -|549 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1 | 33| -|550 | reg_6 |xsdbs_v1_0_2_reg__parameterized39 | 20| -|551 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_303 | 20| -|552 | reg_7 |xsdbs_v1_0_2_reg__parameterized40 | 36| -|553 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized0 | 36| -|554 | reg_8 |xsdbs_v1_0_2_reg__parameterized41 | 6| -|555 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_302 | 6| -|556 | reg_80 |xsdbs_v1_0_2_reg__parameterized60 | 17| -|557 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2_301 | 17| -|558 | reg_81 |xsdbs_v1_0_2_reg__parameterized61 | 17| -|559 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_300 | 17| -|560 | reg_82 |xsdbs_v1_0_2_reg__parameterized62 | 17| -|561 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2 | 17| -|562 | reg_83 |xsdbs_v1_0_2_reg__parameterized63 | 63| -|563 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_299 | 63| -|564 | reg_84 |xsdbs_v1_0_2_reg__parameterized64 | 23| -|565 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_298 | 23| -|566 | reg_85 |xsdbs_v1_0_2_reg__parameterized65 | 17| -|567 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_297 | 17| -|568 | reg_887 |xsdbs_v1_0_2_reg__parameterized67 | 3| -|569 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_296 | 3| -|570 | reg_88d |xsdbs_v1_0_2_reg__parameterized69 | 2| -|571 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_295 | 2| -|572 | reg_88f |xsdbs_v1_0_2_reg__parameterized71 | 38| -|573 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_294 | 38| -|574 | reg_892 |xsdbs_v1_0_2_reg__parameterized70 | 4| -|575 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_293 | 4| -|576 | reg_9 |xsdbs_v1_0_2_reg__parameterized42 | 23| -|577 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_292 | 23| -|578 | reg_srl_fff |xsdbs_v1_0_2_reg_p2s__parameterized56 | 102| -|579 | reg_stream_ffd |xsdbs_v1_0_2_reg_stream__parameterized1 | 18| -|580 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl | 18| -|581 | reg_stream_ffe |xsdbs_v1_0_2_reg_stream__parameterized2 | 16| -|582 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat | 16| -|583 | u_ila_reset_ctrl |ila_v6_2_9_ila_reset_ctrl | 47| -|584 | arm_detection_inst |ltlib_v1_0_0_rising_edge_detection | 5| -|585 | \asyncrounous_transfer.arm_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer | 7| -|586 | \asyncrounous_transfer.arm_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_288 | 7| -|587 | \asyncrounous_transfer.halt_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer_289 | 7| -|588 | \asyncrounous_transfer.halt_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_290 | 6| -|589 | halt_detection_inst |ltlib_v1_0_0_rising_edge_detection_291 | 6| -|590 | u_trig |ila_v6_2_9_ila_trigger | 1217| -|591 | \N_DDR_TC.N_DDR_TC_INST[0].U_TC |ltlib_v1_0_0_match | 19| -|592 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_283 | 18| -|593 | DUT |ltlib_v1_0_0_all_typeA_284 | 18| -|594 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_285 | 5| -|595 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_286 | 5| -|596 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_287 | 6| -|597 | \N_DDR_TC.N_DDR_TC_INST[10].U_TC |ltlib_v1_0_0_match_0 | 19| -|598 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_278 | 18| -|599 | DUT |ltlib_v1_0_0_all_typeA_279 | 18| -|600 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_280 | 5| -|601 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_281 | 5| -|602 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_282 | 6| -|603 | \N_DDR_TC.N_DDR_TC_INST[11].U_TC |ltlib_v1_0_0_match_1 | 19| -|604 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_273 | 18| -|605 | DUT |ltlib_v1_0_0_all_typeA_274 | 18| -|606 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_275 | 5| -|607 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_276 | 5| -|608 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_277 | 6| -|609 | \N_DDR_TC.N_DDR_TC_INST[12].U_TC |ltlib_v1_0_0_match_2 | 19| -|610 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_268 | 18| -|611 | DUT |ltlib_v1_0_0_all_typeA_269 | 18| -|612 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_270 | 5| -|613 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_271 | 5| -|614 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_272 | 6| -|615 | \N_DDR_TC.N_DDR_TC_INST[13].U_TC |ltlib_v1_0_0_match_3 | 19| -|616 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_263 | 18| -|617 | DUT |ltlib_v1_0_0_all_typeA_264 | 18| -|618 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_265 | 5| -|619 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_266 | 5| -|620 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_267 | 6| -|621 | \N_DDR_TC.N_DDR_TC_INST[14].U_TC |ltlib_v1_0_0_match_4 | 19| -|622 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_258 | 18| -|623 | DUT |ltlib_v1_0_0_all_typeA_259 | 18| -|624 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_260 | 5| -|625 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_261 | 5| -|626 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_262 | 6| -|627 | \N_DDR_TC.N_DDR_TC_INST[15].U_TC |ltlib_v1_0_0_match_5 | 19| -|628 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_253 | 18| -|629 | DUT |ltlib_v1_0_0_all_typeA_254 | 18| -|630 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_255 | 5| -|631 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_256 | 5| -|632 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_257 | 6| -|633 | \N_DDR_TC.N_DDR_TC_INST[16].U_TC |ltlib_v1_0_0_match_6 | 19| -|634 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_248 | 18| -|635 | DUT |ltlib_v1_0_0_all_typeA_249 | 18| -|636 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_250 | 5| -|637 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_251 | 5| -|638 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_252 | 6| -|639 | \N_DDR_TC.N_DDR_TC_INST[17].U_TC |ltlib_v1_0_0_match_7 | 19| -|640 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_243 | 18| -|641 | DUT |ltlib_v1_0_0_all_typeA_244 | 18| -|642 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_245 | 5| -|643 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_246 | 5| -|644 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_247 | 6| -|645 | \N_DDR_TC.N_DDR_TC_INST[18].U_TC |ltlib_v1_0_0_match_8 | 19| -|646 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_238 | 18| -|647 | DUT |ltlib_v1_0_0_all_typeA_239 | 18| -|648 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_240 | 5| -|649 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_241 | 5| -|650 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_242 | 6| -|651 | \N_DDR_TC.N_DDR_TC_INST[19].U_TC |ltlib_v1_0_0_match_9 | 19| -|652 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_233 | 18| -|653 | DUT |ltlib_v1_0_0_all_typeA_234 | 18| -|654 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_235 | 5| -|655 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_236 | 5| -|656 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_237 | 6| -|657 | \N_DDR_TC.N_DDR_TC_INST[1].U_TC |ltlib_v1_0_0_match_10 | 19| -|658 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_228 | 18| -|659 | DUT |ltlib_v1_0_0_all_typeA_229 | 18| -|660 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_230 | 5| -|661 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_231 | 5| -|662 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_232 | 6| -|663 | \N_DDR_TC.N_DDR_TC_INST[20].U_TC |ltlib_v1_0_0_match_11 | 19| -|664 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_223 | 18| -|665 | DUT |ltlib_v1_0_0_all_typeA_224 | 18| -|666 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_225 | 5| -|667 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_226 | 5| -|668 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_227 | 6| -|669 | \N_DDR_TC.N_DDR_TC_INST[21].U_TC |ltlib_v1_0_0_match_12 | 19| -|670 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_218 | 18| -|671 | DUT |ltlib_v1_0_0_all_typeA_219 | 18| -|672 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_220 | 5| -|673 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_221 | 5| -|674 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_222 | 6| -|675 | \N_DDR_TC.N_DDR_TC_INST[22].U_TC |ltlib_v1_0_0_match_13 | 19| -|676 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_213 | 18| -|677 | DUT |ltlib_v1_0_0_all_typeA_214 | 18| -|678 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_215 | 5| -|679 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_216 | 5| -|680 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_217 | 6| -|681 | \N_DDR_TC.N_DDR_TC_INST[23].U_TC |ltlib_v1_0_0_match_14 | 19| -|682 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_208 | 18| -|683 | DUT |ltlib_v1_0_0_all_typeA_209 | 18| -|684 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_210 | 5| -|685 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_211 | 5| -|686 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_212 | 6| -|687 | \N_DDR_TC.N_DDR_TC_INST[24].U_TC |ltlib_v1_0_0_match_15 | 19| -|688 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_203 | 18| -|689 | DUT |ltlib_v1_0_0_all_typeA_204 | 18| -|690 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_205 | 5| -|691 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_206 | 5| -|692 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_207 | 6| -|693 | \N_DDR_TC.N_DDR_TC_INST[25].U_TC |ltlib_v1_0_0_match_16 | 19| -|694 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_198 | 18| -|695 | DUT |ltlib_v1_0_0_all_typeA_199 | 18| -|696 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_200 | 5| -|697 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_201 | 5| -|698 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_202 | 6| -|699 | \N_DDR_TC.N_DDR_TC_INST[26].U_TC |ltlib_v1_0_0_match_17 | 19| -|700 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_193 | 18| -|701 | DUT |ltlib_v1_0_0_all_typeA_194 | 18| -|702 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_195 | 5| -|703 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_196 | 5| -|704 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_197 | 6| -|705 | \N_DDR_TC.N_DDR_TC_INST[27].U_TC |ltlib_v1_0_0_match_18 | 19| -|706 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_188 | 18| -|707 | DUT |ltlib_v1_0_0_all_typeA_189 | 18| -|708 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_190 | 5| -|709 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_191 | 5| -|710 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_192 | 6| -|711 | \N_DDR_TC.N_DDR_TC_INST[28].U_TC |ltlib_v1_0_0_match_19 | 19| -|712 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_183 | 18| -|713 | DUT |ltlib_v1_0_0_all_typeA_184 | 18| -|714 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_185 | 5| -|715 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_186 | 5| -|716 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_187 | 6| -|717 | \N_DDR_TC.N_DDR_TC_INST[29].U_TC |ltlib_v1_0_0_match_20 | 19| -|718 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_178 | 18| -|719 | DUT |ltlib_v1_0_0_all_typeA_179 | 18| -|720 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_180 | 5| -|721 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_181 | 5| -|722 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_182 | 6| -|723 | \N_DDR_TC.N_DDR_TC_INST[2].U_TC |ltlib_v1_0_0_match_21 | 19| -|724 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_173 | 18| -|725 | DUT |ltlib_v1_0_0_all_typeA_174 | 18| -|726 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_175 | 5| -|727 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_176 | 5| -|728 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_177 | 6| -|729 | \N_DDR_TC.N_DDR_TC_INST[30].U_TC |ltlib_v1_0_0_match_22 | 19| -|730 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_168 | 18| -|731 | DUT |ltlib_v1_0_0_all_typeA_169 | 18| -|732 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_170 | 5| -|733 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_171 | 5| -|734 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_172 | 6| -|735 | \N_DDR_TC.N_DDR_TC_INST[31].U_TC |ltlib_v1_0_0_match_23 | 19| -|736 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_163 | 18| -|737 | DUT |ltlib_v1_0_0_all_typeA_164 | 18| -|738 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_165 | 5| -|739 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_166 | 5| -|740 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_167 | 6| -|741 | \N_DDR_TC.N_DDR_TC_INST[3].U_TC |ltlib_v1_0_0_match_24 | 19| -|742 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_158 | 18| -|743 | DUT |ltlib_v1_0_0_all_typeA_159 | 18| -|744 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_160 | 5| -|745 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_161 | 5| -|746 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_162 | 6| -|747 | \N_DDR_TC.N_DDR_TC_INST[4].U_TC |ltlib_v1_0_0_match_25 | 19| -|748 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_153 | 18| -|749 | DUT |ltlib_v1_0_0_all_typeA_154 | 18| -|750 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_155 | 5| -|751 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_156 | 5| -|752 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_157 | 6| -|753 | \N_DDR_TC.N_DDR_TC_INST[5].U_TC |ltlib_v1_0_0_match_26 | 19| -|754 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_148 | 18| -|755 | DUT |ltlib_v1_0_0_all_typeA_149 | 18| -|756 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_150 | 5| -|757 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_151 | 5| -|758 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_152 | 6| -|759 | \N_DDR_TC.N_DDR_TC_INST[6].U_TC |ltlib_v1_0_0_match_27 | 19| -|760 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_143 | 18| -|761 | DUT |ltlib_v1_0_0_all_typeA_144 | 18| -|762 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_145 | 5| -|763 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_146 | 5| -|764 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_147 | 6| -|765 | \N_DDR_TC.N_DDR_TC_INST[7].U_TC |ltlib_v1_0_0_match_28 | 19| -|766 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_138 | 18| -|767 | DUT |ltlib_v1_0_0_all_typeA_139 | 18| -|768 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_140 | 5| -|769 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_141 | 5| -|770 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_142 | 6| -|771 | \N_DDR_TC.N_DDR_TC_INST[8].U_TC |ltlib_v1_0_0_match_29 | 19| -|772 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_133 | 18| -|773 | DUT |ltlib_v1_0_0_all_typeA_134 | 18| -|774 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_135 | 5| -|775 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_136 | 5| -|776 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_137 | 6| -|777 | \N_DDR_TC.N_DDR_TC_INST[9].U_TC |ltlib_v1_0_0_match_30 | 19| -|778 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_128 | 18| -|779 | DUT |ltlib_v1_0_0_all_typeA_129 | 18| -|780 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_130 | 5| -|781 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_131 | 5| -|782 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_132 | 6| -|783 | \STRG_QUAL.U_STRG_QUAL |ltlib_v1_0_0_match_31 | 39| -|784 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA | 38| -|785 | DUT |ltlib_v1_0_0_all_typeA | 18| -|786 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_125 | 5| -|787 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_126 | 5| -|788 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_127 | 6| -|789 | U_TM |ila_v6_2_9_ila_trig_match | 522| -|790 | \N_DDR_MODE.G_NMU[0].U_M |ltlib_v1_0_0_match__parameterized0 | 38| -|791 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_121 | 37| -|792 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_122 | 13| -|793 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_123 | 5| -|794 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_124 | 6| -|795 | \N_DDR_MODE.G_NMU[10].U_M |ltlib_v1_0_0_match__parameterized0_32 | 38| -|796 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_117 | 37| -|797 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_118 | 13| -|798 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_119 | 5| -|799 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_120 | 6| -|800 | \N_DDR_MODE.G_NMU[11].U_M |ltlib_v1_0_0_match__parameterized0_33 | 14| -|801 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_113 | 13| -|802 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_114 | 13| -|803 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_115 | 5| -|804 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_116 | 6| -|805 | \N_DDR_MODE.G_NMU[12].U_M |ltlib_v1_0_0_match__parameterized0_34 | 38| -|806 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_109 | 37| -|807 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_110 | 13| -|808 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_111 | 5| -|809 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_112 | 6| -|810 | \N_DDR_MODE.G_NMU[13].U_M |ltlib_v1_0_0_match__parameterized0_35 | 14| -|811 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_105 | 13| -|812 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_106 | 13| -|813 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_107 | 5| -|814 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_108 | 6| -|815 | \N_DDR_MODE.G_NMU[14].U_M |ltlib_v1_0_0_match__parameterized0_36 | 38| -|816 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_101 | 37| -|817 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_102 | 13| -|818 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_103 | 5| -|819 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_104 | 6| -|820 | \N_DDR_MODE.G_NMU[15].U_M |ltlib_v1_0_0_match__parameterized0_37 | 14| -|821 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_97 | 13| -|822 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_98 | 13| -|823 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_99 | 5| -|824 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_100 | 6| -|825 | \N_DDR_MODE.G_NMU[16].U_M |ltlib_v1_0_0_match__parameterized0_38 | 38| -|826 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_93 | 37| -|827 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_94 | 13| -|828 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_95 | 5| -|829 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_96 | 6| -|830 | \N_DDR_MODE.G_NMU[17].U_M |ltlib_v1_0_0_match__parameterized0_39 | 14| -|831 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_89 | 13| -|832 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_90 | 13| -|833 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_91 | 5| -|834 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_92 | 6| -|835 | \N_DDR_MODE.G_NMU[18].U_M |ltlib_v1_0_0_match__parameterized1 | 40| -|836 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_85 | 39| -|837 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_86 | 13| -|838 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_87 | 5| -|839 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_88 | 6| -|840 | \N_DDR_MODE.G_NMU[19].U_M |ltlib_v1_0_0_match__parameterized1_40 | 14| -|841 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1 | 13| -|842 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_82 | 13| -|843 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_83 | 5| -|844 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_84 | 6| -|845 | \N_DDR_MODE.G_NMU[1].U_M |ltlib_v1_0_0_match__parameterized0_41 | 14| -|846 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_78 | 13| -|847 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_79 | 13| -|848 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_80 | 5| -|849 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_81 | 6| -|850 | \N_DDR_MODE.G_NMU[2].U_M |ltlib_v1_0_0_match__parameterized0_42 | 38| -|851 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_74 | 37| -|852 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_75 | 13| -|853 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_76 | 5| -|854 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_77 | 6| -|855 | \N_DDR_MODE.G_NMU[3].U_M |ltlib_v1_0_0_match__parameterized0_43 | 14| -|856 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_70 | 13| -|857 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_71 | 13| -|858 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_72 | 5| -|859 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_73 | 6| -|860 | \N_DDR_MODE.G_NMU[4].U_M |ltlib_v1_0_0_match__parameterized0_44 | 38| -|861 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_66 | 37| -|862 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_67 | 13| -|863 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_68 | 5| -|864 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_69 | 6| -|865 | \N_DDR_MODE.G_NMU[5].U_M |ltlib_v1_0_0_match__parameterized0_45 | 14| -|866 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_62 | 13| -|867 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_63 | 13| -|868 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_64 | 5| -|869 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_65 | 6| -|870 | \N_DDR_MODE.G_NMU[6].U_M |ltlib_v1_0_0_match__parameterized0_46 | 38| -|871 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_58 | 37| -|872 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_59 | 13| -|873 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_60 | 5| -|874 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_61 | 6| -|875 | \N_DDR_MODE.G_NMU[7].U_M |ltlib_v1_0_0_match__parameterized0_47 | 14| -|876 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_54 | 13| -|877 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_55 | 13| -|878 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_56 | 5| -|879 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_57 | 6| -|880 | \N_DDR_MODE.G_NMU[8].U_M |ltlib_v1_0_0_match__parameterized0_48 | 38| -|881 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_50 | 37| -|882 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_51 | 13| -|883 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_52 | 5| -|884 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_53 | 6| -|885 | \N_DDR_MODE.G_NMU[9].U_M |ltlib_v1_0_0_match__parameterized0_49 | 14| -|886 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0 | 13| -|887 | DUT |ltlib_v1_0_0_all_typeA__parameterized0 | 13| -|888 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice | 5| -|889 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0 | 6| -|890 | xsdb_memory_read_inst |ltlib_v1_0_0_generic_memrd | 592| +|264 | \ramloop[210].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized209 | 1| +|265 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized209 | 1| +|266 | \ramloop[211].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized210 | 1| +|267 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized210 | 1| +|268 | \ramloop[212].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized211 | 1| +|269 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized211 | 1| +|270 | \ramloop[213].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized212 | 1| +|271 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized212 | 1| +|272 | \ramloop[214].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized213 | 1| +|273 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized213 | 1| +|274 | \ramloop[215].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized214 | 1| +|275 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized214 | 1| +|276 | \ramloop[216].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized215 | 1| +|277 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized215 | 1| +|278 | \ramloop[217].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized216 | 1| +|279 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized216 | 1| +|280 | \ramloop[218].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized217 | 1| +|281 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized217 | 1| +|282 | \ramloop[219].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized218 | 1| +|283 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized218 | 1| +|284 | \ramloop[21].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized20 | 1| +|285 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized20 | 1| +|286 | \ramloop[220].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized219 | 1| +|287 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized219 | 1| +|288 | \ramloop[221].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized220 | 1| +|289 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized220 | 1| +|290 | \ramloop[222].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized221 | 1| +|291 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized221 | 1| +|292 | \ramloop[223].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized222 | 1| +|293 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized222 | 1| +|294 | \ramloop[224].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized223 | 1| +|295 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized223 | 1| +|296 | \ramloop[225].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized224 | 1| +|297 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized224 | 1| +|298 | \ramloop[226].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized225 | 1| +|299 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized225 | 1| +|300 | \ramloop[227].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized226 | 1| +|301 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized226 | 1| +|302 | \ramloop[228].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized227 | 1| +|303 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized227 | 1| +|304 | \ramloop[229].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized228 | 1| +|305 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized228 | 1| +|306 | \ramloop[22].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized21 | 1| +|307 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized21 | 1| +|308 | \ramloop[230].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized229 | 1| +|309 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized229 | 1| +|310 | \ramloop[231].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized230 | 1| +|311 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized230 | 1| +|312 | \ramloop[232].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized231 | 1| +|313 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized231 | 1| +|314 | \ramloop[233].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized232 | 1| +|315 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized232 | 1| +|316 | \ramloop[234].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized233 | 1| +|317 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized233 | 1| +|318 | \ramloop[235].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized234 | 1| +|319 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized234 | 1| +|320 | \ramloop[236].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized235 | 1| +|321 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized235 | 1| +|322 | \ramloop[237].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized236 | 1| +|323 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized236 | 1| +|324 | \ramloop[238].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized237 | 1| +|325 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized237 | 1| +|326 | \ramloop[239].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized238 | 1| +|327 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized238 | 1| +|328 | \ramloop[23].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized22 | 1| +|329 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized22 | 1| +|330 | \ramloop[240].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized239 | 1| +|331 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized239 | 1| +|332 | \ramloop[241].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized240 | 1| +|333 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized240 | 1| +|334 | \ramloop[242].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized241 | 1| +|335 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized241 | 1| +|336 | \ramloop[243].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized242 | 1| +|337 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized242 | 1| +|338 | \ramloop[244].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized243 | 1| +|339 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized243 | 1| +|340 | \ramloop[245].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized244 | 1| +|341 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized244 | 1| +|342 | \ramloop[246].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized245 | 1| +|343 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized245 | 1| +|344 | \ramloop[247].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized246 | 1| +|345 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized246 | 1| +|346 | \ramloop[248].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized247 | 1| +|347 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized247 | 1| +|348 | \ramloop[249].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized248 | 1| +|349 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized248 | 1| +|350 | \ramloop[24].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized23 | 1| +|351 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized23 | 1| +|352 | \ramloop[250].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized249 | 1| +|353 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized249 | 1| +|354 | \ramloop[251].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized250 | 1| +|355 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized250 | 1| +|356 | \ramloop[252].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized251 | 1| +|357 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized251 | 1| +|358 | \ramloop[253].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized252 | 1| +|359 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized252 | 1| +|360 | \ramloop[254].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized253 | 1| +|361 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized253 | 1| +|362 | \ramloop[255].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized254 | 1| +|363 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized254 | 1| +|364 | \ramloop[256].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized255 | 1| +|365 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized255 | 1| +|366 | \ramloop[257].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized256 | 1| +|367 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized256 | 1| +|368 | \ramloop[258].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized257 | 1| +|369 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized257 | 1| +|370 | \ramloop[259].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized258 | 1| +|371 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized258 | 1| +|372 | \ramloop[25].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized24 | 1| +|373 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized24 | 1| +|374 | \ramloop[260].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized259 | 1| +|375 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized259 | 1| +|376 | \ramloop[261].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized260 | 1| +|377 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized260 | 1| +|378 | \ramloop[262].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized261 | 1| +|379 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized261 | 1| +|380 | \ramloop[263].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized262 | 1| +|381 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized262 | 1| +|382 | \ramloop[264].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized263 | 1| +|383 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized263 | 1| +|384 | \ramloop[265].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized264 | 1| +|385 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized264 | 1| +|386 | \ramloop[266].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized265 | 1| +|387 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized265 | 1| +|388 | \ramloop[267].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized266 | 1| +|389 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized266 | 1| +|390 | \ramloop[268].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized267 | 1| +|391 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized267 | 1| +|392 | \ramloop[269].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized268 | 1| +|393 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized268 | 1| +|394 | \ramloop[26].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized25 | 1| +|395 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized25 | 1| +|396 | \ramloop[270].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized269 | 1| +|397 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized269 | 1| +|398 | \ramloop[271].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized270 | 1| +|399 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized270 | 1| +|400 | \ramloop[272].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized271 | 2| +|401 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized271 | 2| +|402 | \ramloop[27].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized26 | 1| +|403 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized26 | 1| +|404 | \ramloop[28].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized27 | 1| +|405 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized27 | 1| +|406 | \ramloop[29].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized28 | 1| +|407 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized28 | 1| +|408 | \ramloop[2].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized1 | 1| +|409 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 | 1| +|410 | \ramloop[30].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized29 | 1| +|411 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized29 | 1| +|412 | \ramloop[31].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized30 | 1| +|413 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized30 | 1| +|414 | \ramloop[32].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized31 | 1| +|415 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized31 | 1| +|416 | \ramloop[33].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized32 | 1| +|417 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized32 | 1| +|418 | \ramloop[34].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized33 | 1| +|419 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized33 | 1| +|420 | \ramloop[35].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized34 | 1| +|421 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized34 | 1| +|422 | \ramloop[36].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized35 | 1| +|423 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized35 | 1| +|424 | \ramloop[37].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized36 | 1| +|425 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized36 | 1| +|426 | \ramloop[38].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized37 | 1| +|427 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized37 | 1| +|428 | \ramloop[39].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized38 | 1| +|429 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized38 | 1| +|430 | \ramloop[3].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized2 | 1| +|431 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 | 1| +|432 | \ramloop[40].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized39 | 1| +|433 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized39 | 1| +|434 | \ramloop[41].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized40 | 1| +|435 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized40 | 1| +|436 | \ramloop[42].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized41 | 1| +|437 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized41 | 1| +|438 | \ramloop[43].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized42 | 1| +|439 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized42 | 1| +|440 | \ramloop[44].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized43 | 1| +|441 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized43 | 1| +|442 | \ramloop[45].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized44 | 1| +|443 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized44 | 1| +|444 | \ramloop[46].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized45 | 1| +|445 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized45 | 1| +|446 | \ramloop[47].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized46 | 1| +|447 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized46 | 1| +|448 | \ramloop[48].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized47 | 1| +|449 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized47 | 1| +|450 | \ramloop[49].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized48 | 1| +|451 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized48 | 1| +|452 | \ramloop[4].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized3 | 1| +|453 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized3 | 1| +|454 | \ramloop[50].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized49 | 1| +|455 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized49 | 1| +|456 | \ramloop[51].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized50 | 1| +|457 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized50 | 1| +|458 | \ramloop[52].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized51 | 1| +|459 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized51 | 1| +|460 | \ramloop[53].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized52 | 1| +|461 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized52 | 1| +|462 | \ramloop[54].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized53 | 1| +|463 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized53 | 1| +|464 | \ramloop[55].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized54 | 1| +|465 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized54 | 1| +|466 | \ramloop[56].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized55 | 1| +|467 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized55 | 1| +|468 | \ramloop[57].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized56 | 1| +|469 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized56 | 1| +|470 | \ramloop[58].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized57 | 1| +|471 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized57 | 1| +|472 | \ramloop[59].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized58 | 1| +|473 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized58 | 1| +|474 | \ramloop[5].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized4 | 1| +|475 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized4 | 1| +|476 | \ramloop[60].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized59 | 1| +|477 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized59 | 1| +|478 | \ramloop[61].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized60 | 1| +|479 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized60 | 1| +|480 | \ramloop[62].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized61 | 1| +|481 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized61 | 1| +|482 | \ramloop[63].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized62 | 1| +|483 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized62 | 1| +|484 | \ramloop[64].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized63 | 1| +|485 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized63 | 1| +|486 | \ramloop[65].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized64 | 1| +|487 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized64 | 1| +|488 | \ramloop[66].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized65 | 1| +|489 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized65 | 1| +|490 | \ramloop[67].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized66 | 1| +|491 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized66 | 1| +|492 | \ramloop[68].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized67 | 1| +|493 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized67 | 1| +|494 | \ramloop[69].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized68 | 1| +|495 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized68 | 1| +|496 | \ramloop[6].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized5 | 1| +|497 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized5 | 1| +|498 | \ramloop[70].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized69 | 1| +|499 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized69 | 1| +|500 | \ramloop[71].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized70 | 1| +|501 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized70 | 1| +|502 | \ramloop[72].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized71 | 1| +|503 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized71 | 1| +|504 | \ramloop[73].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized72 | 1| +|505 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized72 | 1| +|506 | \ramloop[74].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized73 | 1| +|507 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized73 | 1| +|508 | \ramloop[75].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized74 | 1| +|509 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized74 | 1| +|510 | \ramloop[76].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized75 | 1| +|511 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized75 | 1| +|512 | \ramloop[77].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized76 | 1| +|513 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized76 | 1| +|514 | \ramloop[78].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized77 | 1| +|515 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized77 | 1| +|516 | \ramloop[79].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized78 | 1| +|517 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized78 | 1| +|518 | \ramloop[7].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized6 | 1| +|519 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized6 | 1| +|520 | \ramloop[80].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized79 | 1| +|521 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized79 | 1| +|522 | \ramloop[81].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized80 | 1| +|523 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized80 | 1| +|524 | \ramloop[82].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized81 | 1| +|525 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized81 | 1| +|526 | \ramloop[83].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized82 | 1| +|527 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized82 | 1| +|528 | \ramloop[84].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized83 | 1| +|529 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized83 | 1| +|530 | \ramloop[85].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized84 | 1| +|531 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized84 | 1| +|532 | \ramloop[86].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized85 | 1| +|533 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized85 | 1| +|534 | \ramloop[87].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized86 | 1| +|535 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized86 | 1| +|536 | \ramloop[88].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized87 | 1| +|537 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized87 | 1| +|538 | \ramloop[89].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized88 | 1| +|539 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized88 | 1| +|540 | \ramloop[8].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized7 | 1| +|541 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized7 | 1| +|542 | \ramloop[90].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized89 | 1| +|543 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized89 | 1| +|544 | \ramloop[91].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized90 | 1| +|545 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized90 | 1| +|546 | \ramloop[92].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized91 | 1| +|547 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized91 | 1| +|548 | \ramloop[93].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized92 | 1| +|549 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized92 | 1| +|550 | \ramloop[94].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized93 | 1| +|551 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized93 | 1| +|552 | \ramloop[95].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized94 | 1| +|553 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized94 | 1| +|554 | \ramloop[96].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized95 | 1| +|555 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized95 | 1| +|556 | \ramloop[97].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized96 | 1| +|557 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized96 | 1| +|558 | \ramloop[98].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized97 | 1| +|559 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized97 | 1| +|560 | \ramloop[99].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized98 | 1| +|561 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized98 | 1| +|562 | \ramloop[9].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized8 | 1| +|563 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized8 | 1| +|564 | u_ila_cap_ctrl |ila_v6_2_9_ila_cap_ctrl_legacy | 320| +|565 | U_CDONE |ltlib_v1_0_0_cfglut6__parameterized0 | 5| +|566 | U_NS0 |ltlib_v1_0_0_cfglut7 | 8| +|567 | U_NS1 |ltlib_v1_0_0_cfglut7_330 | 10| +|568 | u_cap_addrgen |ila_v6_2_9_ila_cap_addrgen | 292| +|569 | U_CMPRESET |ltlib_v1_0_0_cfglut6 | 3| +|570 | u_cap_sample_counter |ila_v6_2_9_ila_cap_sample_counter | 71| +|571 | U_SCE |ltlib_v1_0_0_cfglut4_337 | 1| +|572 | U_SCMPCE |ltlib_v1_0_0_cfglut5_338 | 1| +|573 | U_SCRST |ltlib_v1_0_0_cfglut6_339 | 3| +|574 | u_scnt_cmp |ltlib_v1_0_0_match_nodelay_340 | 28| +|575 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_341 | 28| +|576 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_342 | 12| +|577 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_343 | 5| +|578 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_344 | 5| +|579 | u_cap_window_counter |ila_v6_2_9_ila_cap_window_counter | 66| +|580 | U_WCE |ltlib_v1_0_0_cfglut4 | 1| +|581 | U_WHCMPCE |ltlib_v1_0_0_cfglut5 | 1| +|582 | U_WLCMPCE |ltlib_v1_0_0_cfglut5_331 | 1| +|583 | u_wcnt_hcmp |ltlib_v1_0_0_match_nodelay | 12| +|584 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_333 | 12| +|585 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_334 | 12| +|586 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_335 | 5| +|587 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_336 | 5| +|588 | u_wcnt_lcmp |ltlib_v1_0_0_match_nodelay_332 | 28| +|589 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay | 28| +|590 | DUT |ltlib_v1_0_0_all_typeA__parameterized1 | 12| +|591 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1 | 5| +|592 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2 | 5| +|593 | u_ila_regs |ila_v6_2_9_ila_register | 6276| +|594 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 302| +|595 | reg_890 |xsdbs_v1_0_2_reg__parameterized78 | 16| +|596 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_329 | 16| +|597 | \ADV_TRIG_STREAM.reg_stream_ffc |xsdbs_v1_0_2_reg_stream__parameterized0 | 23| +|598 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_328 | 19| +|599 | \ADV_TRIG_STREAM_READBACK.reg_stream_ffb |xsdbs_v1_0_2_reg_stream | 32| +|600 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_327 | 32| +|601 | \CNT.CNT_SRL[0].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized55 | 75| +|602 | \CNT.CNT_SRL[1].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized56 | 76| +|603 | \CNT.CNT_SRL[2].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized57 | 108| +|604 | \CNT.CNT_SRL[3].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized58 | 77| +|605 | \MU_SRL[0].mu_srl_reg |xsdbs_v1_0_2_reg_p2s | 75| +|606 | \MU_SRL[10].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized9 | 75| +|607 | \MU_SRL[11].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized10 | 106| +|608 | \MU_SRL[12].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized11 | 74| +|609 | \MU_SRL[13].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized12 | 75| +|610 | \MU_SRL[14].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized13 | 75| +|611 | \MU_SRL[15].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized14 | 90| +|612 | \MU_SRL[16].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized15 | 74| +|613 | \MU_SRL[17].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized16 | 75| +|614 | \MU_SRL[18].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized17 | 75| +|615 | \MU_SRL[19].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized18 | 122| +|616 | \MU_SRL[1].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized0 | 75| +|617 | \MU_SRL[20].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized19 | 74| +|618 | \MU_SRL[21].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized20 | 75| +|619 | \MU_SRL[22].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized21 | 75| +|620 | \MU_SRL[23].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized22 | 90| +|621 | \MU_SRL[2].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized1 | 75| +|622 | \MU_SRL[3].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized2 | 107| +|623 | \MU_SRL[4].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized3 | 74| +|624 | \MU_SRL[5].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized4 | 75| +|625 | \MU_SRL[6].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized5 | 75| +|626 | \MU_SRL[7].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized6 | 90| +|627 | \MU_SRL[8].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized7 | 74| +|628 | \MU_SRL[9].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized8 | 75| +|629 | \STRG_QUAL.qual_strg_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized59 | 75| +|630 | \TC_SRL[0].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized23 | 75| +|631 | \TC_SRL[10].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized33 | 75| +|632 | \TC_SRL[11].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized34 | 106| +|633 | \TC_SRL[12].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized35 | 74| +|634 | \TC_SRL[13].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized36 | 75| +|635 | \TC_SRL[14].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized37 | 75| +|636 | \TC_SRL[15].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized38 | 90| +|637 | \TC_SRL[16].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized39 | 74| +|638 | \TC_SRL[17].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized40 | 75| +|639 | \TC_SRL[18].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized41 | 75| +|640 | \TC_SRL[19].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized42 | 106| +|641 | \TC_SRL[1].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized24 | 75| +|642 | \TC_SRL[20].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized43 | 74| +|643 | \TC_SRL[21].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized44 | 75| +|644 | \TC_SRL[22].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized45 | 75| +|645 | \TC_SRL[23].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized46 | 90| +|646 | \TC_SRL[24].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized47 | 74| +|647 | \TC_SRL[25].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized48 | 74| +|648 | \TC_SRL[26].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized49 | 74| +|649 | \TC_SRL[27].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized50 | 122| +|650 | \TC_SRL[28].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized51 | 74| +|651 | \TC_SRL[29].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized52 | 74| +|652 | \TC_SRL[2].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized25 | 75| +|653 | \TC_SRL[30].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized53 | 74| +|654 | \TC_SRL[31].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized54 | 90| +|655 | \TC_SRL[3].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized26 | 107| +|656 | \TC_SRL[4].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized27 | 74| +|657 | \TC_SRL[5].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized28 | 75| +|658 | \TC_SRL[6].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized29 | 75| +|659 | \TC_SRL[7].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized30 | 90| +|660 | \TC_SRL[8].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized31 | 74| +|661 | \TC_SRL[9].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized32 | 75| +|662 | reg_15 |xsdbs_v1_0_2_reg__parameterized60 | 35| +|663 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_326 | 35| +|664 | reg_16 |xsdbs_v1_0_2_reg__parameterized61 | 17| +|665 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_325 | 17| +|666 | reg_17 |xsdbs_v1_0_2_reg__parameterized62 | 29| +|667 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_324 | 29| +|668 | reg_18 |xsdbs_v1_0_2_reg__parameterized63 | 30| +|669 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_323 | 30| +|670 | reg_19 |xsdbs_v1_0_2_reg__parameterized64 | 19| +|671 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_322 | 19| +|672 | reg_1a |xsdbs_v1_0_2_reg__parameterized65 | 20| +|673 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1 | 20| +|674 | reg_6 |xsdbs_v1_0_2_reg__parameterized45 | 31| +|675 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_321 | 31| +|676 | reg_7 |xsdbs_v1_0_2_reg__parameterized46 | 30| +|677 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized0 | 30| +|678 | reg_8 |xsdbs_v1_0_2_reg__parameterized47 | 8| +|679 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_320 | 8| +|680 | reg_80 |xsdbs_v1_0_2_reg__parameterized66 | 17| +|681 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2_319 | 17| +|682 | reg_81 |xsdbs_v1_0_2_reg__parameterized67 | 17| +|683 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_318 | 17| +|684 | reg_82 |xsdbs_v1_0_2_reg__parameterized68 | 17| +|685 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2 | 17| +|686 | reg_83 |xsdbs_v1_0_2_reg__parameterized69 | 48| +|687 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_317 | 48| +|688 | reg_84 |xsdbs_v1_0_2_reg__parameterized70 | 44| +|689 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_316 | 44| +|690 | reg_85 |xsdbs_v1_0_2_reg__parameterized71 | 18| +|691 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_315 | 18| +|692 | reg_887 |xsdbs_v1_0_2_reg__parameterized73 | 4| +|693 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_314 | 4| +|694 | reg_88d |xsdbs_v1_0_2_reg__parameterized75 | 2| +|695 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_313 | 2| +|696 | reg_88f |xsdbs_v1_0_2_reg__parameterized77 | 36| +|697 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_312 | 36| +|698 | reg_892 |xsdbs_v1_0_2_reg__parameterized76 | 6| +|699 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_311 | 6| +|700 | reg_9 |xsdbs_v1_0_2_reg__parameterized48 | 23| +|701 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_310 | 23| +|702 | reg_srl_fff |xsdbs_v1_0_2_reg_p2s__parameterized60 | 97| +|703 | reg_stream_ffd |xsdbs_v1_0_2_reg_stream__parameterized1 | 19| +|704 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl | 19| +|705 | reg_stream_ffe |xsdbs_v1_0_2_reg_stream__parameterized2 | 16| +|706 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat | 16| +|707 | u_ila_reset_ctrl |ila_v6_2_9_ila_reset_ctrl | 47| +|708 | arm_detection_inst |ltlib_v1_0_0_rising_edge_detection | 5| +|709 | \asyncrounous_transfer.arm_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer | 7| +|710 | \asyncrounous_transfer.arm_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_306 | 7| +|711 | \asyncrounous_transfer.halt_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer_307 | 7| +|712 | \asyncrounous_transfer.halt_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_308 | 6| +|713 | halt_detection_inst |ltlib_v1_0_0_rising_edge_detection_309 | 6| +|714 | u_trig |ila_v6_2_9_ila_trigger | 1341| +|715 | \N_DDR_TC.N_DDR_TC_INST[0].U_TC |ltlib_v1_0_0_match | 19| +|716 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_301 | 18| +|717 | DUT |ltlib_v1_0_0_all_typeA_302 | 18| +|718 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_303 | 5| +|719 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_304 | 5| +|720 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_305 | 6| +|721 | \N_DDR_TC.N_DDR_TC_INST[10].U_TC |ltlib_v1_0_0_match_0 | 19| +|722 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_296 | 18| +|723 | DUT |ltlib_v1_0_0_all_typeA_297 | 18| +|724 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_298 | 5| +|725 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_299 | 5| +|726 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_300 | 6| +|727 | \N_DDR_TC.N_DDR_TC_INST[11].U_TC |ltlib_v1_0_0_match_1 | 19| +|728 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_291 | 18| +|729 | DUT |ltlib_v1_0_0_all_typeA_292 | 18| +|730 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_293 | 5| +|731 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_294 | 5| +|732 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_295 | 6| +|733 | \N_DDR_TC.N_DDR_TC_INST[12].U_TC |ltlib_v1_0_0_match_2 | 19| +|734 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_286 | 18| +|735 | DUT |ltlib_v1_0_0_all_typeA_287 | 18| +|736 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_288 | 5| +|737 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_289 | 5| +|738 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_290 | 6| +|739 | \N_DDR_TC.N_DDR_TC_INST[13].U_TC |ltlib_v1_0_0_match_3 | 19| +|740 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_281 | 18| +|741 | DUT |ltlib_v1_0_0_all_typeA_282 | 18| +|742 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_283 | 5| +|743 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_284 | 5| +|744 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_285 | 6| +|745 | \N_DDR_TC.N_DDR_TC_INST[14].U_TC |ltlib_v1_0_0_match_4 | 19| +|746 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_276 | 18| +|747 | DUT |ltlib_v1_0_0_all_typeA_277 | 18| +|748 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_278 | 5| +|749 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_279 | 5| +|750 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_280 | 6| +|751 | \N_DDR_TC.N_DDR_TC_INST[15].U_TC |ltlib_v1_0_0_match_5 | 19| +|752 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_271 | 18| +|753 | DUT |ltlib_v1_0_0_all_typeA_272 | 18| +|754 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_273 | 5| +|755 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_274 | 5| +|756 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_275 | 6| +|757 | \N_DDR_TC.N_DDR_TC_INST[16].U_TC |ltlib_v1_0_0_match_6 | 19| +|758 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_266 | 18| +|759 | DUT |ltlib_v1_0_0_all_typeA_267 | 18| +|760 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_268 | 5| +|761 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_269 | 5| +|762 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_270 | 6| +|763 | \N_DDR_TC.N_DDR_TC_INST[17].U_TC |ltlib_v1_0_0_match_7 | 19| +|764 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_261 | 18| +|765 | DUT |ltlib_v1_0_0_all_typeA_262 | 18| +|766 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_263 | 5| +|767 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_264 | 5| +|768 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_265 | 6| +|769 | \N_DDR_TC.N_DDR_TC_INST[18].U_TC |ltlib_v1_0_0_match_8 | 19| +|770 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_256 | 18| +|771 | DUT |ltlib_v1_0_0_all_typeA_257 | 18| +|772 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_258 | 5| +|773 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_259 | 5| +|774 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_260 | 6| +|775 | \N_DDR_TC.N_DDR_TC_INST[19].U_TC |ltlib_v1_0_0_match_9 | 19| +|776 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_251 | 18| +|777 | DUT |ltlib_v1_0_0_all_typeA_252 | 18| +|778 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_253 | 5| +|779 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_254 | 5| +|780 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_255 | 6| +|781 | \N_DDR_TC.N_DDR_TC_INST[1].U_TC |ltlib_v1_0_0_match_10 | 19| +|782 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_246 | 18| +|783 | DUT |ltlib_v1_0_0_all_typeA_247 | 18| +|784 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_248 | 5| +|785 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_249 | 5| +|786 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_250 | 6| +|787 | \N_DDR_TC.N_DDR_TC_INST[20].U_TC |ltlib_v1_0_0_match_11 | 19| +|788 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_241 | 18| +|789 | DUT |ltlib_v1_0_0_all_typeA_242 | 18| +|790 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_243 | 5| +|791 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_244 | 5| +|792 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_245 | 6| +|793 | \N_DDR_TC.N_DDR_TC_INST[21].U_TC |ltlib_v1_0_0_match_12 | 19| +|794 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_236 | 18| +|795 | DUT |ltlib_v1_0_0_all_typeA_237 | 18| +|796 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_238 | 5| +|797 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_239 | 5| +|798 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_240 | 6| +|799 | \N_DDR_TC.N_DDR_TC_INST[22].U_TC |ltlib_v1_0_0_match_13 | 19| +|800 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_231 | 18| +|801 | DUT |ltlib_v1_0_0_all_typeA_232 | 18| +|802 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_233 | 5| +|803 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_234 | 5| +|804 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_235 | 6| +|805 | \N_DDR_TC.N_DDR_TC_INST[23].U_TC |ltlib_v1_0_0_match_14 | 19| +|806 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_226 | 18| +|807 | DUT |ltlib_v1_0_0_all_typeA_227 | 18| +|808 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_228 | 5| +|809 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_229 | 5| +|810 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_230 | 6| +|811 | \N_DDR_TC.N_DDR_TC_INST[24].U_TC |ltlib_v1_0_0_match_15 | 19| +|812 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_221 | 18| +|813 | DUT |ltlib_v1_0_0_all_typeA_222 | 18| +|814 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_223 | 5| +|815 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_224 | 5| +|816 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_225 | 6| +|817 | \N_DDR_TC.N_DDR_TC_INST[25].U_TC |ltlib_v1_0_0_match_16 | 19| +|818 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_216 | 18| +|819 | DUT |ltlib_v1_0_0_all_typeA_217 | 18| +|820 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_218 | 5| +|821 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_219 | 5| +|822 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_220 | 6| +|823 | \N_DDR_TC.N_DDR_TC_INST[26].U_TC |ltlib_v1_0_0_match_17 | 19| +|824 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_211 | 18| +|825 | DUT |ltlib_v1_0_0_all_typeA_212 | 18| +|826 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_213 | 5| +|827 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_214 | 5| +|828 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_215 | 6| +|829 | \N_DDR_TC.N_DDR_TC_INST[27].U_TC |ltlib_v1_0_0_match_18 | 19| +|830 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_206 | 18| +|831 | DUT |ltlib_v1_0_0_all_typeA_207 | 18| +|832 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_208 | 5| +|833 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_209 | 5| +|834 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_210 | 6| +|835 | \N_DDR_TC.N_DDR_TC_INST[28].U_TC |ltlib_v1_0_0_match_19 | 19| +|836 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_201 | 18| +|837 | DUT |ltlib_v1_0_0_all_typeA_202 | 18| +|838 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_203 | 5| +|839 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_204 | 5| +|840 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_205 | 6| +|841 | \N_DDR_TC.N_DDR_TC_INST[29].U_TC |ltlib_v1_0_0_match_20 | 19| +|842 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_196 | 18| +|843 | DUT |ltlib_v1_0_0_all_typeA_197 | 18| +|844 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_198 | 5| +|845 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_199 | 5| +|846 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_200 | 6| +|847 | \N_DDR_TC.N_DDR_TC_INST[2].U_TC |ltlib_v1_0_0_match_21 | 19| +|848 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_191 | 18| +|849 | DUT |ltlib_v1_0_0_all_typeA_192 | 18| +|850 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_193 | 5| +|851 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_194 | 5| +|852 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_195 | 6| +|853 | \N_DDR_TC.N_DDR_TC_INST[30].U_TC |ltlib_v1_0_0_match_22 | 19| +|854 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_186 | 18| +|855 | DUT |ltlib_v1_0_0_all_typeA_187 | 18| +|856 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_188 | 5| +|857 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_189 | 5| +|858 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_190 | 6| +|859 | \N_DDR_TC.N_DDR_TC_INST[31].U_TC |ltlib_v1_0_0_match_23 | 19| +|860 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_181 | 18| +|861 | DUT |ltlib_v1_0_0_all_typeA_182 | 18| +|862 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_183 | 5| +|863 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_184 | 5| +|864 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_185 | 6| +|865 | \N_DDR_TC.N_DDR_TC_INST[3].U_TC |ltlib_v1_0_0_match_24 | 19| +|866 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_176 | 18| +|867 | DUT |ltlib_v1_0_0_all_typeA_177 | 18| +|868 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_178 | 5| +|869 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_179 | 5| +|870 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_180 | 6| +|871 | \N_DDR_TC.N_DDR_TC_INST[4].U_TC |ltlib_v1_0_0_match_25 | 19| +|872 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_171 | 18| +|873 | DUT |ltlib_v1_0_0_all_typeA_172 | 18| +|874 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_173 | 5| +|875 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_174 | 5| +|876 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_175 | 6| +|877 | \N_DDR_TC.N_DDR_TC_INST[5].U_TC |ltlib_v1_0_0_match_26 | 19| +|878 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_166 | 18| +|879 | DUT |ltlib_v1_0_0_all_typeA_167 | 18| +|880 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_168 | 5| +|881 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_169 | 5| +|882 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_170 | 6| +|883 | \N_DDR_TC.N_DDR_TC_INST[6].U_TC |ltlib_v1_0_0_match_27 | 19| +|884 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_161 | 18| +|885 | DUT |ltlib_v1_0_0_all_typeA_162 | 18| +|886 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_163 | 5| +|887 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_164 | 5| +|888 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_165 | 6| +|889 | \N_DDR_TC.N_DDR_TC_INST[7].U_TC |ltlib_v1_0_0_match_28 | 19| +|890 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_156 | 18| +|891 | DUT |ltlib_v1_0_0_all_typeA_157 | 18| +|892 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_158 | 5| +|893 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_159 | 5| +|894 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_160 | 6| +|895 | \N_DDR_TC.N_DDR_TC_INST[8].U_TC |ltlib_v1_0_0_match_29 | 19| +|896 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_151 | 18| +|897 | DUT |ltlib_v1_0_0_all_typeA_152 | 18| +|898 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_153 | 5| +|899 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_154 | 5| +|900 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_155 | 6| +|901 | \N_DDR_TC.N_DDR_TC_INST[9].U_TC |ltlib_v1_0_0_match_30 | 19| +|902 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_146 | 18| +|903 | DUT |ltlib_v1_0_0_all_typeA_147 | 18| +|904 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_148 | 5| +|905 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_149 | 5| +|906 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_150 | 6| +|907 | \STRG_QUAL.U_STRG_QUAL |ltlib_v1_0_0_match_31 | 43| +|908 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA | 42| +|909 | DUT |ltlib_v1_0_0_all_typeA | 18| +|910 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_143 | 5| +|911 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_144 | 5| +|912 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_145 | 6| +|913 | U_TM |ila_v6_2_9_ila_trig_match | 642| +|914 | \N_DDR_MODE.G_NMU[0].U_M |ltlib_v1_0_0_match__parameterized0 | 38| +|915 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_139 | 37| +|916 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_140 | 13| +|917 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_141 | 5| +|918 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_142 | 6| +|919 | \N_DDR_MODE.G_NMU[10].U_M |ltlib_v1_0_0_match__parameterized0_32 | 38| +|920 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_135 | 37| +|921 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_136 | 13| +|922 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_137 | 5| +|923 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_138 | 6| +|924 | \N_DDR_MODE.G_NMU[11].U_M |ltlib_v1_0_0_match__parameterized0_33 | 14| +|925 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_131 | 13| +|926 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_132 | 13| +|927 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_133 | 5| +|928 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_134 | 6| +|929 | \N_DDR_MODE.G_NMU[12].U_M |ltlib_v1_0_0_match__parameterized0_34 | 38| +|930 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_127 | 37| +|931 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_128 | 13| +|932 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_129 | 5| +|933 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_130 | 6| +|934 | \N_DDR_MODE.G_NMU[13].U_M |ltlib_v1_0_0_match__parameterized0_35 | 14| +|935 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_123 | 13| +|936 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_124 | 13| +|937 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_125 | 5| +|938 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_126 | 6| +|939 | \N_DDR_MODE.G_NMU[14].U_M |ltlib_v1_0_0_match__parameterized0_36 | 38| +|940 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_119 | 37| +|941 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_120 | 13| +|942 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_121 | 5| +|943 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_122 | 6| +|944 | \N_DDR_MODE.G_NMU[15].U_M |ltlib_v1_0_0_match__parameterized0_37 | 14| +|945 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_115 | 13| +|946 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_116 | 13| +|947 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_117 | 5| +|948 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_118 | 6| +|949 | \N_DDR_MODE.G_NMU[16].U_M |ltlib_v1_0_0_match__parameterized0_38 | 38| +|950 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_111 | 37| +|951 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_112 | 13| +|952 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_113 | 5| +|953 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_114 | 6| +|954 | \N_DDR_MODE.G_NMU[17].U_M |ltlib_v1_0_0_match__parameterized0_39 | 14| +|955 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_107 | 13| +|956 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_108 | 13| +|957 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_109 | 5| +|958 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_110 | 6| +|959 | \N_DDR_MODE.G_NMU[18].U_M |ltlib_v1_0_0_match__parameterized1 | 40| +|960 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_103 | 39| +|961 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_104 | 13| +|962 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_105 | 5| +|963 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_106 | 6| +|964 | \N_DDR_MODE.G_NMU[19].U_M |ltlib_v1_0_0_match__parameterized1_40 | 14| +|965 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1 | 13| +|966 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_100 | 13| +|967 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_101 | 5| +|968 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_102 | 6| +|969 | \N_DDR_MODE.G_NMU[1].U_M |ltlib_v1_0_0_match__parameterized0_41 | 14| +|970 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_96 | 13| +|971 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_97 | 13| +|972 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_98 | 5| +|973 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_99 | 6| +|974 | \N_DDR_MODE.G_NMU[20].U_M |ltlib_v1_0_0_match__parameterized2 | 46| +|975 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_92 | 45| +|976 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_93 | 13| +|977 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_94 | 5| +|978 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_95 | 6| +|979 | \N_DDR_MODE.G_NMU[21].U_M |ltlib_v1_0_0_match__parameterized2_42 | 14| +|980 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_88 | 13| +|981 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_89 | 13| +|982 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_90 | 5| +|983 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_91 | 6| +|984 | \N_DDR_MODE.G_NMU[22].U_M |ltlib_v1_0_0_match__parameterized2_43 | 46| +|985 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_84 | 45| +|986 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_85 | 13| +|987 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_86 | 5| +|988 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_87 | 6| +|989 | \N_DDR_MODE.G_NMU[23].U_M |ltlib_v1_0_0_match__parameterized2_44 | 14| +|990 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2 | 13| +|991 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_81 | 13| +|992 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_82 | 5| +|993 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_83 | 6| +|994 | \N_DDR_MODE.G_NMU[2].U_M |ltlib_v1_0_0_match__parameterized0_45 | 38| +|995 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_77 | 37| +|996 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_78 | 13| +|997 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_79 | 5| +|998 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_80 | 6| +|999 | \N_DDR_MODE.G_NMU[3].U_M |ltlib_v1_0_0_match__parameterized0_46 | 14| +|1000 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_73 | 13| +|1001 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_74 | 13| +|1002 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_75 | 5| +|1003 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_76 | 6| +|1004 | \N_DDR_MODE.G_NMU[4].U_M |ltlib_v1_0_0_match__parameterized0_47 | 38| +|1005 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_69 | 37| +|1006 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_70 | 13| +|1007 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_71 | 5| +|1008 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_72 | 6| +|1009 | \N_DDR_MODE.G_NMU[5].U_M |ltlib_v1_0_0_match__parameterized0_48 | 14| +|1010 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_65 | 13| +|1011 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_66 | 13| +|1012 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_67 | 5| +|1013 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_68 | 6| +|1014 | \N_DDR_MODE.G_NMU[6].U_M |ltlib_v1_0_0_match__parameterized0_49 | 38| +|1015 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_61 | 37| +|1016 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_62 | 13| +|1017 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_63 | 5| +|1018 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_64 | 6| +|1019 | \N_DDR_MODE.G_NMU[7].U_M |ltlib_v1_0_0_match__parameterized0_50 | 14| +|1020 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_57 | 13| +|1021 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_58 | 13| +|1022 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_59 | 5| +|1023 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_60 | 6| +|1024 | \N_DDR_MODE.G_NMU[8].U_M |ltlib_v1_0_0_match__parameterized0_51 | 38| +|1025 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_53 | 37| +|1026 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_54 | 13| +|1027 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_55 | 5| +|1028 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_56 | 6| +|1029 | \N_DDR_MODE.G_NMU[9].U_M |ltlib_v1_0_0_match__parameterized0_52 | 14| +|1030 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0 | 13| +|1031 | DUT |ltlib_v1_0_0_all_typeA__parameterized0 | 13| +|1032 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice | 5| +|1033 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0 | 6| +|1034 | xsdb_memory_read_inst |ltlib_v1_0_0_generic_memrd | 909| +------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:01:41 ; elapsed = 00:01:54 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 468 ; free virtual = 47484 +Finished Writing Synthesis Report : Time (s): cpu = 00:01:55 ; elapsed = 00:02:08 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1565 ; free virtual = 56775 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 9118 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:01:37 ; elapsed = 00:01:50 . Memory (MB): peak = 2440.000 ; gain = 621.859 ; free physical = 521 ; free virtual = 47537 -Synthesis Optimization Complete : Time (s): cpu = 00:01:41 ; elapsed = 00:01:54 . Memory (MB): peak = 2440.000 ; gain = 714.703 ; free physical = 536 ; free virtual = 47552 +Synthesis finished with 0 errors, 0 critical warnings and 11038 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:51 ; elapsed = 00:02:03 . Memory (MB): peak = 2461.820 ; gain = 657.648 ; free physical = 1612 ; free virtual = 56824 +Synthesis Optimization Complete : Time (s): cpu = 00:01:55 ; elapsed = 00:02:08 . Memory (MB): peak = 2461.820 ; gain = 736.523 ; free physical = 1631 ; free virtual = 56843 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 1603 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 1823 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2440.000 ; gain = 0.000 ; free physical = 433 ; free virtual = 47452 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2461.820 ; gain = 0.000 ; free physical = 1496 ; free virtual = 56638 INFO: [Project 1-111] Unisim Transformation Summary: - A total of 668 instances were transformed. - CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 580 instances - CFGLUT5 => SRLC32E: 56 instances + A total of 704 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 612 instances + CFGLUT5 => SRLC32E: 60 instances RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 32 instances INFO: [Common 17-83] Releasing license: Synthesis -351 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. +364 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:01:45 ; elapsed = 00:01:58 . Memory (MB): peak = 2440.000 ; gain = 1028.543 ; free physical = 542 ; free virtual = 47561 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2440.000 ; gain = 0.000 ; free physical = 542 ; free virtual = 47561 +synth_design: Time (s): cpu = 00:02:00 ; elapsed = 00:02:12 . Memory (MB): peak = 2461.820 ; gain = 1050.363 ; free physical = 1620 ; free virtual = 56763 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2461.820 ; gain = 0.000 ; free physical = 1620 ; free virtual = 56763 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ila_rx_data_cnt, cache-ID = 01624a603582da4f -INFO: [Coretcl 2-1174] Renamed 889 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2464.012 ; gain = 0.000 ; free physical = 524 ; free virtual = 47583 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ila_rx_data_cnt, cache-ID = 01859ea3ec989a3b +INFO: [Coretcl 2-1174] Renamed 1033 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2485.832 ; gain = 0.000 ; free physical = 1579 ; free virtual = 56756 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file ila_rx_data_cnt_utilization_synth.rpt -pb ila_rx_data_cnt_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri May 12 10:13:06 2023... +INFO: [Common 17-206] Exiting Vivado at Tue May 16 20:23:20 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v index fb313b71..4ecb89b9 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:58fe8062145bd2d6b613764a172659ba526a33aed3a141d3deff1768e66ca912 -size 9313139 +oid sha256:e3d21e4075a7c3018ed37d668e390b9c0c0c95d8520271d9d365486e3b8f6305 +size 11127106 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl index 9fae400f..18a1fef2 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3b8c280982b4ebec4e143f0808389c05ec04ca3442de015f049e1b5ac5bfb1e9 -size 11855995 +oid sha256:b3b3d36e9b714a32cf40e2e7a2e08a8c6688d30d5ee593a9a7217bd3c8fa4486 +size 13855799 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v index 361f5c14..fb77bcdd 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Fri May 12 10:13:05 2023 +// Date : Tue May 16 20:23:18 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v @@ -15,8 +15,8 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "ila,Vivado 2019.1.3" *) module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, - probe6, probe7, probe8, probe9) -/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]" */; + probe6, probe7, probe8, probe9, probe10, probe11) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0],probe10[15:0],probe11[15:0]" */; input clk; input [11:0]probe0; input [11:0]probe1; @@ -28,4 +28,6 @@ module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, input [11:0]probe7; input [11:0]probe8; input [12:0]probe9; + input [15:0]probe10; + input [15:0]probe11; endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl index 33c61727..1b0b11d2 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Fri May 12 10:13:05 2023 +-- Date : Tue May 16 20:23:18 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl @@ -24,7 +24,9 @@ entity ila_rx_data_cnt is probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 ); probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 ); probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 ); - probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 ) + probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); end ila_rx_data_cnt; @@ -33,7 +35,7 @@ architecture stub of ila_rx_data_cnt is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0],probe10[15:0],probe11[15:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; begin diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.pb index fb1de642..d828c228 100644 Binary files a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.pb and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.rpt index c3b3073d..d2ce8f39 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.rpt +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Fri May 12 10:13:05 2023 +| Date : Tue May 16 20:23:18 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file ila_rx_data_cnt_utilization_synth.rpt -pb ila_rx_data_cnt_utilization_synth.pb | Design : ila_rx_data_cnt @@ -30,16 +30,16 @@ Table of Contents +----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 4197 | 0 | 277400 | 1.51 | -| LUT as Logic | 3285 | 0 | 277400 | 1.18 | -| LUT as Memory | 912 | 0 | 108200 | 0.84 | +| Slice LUTs* | 4701 | 0 | 277400 | 1.69 | +| LUT as Logic | 3721 | 0 | 277400 | 1.34 | +| LUT as Memory | 980 | 0 | 108200 | 0.91 | | LUT as Distributed RAM | 128 | 0 | | | -| LUT as Shift Register | 784 | 0 | | | -| Slice Registers | 4636 | 0 | 554800 | 0.84 | -| Register as Flip Flop | 4636 | 0 | 554800 | 0.84 | +| LUT as Shift Register | 852 | 0 | | | +| Slice Registers | 5087 | 0 | 554800 | 0.92 | +| Register as Flip Flop | 5087 | 0 | 554800 | 0.92 | | Register as Latch | 0 | 0 | 554800 | 0.00 | -| F7 Muxes | 369 | 0 | 138700 | 0.27 | -| F8 Muxes | 119 | 0 | 69350 | 0.17 | +| F7 Muxes | 449 | 0 | 138700 | 0.32 | +| F8 Muxes | 155 | 0 | 69350 | 0.22 | +----------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -59,7 +59,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 9 | Yes | Set | - | -| 4627 | Yes | Reset | - | +| 5078 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -69,9 +69,9 @@ Table of Contents +-------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 218 | 0 | 755 | 28.87 | -| RAMB36/FIFO* | 218 | 0 | 755 | 28.87 | -| RAMB36E1 only | 218 | | | | +| Block RAM Tile | 274 | 0 | 755 | 36.29 | +| RAMB36/FIFO* | 274 | 0 | 755 | 36.29 | +| RAMB36E1 only | 274 | | | | | RAMB18 | 0 | 0 | 1510 | 0.00 | +-------------------+------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 @@ -155,20 +155,20 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 4627 | Flop & Latch | -| LUT6 | 2079 | LUT | -| SRL16E | 709 | Distributed Memory | -| SRLC32E | 653 | Distributed Memory | -| LUT4 | 569 | LUT | -| LUT3 | 420 | LUT | -| MUXF7 | 369 | MuxFx | +| FDRE | 5078 | Flop & Latch | +| LUT6 | 2662 | LUT | +| SRL16E | 773 | Distributed Memory | +| SRLC32E | 689 | Distributed Memory | +| LUT4 | 596 | LUT | +| MUXF7 | 449 | MuxFx | +| RAMB36E1 | 274 | Block Memory | | LUT5 | 267 | LUT | -| CARRY4 | 229 | CarryLogic | -| RAMB36E1 | 218 | Block Memory | -| LUT2 | 130 | LUT | +| LUT3 | 262 | LUT | +| CARRY4 | 241 | CarryLogic | +| LUT2 | 172 | LUT | +| MUXF8 | 155 | MuxFx | | RAMD64E | 128 | Distributed Memory | -| MUXF8 | 119 | MuxFx | -| LUT1 | 90 | LUT | +| LUT1 | 93 | LUT | | FDSE | 9 | Flop & Latch | | SRLC16E | 2 | Distributed Memory | +----------+------+---------------------+ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/project.wdf index e5fa4bfc..4aa0f06f 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/project.wdf +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/project.wdf @@ -1,5 +1,5 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:39:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3131:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 @@ -13,6 +13,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31325f3132:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31327838:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f72785f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f7072627331305f696e766572745f72657032:636f72655f636f6e7461696e6572:74727565:00:00 @@ -34,12 +35,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3336:00:00 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a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.pb index 1d219822..d99ab812 100644 Binary files a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.pb and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml index e8981890..ea071426 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml @@ -1,9 +1,9 @@ + - diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst similarity index 75% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.vivado.begin.rst rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst index 5ead3798..b575a51a 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/.vivado.begin.rst +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/ISEWrap.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/ISEWrap.js similarity index 100% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/ISEWrap.js rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/ISEWrap.js diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/ISEWrap.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/ISEWrap.sh similarity index 100% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/ISEWrap.sh rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/ISEWrap.sh diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml similarity index 53% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/gen_run.xml rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml index c8e7e69f..ac3205ac 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml @@ -1,20 +1,23 @@ - - - - - - - - - + + + + + + + + + + + + - + @@ -22,19 +25,19 @@ - - - + + - + @@ -42,7 +45,7 @@ - @@ -53,7 +56,9 @@ - + + Vivado Synthesis Defaults + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/htr.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/htr.txt similarity index 65% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/htr.txt rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/htr.txt index 9b4f26c4..f95bba05 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/htr.txt +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/htr.txt @@ -6,4 +6,4 @@ # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -vivado -log fir_prbs7_invert_rep2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs7_invert_rep2.tcl +vivado -log vio_phase_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf similarity index 76% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/project.wdf rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf index d724c79c..61c91402 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/project.wdf +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf @@ -1,28 +1,33 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3131:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 @@ -31,12 +36,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3230:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3339:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3339:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3339:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3339:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3339:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3339:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 -eof:516242679 +eof:3995696185 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/rundef.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/rundef.js similarity index 89% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/rundef.js rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/rundef.js index 058585ea..3c1ce4c0 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/rundef.js +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/rundef.js @@ -27,7 +27,7 @@ eval( EAInclude(ISEJScriptLib) ); ISEStep( "vivado", - "-log fir_prbs7_invert_rep2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs7_invert_rep2.tcl" ); + "-log vio_phase_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl" ); diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.bat b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/runme.bat similarity index 100% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.bat rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/runme.bat diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/runme.sh similarity index 77% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.sh rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/runme.sh index c7d8f5ad..d00547c8 100755 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/runme.sh +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/runme.sh @@ -20,7 +20,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1' +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1' cd "$HD_PWD" HD_LOG=runme.log @@ -36,4 +36,4 @@ EAStep() fi } -EAStep vivado -log fir_prbs7_invert_rep2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs7_invert_rep2.tcl +EAStep vivado -log vio_phase_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp new file mode 100644 index 00000000..45ec0ebe --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d9c0a3e77196533973097fd2831652b2317307d717a408a8da032a94a2731e18 +size 161557 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl similarity index 60% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.tcl rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl index 1d47e291..3facfe97 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.tcl +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl @@ -34,9 +34,9 @@ set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/constraints/fir_compiler_v7_2.xdc] -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2_ooc.xdc] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp_ooc.xdc] # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -46,16 +46,14 @@ set_property used_in_implementation false [get_files -all /home/josh/Workspace/v foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { set_property used_in_implementation false $dcp } -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1 -new_name fir_prbs7_invert_rep2 -ip [get_ips fir_prbs7_invert_rep2]] +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1 -new_name vio_phase_comp -ip [get_ips vio_phase_comp]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] -synth_design -top fir_prbs7_invert_rep2 -part xc7z100ffg900-2 -mode out_of_context +synth_design -top vio_phase_comp -part xc7z100ffg900-2 -mode out_of_context #--------------------------------------------------------- # Generate Checkpoint/Stub/Simulation Files For IP Cache @@ -64,52 +62,52 @@ synth_design -top fir_prbs7_invert_rep2 -part xc7z100ffg900-2 -mode out_of_conte set_param constraints.enableBinaryConstraints false catch { - write_checkpoint -force -noxdef -rename_prefix fir_prbs7_invert_rep2_ fir_prbs7_invert_rep2.dcp + write_checkpoint -force -noxdef -rename_prefix vio_phase_comp_ vio_phase_comp.dcp set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep2_stub.v - lappend ipCachedFiles fir_prbs7_invert_rep2_stub.v + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v + lappend ipCachedFiles vio_phase_comp_stub.v - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep2_stub.vhdl - lappend ipCachedFiles fir_prbs7_invert_rep2_stub.vhdl + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl + lappend ipCachedFiles vio_phase_comp_stub.vhdl - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep2_sim_netlist.v - lappend ipCachedFiles fir_prbs7_invert_rep2_sim_netlist.v + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_sim_netlist.v + lappend ipCachedFiles vio_phase_comp_sim_netlist.v - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs7_invert_rep2_sim_netlist.vhdl - lappend ipCachedFiles fir_prbs7_invert_rep2_sim_netlist.vhdl + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_sim_netlist.vhdl + lappend ipCachedFiles vio_phase_comp_sim_netlist.vhdl set TIME_taken [expr [clock seconds] - $TIME_start] - config_ip_cache -add -dcp fir_prbs7_invert_rep2.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips fir_prbs7_invert_rep2] + config_ip_cache -add -dcp vio_phase_comp.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_phase_comp] } -rename_ref -prefix_all fir_prbs7_invert_rep2_ +rename_ref -prefix_all vio_phase_comp_ # disable binary constraint mode for synth run checkpoints set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef fir_prbs7_invert_rep2.dcp -create_report "fir_prbs7_invert_rep2_synth_1_synth_report_utilization_0" "report_utilization -file fir_prbs7_invert_rep2_utilization_synth.rpt -pb fir_prbs7_invert_rep2_utilization_synth.pb" +write_checkpoint -force -noxdef vio_phase_comp.dcp +create_report "vio_phase_comp_synth_1_synth_report_utilization_0" "report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb" if { [catch { - write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -120,37 +118,37 @@ if { [catch { }; # end if cached_ip -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fir_prbs7_invert_rep2/fir_prbs7_invert_rep2.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xci] -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2 + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2 + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2 + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs7_invert_rep2 + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_phase_comp } } file delete __synthesis_is_running__ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds new file mode 100644 index 00000000..ed7a6730 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds @@ -0,0 +1,564 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Tue May 16 20:22:07 2023 +# Process ID: 834515 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1 +# Command line: vivado -log vio_phase_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.jou +#----------------------------------------------------------- +source vio_phase_comp.tcl -notrace +Command: synth_design -top vio_phase_comp -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 834603 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.477 ; gain = 153.688 ; free physical = 725 ; free virtual = 56023 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'vio_phase_comp' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/synth/vio_phase_comp.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_phase_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/synth/vio_phase_comp.v:88] +INFO: [Synth 8-6155] done synthesizing module 'vio_phase_comp' (8#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/synth/vio_phase_comp.v:59] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_in_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in36[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in37[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in38[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in39[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in40[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in41[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in42[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in43[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in44[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in45[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in46[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in47[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in48[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in49[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in50[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in51[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in52[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in53[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in54[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in55[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in56[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in57[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in58[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in59[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in60[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in61[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in62[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in63[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in64[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in65[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in66[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in67[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in68[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in69[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in70[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in71[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in72[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in73[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in74[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in75[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in76[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in77[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in78[0] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1922.164 ; gain = 215.375 ; free physical = 795 ; free virtual = 56036 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1926.133 ; gain = 219.344 ; free physical = 784 ; free virtual = 56024 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1926.133 ; gain = 219.344 ; free physical = 784 ; free virtual = 56024 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.789 ; gain = 0.000 ; free physical = 700 ; free virtual = 55909 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2111.727 ; gain = 5.938 ; free physical = 699 ; free virtual = 55908 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 776 ; free virtual = 55985 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 776 ; free virtual = 55985 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 776 ; free virtual = 55985 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 770 ; free virtual = 55981 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 15 + 12 Bit Registers := 9 + 7 Bit Registers := 1 + 5 Bit Registers := 2 + 4 Bit Registers := 1 + 3 Bit Registers := 4 + 1 Bit Registers := 28 ++---Muxes : + 2 Input 16 Bit Muxes := 2 + 5 Input 12 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 16 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module vio_v3_0_20_probe_in_one +Detailed RTL Component Info : ++---Registers : + 3 Bit Registers := 1 + 1 Bit Registers := 7 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 12 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 5 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_all +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 1 + 1 Bit Registers := 11 ++---Muxes : + 2 Input 1 Bit Muxes := 2 +Module vio_v3_0_20_probe_width +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 12 Bit Registers := 1 + 3 Bit Registers := 1 ++---Muxes : + 5 Input 12 Bit Muxes := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_decoder +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 3 Bit Registers := 2 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module vio_v3_0_20_vio +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[1]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[2]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[10] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[12]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[13]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[14]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 751 ; free virtual = 55966 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 707 ; free virtual = 55865 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 707 ; free virtual = 55865 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 706 ; free virtual = 55857 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 724 ; free virtual = 55867 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 723 ; free virtual = 55867 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 723 ; free virtual = 55867 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 723 ; free virtual = 55867 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 723 ; free virtual = 55867 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 723 ; free virtual = 55867 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |LUT1 | 2| +|2 |LUT2 | 9| +|3 |LUT3 | 27| +|4 |LUT4 | 8| +|5 |LUT5 | 28| +|6 |LUT6 | 95| +|7 |MUXF7 | 7| +|8 |FDRE | 468| ++------+------+------+ + +Report Instance Areas: ++------+---------------------------------------+------------------------------------------+------+ +| |Instance |Module |Cells | ++------+---------------------------------------+------------------------------------------+------+ +|1 |top | | 644| +|2 | inst |vio_v3_0_20_vio | 644| +|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| +|4 | DECODER_INST |vio_v3_0_20_decoder | 81| +|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 14| +|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 275| +|7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 24| +|8 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 24| +|9 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 24| +|10 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 24| +|11 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_3 | 24| +|12 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_4 | 24| +|13 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_5 | 24| +|14 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_6 | 24| +|15 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 10| +|16 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 10| ++------+---------------------------------------+------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 723 ; free virtual = 55867 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 292 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2111.727 ; gain = 219.344 ; free physical = 774 ; free virtual = 55918 +Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2111.727 ; gain = 404.938 ; free physical = 787 ; free virtual = 55931 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2111.727 ; gain = 0.000 ; free physical = 706 ; free virtual = 55849 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +75 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2111.727 ; gain = 712.809 ; free physical = 799 ; free virtual = 55943 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2111.727 ; gain = 0.000 ; free physical = 799 ; free virtual = 55943 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_phase_comp, cache-ID = dbab88f54d36bef1 +INFO: [Coretcl 2-1174] Renamed 15 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2135.738 ; gain = 0.000 ; free physical = 794 ; free virtual = 55941 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Tue May 16 20:22:24 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v new file mode 100644 index 00000000..2b9397b2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8a728b012261b1286ce2ddcfedc2eecde9e96f716da1a2094500d54e679c5dd3 +size 380163 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl new file mode 100644 index 00000000..ad53fde5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:62b0acda5c13e66909336af54eb0f6e79069e5c29116db14c7adc72123650fd9 +size 674599 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v new file mode 100644 index 00000000..0ed89469 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Tue May 16 20:22:24 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v +// Design : vio_phase_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_phase_comp(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[11:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[4:0]" */; + input clk; + input [0:0]probe_in0; + output [11:0]probe_out0; + output [11:0]probe_out1; + output [11:0]probe_out2; + output [11:0]probe_out3; + output [11:0]probe_out4; + output [11:0]probe_out5; + output [11:0]probe_out6; + output [11:0]probe_out7; + output [4:0]probe_out8; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl new file mode 100644 index 00000000..f86dcd1a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Tue May 16 20:22:24 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl +-- Design : vio_phase_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_phase_comp is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + +end vio_phase_comp; + +architecture stub of vio_phase_comp is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[11:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[4:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb new file mode 100644 index 00000000..62c2af9d Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt similarity index 71% rename from projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.rpt rename to projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt index 30fb7b03..d2b81e9a 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_utilization_synth.rpt +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Mon May 8 19:43:16 2023 +| Date : Tue May 16 20:22:24 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_utilization -file fir_prbs7_invert_rep2_utilization_synth.rpt -pb fir_prbs7_invert_rep2_utilization_synth.pb -| Design : fir_prbs7_invert_rep2 +| Command : report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb +| Design : vio_phase_comp | Device : 7z100ffg900-2 | Design State : Synthesized -------------------------------------------------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------------------------------- Utilization Design Information @@ -27,20 +27,18 @@ Table of Contents 1. Slice Logic -------------- -+----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 839 | 0 | 277400 | 0.30 | -| LUT as Logic | 48 | 0 | 277400 | 0.02 | -| LUT as Memory | 791 | 0 | 108200 | 0.73 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 791 | 0 | | | -| Slice Registers | 2802 | 0 | 554800 | 0.51 | -| Register as Flip Flop | 2802 | 0 | 554800 | 0.51 | -| Register as Latch | 0 | 0 | 554800 | 0.00 | -| F7 Muxes | 0 | 0 | 138700 | 0.00 | -| F8 Muxes | 0 | 0 | 69350 | 0.00 | -+----------------------------+------+-------+-----------+-------+ ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 149 | 0 | 277400 | 0.05 | +| LUT as Logic | 149 | 0 | 277400 | 0.05 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 468 | 0 | 554800 | 0.08 | +| Register as Flip Flop | 468 | 0 | 554800 | 0.08 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 7 | 0 | 138700 | <0.01 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -58,8 +56,8 @@ Table of Contents | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | -| 6 | Yes | Set | - | -| 2796 | Yes | Reset | - | +| 0 | Yes | Set | - | +| 468 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -79,12 +77,11 @@ Table of Contents 3. DSP ------ -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| DSPs | 65 | 0 | 2020 | 3.22 | -| DSP48E1 only | 65 | | | | -+----------------+------+-------+-----------+-------+ ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ 4. IO and GT Specific @@ -155,17 +152,14 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 2796 | Flop & Latch | -| SRL16E | 782 | Distributed Memory | -| DSP48E1 | 65 | Block Arithmetic | -| LUT1 | 21 | LUT | -| LUT3 | 14 | LUT | -| LUT2 | 10 | LUT | -| SRLC32E | 9 | Distributed Memory | -| LUT6 | 7 | LUT | -| LUT5 | 6 | LUT | -| FDSE | 6 | Flop & Latch | -| LUT4 | 4 | LUT | +| FDRE | 468 | Flop & Latch | +| LUT6 | 95 | LUT | +| LUT5 | 28 | LUT | +| LUT3 | 27 | LUT | +| LUT2 | 9 | LUT | +| LUT4 | 8 | LUT | +| MUXF7 | 7 | MuxFx | +| LUT1 | 2 | LUT | +----------+------+---------------------+ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb new file mode 100644 index 00000000..9e783d66 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml index b4b7986a..a328156d 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml @@ -1,8 +1,8 @@ - - + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr index f005e292..b00b5f24 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - @@ -367,6 +375,26 @@ + + + + + + + + + + + + + + + + + + @@ -464,15 +492,6 @@ - - - - - - - - - @@ -500,6 +519,17 @@ + + + + Vivado Synthesis Defaults + + + + + + + @@ -628,22 +658,6 @@ - - - - - - - - - - - - - - - - @@ -692,6 +706,24 @@ + + + + Default settings for Implementation. + + + + + + + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp.xcix b/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp.xcix new file mode 100644 index 00000000..9f32d763 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0ed8a8f9be958a75a11c4e03073d635f5f94eb793272fa393c6925352f513173 +size 735926 diff --git a/projects/duifei/duifei_online_acq_par/project.tcl b/projects/duifei/duifei_online_acq_par/project.tcl index df581da2..39239298 100644 --- a/projects/duifei/duifei_online_acq_par/project.tcl +++ b/projects/duifei/duifei_online_acq_par/project.tcl @@ -3,7 +3,7 @@ # # project.tcl: Tcl script for re-creating project 'project' # -# Generated by Vivado on Fri May 12 10:07:34 CST 2023 +# Generated by Vivado on Tue May 16 20:40:18 CST 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -27,6 +27,7 @@ # # 3. The following remote source files that were added to the original project:- # +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xci" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xci" # "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/vio_manual_ctrl/vio_manual_ctrl.xci" @@ -44,6 +45,7 @@ # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/cmpy_12x8/cmpy_12x8.xci" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fifo_rx_data/fifo_rx_data.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/cmpy_12_12/cmpy_12_12.xci" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" @@ -78,12 +80,14 @@ # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/freq_comp.v" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mgc_ctrl.v" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mod2_rom.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/phase_compensate.v" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/rx_dmf.v" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_master.v" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_salve.v" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_tx.v" # "/home/josh/Workspace/vivado-git/projects/duifei/common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/trunc_32bit_to_12bit.v" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/tx_pre_process.v" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/system_top.v" @@ -205,15 +209,15 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj set_property -name "target_simulator" -value "VCS" -objects $obj -set_property -name "webtalk.activehdl_export_sim" -value "55" -objects $obj -set_property -name "webtalk.ies_export_sim" -value "55" -objects $obj -set_property -name "webtalk.modelsim_export_sim" -value "55" -objects $obj -set_property -name "webtalk.questa_export_sim" -value "55" -objects $obj -set_property -name "webtalk.riviera_export_sim" -value "55" -objects $obj -set_property -name "webtalk.vcs_export_sim" -value "55" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "57" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "57" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "57" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "57" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "57" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "57" -objects $obj set_property -name "webtalk.vcs_launch_sim" -value "59" -objects $obj -set_property -name "webtalk.xcelium_export_sim" -value "3" -objects $obj -set_property -name "webtalk.xsim_export_sim" -value "55" -objects $obj +set_property -name "webtalk.xcelium_export_sim" -value "2" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "57" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj # Create 'sources_1' fileset (if not found) @@ -231,6 +235,7 @@ update_ip_catalog -rebuild # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ + [file normalize "${origin_dir}/ip/vio_phase_comp/vio_phase_comp.xci"] \ [file normalize "${origin_dir}/ip/ila_freq_comp/ila_freq_comp.xci"] \ [file normalize "${origin_dir}/ip/vio_freq_comp/vio_freq_comp.xci"] \ [file normalize "${origin_dir}/../common_ip/basic_driver/vio_manual_ctrl/vio_manual_ctrl.xci"] \ @@ -248,6 +253,7 @@ set files [list \ [file normalize "${origin_dir}/ip/cmpy_12x8/cmpy_12x8.xci"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"] \ [file normalize "${origin_dir}/ip/fifo_rx_data/fifo_rx_data.xci"] \ + [file normalize "${origin_dir}/ip/cmpy_12_12/cmpy_12_12.xci"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"] \ @@ -282,12 +288,14 @@ set files [list \ [file normalize "${origin_dir}/rtl/freq_comp.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/mgc_ctrl.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/mod2_rom.v"] \ + [file normalize "${origin_dir}/rtl/phase_compensate.v"] \ [file normalize "${origin_dir}/rtl/rf_auto_switch_freq.v"] \ [file normalize "${origin_dir}/rtl/rx_dmf.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/spi_master.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/spi_salve.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/spi_tx.v"] \ [file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v"] \ + [file normalize "${origin_dir}/rtl/trunc_32bit_to_12bit.v"] \ [file normalize "${origin_dir}/rtl/tx_pre_process.v"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \ [file normalize "${origin_dir}/rtl/system_top.v"] \ @@ -303,6 +311,15 @@ set files [list \ add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/ip/vio_phase_comp/vio_phase_comp.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + set file "$origin_dir/ip/ila_freq_comp/ila_freq_comp.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -456,6 +473,15 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } +set file "$origin_dir/ip/cmpy_12_12/cmpy_12_12.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + set file "$origin_dir/../../../modules/xc7z100ffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -630,8 +656,6 @@ set obj [get_filesets sim_1] set_property -name "top" -value "tb_freq_comp" -objects $obj set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj -set_property -name "vcs.compile.vlogan.more_options" -value "-kdb -v2005" -objects $obj -set_property -name "vcs.elaborate.vcs.more_options" -value "-debug_access+all" -objects $obj # Set 'utils_1' fileset object set obj [get_filesets utils_1] diff --git a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/debug_nets.ltx b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/debug_nets.ltx index 19426197..280eb0aa 100644 --- a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/debug_nets.ltx +++ b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/debug_nets.ltx @@ -2743,6 +2743,138 @@ ] } ] + }, + { + "name": "probe10", + "id": 52, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 10, + "nets": [ + { + "name": "dout_i", + "isBus": true, + "subnets": [ + { + "name": "dout_i[15]" + }, + { + "name": "dout_i[14]" + }, + { + "name": "dout_i[13]" + }, + { + "name": "dout_i[12]" + }, + { + "name": "dout_i[11]" + }, + { + "name": "dout_i[10]" + }, + { + "name": "dout_i[9]" + }, + { + "name": "dout_i[8]" + }, + { + "name": "dout_i[7]" + }, + { + "name": "dout_i[6]" + }, + { + "name": "dout_i[5]" + }, + { + "name": "dout_i[4]" + }, + { + "name": "dout_i[3]" + }, + { + "name": "dout_i[2]" + }, + { + "name": "dout_i[1]" + }, + { + "name": "dout_i[0]" + } + ] + } + ] + }, + { + "name": "probe11", + "id": 53, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 11, + "nets": [ + { + "name": "dout_q", + "isBus": true, + "subnets": [ + { + "name": "dout_q[15]" + }, + { + "name": "dout_q[14]" + }, + { + "name": "dout_q[13]" + }, + { + "name": "dout_q[12]" + }, + { + "name": "dout_q[11]" + }, + { + "name": "dout_q[10]" + }, + { + "name": "dout_q[9]" + }, + { + "name": "dout_q[8]" + }, + { + "name": "dout_q[7]" + }, + { + "name": "dout_q[6]" + }, + { + "name": "dout_q[5]" + }, + { + "name": "dout_q[4]" + }, + { + "name": "dout_q[3]" + }, + { + "name": "dout_q[2]" + }, + { + "name": "dout_q[1]" + }, + { + "name": "dout_q[0]" + } + ] + } + ] } ] }, @@ -2760,7 +2892,7 @@ "pins": [ { "name": "probe0", - "id": 52, + "id": 54, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -2814,7 +2946,7 @@ }, { "name": "probe1", - "id": 53, + "id": 55, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -2882,7 +3014,7 @@ "pins": [ { "name": "probe_in0", - "id": 54, + "id": 56, "type": "DATA", "direction": "IN", "isVector": true, @@ -2924,7 +3056,7 @@ }, { "name": "probe_in1", - "id": 55, + "id": 57, "type": "DATA", "direction": "IN", "isVector": true, @@ -2966,7 +3098,7 @@ }, { "name": "probe_in2", - "id": 56, + "id": 58, "type": "DATA", "direction": "IN", "isVector": true, @@ -3008,7 +3140,7 @@ }, { "name": "probe_in3", - "id": 57, + "id": 59, "type": "DATA", "direction": "IN", "isVector": true, @@ -3050,7 +3182,7 @@ }, { "name": "probe_in4", - "id": 58, + "id": 60, "type": "DATA", "direction": "IN", "isVector": true, @@ -3164,7 +3296,7 @@ }, { "name": "probe_in5", - "id": 59, + "id": 61, "type": "DATA", "direction": "IN", "isVector": true, @@ -3484,7 +3616,7 @@ "pins": [ { "name": "probe_out0", - "id": 60, + "id": 62, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3500,7 +3632,7 @@ }, { "name": "probe_out1", - "id": 61, + "id": 63, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3516,7 +3648,7 @@ }, { "name": "probe_out2", - "id": 62, + "id": 64, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3532,7 +3664,7 @@ }, { "name": "probe_out3", - "id": 63, + "id": 65, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3612,7 +3744,7 @@ "pins": [ { "name": "probe_in0", - "id": 64, + "id": 66, "type": "DATA", "direction": "IN", "isVector": false, @@ -3628,7 +3760,7 @@ }, { "name": "probe_in1", - "id": 65, + "id": 67, "type": "DATA", "direction": "IN", "isVector": false, @@ -3658,7 +3790,7 @@ "pins": [ { "name": "probe_in0", - "id": 66, + "id": 68, "type": "DATA", "direction": "IN", "isVector": false, @@ -3674,7 +3806,7 @@ }, { "name": "probe_out0", - "id": 67, + "id": 69, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3690,7 +3822,7 @@ }, { "name": "probe_out1", - "id": 68, + "id": 70, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3732,7 +3864,7 @@ }, { "name": "probe_out2", - "id": 69, + "id": 71, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3748,7 +3880,7 @@ }, { "name": "probe_out3", - "id": 70, + "id": 72, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3862,7 +3994,7 @@ }, { "name": "probe_out4", - "id": 71, + "id": 73, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3878,7 +4010,7 @@ }, { "name": "probe_out5", - "id": 72, + "id": 74, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3908,7 +4040,7 @@ "pins": [ { "name": "probe_out0", - "id": 73, + "id": 75, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3932,7 +4064,7 @@ }, { "name": "probe_out1", - "id": 74, + "id": 76, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3948,7 +4080,7 @@ }, { "name": "probe_out2", - "id": 75, + "id": 77, "type": "DATA", "direction": "OUT", "isVector": true, @@ -4062,7 +4194,7 @@ }, { "name": "probe_out3", - "id": 76, + "id": 78, "type": "DATA", "direction": "OUT", "isVector": true, @@ -4086,7 +4218,7 @@ }, { "name": "probe_out4", - "id": 77, + "id": 79, "type": "DATA", "direction": "OUT", "isVector": true, @@ -4118,7 +4250,7 @@ }, { "type": "VIO_V2", - "name": "u_vio_rf_rd", + "name": "u_vio_phase_comp", "spec": "labtools_vio_v3", "ipName": "vio", "core_location": { @@ -4126,11 +4258,506 @@ "slave_index": 10, "bscan_switch_index": 0 }, + "uuid": "4AE9461CA90554D0985B58BEE765E4D3", + "pins": [ + { + "name": "probe_in0", + "id": 80, + "type": "DATA", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 0, + "nets": [ + { + "name": "trunc_overflow", + "isBus": false + } + ] + }, + { + "name": "probe_out0", + "id": 81, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 0, + "nets": [ + { + "name": "vio_sin_0", + "isBus": true, + "subnets": [ + { + "name": "vio_sin_0[11]" + }, + { + "name": "vio_sin_0[10]" + }, + { + "name": "vio_sin_0[9]" + }, + { + "name": "vio_sin_0[8]" + }, + { + "name": "vio_sin_0[7]" + }, + { + "name": "vio_sin_0[6]" + }, + { + "name": "vio_sin_0[5]" + }, + { + "name": "vio_sin_0[4]" + }, + { + "name": "vio_sin_0[3]" + }, + { + "name": "vio_sin_0[2]" + }, + { + "name": "vio_sin_0[1]" + }, + { + "name": "vio_sin_0[0]" + } + ] + } + ] + }, + { + "name": "probe_out1", + "id": 82, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 1, + "nets": [ + { + "name": "vio_sin_1", + "isBus": true, + "subnets": [ + { + "name": "vio_sin_1[11]" + }, + { + "name": "vio_sin_1[10]" + }, + { + "name": "vio_sin_1[9]" + }, + { + "name": "vio_sin_1[8]" + }, + { + "name": "vio_sin_1[7]" + }, + { + "name": "vio_sin_1[6]" + }, + { + "name": "vio_sin_1[5]" + }, + { + "name": "vio_sin_1[4]" + }, + { + "name": "vio_sin_1[3]" + }, + { + "name": "vio_sin_1[2]" + }, + { + "name": "vio_sin_1[1]" + }, + { + "name": "vio_sin_1[0]" + } + ] + } + ] + }, + { + "name": "probe_out2", + "id": 83, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 2, + "nets": [ + { + "name": "vio_sin_2", + "isBus": true, + "subnets": [ + { + "name": "vio_sin_2[11]" + }, + { + "name": "vio_sin_2[10]" + }, + { + "name": "vio_sin_2[9]" + }, + { + "name": "vio_sin_2[8]" + }, + { + "name": "vio_sin_2[7]" + }, + { + "name": "vio_sin_2[6]" + }, + { + "name": "vio_sin_2[5]" + }, + { + "name": "vio_sin_2[4]" + }, + { + "name": "vio_sin_2[3]" + }, + { + "name": "vio_sin_2[2]" + }, + { + "name": "vio_sin_2[1]" + }, + { + "name": "vio_sin_2[0]" + } + ] + } + ] + }, + { + "name": "probe_out3", + "id": 84, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 3, + "nets": [ + { + "name": "vio_sin_3", + "isBus": true, + "subnets": [ + { + "name": "vio_sin_3[11]" + }, + { + "name": "vio_sin_3[10]" + }, + { + "name": "vio_sin_3[9]" + }, + { + "name": "vio_sin_3[8]" + }, + { + "name": "vio_sin_3[7]" + }, + { + "name": "vio_sin_3[6]" + }, + { + "name": "vio_sin_3[5]" + }, + { + "name": "vio_sin_3[4]" + }, + { + "name": "vio_sin_3[3]" + }, + { + "name": "vio_sin_3[2]" + }, + { + "name": "vio_sin_3[1]" + }, + { + "name": "vio_sin_3[0]" + } + ] + } + ] + }, + { + "name": "probe_out4", + "id": 85, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 4, + "nets": [ + { + "name": "vio_cos_0", + "isBus": true, + "subnets": [ + { + "name": "vio_cos_0[11]" + }, + { + "name": "vio_cos_0[10]" + }, + { + "name": "vio_cos_0[9]" + }, + { + "name": "vio_cos_0[8]" + }, + { + "name": "vio_cos_0[7]" + }, + { + "name": "vio_cos_0[6]" + }, + { + "name": "vio_cos_0[5]" + }, + { + "name": "vio_cos_0[4]" + }, + { + "name": "vio_cos_0[3]" + }, + { + "name": "vio_cos_0[2]" + }, + { + "name": "vio_cos_0[1]" + }, + { + "name": "vio_cos_0[0]" + } + ] + } + ] + }, + { + "name": "probe_out5", + "id": 86, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 5, + "nets": [ + { + "name": "vio_cos_1", + "isBus": true, + "subnets": [ + { + "name": "vio_cos_1[11]" + }, + { + "name": "vio_cos_1[10]" + }, + { + "name": "vio_cos_1[9]" + }, + { + "name": "vio_cos_1[8]" + }, + { + "name": "vio_cos_1[7]" + }, + { + "name": "vio_cos_1[6]" + }, + { + "name": "vio_cos_1[5]" + }, + { + "name": "vio_cos_1[4]" + }, + { + "name": "vio_cos_1[3]" + }, + { + "name": "vio_cos_1[2]" + }, + { + "name": "vio_cos_1[1]" + }, + { + "name": "vio_cos_1[0]" + } + ] + } + ] + }, + { + "name": "probe_out6", + "id": 87, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 6, + "nets": [ + { + "name": "vio_cos_2", + "isBus": true, + "subnets": [ + { + "name": "vio_cos_2[11]" + }, + { + "name": "vio_cos_2[10]" + }, + { + "name": "vio_cos_2[9]" + }, + { + "name": "vio_cos_2[8]" + }, + { + "name": "vio_cos_2[7]" + }, + { + "name": "vio_cos_2[6]" + }, + { + "name": "vio_cos_2[5]" + }, + { + "name": "vio_cos_2[4]" + }, + { + "name": "vio_cos_2[3]" + }, + { + "name": "vio_cos_2[2]" + }, + { + "name": "vio_cos_2[1]" + }, + { + "name": "vio_cos_2[0]" + } + ] + } + ] + }, + { + "name": "probe_out7", + "id": 88, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 7, + "nets": [ + { + "name": "vio_cos_3", + "isBus": true, + "subnets": [ + { + "name": "vio_cos_3[11]" + }, + { + "name": "vio_cos_3[10]" + }, + { + "name": "vio_cos_3[9]" + }, + { + "name": "vio_cos_3[8]" + }, + { + "name": "vio_cos_3[7]" + }, + { + "name": "vio_cos_3[6]" + }, + { + "name": "vio_cos_3[5]" + }, + { + "name": "vio_cos_3[4]" + }, + { + "name": "vio_cos_3[3]" + }, + { + "name": "vio_cos_3[2]" + }, + { + "name": "vio_cos_3[1]" + }, + { + "name": "vio_cos_3[0]" + } + ] + } + ] + }, + { + "name": "probe_out8", + "id": 89, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 4, + "portIndex": 8, + "nets": [ + { + "name": "vio_trunc", + "isBus": true, + "subnets": [ + { + "name": "vio_trunc[4]" + }, + { + "name": "vio_trunc[3]" + }, + { + "name": "vio_trunc[2]" + }, + { + "name": "vio_trunc[1]" + }, + { + "name": "vio_trunc[0]" + } + ] + } + ] + } + ] + }, + { + "type": "VIO_V2", + "name": "u_vio_rf_rd", + "spec": "labtools_vio_v3", + "ipName": "vio", + "core_location": { + "user_chain": 1, + "slave_index": 11, + "bscan_switch_index": 0 + }, "uuid": "E61F68815B58500E990715073AE52724", "pins": [ { "name": "probe_in0", - "id": 78, + "id": 90, "type": "DATA", "direction": "IN", "isVector": true, @@ -4172,7 +4799,7 @@ }, { "name": "probe_in1", - "id": 79, + "id": 91, "type": "DATA", "direction": "IN", "isVector": true, @@ -4214,7 +4841,7 @@ }, { "name": "probe_in2", - "id": 80, + "id": 92, "type": "DATA", "direction": "IN", "isVector": true, @@ -4256,7 +4883,7 @@ }, { "name": "probe_in3", - "id": 81, + "id": 93, "type": "DATA", "direction": "IN", "isVector": true, @@ -4298,7 +4925,7 @@ }, { "name": "probe_in4", - "id": 82, + "id": 94, "type": "DATA", "direction": "IN", "isVector": true, @@ -4328,7 +4955,7 @@ }, { "name": "probe_in5", - "id": 83, + "id": 95, "type": "DATA", "direction": "IN", "isVector": true, @@ -4358,7 +4985,7 @@ }, { "name": "probe_in6", - "id": 84, + "id": 96, "type": "DATA", "direction": "IN", "isVector": true, @@ -4388,7 +5015,7 @@ }, { "name": "probe_in7", - "id": 85, + "id": 97, "type": "DATA", "direction": "IN", "isVector": true, @@ -4418,7 +5045,7 @@ }, { "name": "probe_in8", - "id": 86, + "id": 98, "type": "DATA", "direction": "IN", "isVector": true, @@ -4532,7 +5159,7 @@ }, { "name": "probe_in9", - "id": 87, + "id": 99, "type": "DATA", "direction": "IN", "isVector": true, @@ -4845,14 +5472,14 @@ "ipName": "vio", "core_location": { "user_chain": 1, - "slave_index": 11, + "slave_index": 12, "bscan_switch_index": 0 }, "uuid": "3895CB8B6B1755D7963C7298FD0FCD61", "pins": [ { "name": "probe_in0", - "id": 88, + "id": 100, "type": "DATA", "direction": "IN", "isVector": true, @@ -4918,7 +5545,7 @@ }, { "name": "probe_in1", - "id": 89, + "id": 101, "type": "DATA", "direction": "IN", "isVector": false, @@ -4934,7 +5561,7 @@ }, { "name": "probe_out0", - "id": 90, + "id": 102, "type": "DATA", "direction": "OUT", "isVector": false, @@ -4950,7 +5577,7 @@ }, { "name": "probe_out1", - "id": 91, + "id": 103, "type": "DATA", "direction": "OUT", "isVector": false, @@ -4966,7 +5593,7 @@ }, { "name": "probe_out2", - "id": 92, + "id": 104, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5032,7 +5659,7 @@ }, { "name": "probe_out3", - "id": 93, + "id": 105, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5074,7 +5701,7 @@ }, { "name": "probe_out4", - "id": 94, + "id": 106, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5104,7 +5731,7 @@ }, { "name": "probe_out5", - "id": 95, + "id": 107, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5134,7 +5761,7 @@ }, { "name": "probe_out6", - "id": 96, + "id": 108, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5164,7 +5791,7 @@ }, { "name": "probe_out7", - "id": 97, + "id": 109, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5194,7 +5821,7 @@ }, { "name": "probe_out8", - "id": 98, + "id": 110, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5236,7 +5863,7 @@ }, { "name": "probe_out9", - "id": 99, + "id": 111, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5278,7 +5905,7 @@ }, { "name": "probe_out10", - "id": 100, + "id": 112, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5344,7 +5971,7 @@ }, { "name": "probe_out11", - "id": 101, + "id": 113, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5410,7 +6037,7 @@ }, { "name": "probe_out12", - "id": 102, + "id": 114, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5476,7 +6103,7 @@ }, { "name": "probe_out13", - "id": 103, + "id": 115, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5492,7 +6119,7 @@ }, { "name": "probe_out14", - "id": 104, + "id": 116, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5508,7 +6135,7 @@ }, { "name": "probe_out15", - "id": 105, + "id": 117, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5524,7 +6151,7 @@ }, { "name": "probe_out16", - "id": 106, + "id": 118, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5540,7 +6167,7 @@ }, { "name": "probe_out17", - "id": 107, + "id": 119, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5654,7 +6281,7 @@ }, { "name": "probe_out18", - "id": 108, + "id": 120, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5768,7 +6395,7 @@ }, { "name": "probe_out19", - "id": 109, + "id": 121, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5882,7 +6509,7 @@ }, { "name": "probe_out20", - "id": 110, + "id": 122, "type": "DATA", "direction": "OUT", "isVector": true, diff --git a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.bit b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.bit index 5febc1b7..5b40f503 100644 Binary files a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.bit and b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.bit differ diff --git a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.ltx b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.ltx index 19426197..280eb0aa 100644 --- a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.ltx +++ b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.ltx @@ -2743,6 +2743,138 @@ ] } ] + }, + { + "name": "probe10", + "id": 52, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 10, + "nets": [ + { + "name": "dout_i", + "isBus": true, + "subnets": [ + { + "name": "dout_i[15]" + }, + { + "name": "dout_i[14]" + }, + { + "name": "dout_i[13]" + }, + { + "name": "dout_i[12]" + }, + { + "name": "dout_i[11]" + }, + { + "name": "dout_i[10]" + }, + { + "name": "dout_i[9]" + }, + { + "name": "dout_i[8]" + }, + { + "name": "dout_i[7]" + }, + { + "name": "dout_i[6]" + }, + { + "name": "dout_i[5]" + }, + { + "name": "dout_i[4]" + }, + { + "name": "dout_i[3]" + }, + { + "name": "dout_i[2]" + }, + { + "name": "dout_i[1]" + }, + { + "name": "dout_i[0]" + } + ] + } + ] + }, + { + "name": "probe11", + "id": 53, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 11, + "nets": [ + { + "name": "dout_q", + "isBus": true, + "subnets": [ + { + "name": "dout_q[15]" + }, + { + "name": "dout_q[14]" + }, + { + "name": "dout_q[13]" + }, + { + "name": "dout_q[12]" + }, + { + "name": "dout_q[11]" + }, + { + "name": "dout_q[10]" + }, + { + "name": "dout_q[9]" + }, + { + "name": "dout_q[8]" + }, + { + "name": "dout_q[7]" + }, + { + "name": "dout_q[6]" + }, + { + "name": "dout_q[5]" + }, + { + "name": "dout_q[4]" + }, + { + "name": "dout_q[3]" + }, + { + "name": "dout_q[2]" + }, + { + "name": "dout_q[1]" + }, + { + "name": "dout_q[0]" + } + ] + } + ] } ] }, @@ -2760,7 +2892,7 @@ "pins": [ { "name": "probe0", - "id": 52, + "id": 54, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -2814,7 +2946,7 @@ }, { "name": "probe1", - "id": 53, + "id": 55, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -2882,7 +3014,7 @@ "pins": [ { "name": "probe_in0", - "id": 54, + "id": 56, "type": "DATA", "direction": "IN", "isVector": true, @@ -2924,7 +3056,7 @@ }, { "name": "probe_in1", - "id": 55, + "id": 57, "type": "DATA", "direction": "IN", "isVector": true, @@ -2966,7 +3098,7 @@ }, { "name": "probe_in2", - "id": 56, + "id": 58, "type": "DATA", "direction": "IN", "isVector": true, @@ -3008,7 +3140,7 @@ }, { "name": "probe_in3", - "id": 57, + "id": 59, "type": "DATA", "direction": "IN", "isVector": true, @@ -3050,7 +3182,7 @@ }, { "name": "probe_in4", - "id": 58, + "id": 60, "type": "DATA", "direction": "IN", "isVector": true, @@ -3164,7 +3296,7 @@ }, { "name": "probe_in5", - "id": 59, + "id": 61, "type": "DATA", "direction": "IN", "isVector": true, @@ -3484,7 +3616,7 @@ "pins": [ { "name": "probe_out0", - "id": 60, + "id": 62, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3500,7 +3632,7 @@ }, { "name": "probe_out1", - "id": 61, + "id": 63, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3516,7 +3648,7 @@ }, { "name": "probe_out2", - "id": 62, + "id": 64, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3532,7 +3664,7 @@ }, { "name": "probe_out3", - "id": 63, + "id": 65, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3612,7 +3744,7 @@ "pins": [ { "name": "probe_in0", - "id": 64, + "id": 66, "type": "DATA", "direction": "IN", "isVector": false, @@ -3628,7 +3760,7 @@ }, { "name": "probe_in1", - "id": 65, + "id": 67, "type": "DATA", "direction": "IN", "isVector": false, @@ -3658,7 +3790,7 @@ "pins": [ { "name": "probe_in0", - "id": 66, + "id": 68, "type": "DATA", "direction": "IN", "isVector": false, @@ -3674,7 +3806,7 @@ }, { "name": "probe_out0", - "id": 67, + "id": 69, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3690,7 +3822,7 @@ }, { "name": "probe_out1", - "id": 68, + "id": 70, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3732,7 +3864,7 @@ }, { "name": "probe_out2", - "id": 69, + "id": 71, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3748,7 +3880,7 @@ }, { "name": "probe_out3", - "id": 70, + "id": 72, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3862,7 +3994,7 @@ }, { "name": "probe_out4", - "id": 71, + "id": 73, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3878,7 +4010,7 @@ }, { "name": "probe_out5", - "id": 72, + "id": 74, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3908,7 +4040,7 @@ "pins": [ { "name": "probe_out0", - "id": 73, + "id": 75, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3932,7 +4064,7 @@ }, { "name": "probe_out1", - "id": 74, + "id": 76, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3948,7 +4080,7 @@ }, { "name": "probe_out2", - "id": 75, + "id": 77, "type": "DATA", "direction": "OUT", "isVector": true, @@ -4062,7 +4194,7 @@ }, { "name": "probe_out3", - "id": 76, + "id": 78, "type": "DATA", "direction": "OUT", "isVector": true, @@ -4086,7 +4218,7 @@ }, { "name": "probe_out4", - "id": 77, + "id": 79, "type": "DATA", "direction": "OUT", "isVector": true, @@ -4118,7 +4250,7 @@ }, { "type": "VIO_V2", - "name": "u_vio_rf_rd", + "name": "u_vio_phase_comp", "spec": "labtools_vio_v3", "ipName": "vio", "core_location": { @@ -4126,11 +4258,506 @@ "slave_index": 10, "bscan_switch_index": 0 }, + "uuid": "4AE9461CA90554D0985B58BEE765E4D3", + "pins": [ + { + "name": "probe_in0", + "id": 80, + "type": "DATA", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 0, + "nets": [ + { + "name": "trunc_overflow", + "isBus": false + } + ] + }, + { + "name": "probe_out0", + "id": 81, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 0, + "nets": [ + { + "name": "vio_sin_0", + "isBus": true, + "subnets": [ + { + "name": "vio_sin_0[11]" + }, + { + "name": "vio_sin_0[10]" + }, + { + "name": "vio_sin_0[9]" + }, + { + "name": "vio_sin_0[8]" + }, + { + "name": "vio_sin_0[7]" + }, + { + "name": "vio_sin_0[6]" + }, + { + "name": "vio_sin_0[5]" + }, + { + "name": "vio_sin_0[4]" + }, + { + "name": "vio_sin_0[3]" + }, + { + "name": "vio_sin_0[2]" + }, + { + "name": "vio_sin_0[1]" + }, + { + "name": "vio_sin_0[0]" + } + ] + } + ] + }, + { + "name": "probe_out1", + "id": 82, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 1, + "nets": [ + { + "name": "vio_sin_1", + "isBus": true, + "subnets": [ + { + "name": "vio_sin_1[11]" + }, + { + "name": "vio_sin_1[10]" + }, + { + "name": "vio_sin_1[9]" + }, + { + "name": "vio_sin_1[8]" + }, + { + "name": "vio_sin_1[7]" + }, + { + "name": "vio_sin_1[6]" + }, + { + "name": "vio_sin_1[5]" + }, + { + "name": "vio_sin_1[4]" + }, + { + "name": "vio_sin_1[3]" + }, + { + "name": "vio_sin_1[2]" + }, + { + "name": "vio_sin_1[1]" + }, + { + "name": "vio_sin_1[0]" + } + ] + } + ] + }, + { + "name": "probe_out2", + "id": 83, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 2, + "nets": [ + { + "name": "vio_sin_2", + "isBus": true, + "subnets": [ + { + "name": "vio_sin_2[11]" + }, + { + "name": "vio_sin_2[10]" + }, + { + "name": "vio_sin_2[9]" + }, + { + "name": "vio_sin_2[8]" + }, + { + "name": "vio_sin_2[7]" + }, + { + "name": "vio_sin_2[6]" + }, + { + "name": "vio_sin_2[5]" + }, + { + "name": "vio_sin_2[4]" + }, + { + "name": "vio_sin_2[3]" + }, + { + "name": "vio_sin_2[2]" + }, + { + "name": "vio_sin_2[1]" + }, + { + "name": "vio_sin_2[0]" + } + ] + } + ] + }, + { + "name": "probe_out3", + "id": 84, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 3, + "nets": [ + { + "name": "vio_sin_3", + "isBus": true, + "subnets": [ + { + "name": "vio_sin_3[11]" + }, + { + "name": "vio_sin_3[10]" + }, + { + "name": "vio_sin_3[9]" + }, + { + "name": "vio_sin_3[8]" + }, + { + "name": "vio_sin_3[7]" + }, + { + "name": "vio_sin_3[6]" + }, + { + "name": "vio_sin_3[5]" + }, + { + "name": "vio_sin_3[4]" + }, + { + "name": "vio_sin_3[3]" + }, + { + "name": "vio_sin_3[2]" + }, + { + "name": "vio_sin_3[1]" + }, + { + "name": "vio_sin_3[0]" + } + ] + } + ] + }, + { + "name": "probe_out4", + "id": 85, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 4, + "nets": [ + { + "name": "vio_cos_0", + "isBus": true, + "subnets": [ + { + "name": "vio_cos_0[11]" + }, + { + "name": "vio_cos_0[10]" + }, + { + "name": "vio_cos_0[9]" + }, + { + "name": "vio_cos_0[8]" + }, + { + "name": "vio_cos_0[7]" + }, + { + "name": "vio_cos_0[6]" + }, + { + "name": "vio_cos_0[5]" + }, + { + "name": "vio_cos_0[4]" + }, + { + "name": "vio_cos_0[3]" + }, + { + "name": "vio_cos_0[2]" + }, + { + "name": "vio_cos_0[1]" + }, + { + "name": "vio_cos_0[0]" + } + ] + } + ] + }, + { + "name": "probe_out5", + "id": 86, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 5, + "nets": [ + { + "name": "vio_cos_1", + "isBus": true, + "subnets": [ + { + "name": "vio_cos_1[11]" + }, + { + "name": "vio_cos_1[10]" + }, + { + "name": "vio_cos_1[9]" + }, + { + "name": "vio_cos_1[8]" + }, + { + "name": "vio_cos_1[7]" + }, + { + "name": "vio_cos_1[6]" + }, + { + "name": "vio_cos_1[5]" + }, + { + "name": "vio_cos_1[4]" + }, + { + "name": "vio_cos_1[3]" + }, + { + "name": "vio_cos_1[2]" + }, + { + "name": "vio_cos_1[1]" + }, + { + "name": "vio_cos_1[0]" + } + ] + } + ] + }, + { + "name": "probe_out6", + "id": 87, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 6, + "nets": [ + { + "name": "vio_cos_2", + "isBus": true, + "subnets": [ + { + "name": "vio_cos_2[11]" + }, + { + "name": "vio_cos_2[10]" + }, + { + "name": "vio_cos_2[9]" + }, + { + "name": "vio_cos_2[8]" + }, + { + "name": "vio_cos_2[7]" + }, + { + "name": "vio_cos_2[6]" + }, + { + "name": "vio_cos_2[5]" + }, + { + "name": "vio_cos_2[4]" + }, + { + "name": "vio_cos_2[3]" + }, + { + "name": "vio_cos_2[2]" + }, + { + "name": "vio_cos_2[1]" + }, + { + "name": "vio_cos_2[0]" + } + ] + } + ] + }, + { + "name": "probe_out7", + "id": 88, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 7, + "nets": [ + { + "name": "vio_cos_3", + "isBus": true, + "subnets": [ + { + "name": "vio_cos_3[11]" + }, + { + "name": "vio_cos_3[10]" + }, + { + "name": "vio_cos_3[9]" + }, + { + "name": "vio_cos_3[8]" + }, + { + "name": "vio_cos_3[7]" + }, + { + "name": "vio_cos_3[6]" + }, + { + "name": "vio_cos_3[5]" + }, + { + "name": "vio_cos_3[4]" + }, + { + "name": "vio_cos_3[3]" + }, + { + "name": "vio_cos_3[2]" + }, + { + "name": "vio_cos_3[1]" + }, + { + "name": "vio_cos_3[0]" + } + ] + } + ] + }, + { + "name": "probe_out8", + "id": 89, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 4, + "portIndex": 8, + "nets": [ + { + "name": "vio_trunc", + "isBus": true, + "subnets": [ + { + "name": "vio_trunc[4]" + }, + { + "name": "vio_trunc[3]" + }, + { + "name": "vio_trunc[2]" + }, + { + "name": "vio_trunc[1]" + }, + { + "name": "vio_trunc[0]" + } + ] + } + ] + } + ] + }, + { + "type": "VIO_V2", + "name": "u_vio_rf_rd", + "spec": "labtools_vio_v3", + "ipName": "vio", + "core_location": { + "user_chain": 1, + "slave_index": 11, + "bscan_switch_index": 0 + }, "uuid": "E61F68815B58500E990715073AE52724", "pins": [ { "name": "probe_in0", - "id": 78, + "id": 90, "type": "DATA", "direction": "IN", "isVector": true, @@ -4172,7 +4799,7 @@ }, { "name": "probe_in1", - "id": 79, + "id": 91, "type": "DATA", "direction": "IN", "isVector": true, @@ -4214,7 +4841,7 @@ }, { "name": "probe_in2", - "id": 80, + "id": 92, "type": "DATA", "direction": "IN", "isVector": true, @@ -4256,7 +4883,7 @@ }, { "name": "probe_in3", - "id": 81, + "id": 93, "type": "DATA", "direction": "IN", "isVector": true, @@ -4298,7 +4925,7 @@ }, { "name": "probe_in4", - "id": 82, + "id": 94, "type": "DATA", "direction": "IN", "isVector": true, @@ -4328,7 +4955,7 @@ }, { "name": "probe_in5", - "id": 83, + "id": 95, "type": "DATA", "direction": "IN", "isVector": true, @@ -4358,7 +4985,7 @@ }, { "name": "probe_in6", - "id": 84, + "id": 96, "type": "DATA", "direction": "IN", "isVector": true, @@ -4388,7 +5015,7 @@ }, { "name": "probe_in7", - "id": 85, + "id": 97, "type": "DATA", "direction": "IN", "isVector": true, @@ -4418,7 +5045,7 @@ }, { "name": "probe_in8", - "id": 86, + "id": 98, "type": "DATA", "direction": "IN", "isVector": true, @@ -4532,7 +5159,7 @@ }, { "name": "probe_in9", - "id": 87, + "id": 99, "type": "DATA", "direction": "IN", "isVector": true, @@ -4845,14 +5472,14 @@ "ipName": "vio", "core_location": { "user_chain": 1, - "slave_index": 11, + "slave_index": 12, "bscan_switch_index": 0 }, "uuid": "3895CB8B6B1755D7963C7298FD0FCD61", "pins": [ { "name": "probe_in0", - "id": 88, + "id": 100, "type": "DATA", "direction": "IN", "isVector": true, @@ -4918,7 +5545,7 @@ }, { "name": "probe_in1", - "id": 89, + "id": 101, "type": "DATA", "direction": "IN", "isVector": false, @@ -4934,7 +5561,7 @@ }, { "name": "probe_out0", - "id": 90, + "id": 102, "type": "DATA", "direction": "OUT", "isVector": false, @@ -4950,7 +5577,7 @@ }, { "name": "probe_out1", - "id": 91, + "id": 103, "type": "DATA", "direction": "OUT", "isVector": false, @@ -4966,7 +5593,7 @@ }, { "name": "probe_out2", - "id": 92, + "id": 104, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5032,7 +5659,7 @@ }, { "name": "probe_out3", - "id": 93, + "id": 105, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5074,7 +5701,7 @@ }, { "name": "probe_out4", - "id": 94, + "id": 106, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5104,7 +5731,7 @@ }, { "name": "probe_out5", - "id": 95, + "id": 107, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5134,7 +5761,7 @@ }, { "name": "probe_out6", - "id": 96, + "id": 108, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5164,7 +5791,7 @@ }, { "name": "probe_out7", - "id": 97, + "id": 109, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5194,7 +5821,7 @@ }, { "name": "probe_out8", - "id": 98, + "id": 110, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5236,7 +5863,7 @@ }, { "name": "probe_out9", - "id": 99, + "id": 111, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5278,7 +5905,7 @@ }, { "name": "probe_out10", - "id": 100, + "id": 112, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5344,7 +5971,7 @@ }, { "name": "probe_out11", - "id": 101, + "id": 113, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5410,7 +6037,7 @@ }, { "name": "probe_out12", - "id": 102, + "id": 114, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5476,7 +6103,7 @@ }, { "name": "probe_out13", - "id": 103, + "id": 115, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5492,7 +6119,7 @@ }, { "name": "probe_out14", - "id": 104, + "id": 116, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5508,7 +6135,7 @@ }, { "name": "probe_out15", - "id": 105, + "id": 117, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5524,7 +6151,7 @@ }, { "name": "probe_out16", - "id": 106, + "id": 118, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5540,7 +6167,7 @@ }, { "name": "probe_out17", - "id": 107, + "id": 119, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5654,7 +6281,7 @@ }, { "name": "probe_out18", - "id": 108, + "id": 120, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5768,7 +6395,7 @@ }, { "name": "probe_out19", - "id": 109, + "id": 121, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5882,7 +6509,7 @@ }, { "name": "probe_out20", - "id": 110, + "id": 122, "type": "DATA", "direction": "OUT", "isVector": true, diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf b/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf index 71d15df8..a22d6d1b 100644 Binary files a/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf and b/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf differ diff --git a/projects/duifei/duifei_online_acq_par/rtl/phase_compensate.v b/projects/duifei/duifei_online_acq_par/rtl/phase_compensate.v new file mode 100755 index 00000000..8251a0f7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/phase_compensate.v @@ -0,0 +1,196 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/05/16 02:00:43 +// Design Name: +// Module Name: phase_compensate +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module phase_compensate( + input clk , + input rst , + input [11:0] vio_sin_0 , + input [11:0] vio_sin_1 , + input [11:0] vio_sin_2 , + input [11:0] vio_sin_3 , + input [11:0] vio_cos_0 , + input [11:0] vio_cos_1 , + input [11:0] vio_cos_2 , + input [11:0] vio_cos_3 , + input [11:0] din_i_0 , + input [11:0] din_i_1 , + input [11:0] din_i_2 , + input [11:0] din_i_3 , + input [11:0] din_q_0 , + input [11:0] din_q_1 , + input [11:0] din_q_2 , + input [11:0] din_q_3 , + input [4:0] vio_trunc , + + output [15:0] dout_i , + output [15:0] dout_q , + output trunc_overflow +); + + wire [63:0] dout_comp_0; + wire [63:0] dout_comp_1; + wire [63:0] dout_comp_2; + wire [63:0] dout_comp_3; + cmpy_12_12 cmpy_12_12_0 ( + .aclk(clk), // input wire aclk + .s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid + .s_axis_a_tdata({{4{vio_sin_0[11]}},vio_sin_0[11:0],{4{vio_cos_0[11]}},vio_cos_0[11:0]}), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid + .s_axis_b_tdata({{4{din_q_0[11]}},din_q_0[11:0],{4{din_i_0[11]}},din_i_0[11:0]}), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(dout_comp_0) // output wire [63 : 0] m_axis_dout_tdata + ); + + cmpy_12_12 cmpy_12_12_1 ( + .aclk(clk), // input wire aclk + .s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid + .s_axis_a_tdata({{4{vio_sin_1[11]}},vio_sin_1[11:0],{4{vio_cos_1[11]}},vio_cos_1[11:0]}), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid + .s_axis_b_tdata({{4{din_q_1[11]}},din_q_1[11:0],{4{din_i_1[11]}},din_i_1[11:0]}), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(dout_comp_1) // output wire [63 : 0] m_axis_dout_tdata + ); + + cmpy_12_12 cmpy_12_12_2 ( + .aclk(clk), // input wire aclk + .s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid + .s_axis_a_tdata({{4{vio_sin_2[11]}},vio_sin_2[11:0],{4{vio_cos_2[11]}},vio_cos_2[11:0]}), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid + .s_axis_b_tdata({{4{din_q_2[11]}},din_q_2[11:0],{4{din_i_2[11]}},din_i_2[11:0]}), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(dout_comp_2) // output wire [63 : 0] m_axis_dout_tdata + ); + + cmpy_12_12 cmpy_12_12_3 ( + .aclk(clk), // input wire aclk + .s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid + .s_axis_a_tdata({{4{vio_sin_3[11]}},vio_sin_3[11:0],{4{vio_cos_3[11]}},vio_cos_3[11:0]}), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid + .s_axis_b_tdata({{4{din_q_3[11]}},din_q_3[11:0],{4{din_i_3[11]}},din_i_3[11:0]}), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(dout_comp_3) // output wire [63 : 0] m_axis_dout_tdata + ); + wire [11:0] dout_trunc_0i, dout_trunc_0q; + wire [11:0] dout_trunc_1i, dout_trunc_1q; + wire [11:0] dout_trunc_2i, dout_trunc_2q; + wire [11:0] dout_trunc_3i, dout_trunc_3q; + wire [11:0] trunc_overflow_0i, trunc_overflow_0q; + wire [11:0] trunc_overflow_1i, trunc_overflow_1q; + wire [11:0] trunc_overflow_2i, trunc_overflow_2q; + wire [11:0] trunc_overflow_3i, trunc_overflow_3q; + trunc_32bit_to_12bit trunc_32bit_to_12bit_0i( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_0[24]}},dout_comp_0[24:0]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_0i), + .trunc_overflow(trunc_overflow_0i) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_0q( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_0[56]}},dout_comp_0[56:32]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_0q), + .trunc_overflow(trunc_overflow_0q) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_1i( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_1[24]}},dout_comp_1[24:0]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_1i), + .trunc_overflow(trunc_overflow_1i) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_1q( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_1[56]}},dout_comp_1[56:32]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_1q), + .trunc_overflow(trunc_overflow_1q) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_2i( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_2[24]}},dout_comp_2[24:0]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_2i), + .trunc_overflow(trunc_overflow_2i) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_2q( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_2[56]}},dout_comp_2[56:32]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_2q), + .trunc_overflow(trunc_overflow_2q) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_3i( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_3[24]}},dout_comp_3[24:0]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_3i), + .trunc_overflow(trunc_overflow_3i) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_3q( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_3[56]}},dout_comp_3[56:32]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_3q), + .trunc_overflow(trunc_overflow_3q) + ); + + reg [15:0] data_i_combine = 16'd0; + reg [15:0] data_q_combine = 16'd0; + always @ (posedge clk) begin + if(rst) begin + data_i_combine[15:0] <= 16'd0; + data_q_combine[15:0] <= 16'd0; + end + else begin + data_i_combine[15:0] <= {{4{dout_trunc_0i[11]}},dout_trunc_0i[11:0]} + {{4{dout_trunc_1i[11]}},dout_trunc_1i[11:0]} + {{4{dout_trunc_2i[11]}},dout_trunc_2i[11:0]} + {{4{dout_trunc_3i[11]}},dout_trunc_3i[11:0]}; + data_q_combine[15:0] <= {{4{dout_trunc_0q[11]}},dout_trunc_0q[11:0]} + {{4{dout_trunc_1q[11]}},dout_trunc_1q[11:0]} + {{4{dout_trunc_2q[11]}},dout_trunc_2q[11:0]} + {{4{dout_trunc_3q[11]}},dout_trunc_3q[11:0]}; + end + end + + assign dout_i[15:0] = data_i_combine[15:0]; + assign dout_q[15:0] = data_q_combine[15:0]; + assign trunc_overflow = trunc_overflow_3q || trunc_overflow_2q || trunc_overflow_1q || trunc_overflow_0q || trunc_overflow_3i || trunc_overflow_2i || trunc_overflow_1i || trunc_overflow_0i; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/system_top.v b/projects/duifei/duifei_online_acq_par/rtl/system_top.v index 8e67c577..b8754b11 100644 --- a/projects/duifei/duifei_online_acq_par/rtl/system_top.v +++ b/projects/duifei/duifei_online_acq_par/rtl/system_top.v @@ -676,6 +676,50 @@ ad9361_phase_cal_coarse u_ad9361_phase_cal // <---------------------------------------------------------------------------> // <----------------------- insert receiver logic below -----------------------> // <---------------------------------------------------------------------------> +// weighted summation +wire [11:0] vio_sin_0; +wire [11:0] vio_sin_1; +wire [11:0] vio_sin_2; +wire [11:0] vio_sin_3; +wire [11:0] vio_cos_0; +wire [11:0] vio_cos_1; +wire [11:0] vio_cos_2; +wire [11:0] vio_cos_3; + +wire [4:0] vio_trunc; +wire trunc_overflow; + +wire [15:0] dout_i; +wire [15:0] dout_q; + +phase_compensate u_phase_compensate +( + .clk (sys_clk ), // input clk + .rst (sys_rst ), // input rst + .vio_sin_0 (vio_sin_0 ), // input [11:0] vio_sin_0 + .vio_sin_1 (vio_sin_1 ), // input [11:0] vio_sin_1 + .vio_sin_2 (vio_sin_2 ), // input [11:0] vio_sin_2 + .vio_sin_3 (vio_sin_3 ), // input [11:0] vio_sin_3 + .vio_cos_0 (vio_cos_0 ), // input [11:0] vio_cos_0 + .vio_cos_1 (vio_cos_1 ), // input [11:0] vio_cos_1 + .vio_cos_2 (vio_cos_2 ), // input [11:0] vio_cos_2 + .vio_cos_3 (vio_cos_3 ), // input [11:0] vio_cos_3 + .din_i_0 (rx_cal_ch1_i ), // input [11:0] din_i_0 + .din_i_1 (rx_cal_ch2_i ), // input [11:0] din_i_1 + .din_i_2 (rx_cal_ch3_i ), // input [11:0] din_i_2 + .din_i_3 (rx_cal_ch4_i ), // input [11:0] din_i_3 + .din_q_0 (rx_cal_ch1_q ), // input [11:0] din_q_0 + .din_q_1 (rx_cal_ch2_q ), // input [11:0] din_q_1 + .din_q_2 (rx_cal_ch3_q ), // input [11:0] din_q_2 + .din_q_3 (rx_cal_ch4_q ), // input [11:0] din_q_3 + .vio_trunc (vio_trunc ), // input [4:0] vio_trunc + + .dout_i (dout_i ), // output [15:0] dout_i + .dout_q (dout_q ), // output [15:0] dout_q + .trunc_overflow (trunc_overflow ) // output trunc_overflow +); + +// online acquisition wire freq_comp_start ; wire freq_comp_auto_enable_vio; wire freq_comp_start_vio; @@ -952,7 +996,9 @@ ila_rx_data_cnt u_ila_rx .probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6 .probe7 (rx_cal_ch4_q ), // input wire [11:0] probe7 .probe8 (vio_frequency_auto[11:0] ), // input wire [11:0] probe8 - .probe9 (chip_cnt ) // input wire [9:0] probe9 + .probe9 (chip_cnt ), // input wire [9:0] probe9 + .probe10(dout_i ), // input wire [15:0] probe10 + .probe11(dout_q ) // input wire [15:0] probe11 ); ila_cal u_ila_cal @@ -1023,4 +1069,19 @@ ila_freq_comp u_ila_freq_comp .probe20(vio_frequency_auto[11:0] ) // input wire [11:0] probe20 ); +vio_phase_comp u_vio_phase_comp +( + .clk (sys_clk ), // input wire clk + .probe_in0 (trunc_overflow ), // input wire [0 : 0] probe_in0 + .probe_out0 (vio_sin_0 ), // output wire [11 : 0] probe_out0 + .probe_out1 (vio_sin_1 ), // output wire [11 : 0] probe_out1 + .probe_out2 (vio_sin_2 ), // output wire [11 : 0] probe_out2 + .probe_out3 (vio_sin_3 ), // output wire [11 : 0] probe_out3 + .probe_out4 (vio_cos_0 ), // output wire [11 : 0] probe_out4 + .probe_out5 (vio_cos_1 ), // output wire [11 : 0] probe_out5 + .probe_out6 (vio_cos_2 ), // output wire [11 : 0] probe_out6 + .probe_out7 (vio_cos_3 ), // output wire [11 : 0] probe_out7 + .probe_out8 (vio_trunc ) // output wire [4 : 0] probe_out8 +); + endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/trunc_32bit_to_12bit.v b/projects/duifei/duifei_online_acq_par/rtl/trunc_32bit_to_12bit.v new file mode 100755 index 00000000..51a91be7 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/rtl/trunc_32bit_to_12bit.v @@ -0,0 +1,515 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/03/01 10:44:50 +// Design Name: +// Module Name: trunc_32bit_to_12bit +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module trunc_32bit_to_12bit( + input clk, + input rst, + input [31:0] trunc_32bit_in, + input [4:0] vio_trunc, + + output reg [11:0] trunc_12bit_out = 12'd0, + output reg trunc_overflow = 1'd0 + ); + + always @ (posedge clk) begin + if(rst) begin + trunc_12bit_out[11:0] <= 12'd0; + trunc_overflow <= 1'd0; + end else begin + case(vio_trunc[4:0]) + 5'd0:begin + if(trunc_32bit_in[31:31] == 1'd1 || trunc_32bit_in[31:31] == 1'd0) begin + if(trunc_32bit_in[31:31] == 1'd0 &&trunc_32bit_in[19] == 1'd1 && trunc_32bit_in[31:20] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1; + end + else begin + if(trunc_32bit_in[31:31] == 1'd1 && trunc_32bit_in[19:0] > 20'd524288) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[31:20]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd1:begin + if(trunc_32bit_in[31:30] == 2'd3 || trunc_32bit_in[31:30] == 2'd0) begin + if(trunc_32bit_in[31:30] == 2'd0 &&trunc_32bit_in[18] == 1'd1 && trunc_32bit_in[30:19] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1; + end + else begin + if(trunc_32bit_in[31:30] == 2'd3 && trunc_32bit_in[18:0] > 19'd262144) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[30:19]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd2:begin + if(trunc_32bit_in[31:29] == 3'd7 || trunc_32bit_in[31:29] == 3'd0) begin + if(trunc_32bit_in[31:29] == 3'd0 &&trunc_32bit_in[17] == 1'd1 && trunc_32bit_in[29:18] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1; + end + else begin + if(trunc_32bit_in[31:29] == 3'd7 && trunc_32bit_in[17:0] > 18'd131072) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[29:18]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd3:begin + if(trunc_32bit_in[31:28] == 4'd15 || trunc_32bit_in[31:28] == 4'd0) begin + if(trunc_32bit_in[31:28] == 4'd0 &&trunc_32bit_in[16] == 1'd1 && trunc_32bit_in[28:17] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1; + end + else begin + if(trunc_32bit_in[31:28] == 4'd15 && trunc_32bit_in[16:0] > 17'd65536) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[28:17]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd4:begin + if(trunc_32bit_in[31:27] == 5'd31 || trunc_32bit_in[31:27] == 5'd0) begin + if(trunc_32bit_in[31:27] == 5'd0 &&trunc_32bit_in[15] == 1'd1 && trunc_32bit_in[27:16] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1; + end + else begin + if(trunc_32bit_in[31:27] == 5'd31 && trunc_32bit_in[15:0] > 16'd32768) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[27:16]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd5:begin + if(trunc_32bit_in[31:26] == 6'd63 || trunc_32bit_in[31:26] == 6'd0) begin + if(trunc_32bit_in[31:26] == 6'd0 &&trunc_32bit_in[14] == 1'd1 && trunc_32bit_in[26:15] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1; + end + else begin + if(trunc_32bit_in[31:26] == 6'd63 && trunc_32bit_in[14:0] > 15'd16384) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[26:15]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd6:begin + if(trunc_32bit_in[31:25] == 7'd127 || trunc_32bit_in[31:25] == 7'd0) begin + if(trunc_32bit_in[31:25] == 7'd0 &&trunc_32bit_in[13] == 1'd1 && trunc_32bit_in[25:14] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1; + end + else begin + if(trunc_32bit_in[31:25] == 7'd127 && trunc_32bit_in[13:0] > 14'd8192) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[25:14]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd7:begin + if(trunc_32bit_in[31:24] == 8'd255 || trunc_32bit_in[31:24] == 8'd0) begin + if(trunc_32bit_in[31:24] == 8'd0 &&trunc_32bit_in[12] == 1'd1 && trunc_32bit_in[24:13] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1; + end + else begin + if(trunc_32bit_in[31:24] == 8'd255 && trunc_32bit_in[12:0] > 13'd4096) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[24:13]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd8:begin + if(trunc_32bit_in[31:23] == 9'd511 || trunc_32bit_in[31:23] == 9'd0) begin + if(trunc_32bit_in[31:23] == 9'd0 &&trunc_32bit_in[11] == 1'd1 && trunc_32bit_in[23:12] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1; + end + else begin + if(trunc_32bit_in[31:23] == 9'd511 && trunc_32bit_in[11:0] > 12'd2048) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[23:12]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd9:begin + if(trunc_32bit_in[31:22] == 10'd1023 || trunc_32bit_in[31:22] == 10'd0) begin + if(trunc_32bit_in[31:22] == 10'd0 &&trunc_32bit_in[10] == 1'd1 && trunc_32bit_in[22:11] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1; + end + else begin + if(trunc_32bit_in[31:22] == 10'd1023 && trunc_32bit_in[10:0] > 11'd1024) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[22:11]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd10:begin + if(trunc_32bit_in[31:21] == 11'd2047 || trunc_32bit_in[31:21] == 11'd0) begin + if(trunc_32bit_in[31:21] == 11'd0 &&trunc_32bit_in[9] == 1'd1 && trunc_32bit_in[21:10] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1; + end + else begin + if(trunc_32bit_in[31:21] == 11'd2047 && trunc_32bit_in[9:0] > 10'd512) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[21:10]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd11:begin + if(trunc_32bit_in[31:20] == 12'd4095 || trunc_32bit_in[31:20] == 12'd0) begin + if(trunc_32bit_in[31:20] == 12'd0 &&trunc_32bit_in[8] == 1'd1 && trunc_32bit_in[20:9] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1; + end + else begin + if(trunc_32bit_in[31:20] == 12'd4095 && trunc_32bit_in[8:0] > 9'd256) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[20:9]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd12:begin + if(trunc_32bit_in[31:19] == 13'd8191 || trunc_32bit_in[31:19] == 13'd0) begin + if(trunc_32bit_in[31:19] == 13'd0 &&trunc_32bit_in[7] == 1'd1 && trunc_32bit_in[19:8] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1; + end + else begin + if(trunc_32bit_in[31:19] == 13'd8191 && trunc_32bit_in[7:0] > 8'd128) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[19:8]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd13:begin + if(trunc_32bit_in[31:18] == 14'd16383 || trunc_32bit_in[31:18] == 14'd0) begin + if(trunc_32bit_in[31:18] == 14'd0 &&trunc_32bit_in[6] == 1'd1 && trunc_32bit_in[18:7] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1; + end + else begin + if(trunc_32bit_in[31:18] == 14'd16383 && trunc_32bit_in[6:0] > 7'd64) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[18:7]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd14:begin + if(trunc_32bit_in[31:17] == 15'd32767 || trunc_32bit_in[31:17] == 15'd0) begin + if(trunc_32bit_in[31:17] == 15'd0 &&trunc_32bit_in[5] == 1'd1 && trunc_32bit_in[17:6] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1; + end + else begin + if(trunc_32bit_in[31:17] == 15'd32767 && trunc_32bit_in[5:0] > 6'd32) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[17:6]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd15:begin + if(trunc_32bit_in[31:16] == 16'd65535 || trunc_32bit_in[31:16] == 16'd0) begin + if(trunc_32bit_in[31:16] == 16'd0 &&trunc_32bit_in[4] == 1'd1 && trunc_32bit_in[16:5] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1; + end + else begin + if(trunc_32bit_in[31:16] == 16'd65535 && trunc_32bit_in[4:0] > 5'd16) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[16:5]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd16:begin + if(trunc_32bit_in[31:15] == 17'd131071 || trunc_32bit_in[31:15] == 17'd0) begin + if(trunc_32bit_in[31:15] == 17'd0 &&trunc_32bit_in[3] == 1'd1 && trunc_32bit_in[15:4] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1; + end + else begin + if(trunc_32bit_in[31:15] == 17'd131071 && trunc_32bit_in[3:0] > 4'd8) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[15:4]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd17:begin + if(trunc_32bit_in[31:14] == 18'd262143 || trunc_32bit_in[31:14] == 18'd0) begin + if(trunc_32bit_in[31:14] == 18'd0 &&trunc_32bit_in[2] == 1'd1 && trunc_32bit_in[14:3] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1; + end + else begin + if(trunc_32bit_in[31:14] == 18'd262143 && trunc_32bit_in[2:0] > 3'd4) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[14:3]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd18:begin + if(trunc_32bit_in[31:13] == 19'd524287 || trunc_32bit_in[31:13] == 19'd0) begin + if(trunc_32bit_in[31:13] == 19'd0 &&trunc_32bit_in[1] == 1'd1 && trunc_32bit_in[13:2] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1; + end + else begin + if(trunc_32bit_in[31:13] == 19'd524287 && trunc_32bit_in[1:0] > 2'd2) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[13:2]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd19:begin + if(trunc_32bit_in[31:12] == 20'd1048575 || trunc_32bit_in[31:12] == 20'd0) begin + if(trunc_32bit_in[31:12] == 20'd0 &&trunc_32bit_in[0] == 1'd1 && trunc_32bit_in[12:1] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1; + end + else begin + if(trunc_32bit_in[31:12] == 20'd1048575 && trunc_32bit_in[0:0] > 1'd1) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[12:1]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + default:begin + if(trunc_32bit_in[31:11] == 21'd2097151 || trunc_32bit_in[31:11] == 21'd0) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[11:0]; + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + endcase + end + end +endmodule \ No newline at end of file