diff --git a/projects/dl814_dj/dl814_dj_48m/project.tcl b/projects/dl814_dj/dl814_dj_48m/project.tcl index 7a0af4ab..84143cd6 100644 --- a/projects/dl814_dj/dl814_dj_48m/project.tcl +++ b/projects/dl814_dj/dl814_dj_48m/project.tcl @@ -3,7 +3,7 @@ # # project.tcl: Tcl script for re-creating project 'project' # -# Generated by Vivado on Thu May 11 19:05:20 CST 2023 +# Generated by Vivado on Fri May 12 10:01:28 CST 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* diff --git a/projects/dl814_dj/dl814_dj_48m/project/project.runs/impl_1/system_top.bit b/projects/dl814_dj/dl814_dj_48m/project/project.runs/impl_1/system_top.bit index 17f9f70a..a19991a9 100644 Binary files a/projects/dl814_dj/dl814_dj_48m/project/project.runs/impl_1/system_top.bit and b/projects/dl814_dj/dl814_dj_48m/project/project.runs/impl_1/system_top.bit differ diff --git a/projects/dl814_dj/dl814_dj_48m/project/project.sdk/system_top.hdf b/projects/dl814_dj/dl814_dj_48m/project/project.sdk/system_top.hdf index a7a0a142..8b93e17d 100644 Binary files a/projects/dl814_dj/dl814_dj_48m/project/project.sdk/system_top.hdf and b/projects/dl814_dj/dl814_dj_48m/project/project.sdk/system_top.hdf differ diff --git a/projects/dl814_dj/dl814_dj_48m/rtl/tx_control.v b/projects/dl814_dj/dl814_dj_48m/rtl/tx_control.v index 906a1f49..1757c6d8 100644 --- a/projects/dl814_dj/dl814_dj_48m/rtl/tx_control.v +++ b/projects/dl814_dj/dl814_dj_48m/rtl/tx_control.v @@ -42,7 +42,9 @@ wire [15:0] tx_pn_seq_i; wire [15:0] tx_pn_seq_q; tx_pn_seq_6mcps #( - .DATA_WIDTH (16) + .DATA_WIDTH (16), + .BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001), + .BIT_DATA_LEN (1024) ) u_tx_pn_seq ( .sys_clk (sys_clk ), // 122.88MHz diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/coe/prbs10_invert_rep2.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/coe/prbs10_invert_rep2.coe new file mode 100644 index 00000000..0ab98031 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/coe/prbs10_invert_rep2.coe @@ -0,0 +1,2050 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, 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a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd deleted file mode 100644 index 98593b04..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd +++ /dev/null @@ -1,239 +0,0 @@ --- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:dds_compiler:6.0 --- IP Revision: 18 - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY dds_compiler_v6_0_18; -USE dds_compiler_v6_0_18.dds_compiler_v6_0_18; - -ENTITY dds_32b_8b_comp IS - PORT ( - aclk : IN STD_LOGIC; - s_axis_config_tvalid : IN STD_LOGIC; - s_axis_config_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - m_axis_phase_tvalid : OUT STD_LOGIC; - m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END dds_32b_8b_comp; - -ARCHITECTURE dds_32b_8b_comp_arch OF dds_32b_8b_comp IS - ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; - ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_32b_8b_comp_arch: ARCHITECTURE IS "yes"; - COMPONENT dds_compiler_v6_0_18 IS - GENERIC ( - C_XDEVICEFAMILY : STRING; - C_MODE_OF_OPERATION : INTEGER; - C_MODULUS : INTEGER; - C_ACCUMULATOR_WIDTH : INTEGER; - C_CHANNELS : INTEGER; - C_HAS_PHASE_OUT : INTEGER; - C_HAS_PHASEGEN : INTEGER; - C_HAS_SINCOS : INTEGER; - C_LATENCY : INTEGER; - C_MEM_TYPE : INTEGER; - C_NEGATIVE_COSINE : INTEGER; - C_NEGATIVE_SINE : INTEGER; - C_NOISE_SHAPING : INTEGER; - C_OUTPUTS_REQUIRED : INTEGER; - C_OUTPUT_FORM : INTEGER; - C_OUTPUT_WIDTH : INTEGER; - C_PHASE_ANGLE_WIDTH : INTEGER; - C_PHASE_INCREMENT : INTEGER; - C_PHASE_INCREMENT_VALUE : STRING; - C_RESYNC : INTEGER; - C_PHASE_OFFSET : INTEGER; - C_PHASE_OFFSET_VALUE : STRING; - C_OPTIMISE_GOAL : INTEGER; - C_USE_DSP48 : INTEGER; - C_POR_MODE : INTEGER; - C_AMPLITUDE : INTEGER; - C_HAS_ACLKEN : INTEGER; - C_HAS_ARESETN : INTEGER; - C_HAS_TLAST : INTEGER; - C_HAS_TREADY : INTEGER; - C_HAS_S_PHASE : INTEGER; - C_S_PHASE_TDATA_WIDTH : INTEGER; - C_S_PHASE_HAS_TUSER : INTEGER; - C_S_PHASE_TUSER_WIDTH : INTEGER; - C_HAS_S_CONFIG : INTEGER; - C_S_CONFIG_SYNC_MODE : INTEGER; - C_S_CONFIG_TDATA_WIDTH : INTEGER; - C_HAS_M_DATA : INTEGER; - C_M_DATA_TDATA_WIDTH : INTEGER; - C_M_DATA_HAS_TUSER : INTEGER; - C_M_DATA_TUSER_WIDTH : INTEGER; - C_HAS_M_PHASE : INTEGER; - C_M_PHASE_TDATA_WIDTH : INTEGER; - C_M_PHASE_HAS_TUSER : INTEGER; - C_M_PHASE_TUSER_WIDTH : INTEGER; - C_DEBUG_INTERFACE : INTEGER; - C_CHAN_WIDTH : INTEGER - ); - PORT ( - aclk : IN STD_LOGIC; - aclken : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - s_axis_phase_tvalid : IN STD_LOGIC; - s_axis_phase_tready : OUT STD_LOGIC; - s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - s_axis_phase_tlast : IN STD_LOGIC; - s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - s_axis_config_tvalid : IN STD_LOGIC; - s_axis_config_tready : OUT STD_LOGIC; - s_axis_config_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - s_axis_config_tlast : IN STD_LOGIC; - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tready : IN STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - m_axis_data_tlast : OUT STD_LOGIC; - m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - m_axis_phase_tvalid : OUT STD_LOGIC; - m_axis_phase_tready : IN STD_LOGIC; - m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axis_phase_tlast : OUT STD_LOGIC; - m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - event_pinc_invalid : OUT STD_LOGIC; - event_poff_invalid : OUT STD_LOGIC; - event_phase_in_invalid : OUT STD_LOGIC; - event_s_phase_tlast_missing : OUT STD_LOGIC; - event_s_phase_tlast_unexpected : OUT STD_LOGIC; - event_s_phase_chanid_incorrect : OUT STD_LOGIC; - event_s_config_tlast_missing : OUT STD_LOGIC; - event_s_config_tlast_unexpected : OUT STD_LOGIC - ); - END COMPONENT dds_compiler_v6_0_18; - ATTRIBUTE X_INTERFACE_INFO : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER : STRING; - ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TDATA"; - ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_phase_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_PHASE, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID"; - ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; - ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; - ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TDATA"; - ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_config_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CONFIG, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TVALID"; - ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; -BEGIN - U0 : dds_compiler_v6_0_18 - GENERIC MAP ( - C_XDEVICEFAMILY => "kintex7", - C_MODE_OF_OPERATION => 0, - C_MODULUS => 9, - C_ACCUMULATOR_WIDTH => 32, - C_CHANNELS => 1, - C_HAS_PHASE_OUT => 1, - C_HAS_PHASEGEN => 1, - C_HAS_SINCOS => 1, - C_LATENCY => 4, - C_MEM_TYPE => 1, - C_NEGATIVE_COSINE => 0, - C_NEGATIVE_SINE => 0, - C_NOISE_SHAPING => 0, - C_OUTPUTS_REQUIRED => 2, - C_OUTPUT_FORM => 0, - C_OUTPUT_WIDTH => 8, - C_PHASE_ANGLE_WIDTH => 8, - C_PHASE_INCREMENT => 1, - C_PHASE_INCREMENT_VALUE => "1101000110110111,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", - C_RESYNC => 0, - C_PHASE_OFFSET => 1, - C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", - C_OPTIMISE_GOAL => 0, - C_USE_DSP48 => 0, - C_POR_MODE => 0, - C_AMPLITUDE => 0, - C_HAS_ACLKEN => 0, - C_HAS_ARESETN => 0, - C_HAS_TLAST => 0, - C_HAS_TREADY => 0, - C_HAS_S_PHASE => 0, - C_S_PHASE_TDATA_WIDTH => 1, - C_S_PHASE_HAS_TUSER => 0, - C_S_PHASE_TUSER_WIDTH => 1, - C_HAS_S_CONFIG => 1, - C_S_CONFIG_SYNC_MODE => 0, - C_S_CONFIG_TDATA_WIDTH => 64, - C_HAS_M_DATA => 1, - C_M_DATA_TDATA_WIDTH => 16, - C_M_DATA_HAS_TUSER => 0, - C_M_DATA_TUSER_WIDTH => 1, - C_HAS_M_PHASE => 1, - C_M_PHASE_TDATA_WIDTH => 32, - C_M_PHASE_HAS_TUSER => 0, - C_M_PHASE_TUSER_WIDTH => 1, - C_DEBUG_INTERFACE => 0, - C_CHAN_WIDTH => 1 - ) - PORT MAP ( - aclk => aclk, - aclken => '1', - aresetn => '1', - s_axis_phase_tvalid => '0', - s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), - s_axis_phase_tlast => '0', - s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), - s_axis_config_tvalid => s_axis_config_tvalid, - s_axis_config_tdata => s_axis_config_tdata, - s_axis_config_tlast => '0', - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tready => '0', - m_axis_data_tdata => m_axis_data_tdata, - m_axis_phase_tvalid => m_axis_phase_tvalid, - m_axis_phase_tready => '0', - m_axis_phase_tdata => m_axis_phase_tdata - ); -END dds_32b_8b_comp_arch; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/dds_32b_8b_comp.veo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data.veo similarity index 75% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/dds_32b_8b_comp.veo rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data.veo index d386c461..d9de0a6a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/dds_32b_8b_comp.veo +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data.veo @@ -46,26 +46,28 @@ // // DO NOT MODIFY THIS FILE. -// IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 18 +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 4 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections // (in parentheses) to your own signal names. //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -dds_32b_8b_comp your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid - .s_axis_config_tdata(s_axis_config_tdata), // input wire [63 : 0] s_axis_config_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata), // output wire [15 : 0] m_axis_data_tdata - .m_axis_phase_tvalid(m_axis_phase_tvalid), // output wire m_axis_phase_tvalid - .m_axis_phase_tdata(m_axis_phase_tdata) // output wire [31 : 0] m_axis_phase_tdata +fifo_rx_data your_instance_name ( + .rst(rst), // input wire rst + .wr_clk(wr_clk), // input wire wr_clk + .rd_clk(rd_clk), // input wire rd_clk + .din(din), // input wire [95 : 0] din + .wr_en(wr_en), // input wire wr_en + .rd_en(rd_en), // input wire rd_en + .dout(dout), // output wire [95 : 0] dout + .full(full), // output wire full + .empty(empty) // output wire empty ); // INST_TAG_END ------ End INSTANTIATION Template --------- -// You must compile the wrapper file dds_32b_8b_comp.v when simulating -// the core, dds_32b_8b_comp. When compiling the wrapper file, be sure to +// You must compile the wrapper file fifo_rx_data.v when simulating +// the core, fifo_rx_data. When compiling the wrapper file, be sure to // reference the Verilog simulation library. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data.vho b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data.vho new file mode 100644 index 00000000..5bdcf3dc --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data.vho @@ -0,0 +1,91 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT fifo_rx_data + PORT ( + rst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(95 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_rx_data + PORT MAP ( + rst => rst, + wr_clk => wr_clk, + rd_clk => rd_clk, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file fifo_rx_data.vhd when simulating +-- the core, fifo_rx_data. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_sim_netlist.v new file mode 100644 index 00000000..f8ebe84d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c045e1dbd6d623be59942e501ae9331d174a02d6ff7537125f01fcdff7944a7e +size 141399 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_sim_netlist.vhdl new file mode 100644 index 00000000..544d26e3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ab1d169eb1f1cc2f544dd343e261187a2808e901bf0371c80006113153a67a8c +size 218893 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_stub.v new file mode 100644 index 00000000..6dc32dc5 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_stub.v @@ -0,0 +1,29 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:08:03 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.v +// Design : fifo_rx_data +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *) +module fifo_rx_data(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty) +/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[95:0],wr_en,rd_en,dout[95:0],full,empty" */; + input rst; + input wr_clk; + input rd_clk; + input [95:0]din; + input wr_en; + input rd_en; + output [95:0]dout; + output full; + output empty; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_stub.vhdl new file mode 100644 index 00000000..79d3bbca --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_stub.vhdl @@ -0,0 +1,38 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:08:04 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.vhdl +-- Design : fifo_rx_data +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity fifo_rx_data is + Port ( + rst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 95 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 95 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC + ); + +end fifo_rx_data; + +architecture stub of fifo_rx_data is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[95:0],wr_en,rd_en,dout[95:0],full,empty"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/sim/fifo_rx_data.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/sim/fifo_rx_data.v new file mode 100644 index 00000000..97f77ec5 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/sim/fifo_rx_data.v @@ -0,0 +1,524 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 4 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module fifo_rx_data ( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty +); + +input wire rst; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *) +input wire wr_clk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *) +input wire rd_clk; +(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) +input wire [95 : 0] din; +(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) +input wire wr_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) +input wire rd_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) +output wire [95 : 0] dout; +(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) +output wire full; +(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) +output wire empty; + + fifo_generator_v13_2_4 #( + .C_COMMON_CLOCK(0), + .C_SELECT_XPM(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(4), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(96), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(96), + .C_ENABLE_RLOCS(0), + .C_FAMILY("kintex7"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(2), + .C_MIF_FILE_NAME("BlankString"), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(1), + .C_PRELOAD_REGS(0), + .C_PRIM_FIFO_TYPE("512x72"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(2), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(3), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(13), + .C_PROG_FULL_THRESH_NEGATE_VAL(12), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(4), + .C_RD_DEPTH(16), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(4), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_PIPELINE_REG(0), + .C_POWER_SAVING_MODE(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(4), + .C_WR_DEPTH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(4), + .C_WR_RESPONSE_LATENCY(1), + .C_MSGON_VAL(1), + .C_ENABLE_RST_SYNC(1), + .C_EN_SAFETY_CKT(0), + .C_ERROR_INJECTION_TYPE(0), + .C_SYNCHRONIZER_STAGE(3), + .C_INTERFACE_TYPE(0), + .C_AXI_TYPE(1), + .C_HAS_AXI_WR_CHANNEL(1), + .C_HAS_AXI_RD_CHANNEL(1), + .C_HAS_SLAVE_CE(0), + .C_HAS_MASTER_CE(0), + .C_ADD_NGC_CONSTRAINT(0), + .C_USE_COMMON_OVERFLOW(0), + .C_USE_COMMON_UNDERFLOW(0), + .C_USE_DEFAULT_SETTINGS(0), + .C_AXI_ID_WIDTH(1), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_DATA_WIDTH(64), + .C_AXI_LEN_WIDTH(8), + .C_AXI_LOCK_WIDTH(1), + .C_HAS_AXI_ID(0), + .C_HAS_AXI_AWUSER(0), + .C_HAS_AXI_WUSER(0), + .C_HAS_AXI_BUSER(0), + .C_HAS_AXI_ARUSER(0), + .C_HAS_AXI_RUSER(0), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_WUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_AXI_RUSER_WIDTH(1), + .C_HAS_AXIS_TDATA(1), + .C_HAS_AXIS_TID(0), + .C_HAS_AXIS_TDEST(0), + .C_HAS_AXIS_TUSER(1), + .C_HAS_AXIS_TREADY(1), + .C_HAS_AXIS_TLAST(0), + .C_HAS_AXIS_TSTRB(0), + .C_HAS_AXIS_TKEEP(0), + .C_AXIS_TDATA_WIDTH(8), + .C_AXIS_TID_WIDTH(1), + .C_AXIS_TDEST_WIDTH(1), + .C_AXIS_TUSER_WIDTH(4), + .C_AXIS_TSTRB_WIDTH(1), + .C_AXIS_TKEEP_WIDTH(1), + .C_WACH_TYPE(0), + .C_WDCH_TYPE(0), + .C_WRCH_TYPE(0), + .C_RACH_TYPE(0), + .C_RDCH_TYPE(0), + .C_AXIS_TYPE(0), + .C_IMPLEMENTATION_TYPE_WACH(1), + .C_IMPLEMENTATION_TYPE_WDCH(1), + .C_IMPLEMENTATION_TYPE_WRCH(1), + .C_IMPLEMENTATION_TYPE_RACH(1), + .C_IMPLEMENTATION_TYPE_RDCH(1), + .C_IMPLEMENTATION_TYPE_AXIS(1), + .C_APPLICATION_TYPE_WACH(0), + .C_APPLICATION_TYPE_WDCH(0), + .C_APPLICATION_TYPE_WRCH(0), + .C_APPLICATION_TYPE_RACH(0), + .C_APPLICATION_TYPE_RDCH(0), + .C_APPLICATION_TYPE_AXIS(0), + .C_PRIM_FIFO_TYPE_WACH("512x36"), + .C_PRIM_FIFO_TYPE_WDCH("1kx36"), + .C_PRIM_FIFO_TYPE_WRCH("512x36"), + .C_PRIM_FIFO_TYPE_RACH("512x36"), + .C_PRIM_FIFO_TYPE_RDCH("1kx36"), + .C_PRIM_FIFO_TYPE_AXIS("1kx18"), + .C_USE_ECC_WACH(0), + .C_USE_ECC_WDCH(0), + .C_USE_ECC_WRCH(0), + .C_USE_ECC_RACH(0), + .C_USE_ECC_RDCH(0), + .C_USE_ECC_AXIS(0), + .C_ERROR_INJECTION_TYPE_WACH(0), + .C_ERROR_INJECTION_TYPE_WDCH(0), + .C_ERROR_INJECTION_TYPE_WRCH(0), + .C_ERROR_INJECTION_TYPE_RACH(0), + .C_ERROR_INJECTION_TYPE_RDCH(0), + .C_ERROR_INJECTION_TYPE_AXIS(0), + .C_DIN_WIDTH_WACH(1), + .C_DIN_WIDTH_WDCH(64), + .C_DIN_WIDTH_WRCH(2), + .C_DIN_WIDTH_RACH(32), + .C_DIN_WIDTH_RDCH(64), + .C_DIN_WIDTH_AXIS(1), + .C_WR_DEPTH_WACH(16), + .C_WR_DEPTH_WDCH(1024), + .C_WR_DEPTH_WRCH(16), + .C_WR_DEPTH_RACH(16), + .C_WR_DEPTH_RDCH(1024), + .C_WR_DEPTH_AXIS(1024), + .C_WR_PNTR_WIDTH_WACH(4), + .C_WR_PNTR_WIDTH_WDCH(10), + .C_WR_PNTR_WIDTH_WRCH(4), + .C_WR_PNTR_WIDTH_RACH(4), + .C_WR_PNTR_WIDTH_RDCH(10), + .C_WR_PNTR_WIDTH_AXIS(10), + .C_HAS_DATA_COUNTS_WACH(0), + .C_HAS_DATA_COUNTS_WDCH(0), + .C_HAS_DATA_COUNTS_WRCH(0), + .C_HAS_DATA_COUNTS_RACH(0), + .C_HAS_DATA_COUNTS_RDCH(0), + .C_HAS_DATA_COUNTS_AXIS(0), + .C_HAS_PROG_FLAGS_WACH(0), + .C_HAS_PROG_FLAGS_WDCH(0), + .C_HAS_PROG_FLAGS_WRCH(0), + .C_HAS_PROG_FLAGS_RACH(0), + .C_HAS_PROG_FLAGS_RDCH(0), + .C_HAS_PROG_FLAGS_AXIS(0), + .C_PROG_FULL_TYPE_WACH(0), + .C_PROG_FULL_TYPE_WDCH(0), + .C_PROG_FULL_TYPE_WRCH(0), + .C_PROG_FULL_TYPE_RACH(0), + .C_PROG_FULL_TYPE_RDCH(0), + .C_PROG_FULL_TYPE_AXIS(0), + .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), + .C_PROG_EMPTY_TYPE_WACH(0), + .C_PROG_EMPTY_TYPE_WDCH(0), + .C_PROG_EMPTY_TYPE_WRCH(0), + .C_PROG_EMPTY_TYPE_RACH(0), + .C_PROG_EMPTY_TYPE_RDCH(0), + .C_PROG_EMPTY_TYPE_AXIS(0), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), + .C_REG_SLICE_MODE_WACH(0), + .C_REG_SLICE_MODE_WDCH(0), + .C_REG_SLICE_MODE_WRCH(0), + .C_REG_SLICE_MODE_RACH(0), + .C_REG_SLICE_MODE_RDCH(0), + .C_REG_SLICE_MODE_AXIS(0) + ) inst ( + .backup(1'D0), + .backup_marker(1'D0), + .clk(1'D0), + .rst(rst), + .srst(1'D0), + .wr_clk(wr_clk), + .wr_rst(1'D0), + .rd_clk(rd_clk), + .rd_rst(1'D0), + .din(din), + .wr_en(wr_en), + .rd_en(rd_en), + .prog_empty_thresh(4'B0), + .prog_empty_thresh_assert(4'B0), + .prog_empty_thresh_negate(4'B0), + .prog_full_thresh(4'B0), + .prog_full_thresh_assert(4'B0), + .prog_full_thresh_negate(4'B0), + .int_clk(1'D0), + .injectdbiterr(1'D0), + .injectsbiterr(1'D0), + .sleep(1'D0), + .dout(dout), + .full(full), + .almost_full(), + .wr_ack(), + .overflow(), + .empty(empty), + .almost_empty(), + .valid(), + .underflow(), + .data_count(), + .rd_data_count(), + .wr_data_count(), + .prog_full(), + .prog_empty(), + .sbiterr(), + .dbiterr(), + .wr_rst_busy(), + .rd_rst_busy(), + .m_aclk(1'D0), + .s_aclk(1'D0), + .s_aresetn(1'D0), + .m_aclk_en(1'D0), + .s_aclk_en(1'D0), + .s_axi_awid(1'B0), + .s_axi_awaddr(32'B0), + .s_axi_awlen(8'B0), + .s_axi_awsize(3'B0), + .s_axi_awburst(2'B0), + .s_axi_awlock(1'B0), + .s_axi_awcache(4'B0), + .s_axi_awprot(3'B0), + .s_axi_awqos(4'B0), + .s_axi_awregion(4'B0), + .s_axi_awuser(1'B0), + .s_axi_awvalid(1'D0), + .s_axi_awready(), + .s_axi_wid(1'B0), + .s_axi_wdata(64'B0), + .s_axi_wstrb(8'B0), + .s_axi_wlast(1'D0), + .s_axi_wuser(1'B0), + .s_axi_wvalid(1'D0), + .s_axi_wready(), + .s_axi_bid(), + .s_axi_bresp(), + .s_axi_buser(), + .s_axi_bvalid(), + .s_axi_bready(1'D0), + .m_axi_awid(), + .m_axi_awaddr(), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awlock(), + .m_axi_awcache(), + .m_axi_awprot(), + .m_axi_awqos(), + .m_axi_awregion(), + .m_axi_awuser(), + .m_axi_awvalid(), + .m_axi_awready(1'D0), + .m_axi_wid(), + .m_axi_wdata(), + .m_axi_wstrb(), + .m_axi_wlast(), + .m_axi_wuser(), + .m_axi_wvalid(), + .m_axi_wready(1'D0), + .m_axi_bid(1'B0), + .m_axi_bresp(2'B0), + .m_axi_buser(1'B0), + .m_axi_bvalid(1'D0), + .m_axi_bready(), + .s_axi_arid(1'B0), + .s_axi_araddr(32'B0), + .s_axi_arlen(8'B0), + .s_axi_arsize(3'B0), + .s_axi_arburst(2'B0), + .s_axi_arlock(1'B0), + .s_axi_arcache(4'B0), + .s_axi_arprot(3'B0), + .s_axi_arqos(4'B0), + .s_axi_arregion(4'B0), + .s_axi_aruser(1'B0), + .s_axi_arvalid(1'D0), + .s_axi_arready(), + .s_axi_rid(), + .s_axi_rdata(), + .s_axi_rresp(), + .s_axi_rlast(), + .s_axi_ruser(), + .s_axi_rvalid(), + .s_axi_rready(1'D0), + .m_axi_arid(), + .m_axi_araddr(), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arlock(), + .m_axi_arcache(), + .m_axi_arprot(), + .m_axi_arqos(), + .m_axi_arregion(), + .m_axi_aruser(), + .m_axi_arvalid(), + .m_axi_arready(1'D0), + .m_axi_rid(1'B0), + .m_axi_rdata(64'B0), + .m_axi_rresp(2'B0), + .m_axi_rlast(1'D0), + .m_axi_ruser(1'B0), + .m_axi_rvalid(1'D0), + .m_axi_rready(), + .s_axis_tvalid(1'D0), + .s_axis_tready(), + .s_axis_tdata(8'B0), + .s_axis_tstrb(1'B0), + .s_axis_tkeep(1'B0), + .s_axis_tlast(1'D0), + .s_axis_tid(1'B0), + .s_axis_tdest(1'B0), + .s_axis_tuser(4'B0), + .m_axis_tvalid(), + .m_axis_tready(1'D0), + .m_axis_tdata(), + .m_axis_tstrb(), + .m_axis_tkeep(), + .m_axis_tlast(), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(), + .axi_aw_injectsbiterr(1'D0), + .axi_aw_injectdbiterr(1'D0), + .axi_aw_prog_full_thresh(4'B0), + .axi_aw_prog_empty_thresh(4'B0), + .axi_aw_data_count(), + .axi_aw_wr_data_count(), + .axi_aw_rd_data_count(), + .axi_aw_sbiterr(), + .axi_aw_dbiterr(), + .axi_aw_overflow(), + .axi_aw_underflow(), + .axi_aw_prog_full(), + .axi_aw_prog_empty(), + .axi_w_injectsbiterr(1'D0), + .axi_w_injectdbiterr(1'D0), + .axi_w_prog_full_thresh(10'B0), + .axi_w_prog_empty_thresh(10'B0), + .axi_w_data_count(), + .axi_w_wr_data_count(), + .axi_w_rd_data_count(), + .axi_w_sbiterr(), + .axi_w_dbiterr(), + .axi_w_overflow(), + .axi_w_underflow(), + .axi_w_prog_full(), + .axi_w_prog_empty(), + .axi_b_injectsbiterr(1'D0), + .axi_b_injectdbiterr(1'D0), + .axi_b_prog_full_thresh(4'B0), + .axi_b_prog_empty_thresh(4'B0), + .axi_b_data_count(), + .axi_b_wr_data_count(), + .axi_b_rd_data_count(), + .axi_b_sbiterr(), + .axi_b_dbiterr(), + .axi_b_overflow(), + .axi_b_underflow(), + .axi_b_prog_full(), + .axi_b_prog_empty(), + .axi_ar_injectsbiterr(1'D0), + .axi_ar_injectdbiterr(1'D0), + .axi_ar_prog_full_thresh(4'B0), + .axi_ar_prog_empty_thresh(4'B0), + .axi_ar_data_count(), + .axi_ar_wr_data_count(), + .axi_ar_rd_data_count(), + .axi_ar_sbiterr(), + .axi_ar_dbiterr(), + .axi_ar_overflow(), + .axi_ar_underflow(), + .axi_ar_prog_full(), + .axi_ar_prog_empty(), + .axi_r_injectsbiterr(1'D0), + .axi_r_injectdbiterr(1'D0), + .axi_r_prog_full_thresh(10'B0), + .axi_r_prog_empty_thresh(10'B0), + .axi_r_data_count(), + .axi_r_wr_data_count(), + .axi_r_rd_data_count(), + .axi_r_sbiterr(), + .axi_r_dbiterr(), + .axi_r_overflow(), + .axi_r_underflow(), + .axi_r_prog_full(), + .axi_r_prog_empty(), + .axis_injectsbiterr(1'D0), + .axis_injectdbiterr(1'D0), + .axis_prog_full_thresh(10'B0), + .axis_prog_empty_thresh(10'B0), + .axis_data_count(), + .axis_wr_data_count(), + .axis_rd_data_count(), + .axis_sbiterr(), + .axis_dbiterr(), + .axis_overflow(), + .axis_underflow(), + .axis_prog_full(), + .axis_prog_empty() + ); +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/demo_tb/tb_fir_prbs7_invert_rep4.vhd b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/demo_tb/tb_fir_prbs10_invert_rep2.vhd similarity index 93% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/demo_tb/tb_fir_prbs7_invert_rep4.vhd rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/demo_tb/tb_fir_prbs10_invert_rep2.vhd index 95825970..77c31b49 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/demo_tb/tb_fir_prbs7_invert_rep4.vhd +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/demo_tb/tb_fir_prbs10_invert_rep2.vhd @@ -60,7 +60,7 @@ -- Using this testbench -- -- This testbench instantiates your generated FIR Compiler core --- instance named "fir_prbs7_invert_rep4". +-- instance named "fir_prbs10_invert_rep2". -- -- Use Vivado's Run Simulation flow to run this testbench. See the Vivado -- documentation for details. @@ -70,10 +70,10 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -entity tb_fir_prbs7_invert_rep4 is -end tb_fir_prbs7_invert_rep4; +entity tb_fir_prbs10_invert_rep2 is +end tb_fir_prbs10_invert_rep2; -architecture tb of tb_fir_prbs7_invert_rep4 is +architecture tb of tb_fir_prbs10_invert_rep2 is ----------------------------------------------------------------------- -- Timing constants @@ -110,7 +110,7 @@ architecture tb of tb_fir_prbs7_invert_rep4 is signal s_axis_data_tdata_data : std_logic_vector(11 downto 0) := (others => '0'); -- Data master channel alias signals - signal m_axis_data_tdata_data : std_logic_vector(20 downto 0) := (others => '0'); + signal m_axis_data_tdata_data : std_logic_vector(22 downto 0) := (others => '0'); begin @@ -119,7 +119,7 @@ begin -- Instantiate the DUT ----------------------------------------------------------------------- - dut : entity work.fir_prbs7_invert_rep4 + dut : entity work.fir_prbs10_invert_rep2 port map ( aclk => aclk, aresetn => aresetn, @@ -169,9 +169,9 @@ begin end loop; ip_count := ip_count + 1; wait for T_HOLD; - -- Input rate is 1 input each 2 clock cycles: drive valid inputs at this rate + -- Input rate is 1 input each 16 clock cycles: drive valid inputs at this rate s_axis_data_tvalid <= '0'; - wait for CLOCK_PERIOD * 1; + wait for CLOCK_PERIOD * 15; exit when ip_count >= samples; end loop; end procedure drive_data; @@ -185,7 +185,7 @@ begin -- Procedure to drive an impulse and let the impulse response emerge on the data master channel -- samples is the number of input samples to drive; default is enough for impulse response output to emerge - procedure drive_impulse ( samples : natural := 651 ) is + procedure drive_impulse ( samples : natural := 2062 ) is variable impulse : std_logic_vector(15 downto 0); begin impulse := (others => '0'); -- initialize unused bits to zero @@ -208,15 +208,15 @@ begin -- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals drive_impulse(2); -- start of impulse; data is now zero s_axis_data_tvalid <= '0'; - wait for CLOCK_PERIOD * 10; -- provide no data for 5 input samples worth + wait for CLOCK_PERIOD * 80; -- provide no data for 5 input samples worth drive_zeros(2); -- 2 normal input samples s_axis_data_tvalid <= '1'; - wait for CLOCK_PERIOD * 10; -- provide data as fast as the core can accept it for 5 input samples worth - drive_zeros(642); -- back to normal operation + wait for CLOCK_PERIOD * 80; -- provide data as fast as the core can accept it for 5 input samples worth + drive_zeros(2053); -- back to normal operation -- Drive another impulse, during which demonstrate: -- reset (aresetn) - drive_impulse(262); -- to partway through impulse response + drive_impulse(521); -- to partway through impulse response s_axis_data_tvalid <= '0'; aresetn <= '0'; -- assert reset (active low) wait for CLOCK_PERIOD * 2; -- hold reset active for 2 clock cycles, as recommended in FIR Compiler Datasheet @@ -267,6 +267,6 @@ begin s_axis_data_tdata_data <= s_axis_data_tdata(11 downto 0); -- Data master channel alias signals: update these only when they are valid - m_axis_data_tdata_data <= m_axis_data_tdata(20 downto 0) when m_axis_data_tvalid = '1'; + m_axis_data_tdata_data <= m_axis_data_tdata(22 downto 0) when m_axis_data_tvalid = '1'; end tb; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4.veo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.veo similarity index 94% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4.veo rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.veo index e25645da..b8f870a1 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4.veo +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.veo @@ -54,7 +54,7 @@ // (in parentheses) to your own signal names. //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fir_prbs7_invert_rep4 your_instance_name ( +fir_prbs10_invert_rep2 your_instance_name ( .aresetn(aresetn), // input wire aresetn .aclk(aclk), // input wire aclk .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid @@ -65,7 +65,7 @@ fir_prbs7_invert_rep4 your_instance_name ( ); // INST_TAG_END ------ End INSTANTIATION Template --------- -// You must compile the wrapper file fir_prbs7_invert_rep4.v when simulating -// the core, fir_prbs7_invert_rep4. When compiling the wrapper file, be sure to +// You must compile the wrapper file fir_prbs10_invert_rep2.v when simulating +// the core, fir_prbs10_invert_rep2. When compiling the wrapper file, be sure to // reference the Verilog simulation library. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4.vho b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.vho similarity index 93% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4.vho rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.vho index ba78d6d8..9c031bab 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4.vho +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.vho @@ -52,7 +52,7 @@ -- The following code must appear in the VHDL architecture header. ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT fir_prbs7_invert_rep4 +COMPONENT fir_prbs10_invert_rep2 PORT ( aresetn : IN STD_LOGIC; aclk : IN STD_LOGIC; @@ -69,7 +69,7 @@ END COMPONENT; -- body. Substitute your own instance name and net names. ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : fir_prbs7_invert_rep4 +your_instance_name : fir_prbs10_invert_rep2 PORT MAP ( aresetn => aresetn, aclk => aclk, @@ -81,7 +81,7 @@ your_instance_name : fir_prbs7_invert_rep4 ); -- INST_TAG_END ------ End INSTANTIATION Template --------- --- You must compile the wrapper file fir_prbs7_invert_rep4.vhd when simulating --- the core, fir_prbs7_invert_rep4. When compiling the wrapper file, be sure to +-- You must compile the wrapper file fir_prbs10_invert_rep2.vhd when simulating +-- the core, fir_prbs10_invert_rep2. When compiling the wrapper file, be sure to -- reference the VHDL simulation library. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_sim_netlist.v new file mode 100644 index 00000000..a873d67d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7eebab10140c57d453e3d92224f3b5fec9139fc31309a8f522a672f514788fe4 +size 6464147 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_sim_netlist.vhdl new file mode 100644 index 00000000..eca6dd9a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8d2e59eae4787eafe8638f7fbb7dd093f1697da0b3f8c0c300c196e0cc4ebfb2 +size 9196281 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/dds_32b_8b_comp_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_stub.v similarity index 59% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/dds_32b_8b_comp_stub.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_stub.v index 8dea4d6d..91a01ee8 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/dds_32b_8b_comp_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_stub.v @@ -1,11 +1,11 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 00:29:10 2023 +// Date : Fri May 12 16:05:14 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.v -// Design : dds_32b_8b_comp +// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.v +// Design : fir_prbs10_invert_rep2 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 // -------------------------------------------------------------------------------- @@ -13,16 +13,15 @@ // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "dds_compiler_v6_0_18,Vivado 2019.1.3" *) -module dds_32b_8b_comp(aclk, s_axis_config_tvalid, - s_axis_config_tdata, m_axis_data_tvalid, m_axis_data_tdata, m_axis_phase_tvalid, - m_axis_phase_tdata) -/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tvalid,s_axis_config_tdata[63:0],m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0]" */; +(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) +module fir_prbs10_invert_rep2(aresetn, aclk, s_axis_data_tvalid, + s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) +/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */; + input aresetn; input aclk; - input s_axis_config_tvalid; - input [63:0]s_axis_config_tdata; + input s_axis_data_tvalid; + output s_axis_data_tready; + input [15:0]s_axis_data_tdata; output m_axis_data_tvalid; - output [15:0]m_axis_data_tdata; - output m_axis_phase_tvalid; - output [31:0]m_axis_phase_tdata; + output [23:0]m_axis_data_tdata; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_stub.vhdl similarity index 55% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.vhdl rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_stub.vhdl index 4db19e1c..656c5a79 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_stub.vhdl @@ -1,36 +1,36 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 00:29:10 2023 +-- Date : Fri May 12 16:05:14 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.vhdl --- Design : dds_32b_8b_comp +-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.vhdl +-- Design : fir_prbs10_invert_rep2 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -entity dds_32b_8b_comp is +entity fir_prbs10_invert_rep2 is Port ( + aresetn : in STD_LOGIC; aclk : in STD_LOGIC; - s_axis_config_tvalid : in STD_LOGIC; - s_axis_config_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_data_tvalid : in STD_LOGIC; + s_axis_data_tready : out STD_LOGIC; + s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); - m_axis_phase_tvalid : out STD_LOGIC; - m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) + m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ) ); -end dds_32b_8b_comp; +end fir_prbs10_invert_rep2; -architecture stub of dds_32b_8b_comp is +architecture stub of fir_prbs10_invert_rep2 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_config_tvalid,s_axis_config_tdata[63:0],m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0]"; +attribute black_box_pad_pin of stub : architecture is "aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]"; attribute x_core_info : string; -attribute x_core_info of stub : architecture is "dds_compiler_v6_0_18,Vivado 2019.1.3"; +attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; begin end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd similarity index 93% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd index 39221785..460e37b4 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd @@ -56,7 +56,7 @@ USE ieee.numeric_std.ALL; LIBRARY fir_compiler_v7_2_12; USE fir_compiler_v7_2_12.fir_compiler_v7_2_12; -ENTITY fir_prbs7_invert_rep4 IS +ENTITY fir_prbs10_invert_rep2 IS PORT ( aresetn : IN STD_LOGIC; aclk : IN STD_LOGIC; @@ -66,11 +66,11 @@ ENTITY fir_prbs7_invert_rep4 IS m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); -END fir_prbs7_invert_rep4; +END fir_prbs10_invert_rep2; -ARCHITECTURE fir_prbs7_invert_rep4_arch OF fir_prbs7_invert_rep4 IS +ARCHITECTURE fir_prbs10_invert_rep2_arch OF fir_prbs10_invert_rep2 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; - ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_prbs7_invert_rep4_arch: ARCHITECTURE IS "yes"; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_prbs10_invert_rep2_arch: ARCHITECTURE IS "yes"; COMPONENT fir_compiler_v7_2_12 IS GENERIC ( C_XDEVICEFAMILY : STRING; @@ -193,16 +193,16 @@ BEGIN GENERIC MAP ( C_XDEVICEFAMILY => "kintex7", C_ELABORATION_DIR => "./", - C_COMPONENT_NAME => "fir_prbs7_invert_rep4", - C_COEF_FILE => "fir_prbs7_invert_rep4.mif", - C_COEF_FILE_LINES => 512, + C_COMPONENT_NAME => "fir_prbs10_invert_rep2", + C_COEF_FILE => "fir_prbs10_invert_rep2.mif", + C_COEF_FILE_LINES => 2048, C_FILTER_TYPE => 0, C_INTERP_RATE => 1, C_DECIM_RATE => 1, C_ZERO_PACKING_FACTOR => 1, C_SYMMETRY => 0, C_NUM_FILTS => 1, - C_NUM_TAPS => 512, + C_NUM_TAPS => 2048, C_NUM_CHANNELS => 1, C_CHANNEL_PATTERN => "fixed", C_ROUND_MODE => 0, @@ -210,7 +210,7 @@ BEGIN C_NUM_RELOAD_SLOTS => 1, C_COL_MODE => 1, C_COL_PIPE_LEN => 4, - C_COL_CONFIG => "140,116", + C_COL_CONFIG => "128", C_OPTIMIZATION => 0, C_DATA_PATH_WIDTHS => "12", C_DATA_IP_PATH_WIDTHS => "12", @@ -223,18 +223,18 @@ BEGIN C_PX_PATH_SRC => "0", C_DATA_PATH_SIGN => "0", C_COEF_PATH_SIGN => "0", - C_ACCUM_PATH_WIDTHS => "21", - C_OUTPUT_WIDTH => 21, - C_OUTPUT_PATH_WIDTHS => "21", - C_ACCUM_OP_PATH_WIDTHS => "21", + C_ACCUM_PATH_WIDTHS => "23", + C_OUTPUT_WIDTH => 23, + C_OUTPUT_PATH_WIDTHS => "23", + C_ACCUM_OP_PATH_WIDTHS => "23", C_EXT_MULT_CNFG => "none", C_DATA_PATH_PSAMP_SRC => "0", C_OP_PATH_PSAMP_SRC => "0", - C_NUM_MADDS => 256, + C_NUM_MADDS => 128, C_OPT_MADDS => "none", - C_OVERSAMPLING_RATE => 2, - C_INPUT_RATE => 2, - C_OUTPUT_RATE => 2, + C_OVERSAMPLING_RATE => 16, + C_INPUT_RATE => 16, + C_OUTPUT_RATE => 16, C_DATA_MEMTYPE => 0, C_COEF_MEMTYPE => 2, C_IPBUFF_MEMTYPE => 2, @@ -244,7 +244,7 @@ BEGIN C_DATA_MEM_PACKING => 0, C_COEF_MEM_PACKING => 0, C_FILTS_PACKED => 0, - C_LATENCY => 269, + C_LATENCY => 151, C_HAS_ARESETn => 1, C_HAS_ACLKEN => 0, C_DATA_HAS_TLAST => 0, @@ -281,4 +281,4 @@ BEGIN m_axis_data_tready => '1', m_axis_data_tdata => m_axis_data_tdata ); -END fir_prbs7_invert_rep4_arch; +END fir_prbs10_invert_rep2_arch; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_sim_netlist.v deleted file mode 100644 index 06ce6714..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:4e8849873bf864661b94d142e32f5e66479aa8a37841ac0552f47ccaa52eda4e -size 11474365 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_sim_netlist.vhdl deleted file mode 100644 index 50662ae5..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:b38ce17b1a5c15bca87ad96b79875838d3667985234c7f66ccea132901f5372a -size 16671368 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp.veo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp.veo index da7c7ebc..ff734bd7 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp.veo +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp.veo @@ -57,7 +57,7 @@ ila_freq_comp your_instance_name ( .clk(clk), // input wire clk - .probe0(probe0), // input wire [17:0] probe0 + .probe0(probe0), // input wire [0:0] probe0 .probe1(probe1), // input wire [17:0] probe1 .probe2(probe2), // input wire [17:0] probe2 .probe3(probe3), // input wire [17:0] probe3 @@ -66,19 +66,18 @@ ila_freq_comp your_instance_name ( .probe6(probe6), // input wire [17:0] probe6 .probe7(probe7), // input wire [17:0] probe7 .probe8(probe8), // input wire [17:0] probe8 - .probe9(probe9), // input wire [2:0] probe9 - .probe10(probe10), // input wire [0:0] probe10 - .probe11(probe11), // input wire [0:0] probe11 - .probe12(probe12), // input wire [0:0] probe12 - .probe13(probe13), // input wire [31:0] probe13 - .probe14(probe14), // input wire [0:0] probe14 - .probe15(probe15), // input wire [31:0] probe15 + .probe9(probe9), // input wire [10:0] probe9 + .probe10(probe10), // input wire [10:0] probe10 + .probe11(probe11), // input wire [10:0] probe11 + .probe12(probe12), // input wire [10:0] probe12 + .probe13(probe13), // input wire [0:0] probe13 + .probe14(probe14), // input wire [2:0] probe14 + .probe15(probe15), // input wire [11:0] probe15 .probe16(probe16), // input wire [11:0] probe16 - .probe17(probe17), // input wire [11:0] probe17 - .probe18(probe18), // input wire [9:0] probe18 - .probe19(probe19), // input wire [9:0] probe19 - .probe20(probe20), // input wire [9:0] probe20 - .probe21(probe21) // input wire [9:0] probe21 + .probe17(probe17), // input wire [17:0] probe17 + .probe18(probe18), // input wire [17:0] probe18 + .probe19(probe19), // input wire [31:0] probe19 + .probe20(probe20) // input wire [11:0] probe20 ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.v index 4f923514..2c7ee1a9 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e8e7200f4395edba4481919e098863a6a7fd3778af090109fcee96297f7db274 -size 18011561 +oid sha256:89c5e821de1bbd17ea62f021a9991db343820db0f85a52c7312ce1c5d1a70a25 +size 12146898 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.vhdl index 578dac67..7440011d 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f141430a5a41fde5e9944483f8cda8a2648c839774ff52828aed356e6de3dcfd -size 21597145 +oid sha256:a17d9c1e5462a5933eb41329e115f3eae9713ad2775740a719930a516b4e7daf +size 15059408 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.v index df69028e..057f4af7 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 12:16:12 2023 +// Date : Fri May 12 16:06:03 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v @@ -16,10 +16,10 @@ (* X_CORE_INFO = "ila,Vivado 2019.1.3" *) module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5, probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, - probe18, probe19, probe20, probe21) -/* synthesis syn_black_box black_box_pad_pin="clk,probe0[17:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[2:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[31:0],probe14[0:0],probe15[31:0],probe16[11:0],probe17[11:0],probe18[9:0],probe19[9:0],probe20[9:0],probe21[9:0]" */; + probe18, probe19, probe20) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[10:0],probe10[10:0],probe11[10:0],probe12[10:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[31:0],probe20[11:0]" */; input clk; - input [17:0]probe0; + input [0:0]probe0; input [17:0]probe1; input [17:0]probe2; input [17:0]probe3; @@ -28,17 +28,16 @@ module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5, input [17:0]probe6; input [17:0]probe7; input [17:0]probe8; - input [2:0]probe9; - input [0:0]probe10; - input [0:0]probe11; - input [0:0]probe12; - input [31:0]probe13; - input [0:0]probe14; - input [31:0]probe15; + input [10:0]probe9; + input [10:0]probe10; + input [10:0]probe11; + input [10:0]probe12; + input [0:0]probe13; + input [2:0]probe14; + input [11:0]probe15; input [11:0]probe16; - input [11:0]probe17; - input [9:0]probe18; - input [9:0]probe19; - input [9:0]probe20; - input [9:0]probe21; + input [17:0]probe17; + input [17:0]probe18; + input [31:0]probe19; + input [11:0]probe20; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.vhdl index 2531f1e9..51c469a0 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 12:16:12 2023 +-- Date : Fri May 12 16:06:03 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl @@ -15,7 +15,7 @@ use IEEE.STD_LOGIC_1164.ALL; entity ila_freq_comp is Port ( clk : in STD_LOGIC; - probe0 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 ); probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 ); probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 ); @@ -24,19 +24,18 @@ entity ila_freq_comp is probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 ); probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 ); probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 ); - probe9 : in STD_LOGIC_VECTOR ( 2 downto 0 ); - probe10 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe11 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe12 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe13 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - probe14 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe15 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe12 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe13 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe14 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + probe15 : in STD_LOGIC_VECTOR ( 11 downto 0 ); probe16 : in STD_LOGIC_VECTOR ( 11 downto 0 ); - probe17 : in STD_LOGIC_VECTOR ( 11 downto 0 ); - probe18 : in STD_LOGIC_VECTOR ( 9 downto 0 ); - probe19 : in STD_LOGIC_VECTOR ( 9 downto 0 ); - probe20 : in STD_LOGIC_VECTOR ( 9 downto 0 ); - probe21 : in STD_LOGIC_VECTOR ( 9 downto 0 ) + probe17 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe18 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe19 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe20 : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end ila_freq_comp; @@ -45,7 +44,7 @@ architecture stub of ila_freq_comp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe0[17:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[2:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[31:0],probe14[0:0],probe15[31:0],probe16[11:0],probe17[11:0],probe18[9:0],probe19[9:0],probe20[9:0],probe21[9:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[10:0],probe10[10:0],probe11[10:0],probe12[10:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[31:0],probe20[11:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/sim/ila_freq_comp.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/sim/ila_freq_comp.v index 3c6dd99f..a19f4753 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/sim/ila_freq_comp.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_freq_comp/sim/ila_freq_comp.v @@ -70,14 +70,13 @@ probe16, probe17, probe18, probe19, -probe20, -probe21 +probe20 ); input clk; -input [17 : 0] probe0; +input [0 : 0] probe0; input [17 : 0] probe1; input [17 : 0] probe2; input [17 : 0] probe3; @@ -86,19 +85,18 @@ input [17 : 0] probe5; input [17 : 0] probe6; input [17 : 0] probe7; input [17 : 0] probe8; -input [2 : 0] probe9; -input [0 : 0] probe10; -input [0 : 0] probe11; -input [0 : 0] probe12; -input [31 : 0] probe13; -input [0 : 0] probe14; -input [31 : 0] probe15; +input [10 : 0] probe9; +input [10 : 0] probe10; +input [10 : 0] probe11; +input [10 : 0] probe12; +input [0 : 0] probe13; +input [2 : 0] probe14; +input [11 : 0] probe15; input [11 : 0] probe16; -input [11 : 0] probe17; -input [9 : 0] probe18; -input [9 : 0] probe19; -input [9 : 0] probe20; -input [9 : 0] probe21; +input [17 : 0] probe17; +input [17 : 0] probe18; +input [31 : 0] probe19; +input [11 : 0] probe20; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control.veo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control.veo new file mode 100644 index 00000000..69b64ac2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control.veo @@ -0,0 +1,74 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + +ila_rf_auto_control your_instance_name ( + .clk(clk), // input wire clk + + + .probe0(probe0), // input wire [0:0] probe0 + .probe1(probe1), // input wire [31:0] probe1 + .probe2(probe2), // input wire [31:0] probe2 + .probe3(probe3), // input wire [0:0] probe3 + .probe4(probe4), // input wire [0:0] probe4 + .probe5(probe5) // input wire [7:0] probe5 +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file ila_rf_auto_control when simulating +// the core, ila_rf_auto_control. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_sim_netlist.v new file mode 100644 index 00000000..6f425552 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fd00fae9279829fda4b4e1885ebe5256e00b408d06eb2cd8357fbb8c7b2e3412 +size 3340781 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_sim_netlist.vhdl new file mode 100644 index 00000000..83d015ce --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2773b07ea9fba2823d7714c5628c03c1b356e5468d20ea057d97aa443968d0e0 +size 5402482 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_stub.v new file mode 100644 index 00000000..2e98375f --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:03:15 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.v +// Design : ila_rf_auto_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_rf_auto_control(clk, probe0, probe1, probe2, probe3, probe4, probe5) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]" */; + input clk; + input [0:0]probe0; + input [31:0]probe1; + input [31:0]probe2; + input [0:0]probe3; + input [0:0]probe4; + input [7:0]probe5; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_stub.vhdl new file mode 100644 index 00000000..9748e094 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/ila_rf_auto_control_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:03:15 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.vhdl +-- Design : ila_rf_auto_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_rf_auto_control is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe4 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + +end ila_rf_auto_control; + +architecture stub of ila_rf_auto_control is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/sim/ila_rf_auto_control.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/sim/ila_rf_auto_control.v new file mode 100644 index 00000000..001de53c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control/sim/ila_rf_auto_control.v @@ -0,0 +1,72 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module ila_rf_auto_control ( +clk, + + +probe0, +probe1, +probe2, +probe3, +probe4, +probe5 +); + +input clk; + + +input [0 : 0] probe0; +input [31 : 0] probe1; +input [31 : 0] probe2; +input [0 : 0] probe3; +input [0 : 0] probe4; +input [7 : 0] probe5; + + +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo new file mode 100644 index 00000000..f2bdb947 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo @@ -0,0 +1,78 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + +ila_rx_data_cnt your_instance_name ( + .clk(clk), // input wire clk + + + .probe0(probe0), // input wire [11:0] probe0 + .probe1(probe1), // input wire [11:0] probe1 + .probe2(probe2), // input wire [11:0] probe2 + .probe3(probe3), // input wire [11:0] probe3 + .probe4(probe4), // input wire [11:0] probe4 + .probe5(probe5), // input wire [11:0] probe5 + .probe6(probe6), // input wire [11:0] probe6 + .probe7(probe7), // input wire [11:0] probe7 + .probe8(probe8), // input wire [11:0] probe8 + .probe9(probe9) // input wire [12:0] probe9 +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file ila_rx_data_cnt when simulating +// the core, ila_rx_data_cnt. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.v new file mode 100644 index 00000000..21ec7c01 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:02dda248f9b1a8197f772221bda8b56d04bea26b3792357949d51d05a91afa5e +size 9313152 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.vhdl new file mode 100644 index 00000000..cbfa4c7b --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:61d9c165e3418160c7fe9dc268aff1d33f63f0208399fdad58ae469efb9aaa9c +size 11856008 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v new file mode 100644 index 00000000..912209ee --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:03:10 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v +// Design : ila_rx_data_cnt +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]" */; + input clk; + input [11:0]probe0; + input [11:0]probe1; + input [11:0]probe2; + input [11:0]probe3; + input [11:0]probe4; + input [11:0]probe5; + input [11:0]probe6; + input [11:0]probe7; + input [11:0]probe8; + input [12:0]probe9; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl new file mode 100644 index 00000000..5939820e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:03:10 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl +-- Design : ila_rx_data_cnt +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_rx_data_cnt is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 ) + ); + +end ila_rx_data_cnt; + +architecture stub of ila_rx_data_cnt is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v new file mode 100644 index 00000000..8cf8464f --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module ila_rx_data_cnt ( +clk, + + +probe0, +probe1, +probe2, +probe3, +probe4, +probe5, +probe6, +probe7, +probe8, +probe9 +); + +input clk; + + +input [11 : 0] probe0; +input [11 : 0] probe1; +input [11 : 0] probe2; +input [11 : 0] probe3; +input [11 : 0] probe4; +input [11 : 0] probe5; +input [11 : 0] probe6; +input [11 : 0] probe7; +input [11 : 0] probe8; +input [12 : 0] probe9; + + +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v index a69fa1e3..500264d2 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4b4a24873a254183cff7fd29b02c4d9ab739b50e91503717fc79804b2c61dab1 +oid sha256:d505363140e83ab4ba85f39ee9c59f527bbf5844fd7a46084f7effc591c65fd3 size 28713 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl index 17de3cab..18f20291 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b005766068cddc9213805a499ec6154d69816f71aeeb6e1e36e9158c5c2ed978 +oid sha256:381310f0847e8c98a4f35bc631b3508f4fd6df934e1e070b0d680869a20b8f5e size 42212 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v index bbe2ee09..a485cca8 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 11:44:03 2023 +// Date : Fri May 12 16:06:19 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl index c01133d3..20e02f43 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 11:44:03 2023 +-- Date : Fri May 12 16:06:19 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/sim/vio_freq_comp.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/sim/vio_freq_comp.v index a849e389..c86ea40e 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/sim/vio_freq_comp.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/sim/vio_freq_comp.v @@ -52,7 +52,9 @@ probe_in0, probe_out0, probe_out1, probe_out2, -probe_out3 +probe_out3, +probe_out4, +probe_out5 ); input clk; @@ -62,6 +64,8 @@ output reg [0 : 0] probe_out0 = 'h0 ; output reg [7 : 0] probe_out1 = 'h0A ; output reg [0 : 0] probe_out2 = 'h0 ; output reg [31 : 0] probe_out3 = 'h00000000 ; +output reg [0 : 0] probe_out4 = 'h0 ; +output reg [0 : 0] probe_out5 = 'h0 ; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo index ae201a7c..6c36c182 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo @@ -60,7 +60,9 @@ vio_freq_comp your_instance_name ( .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 .probe_out1(probe_out1), // output wire [7 : 0] probe_out1 .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 - .probe_out3(probe_out3) // output wire [31 : 0] probe_out3 + .probe_out3(probe_out3), // output wire [31 : 0] probe_out3 + .probe_out4(probe_out4), // output wire [0 : 0] probe_out4 + .probe_out5(probe_out5) // output wire [0 : 0] probe_out5 ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho index 72f0bda5..f52e0add 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho @@ -59,7 +59,9 @@ COMPONENT vio_freq_comp probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ @@ -75,7 +77,9 @@ your_instance_name : vio_freq_comp probe_out0 => probe_out0, probe_out1 => probe_out1, probe_out2 => probe_out2, - probe_out3 => probe_out3 + probe_out3 => probe_out3, + probe_out4 => probe_out4, + probe_out5 => probe_out5 ); -- INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v index d54750ef..fd3b68ef 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2bb0eafe7db4192794511ba4732de759cc0b98077a25b784358aa0ce15434f25 -size 347806 +oid sha256:dd9cd9018e27390f56912a6e268e1cc1df6ac463e944eefbb1088577a51cb6b2 +size 358856 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl index 8f375e59..a69cf7d3 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3e1aa647a426193095c2bb4086b35050e3cc56a9af17458cac22aa0bdf6f4196 -size 626004 +oid sha256:16cbd9d7067933092574fe5c65db17db5a9175430cab7321e7c26769844e4179 +size 638631 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v index b605a111..b5aab159 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Sun May 7 16:51:33 2023 +// Date : Fri May 12 16:01:59 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v @@ -15,12 +15,14 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1, - probe_out2, probe_out3) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]" */; + probe_out2, probe_out3, probe_out4, probe_out5) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0],probe_out5[0:0]" */; input clk; input [0:0]probe_in0; output [0:0]probe_out0; output [7:0]probe_out1; output [0:0]probe_out2; output [31:0]probe_out3; + output [0:0]probe_out4; + output [0:0]probe_out5; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl index 538f6928..767f4405 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Sun May 7 16:51:33 2023 +-- Date : Fri May 12 16:01:59 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl @@ -19,7 +19,9 @@ entity vio_freq_comp is probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end vio_freq_comp; @@ -28,7 +30,7 @@ architecture stub of vio_freq_comp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0],probe_out5[0:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/sim/vio_rfcontrl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/sim/vio_rfcontrl.v index d8bfddec..54ec031a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/sim/vio_rfcontrl.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/sim/vio_rfcontrl.v @@ -48,7 +48,7 @@ `timescale 1ns / 1ps module vio_rfcontrl ( clk, -probe_in0, +probe_in0,probe_in1, probe_out0, probe_out1, probe_out2, @@ -66,11 +66,15 @@ probe_out13, probe_out14, probe_out15, probe_out16, -probe_out17 +probe_out17, +probe_out18, +probe_out19, +probe_out20 ); input clk; input [15 : 0] probe_in0; +input [0 : 0] probe_in1; output reg [0 : 0] probe_out0 = 'h0 ; output reg [0 : 0] probe_out1 = 'h0 ; @@ -89,7 +93,10 @@ output reg [0 : 0] probe_out13 = 'h0 ; output reg [0 : 0] probe_out14 = 'h0 ; output reg [0 : 0] probe_out15 = 'h0 ; output reg [0 : 0] probe_out16 = 'h0 ; -output reg [15 : 0] probe_out17 = 'h0000 ; +output reg [31 : 0] probe_out17 = 'h00000000 ; +output reg [31 : 0] probe_out18 = 'h00000000 ; +output reg [31 : 0] probe_out19 = 'h00000000 ; +output reg [31 : 0] probe_out20 = 'h00000000 ; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo index 59ec6ab1..443d94a9 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo @@ -57,6 +57,7 @@ vio_rfcontrl your_instance_name ( .clk(clk), // input wire clk .probe_in0(probe_in0), // input wire [15 : 0] probe_in0 + .probe_in1(probe_in1), // input wire [0 : 0] probe_in1 .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 .probe_out1(probe_out1), // output wire [0 : 0] probe_out1 .probe_out2(probe_out2), // output wire [15 : 0] probe_out2 @@ -74,7 +75,10 @@ vio_rfcontrl your_instance_name ( .probe_out14(probe_out14), // output wire [0 : 0] probe_out14 .probe_out15(probe_out15), // output wire [0 : 0] probe_out15 .probe_out16(probe_out16), // output wire [0 : 0] probe_out16 - .probe_out17(probe_out17) // output wire [15 : 0] probe_out17 + .probe_out17(probe_out17), // output wire [31 : 0] probe_out17 + .probe_out18(probe_out18), // output wire [31 : 0] probe_out18 + .probe_out19(probe_out19), // output wire [31 : 0] probe_out19 + .probe_out20(probe_out20) // output wire [31 : 0] probe_out20 ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho index 8e3710c3..d1e17d31 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho @@ -56,6 +56,7 @@ COMPONENT vio_rfcontrl PORT ( clk : IN STD_LOGIC; probe_in0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); @@ -73,7 +74,10 @@ COMPONENT vio_rfcontrl probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out15 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out16 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + probe_out17 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out18 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out19 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out20 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ @@ -86,6 +90,7 @@ your_instance_name : vio_rfcontrl PORT MAP ( clk => clk, probe_in0 => probe_in0, + probe_in1 => probe_in1, probe_out0 => probe_out0, probe_out1 => probe_out1, probe_out2 => probe_out2, @@ -103,7 +108,10 @@ your_instance_name : vio_rfcontrl probe_out14 => probe_out14, probe_out15 => probe_out15, probe_out16 => probe_out16, - probe_out17 => probe_out17 + probe_out17 => probe_out17, + probe_out18 => probe_out18, + probe_out19 => probe_out19, + probe_out20 => probe_out20 ); -- INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v index 3c1dab1a..3833ab7f 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:48b2ebe7c1dfe52efb1244db5038274527b29b3e7d11c399a766d95112881ad2 -size 429602 +oid sha256:e1d99c0d0e86597ef6f9fe9afc245f663ef8c0b0f727de31af1e971a9e2daa33 +size 533583 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl index 9c6cd38c..89d07167 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:15118e44db5067dd4c76ab789bc6bf18a0975b87050cfe9e886e2e5154da11ab -size 743535 +oid sha256:a74bd47953750e25a410aa206713f24fceb04072583e91b5e9c663b8c3319a39 +size 884753 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v index bbec2e33..bf8c2df3 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 10:18:46 2023 +// Date : Fri May 12 15:59:09 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v @@ -14,13 +14,14 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, - probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, - probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, probe_out16, - probe_out17) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]" */; +module vio_rfcontrl(clk, probe_in0, probe_in1, probe_out0, + probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, + probe_out9, probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, + probe_out16, probe_out17, probe_out18, probe_out19, probe_out20) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]" */; input clk; input [15:0]probe_in0; + input [0:0]probe_in1; output [0:0]probe_out0; output [0:0]probe_out1; output [15:0]probe_out2; @@ -38,5 +39,8 @@ module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, output [0:0]probe_out14; output [0:0]probe_out15; output [0:0]probe_out16; - output [15:0]probe_out17; + output [31:0]probe_out17; + output [31:0]probe_out18; + output [31:0]probe_out19; + output [31:0]probe_out20; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl index f76a93c0..1262f137 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 10:18:46 2023 +-- Date : Fri May 12 15:59:09 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl @@ -16,6 +16,7 @@ entity vio_rfcontrl is Port ( clk : in STD_LOGIC; probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); @@ -33,7 +34,10 @@ entity vio_rfcontrl is probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + probe_out17 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out18 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out19 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out20 : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); end vio_rfcontrl; @@ -42,7 +46,7 @@ architecture stub of vio_rfcontrl is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v new file mode 100644 index 00000000..5ddf59df --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v @@ -0,0 +1,7759 @@ +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "XILINX" +`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`pragma protect key_block +DjS90P3uFTSw2mNkyo7whVN8nQMcIWM6EHWVElsN47CcN0PotbZr5yaRyuvD56v2YltRSiZwXSQy +t7AcNCbGZQ== + +`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +hiVCRxNjjt2CnC5oMAP3ypF4T/SDQoivbp3hHV/egYgk2rTt3KW8s20nPTdA7bqwu15MQ4AjN0Ew +gz2/uFDH24mvKdEJjniutuoeoEoaq6PuIRR6tRvoNST0uraQpYDfFhfmYm1yWCMa5EdGH4j2xTuc +Ijhyd8+GE0AaXM0xQIU= + +`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +e1mRT8ojQhBviZ5mhgrVX6nk2Hin2nFB3sL8+GGF6uHJiaKlQcx1qiiIsa29NwwY+8L0+Sdc7Bwe +mimrmbB5AW3jQqY6SEA/pBsbopf8h5Cs+GFB69BVnMkH76EcmugXQ/U/WMttt/+0U8ebTqOzvVsh +maHchLdTcOMOGk0KOjqA3xeuYmSZ6QeTgx46yhlrFl02l5IxZBDyc3AMp2ewPv16zqkfWaJOnoMI +96IlQUocffCNrvYI9VB7uzEeo3jTE38GXFtw3Q00lt2MHP9hUS/CiFr2UC6MC78dvswwb6bkVW3D +8ky4L9f1zBEmW5MWwTmiVti/DPrF3aEru1ofBA== + +`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +mUmBQsaNGyqiVGrFwcTlR7MlTbnLOIYvHGlTVF0C1ji5bA0lK7umMKDXoVdfcTdwSKMExNj7Gqox +VFyrxtLrcpmqGiIap2SWS3Pbm874s4Y6boEMWVg7iUp4jnShKY232v9uNA++5R50qMYGP28FrJIe +67CdBh1O5ebOulWQaNirGAhsjQsF7b3Cz6jaLeI1oJdU9hFy1i5CotH3pUIwl75WQTFELhIzGFJw +r+KBwc5Dq/NP/wLmLPF62Bjy5X55LNsAHF1KZHrn/0SAiUai5QTpvrF1bMBhdoOwgj9TdBxp10UR +ydrxJub3MKUcBFv82RIymzgfizOLvI3D5Nbw4g== + +`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +P6yM9rb+3ZSH3KAr+tYUrDq1Lk26TDI18CdQdkrwI/gFgEiezF7pits6q49vdg27InqmPAeVCPYY +tosVszatEbVDv25/d5bIqaJAFdItcv/k8LBENIcclMqHXboE89+WBj/paWV33wGxzetDbrLUcN8F +CaZYqeKlNRLefNFQj5Dsfj4UTij0sgLfOH1iy26WYH6nIn71GQwdEOL8SXnt5COpc8vW2pK0rfcc +Q44nD+DVeUtyJfi0pNnjRnxB8RG3XpHT+y5InxzplAQwqNX3jEOvGWKeGvFE2URX7ShCbxAO23ZZ +RlGALFYygMBRaRB81iOtWsbirGnPKHdywhWj5g== + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +n4o0T1bNPxuQFkrUx0Ji5GI/A+zutd6cZlB6EJIp/nUQ6V6+8P3wlB0UwPr9oZS0abDQuVXUihUq +uDu7HyKmHJy++CIFFJDIQv4rl9HX54ETfMZCCR0RjpZIYxW63Uvllzoja06zTD3BSPM8PoTAObKo +7XfbQrWoFsgjPX2Ts2Y= + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +DPQpIqZ6YzUjSFNpvyY7jAnjsdVo1QBPFA7qtFu6mz76h7KyHee6vS2ejnLNPq3d8NvwNWkXhNH3 +R56P15Df3xRt8kSokTs3j8NQHP7c+hkMmTiaOywTBVnrai2/oFILCt5ujXPbRzSy9jj9uukoddqa +R0OW369sAbUuHvDLDzp81bKH2NDTec7Ck8Zl8yvn3wzENYP/JI/e/FPV8iwcHuOMZIeOxknj4jly +Dp++plsL1cTqYFr3bhNi+pvHFGEtI5hCat9fJgyLsQjsng02YP76lS5wANjNmtc6NawCEIpNflSn +Q9QNQWFy2rnD1nT1TUSPf/hMBMpWP8JW4UkN0A== + +`pragma protect data_method = "AES128-CBC" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 438576) +`pragma protect data_block +HX36iU68pDvdSeX+AwGrhWdDMdGxhZr/Tuwx9UlSWc8p3R9ZmajXwkYdJ7rRY5BneNZfpCWnv5GW +sxa8cAU0r1hatJk8YNlsocVmTz7OEH3nIai9l7va98Fh4P1dn3x0oa8IG+sAT0uWK+mOuuQMqPj1 +0JhsZdLZDSrIdmpQYPH3u7GfR0QKfF0h+UX2sMuckAzaMa9GjXTVB2Tke1o9f1qQUWJw7UMtLUac +A9WJXduixx2YWsjpPQ2o5cF93rvp4XFEI941SxWGUQLMJKA9r7c3wAfpjh1kxMmP45JO9kS58kg4 +pEoKtckY70mZqistG8V7/UEIvvPx3rk6flYy2kXCvo/vzsHcJWdd6VrMXemEq6EOPVTQpJ+Ohi0T +PjY9w9QNP49M4N1kXarbQuPcY+0Mk4vcloIkChVDU68PwD7eXV5zASW/l6KxtYeV6Ixs893EJwjM +2sWPNKiFw3oj/tqHZa2LrjjWKYMf9VQx8gC/gfFftrmQA5iGOE/unsvniGAytXTtFcxQSmBENwZe +tbOUmqF42a+hyWVP/YFRI7NMCPPoXNlhBoGUVjZPag8mGPQH4xMzVXdt+Qj5qhkFSaItQassvZ8f +EQUvd0w2YPjO8rCXuXxC8oR9HVwndUmKDn9UQuGontqQGi/YP/Onzk+hI+mYqSaMKDLPYyyf1yn0 +wegO8jHIUBb4GcxPWarr21pmu8/r/+GGv3oVN3t5zsdfQieIYRD2sqCLPxpCAfHtKHK+HOSSTUG3 +r5fHR9N8AAn/h85AaHB2FAwo/Yaj8HBWaZIl2ywy2kxtA6KAlsTVa3MzwJI+D+/oLF9WPpC5Y6jw +Gy4vQeyoMedomKDQepUKkwCUV6die0ue7G4DifkqaAaD1rafRnfXz2AdUTnZcbFZvK2Vs7MSNZFY +8q7OzLZQ+1OgwjKVNyM1ZRJTNsYo39KbD9cqMwCX7ZzSHhBC7Zi5FpJ6Sr8tCx5ahKS56S78eO5v +8w74td+w+yu/pBFG8qtTO0eRgRACsj190ET+GbaB07+7xrwVS/JDHwm36HfyhDcm1BRGDNOdy47f +3Ctew7/lbApv8jCwz2yxsvOz1g3aoOK1uzLHRRpI3+oVkGSiYzjAYQADILeczm6Opw8pyJi3Kv4u +oS9RTXeuvGebYL6YnyIQUdWGTrSMkwb6gV1CI5Ja8jUbqWsM+KBmdKPuHKx+geKlh654JLSOekTL +Zhu/5oMrU0IWZWHthXlxupsvoCnPL0GlHzVSD/0CriVAOVmTx4n5ioPqKUaeIkYBOM/3OqgMB2BG +BaXw5rRA1SFXBZUZqkjh6faXGRH4xMbh6FBNzaq1cGFVJ2syJmO9vGlwwt+0N05ZSwH1xs9Sf41k +IpNvhKt4Sd6+3/RuVpGr6w1ygLnKi09D0OvuwE4rP9qJfNaDPaCtA2xVr9b34HzA//ehbmmso16a +CXvtGBvyH1oLLiOXdQ7+KvVsOb6bWm5xT1yXdUaoidNFMuvi2WUjQ5y/+HA6BTeb3mqZMMvYYFOH +1BtLuQ5EgZH142wYO7q7M999tf0rIh+ohqzsY1a92xKYcVK2bj/MHi+DAKYwUNTFqyzonL87LXgR +4SkOCOzRgnYVvHM+gONJWqQpwQsMWu98zC1fLZnilgKbcxPqiE/lspgq46LpDsUOT0rowgb0lL/E +OB9Wit4oKdQDTcbOcVDAyq3/HzAmx/lKv/k2dkF24x641lcboFkdHI1rRV11qrCgLHSpiNbzYEjT +4s/tZyFptJn/ppksHjLlElXQg6SzPZwIqlThV3xFg6BUccGaVmcvhfiQQqx3n0KsESj1/W9/+K73 +9EyQ59RN/FUTnIfXd1fIsgU8wWFAi/b/4Mjt9XtJV+S7t2bajLwdzi5Fd/TNImYcSeDIbIyau8Zc +//0TLaGoysIFhzVEH8HjXuUZ6lAuugqouq3T+LJC8F+u8kHz1IGVk5RRu2yz5KOb4FNFXM/xT6Y4 +4eR8i7X0H+WIxuY0V408/Famxy1ju9lNZittvEzTSoSgoKn9+Wtwl3V4WZ1iGdSdKMBUsL2CA0JI +aIkfpS14t+MAbpNBKeB8v0fDa+Shw4frx0ZX9XfgyBPn6ohb88iKhpwOfaXK+oBa35/qEV+b3EM3 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b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd new file mode 100644 index 00000000..3fa2d8e3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd @@ -0,0 +1,18807 @@ +`protect begin_protected +`protect version = 1 +`protect encrypt_agent = "XILINX" +`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`protect key_block +V2sN9exa/LuXzcbeVcpOxpZc6tzWAwGPfMmjvtjv1Nf1Yj/fq48gtvabqkzsUD0bopkTPP5NDtkl +ihTdCj3S0Q== + +`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +h7ng0L736kJb9TWvsm0D0ZDFqIPvGS8wxd+fOBzJWJdWc5TSyxYiOgf+vn23e8Xg+mx5hjEdVsH+ +QXFbV6XsfUL4WtZvXysWqDjcV6qTWQEyrE8DFhVmz9hVfMUUJ7MBz0OPXVTSNzoDyGrkji8Ze3uG +N9vXCjvjJtNsOeZ+1N0= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +rF1s29ceyNBGDssRabPL/UtCTca0rA/dplPVmdyPEmUhwYfsDggcbEhdlEHOrHEAug/eLNyc2vOb +MTEOC0QmlcSu8L7ZAT+KPP/TeM56QFlWS6AiCdxgezKzEI2SqLzIxp5t9tsYnLWEIrHJAxqD+fE+ +vcrpS3Ub5KbBmaHzEz41LNnl7EMOtSMy5fuFgoWVvqhYypouQArv/p3vakIidVNrF02vNSHud8xo +VjXQlbfiLs8m2t3qQGQgCsSOde72tO++445FMm7Oy0juKmEqZzO42Foux8QYfQMGOJjr0w/Z95E0 +AonluWLez3Z3a4NGGJA19XUv0sb/4ijZbDJ8CQ== + +`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +n8hn6RWmPq/J0Rqx2sGnIG0LSqUf8PkRtLB726c65BS6sGNAgzDVAtP++DrLKZLkl45qsKkQC9YF +kn8Dj1+HMZtp+WDzRX3eQctaAEtZXFu+fO4VPqOom1ElpZvHVJow8QftAm9YmTN6tBjkunFjU+Ps +S+AZrvcB4Pccu9kBRolL+2MO5bB4Ncvvp6CM+hg693sPSWXdusIx9WPWQXlEJgFrAznTyQrpL9qI +yeR1yBJlIjueFEayWBprLJvKMcceIPRgWhKZseDVUj/tPvRmZe1yqNdi/2nCHkmXmUDL0MZ0SRb5 +8wu1ZPY4CGlUDSjkC/IPXwhab6kDriR77+6ylw== + +`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +cWtffUmo3Aa2CU8y/9bRBbfbn+5QjemnWBAtSYDYzke7H+C7Wcnm4jtWqsPDty1bhS8bJNU4J5RI +zXSpO96ITImT0MJB6u37hnuw98u2paJkQPttMoQ2rCd2JOrxWPpauRilz8s5mSpXDPJkYd7+9CaT +TT0AFjPsjD9iO3VM8at915gmQFx4V4Wl5W3/f0cJlytrny2ope1/AIEUsvRdTD5piF1sTDBTYvyF +CEQHonvsTJtnvWrGhjy6CzWFtDRsxQFznWRYEz8OT+fzyMppOgHLBCPhpTqsEA77o5Hh9R7dgCHp +bJaTS9Lb3qCGKFK4lS42qGlIgFzwXOE4wKv7+Q== + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +ERh+6MeszTrqJ3nKdkTGhpC1G14E9qvR1265MEtmcBFoMy4FC8tefkRbx/tt2sBVI+8y8jvIneiT +LVxUeKXl+K3jaqaRX0zMC4Fop1uCJv/vU2G7rcqtHFNSLENbKFTkmvlkjk9PA2UKknlM0TjSOBqS +B11TyJDp/lYe5fNw6W8= + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +EFc/Zj3G+eZ8YI+uowpq4sfQKeeVeJ8b0LtOOnxGqsJQJfwab2p8jkAR59Ptx048P1NXrMNlKFy/ +wBEoURarBZ4hXNnLW3ai850YZfX6TxyVvCO3nGQw115QGzRnHHxRIcjZY1HCPwf8iz/y0Ic8xZ/o +oFJW+LXFXDtDjHS8eFlL+RqHdg9Tw2fL0L6EIAxJpRob0/jGv3RvouDJRf1D6fqLqT4xi1k+VBrj +Y9jjNBJoBZrUtbfQGB/+eYufqWwXjJ8BE0jo+4UDhtFqzpO2xaTsrKx6OnQ17YAFWSDalA2oyzTg +6q4RLJDRBub/VmmDlGF5kbiGqtUX0joCTdoIbQ== + +`protect data_method = "AES128-CBC" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 1068304) +`protect data_block +Nzo9zCHrPiSqQ/RBXmcnbVqmAPcXUT/f3SmIAoETTHRhCD9IHXyA5GdYEMaQCgjsDC84MUtuRA2H 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00000000..54ebbe2f --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v @@ -0,0 +1,10519 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: fifo_generator_vlog_beh.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_vlog_beh.v + * | + * +-fifo_generator_v13_2_4_bhv_ver_as + * | + * +-fifo_generator_v13_2_4_bhv_ver_ss + * | + * +-fifo_generator_v13_2_4_bhv_ver_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_vlog_beh + #( + //----------------------------------------------------------------------- + // Generic Declarations + //----------------------------------------------------------------------- + parameter C_COMMON_CLOCK = 0, + parameter C_COUNT_TYPE = 0, + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DEFAULT_VALUE = "", + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_ENABLE_RLOCS = 0, + parameter C_FAMILY = "", + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_BACKUP = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_INT_CLK = 0, + parameter C_HAS_MEMINIT_FILE = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RD_RST = 0, + parameter C_HAS_RST = 1, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_HAS_WR_RST = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_INIT_WR_PNTR_VAL = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_MIF_FILE_NAME = "", + parameter C_OPTIMIZATION_MODE = 0, + parameter C_OVERFLOW_LOW = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PRIM_FIFO_TYPE = "4kx4", + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_FREQ = 1, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_PIPELINE_REG = 0, + parameter C_POWER_SAVING_MODE = 0, + parameter C_USE_FIFO16_FLAGS = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_FREQ = 1, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_WR_RESPONSE_LATENCY = 1, + parameter C_MSGON_VAL = 1, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_SYNCHRONIZER_STAGE = 2, + + // AXI Interface related parameters start here + parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3 + parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3 + parameter C_HAS_AXI_WR_CHANNEL = 0, + parameter C_HAS_AXI_RD_CHANNEL = 0, + parameter C_HAS_SLAVE_CE = 0, + parameter C_HAS_MASTER_CE = 0, + parameter C_ADD_NGC_CONSTRAINT = 0, + parameter C_USE_COMMON_UNDERFLOW = 0, + parameter C_USE_COMMON_OVERFLOW = 0, + parameter C_USE_DEFAULT_SETTINGS = 0, + + // AXI Full/Lite + parameter C_AXI_ID_WIDTH = 0, + parameter C_AXI_ADDR_WIDTH = 0, + parameter C_AXI_DATA_WIDTH = 0, + parameter C_AXI_LEN_WIDTH = 8, + parameter C_AXI_LOCK_WIDTH = 2, + parameter C_HAS_AXI_ID = 0, + parameter C_HAS_AXI_AWUSER = 0, + parameter C_HAS_AXI_WUSER = 0, + parameter C_HAS_AXI_BUSER = 0, + parameter C_HAS_AXI_ARUSER = 0, + parameter C_HAS_AXI_RUSER = 0, + parameter C_AXI_ARUSER_WIDTH = 0, + parameter C_AXI_AWUSER_WIDTH = 0, + parameter C_AXI_WUSER_WIDTH = 0, + parameter C_AXI_BUSER_WIDTH = 0, + parameter C_AXI_RUSER_WIDTH = 0, + + // AXI Streaming + parameter C_HAS_AXIS_TDATA = 0, + parameter C_HAS_AXIS_TID = 0, + parameter C_HAS_AXIS_TDEST = 0, + parameter C_HAS_AXIS_TUSER = 0, + parameter C_HAS_AXIS_TREADY = 0, + parameter C_HAS_AXIS_TLAST = 0, + parameter C_HAS_AXIS_TSTRB = 0, + parameter C_HAS_AXIS_TKEEP = 0, + parameter C_AXIS_TDATA_WIDTH = 1, + parameter C_AXIS_TID_WIDTH = 1, + parameter C_AXIS_TDEST_WIDTH = 1, + parameter C_AXIS_TUSER_WIDTH = 1, + parameter C_AXIS_TSTRB_WIDTH = 1, + parameter C_AXIS_TKEEP_WIDTH = 1, + + // AXI Channel Type + // WACH --> Write Address Channel + // WDCH --> Write Data Channel + // WRCH --> Write Response Channel + // RACH --> Read Address Channel + // RDCH --> Read Data Channel + // AXIS --> AXI Streaming + parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic + parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + + // AXI Implementation Type + // 1 = Common Clock Block RAM FIFO + // 2 = Common Clock Distributed RAM FIFO + // 11 = Independent Clock Block RAM FIFO + // 12 = Independent Clock Distributed RAM FIFO + parameter C_IMPLEMENTATION_TYPE_WACH = 0, + parameter C_IMPLEMENTATION_TYPE_WDCH = 0, + parameter C_IMPLEMENTATION_TYPE_WRCH = 0, + parameter C_IMPLEMENTATION_TYPE_RACH = 0, + parameter C_IMPLEMENTATION_TYPE_RDCH = 0, + parameter C_IMPLEMENTATION_TYPE_AXIS = 0, + + // AXI FIFO Type + // 0 = Data FIFO + // 1 = Packet FIFO + // 2 = Low Latency Sync FIFO + // 3 = Low Latency Async FIFO + parameter C_APPLICATION_TYPE_WACH = 0, + parameter C_APPLICATION_TYPE_WDCH = 0, + parameter C_APPLICATION_TYPE_WRCH = 0, + parameter C_APPLICATION_TYPE_RACH = 0, + parameter C_APPLICATION_TYPE_RDCH = 0, + parameter C_APPLICATION_TYPE_AXIS = 0, + + // AXI Built-in FIFO Primitive Type + // 512x36, 1kx18, 2kx9, 4kx4, etc + parameter C_PRIM_FIFO_TYPE_WACH = "512x36", + parameter C_PRIM_FIFO_TYPE_WDCH = "512x36", + parameter C_PRIM_FIFO_TYPE_WRCH = "512x36", + parameter C_PRIM_FIFO_TYPE_RACH = "512x36", + parameter C_PRIM_FIFO_TYPE_RDCH = "512x36", + parameter C_PRIM_FIFO_TYPE_AXIS = "512x36", + + // Enable ECC + // 0 = ECC disabled + // 1 = ECC enabled + parameter C_USE_ECC_WACH = 0, + parameter C_USE_ECC_WDCH = 0, + parameter C_USE_ECC_WRCH = 0, + parameter C_USE_ECC_RACH = 0, + parameter C_USE_ECC_RDCH = 0, + parameter C_USE_ECC_AXIS = 0, + + // ECC Error Injection Type + // 0 = No Error Injection + // 1 = Single Bit Error Injection + // 2 = Double Bit Error Injection + // 3 = Single Bit and Double Bit Error Injection + parameter C_ERROR_INJECTION_TYPE_WACH = 0, + parameter C_ERROR_INJECTION_TYPE_WDCH = 0, + parameter C_ERROR_INJECTION_TYPE_WRCH = 0, + parameter C_ERROR_INJECTION_TYPE_RACH = 0, + parameter C_ERROR_INJECTION_TYPE_RDCH = 0, + parameter C_ERROR_INJECTION_TYPE_AXIS = 0, + + // Input Data Width + // Accumulation of all AXI input signal's width + parameter C_DIN_WIDTH_WACH = 1, + parameter C_DIN_WIDTH_WDCH = 1, + parameter C_DIN_WIDTH_WRCH = 1, + parameter C_DIN_WIDTH_RACH = 1, + parameter C_DIN_WIDTH_RDCH = 1, + parameter C_DIN_WIDTH_AXIS = 1, + + parameter C_WR_DEPTH_WACH = 16, + parameter C_WR_DEPTH_WDCH = 16, + parameter C_WR_DEPTH_WRCH = 16, + parameter C_WR_DEPTH_RACH = 16, + parameter C_WR_DEPTH_RDCH = 16, + parameter C_WR_DEPTH_AXIS = 16, + + parameter C_WR_PNTR_WIDTH_WACH = 4, + parameter C_WR_PNTR_WIDTH_WDCH = 4, + parameter C_WR_PNTR_WIDTH_WRCH = 4, + parameter C_WR_PNTR_WIDTH_RACH = 4, + parameter C_WR_PNTR_WIDTH_RDCH = 4, + parameter C_WR_PNTR_WIDTH_AXIS = 4, + + parameter C_HAS_DATA_COUNTS_WACH = 0, + parameter C_HAS_DATA_COUNTS_WDCH = 0, + parameter C_HAS_DATA_COUNTS_WRCH = 0, + parameter C_HAS_DATA_COUNTS_RACH = 0, + parameter C_HAS_DATA_COUNTS_RDCH = 0, + parameter C_HAS_DATA_COUNTS_AXIS = 0, + + parameter C_HAS_PROG_FLAGS_WACH = 0, + parameter C_HAS_PROG_FLAGS_WDCH = 0, + parameter C_HAS_PROG_FLAGS_WRCH = 0, + parameter C_HAS_PROG_FLAGS_RACH = 0, + parameter C_HAS_PROG_FLAGS_RDCH = 0, + parameter C_HAS_PROG_FLAGS_AXIS = 0, + + parameter C_PROG_FULL_TYPE_WACH = 0, + parameter C_PROG_FULL_TYPE_WDCH = 0, + parameter C_PROG_FULL_TYPE_WRCH = 0, + parameter C_PROG_FULL_TYPE_RACH = 0, + parameter C_PROG_FULL_TYPE_RDCH = 0, + parameter C_PROG_FULL_TYPE_AXIS = 0, + + parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0, + + parameter C_PROG_EMPTY_TYPE_WACH = 0, + parameter C_PROG_EMPTY_TYPE_WDCH = 0, + parameter C_PROG_EMPTY_TYPE_WRCH = 0, + parameter C_PROG_EMPTY_TYPE_RACH = 0, + parameter C_PROG_EMPTY_TYPE_RDCH = 0, + parameter C_PROG_EMPTY_TYPE_AXIS = 0, + + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0, + + parameter C_REG_SLICE_MODE_WACH = 0, + parameter C_REG_SLICE_MODE_WDCH = 0, + parameter C_REG_SLICE_MODE_WRCH = 0, + parameter C_REG_SLICE_MODE_RACH = 0, + parameter C_REG_SLICE_MODE_RDCH = 0, + parameter C_REG_SLICE_MODE_AXIS = 0 + + ) + + ( + //------------------------------------------------------------------------------ + // Input and Output Declarations + //------------------------------------------------------------------------------ + + // Conventional FIFO Interface Signals + input backup, + input backup_marker, + input clk, + input rst, + input srst, + input wr_clk, + input wr_rst, + input rd_clk, + input rd_rst, + input [C_DIN_WIDTH-1:0] din, + input wr_en, + input rd_en, + // Optional inputs + input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh, + input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert, + input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate, + input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh, + input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert, + input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate, + input int_clk, + input injectdbiterr, + input injectsbiterr, + input sleep, + + output [C_DOUT_WIDTH-1:0] dout, + output full, + output almost_full, + output wr_ack, + output overflow, + output empty, + output almost_empty, + output valid, + output underflow, + output [C_DATA_COUNT_WIDTH-1:0] data_count, + output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count, + output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count, + output prog_full, + output prog_empty, + output sbiterr, + output dbiterr, + output wr_rst_busy, + output rd_rst_busy, + + + // AXI Global Signal + input m_aclk, + input s_aclk, + input s_aresetn, + input s_aclk_en, + input m_aclk_en, + + // AXI Full/Lite Slave Write Channel (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_awid, + input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen, + input [3-1:0] s_axi_awsize, + input [2-1:0] s_axi_awburst, + input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock, + input [4-1:0] s_axi_awcache, + input [3-1:0] s_axi_awprot, + input [4-1:0] s_axi_awqos, + input [4-1:0] s_axi_awregion, + input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + input s_axi_awvalid, + output s_axi_awready, + input [C_AXI_ID_WIDTH-1:0] s_axi_wid, + input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, + input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, + input s_axi_wlast, + input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + input s_axi_wvalid, + output s_axi_wready, + output [C_AXI_ID_WIDTH-1:0] s_axi_bid, + output [2-1:0] s_axi_bresp, + output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + output s_axi_bvalid, + input s_axi_bready, + + // AXI Full/Lite Master Write Channel (read side) + output [C_AXI_ID_WIDTH-1:0] m_axi_awid, + output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen, + output [3-1:0] m_axi_awsize, + output [2-1:0] m_axi_awburst, + output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock, + output [4-1:0] m_axi_awcache, + output [3-1:0] m_axi_awprot, + output [4-1:0] m_axi_awqos, + output [4-1:0] m_axi_awregion, + output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output m_axi_awvalid, + input m_axi_awready, + output [C_AXI_ID_WIDTH-1:0] m_axi_wid, + output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, + output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, + output m_axi_wlast, + output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output m_axi_wvalid, + input m_axi_wready, + input [C_AXI_ID_WIDTH-1:0] m_axi_bid, + input [2-1:0] m_axi_bresp, + input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + input m_axi_bvalid, + output m_axi_bready, + + + // AXI Full/Lite Slave Read Channel (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_arid, + input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen, + input [3-1:0] s_axi_arsize, + input [2-1:0] s_axi_arburst, + input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock, + input [4-1:0] s_axi_arcache, + input [3-1:0] s_axi_arprot, + input [4-1:0] s_axi_arqos, + input [4-1:0] s_axi_arregion, + input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + input s_axi_arvalid, + output s_axi_arready, + output [C_AXI_ID_WIDTH-1:0] s_axi_rid, + output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, + output [2-1:0] s_axi_rresp, + output s_axi_rlast, + output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + output s_axi_rvalid, + input s_axi_rready, + + + + // AXI Full/Lite Master Read Channel (read side) + output [C_AXI_ID_WIDTH-1:0] m_axi_arid, + output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen, + output [3-1:0] m_axi_arsize, + output [2-1:0] m_axi_arburst, + output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock, + output [4-1:0] m_axi_arcache, + output [3-1:0] m_axi_arprot, + output [4-1:0] m_axi_arqos, + output [4-1:0] m_axi_arregion, + output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output m_axi_arvalid, + input m_axi_arready, + input [C_AXI_ID_WIDTH-1:0] m_axi_rid, + input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, + input [2-1:0] m_axi_rresp, + input m_axi_rlast, + input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input m_axi_rvalid, + output m_axi_rready, + + + // AXI Streaming Slave Signals (Write side) + input s_axis_tvalid, + output s_axis_tready, + input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata, + input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb, + input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep, + input s_axis_tlast, + input [C_AXIS_TID_WIDTH-1:0] s_axis_tid, + input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest, + input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser, + + // AXI Streaming Master Signals (Read side) + output m_axis_tvalid, + input m_axis_tready, + output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata, + output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb, + output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep, + output m_axis_tlast, + output [C_AXIS_TID_WIDTH-1:0] m_axis_tid, + output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest, + output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser, + + + + + // AXI Full/Lite Write Address Channel signals + input axi_aw_injectsbiterr, + input axi_aw_injectdbiterr, + input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh, + input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count, + output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count, + output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count, + output axi_aw_sbiterr, + output axi_aw_dbiterr, + output axi_aw_overflow, + output axi_aw_underflow, + output axi_aw_prog_full, + output axi_aw_prog_empty, + + + // AXI Full/Lite Write Data Channel signals + input axi_w_injectsbiterr, + input axi_w_injectdbiterr, + input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh, + input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count, + output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count, + output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count, + output axi_w_sbiterr, + output axi_w_dbiterr, + output axi_w_overflow, + output axi_w_underflow, + output axi_w_prog_full, + output axi_w_prog_empty, + + + // AXI Full/Lite Write Response Channel signals + input axi_b_injectsbiterr, + input axi_b_injectdbiterr, + input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh, + input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count, + output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count, + output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count, + output axi_b_sbiterr, + output axi_b_dbiterr, + output axi_b_overflow, + output axi_b_underflow, + output axi_b_prog_full, + output axi_b_prog_empty, + + + + // AXI Full/Lite Read Address Channel signals + input axi_ar_injectsbiterr, + input axi_ar_injectdbiterr, + input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh, + input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count, + output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count, + output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count, + output axi_ar_sbiterr, + output axi_ar_dbiterr, + output axi_ar_overflow, + output axi_ar_underflow, + output axi_ar_prog_full, + output axi_ar_prog_empty, + + + // AXI Full/Lite Read Data Channel Signals + input axi_r_injectsbiterr, + input axi_r_injectdbiterr, + input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh, + input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count, + output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count, + output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count, + output axi_r_sbiterr, + output axi_r_dbiterr, + output axi_r_overflow, + output axi_r_underflow, + output axi_r_prog_full, + output axi_r_prog_empty, + + + // AXI Streaming FIFO Related Signals + input axis_injectsbiterr, + input axis_injectdbiterr, + input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh, + input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count, + output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count, + output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count, + output axis_sbiterr, + output axis_dbiterr, + output axis_overflow, + output axis_underflow, + output axis_prog_full, + output axis_prog_empty + + ); + + wire BACKUP; + wire BACKUP_MARKER; + wire CLK; + wire RST; + wire SRST; + wire WR_CLK; + wire WR_RST; + wire RD_CLK; + wire RD_RST; + wire [C_DIN_WIDTH-1:0] DIN; + wire WR_EN; + wire RD_EN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire INT_CLK; + wire INJECTDBITERR; + wire INJECTSBITERR; + wire SLEEP; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire FULL; + wire ALMOST_FULL; + wire WR_ACK; + wire OVERFLOW; + wire EMPTY; + wire ALMOST_EMPTY; + wire VALID; + wire UNDERFLOW; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + wire PROG_FULL; + wire PROG_EMPTY; + wire SBITERR; + wire DBITERR; + wire WR_RST_BUSY; + wire RD_RST_BUSY; + wire M_ACLK; + wire S_ACLK; + wire S_ARESETN; + wire S_ACLK_EN; + wire M_ACLK_EN; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID; + wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR; + wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN; + wire [3-1:0] S_AXI_AWSIZE; + wire [2-1:0] S_AXI_AWBURST; + wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK; + wire [4-1:0] S_AXI_AWCACHE; + wire [3-1:0] S_AXI_AWPROT; + wire [4-1:0] S_AXI_AWQOS; + wire [4-1:0] S_AXI_AWREGION; + wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER; + wire S_AXI_AWVALID; + wire S_AXI_AWREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID; + wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA; + wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB; + wire S_AXI_WLAST; + wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER; + wire S_AXI_WVALID; + wire S_AXI_WREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; + wire [2-1:0] S_AXI_BRESP; + wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER; + wire S_AXI_BVALID; + wire S_AXI_BREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID; + wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR; + wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN; + wire [3-1:0] M_AXI_AWSIZE; + wire [2-1:0] M_AXI_AWBURST; + wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK; + wire [4-1:0] M_AXI_AWCACHE; + wire [3-1:0] M_AXI_AWPROT; + wire [4-1:0] M_AXI_AWQOS; + wire [4-1:0] M_AXI_AWREGION; + wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER; + wire M_AXI_AWVALID; + wire M_AXI_AWREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID; + wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA; + wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB; + wire M_AXI_WLAST; + wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER; + wire M_AXI_WVALID; + wire M_AXI_WREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID; + wire [2-1:0] M_AXI_BRESP; + wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER; + wire M_AXI_BVALID; + wire M_AXI_BREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID; + wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR; + wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN; + wire [3-1:0] S_AXI_ARSIZE; + wire [2-1:0] S_AXI_ARBURST; + wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK; + wire [4-1:0] S_AXI_ARCACHE; + wire [3-1:0] S_AXI_ARPROT; + wire [4-1:0] S_AXI_ARQOS; + wire [4-1:0] S_AXI_ARREGION; + wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER; + wire S_AXI_ARVALID; + wire S_AXI_ARREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; + wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA; + wire [2-1:0] S_AXI_RRESP; + wire S_AXI_RLAST; + wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER; + wire S_AXI_RVALID; + wire S_AXI_RREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID; + wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR; + wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN; + wire [3-1:0] M_AXI_ARSIZE; + wire [2-1:0] M_AXI_ARBURST; + wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK; + wire [4-1:0] M_AXI_ARCACHE; + wire [3-1:0] M_AXI_ARPROT; + wire [4-1:0] M_AXI_ARQOS; + wire [4-1:0] M_AXI_ARREGION; + wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER; + wire M_AXI_ARVALID; + wire M_AXI_ARREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID; + wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA; + wire [2-1:0] M_AXI_RRESP; + wire M_AXI_RLAST; + wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER; + wire M_AXI_RVALID; + wire M_AXI_RREADY; + wire S_AXIS_TVALID; + wire S_AXIS_TREADY; + wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA; + wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB; + wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP; + wire S_AXIS_TLAST; + wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID; + wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST; + wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER; + wire M_AXIS_TVALID; + wire M_AXIS_TREADY; + wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA; + wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB; + wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP; + wire M_AXIS_TLAST; + wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID; + wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST; + wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER; + wire AXI_AW_INJECTSBITERR; + wire AXI_AW_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT; + wire AXI_AW_SBITERR; + wire AXI_AW_DBITERR; + wire AXI_AW_OVERFLOW; + wire AXI_AW_UNDERFLOW; + wire AXI_AW_PROG_FULL; + wire AXI_AW_PROG_EMPTY; + wire AXI_W_INJECTSBITERR; + wire AXI_W_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT; + wire AXI_W_SBITERR; + wire AXI_W_DBITERR; + wire AXI_W_OVERFLOW; + wire AXI_W_UNDERFLOW; + wire AXI_W_PROG_FULL; + wire AXI_W_PROG_EMPTY; + wire AXI_B_INJECTSBITERR; + wire AXI_B_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT; + wire AXI_B_SBITERR; + wire AXI_B_DBITERR; + wire AXI_B_OVERFLOW; + wire AXI_B_UNDERFLOW; + wire AXI_B_PROG_FULL; + wire AXI_B_PROG_EMPTY; + wire AXI_AR_INJECTSBITERR; + wire AXI_AR_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT; + wire AXI_AR_SBITERR; + wire AXI_AR_DBITERR; + wire AXI_AR_OVERFLOW; + wire AXI_AR_UNDERFLOW; + wire AXI_AR_PROG_FULL; + wire AXI_AR_PROG_EMPTY; + wire AXI_R_INJECTSBITERR; + wire AXI_R_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT; + wire AXI_R_SBITERR; + wire AXI_R_DBITERR; + wire AXI_R_OVERFLOW; + wire AXI_R_UNDERFLOW; + wire AXI_R_PROG_FULL; + wire AXI_R_PROG_EMPTY; + wire AXIS_INJECTSBITERR; + wire AXIS_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT; + wire AXIS_SBITERR; + wire AXIS_DBITERR; + wire AXIS_OVERFLOW; + wire AXIS_UNDERFLOW; + wire AXIS_PROG_FULL; + wire AXIS_PROG_EMPTY; + wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in; + wire wr_rst_int; + wire rd_rst_int; + wire wr_rst_busy_o; + wire wr_rst_busy_ntve; + wire wr_rst_busy_axis; + wire wr_rst_busy_wach; + wire wr_rst_busy_wdch; + wire wr_rst_busy_wrch; + wire wr_rst_busy_rach; + wire wr_rst_busy_rdch; + + + + function integer find_log2; + input integer int_val; + integer i,j; + begin + i = 1; + j = 0; + for (i = 1; i < int_val; i = i*2) begin + j = j + 1; + end + find_log2 = j; + end + endfunction + + + + + // Conventional FIFO Interface Signals + assign BACKUP = backup; + assign BACKUP_MARKER = backup_marker; + assign CLK = clk; + assign RST = rst; + assign SRST = srst; + assign WR_CLK = wr_clk; + assign WR_RST = wr_rst; + assign RD_CLK = rd_clk; + assign RD_RST = rd_rst; + assign WR_EN = wr_en; + assign RD_EN = rd_en; + assign INT_CLK = int_clk; + assign INJECTDBITERR = injectdbiterr; + assign INJECTSBITERR = injectsbiterr; + assign SLEEP = sleep; + assign full = FULL; + assign almost_full = ALMOST_FULL; + assign wr_ack = WR_ACK; + assign overflow = OVERFLOW; + assign empty = EMPTY; + assign almost_empty = ALMOST_EMPTY; + assign valid = VALID; + assign underflow = UNDERFLOW; + assign prog_full = PROG_FULL; + assign prog_empty = PROG_EMPTY; + assign sbiterr = SBITERR; + assign dbiterr = DBITERR; +// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o; + assign wr_rst_busy = wr_rst_busy_o; + assign rd_rst_busy = RD_RST_BUSY; + assign M_ACLK = m_aclk; + assign S_ACLK = s_aclk; + assign S_ARESETN = s_aresetn; + assign S_ACLK_EN = s_aclk_en; + assign M_ACLK_EN = m_aclk_en; + assign S_AXI_AWVALID = s_axi_awvalid; + assign s_axi_awready = S_AXI_AWREADY; + assign S_AXI_WLAST = s_axi_wlast; + assign S_AXI_WVALID = s_axi_wvalid; + assign s_axi_wready = S_AXI_WREADY; + assign s_axi_bvalid = S_AXI_BVALID; + assign S_AXI_BREADY = s_axi_bready; + assign m_axi_awvalid = M_AXI_AWVALID; + assign M_AXI_AWREADY = m_axi_awready; + assign m_axi_wlast = M_AXI_WLAST; + assign m_axi_wvalid = M_AXI_WVALID; + assign M_AXI_WREADY = m_axi_wready; + assign M_AXI_BVALID = m_axi_bvalid; + assign m_axi_bready = M_AXI_BREADY; + assign S_AXI_ARVALID = s_axi_arvalid; + assign s_axi_arready = S_AXI_ARREADY; + assign s_axi_rlast = S_AXI_RLAST; + assign s_axi_rvalid = S_AXI_RVALID; + assign S_AXI_RREADY = s_axi_rready; + assign m_axi_arvalid = M_AXI_ARVALID; + assign M_AXI_ARREADY = m_axi_arready; + assign M_AXI_RLAST = m_axi_rlast; + assign M_AXI_RVALID = m_axi_rvalid; + assign m_axi_rready = M_AXI_RREADY; + assign S_AXIS_TVALID = s_axis_tvalid; + assign s_axis_tready = S_AXIS_TREADY; + assign S_AXIS_TLAST = s_axis_tlast; + assign m_axis_tvalid = M_AXIS_TVALID; + assign M_AXIS_TREADY = m_axis_tready; + assign m_axis_tlast = M_AXIS_TLAST; + assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr; + assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr; + assign axi_aw_sbiterr = AXI_AW_SBITERR; + assign axi_aw_dbiterr = AXI_AW_DBITERR; + assign axi_aw_overflow = AXI_AW_OVERFLOW; + assign axi_aw_underflow = AXI_AW_UNDERFLOW; + assign axi_aw_prog_full = AXI_AW_PROG_FULL; + assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY; + assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr; + assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr; + assign axi_w_sbiterr = AXI_W_SBITERR; + assign axi_w_dbiterr = AXI_W_DBITERR; + assign axi_w_overflow = AXI_W_OVERFLOW; + assign axi_w_underflow = AXI_W_UNDERFLOW; + assign axi_w_prog_full = AXI_W_PROG_FULL; + assign axi_w_prog_empty = AXI_W_PROG_EMPTY; + assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr; + assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr; + assign axi_b_sbiterr = AXI_B_SBITERR; + assign axi_b_dbiterr = AXI_B_DBITERR; + assign axi_b_overflow = AXI_B_OVERFLOW; + assign axi_b_underflow = AXI_B_UNDERFLOW; + assign axi_b_prog_full = AXI_B_PROG_FULL; + assign axi_b_prog_empty = AXI_B_PROG_EMPTY; + assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr; + assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr; + assign axi_ar_sbiterr = AXI_AR_SBITERR; + assign axi_ar_dbiterr = AXI_AR_DBITERR; + assign axi_ar_overflow = AXI_AR_OVERFLOW; + assign axi_ar_underflow = AXI_AR_UNDERFLOW; + assign axi_ar_prog_full = AXI_AR_PROG_FULL; + assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY; + assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr; + assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr; + assign axi_r_sbiterr = AXI_R_SBITERR; + assign axi_r_dbiterr = AXI_R_DBITERR; + assign axi_r_overflow = AXI_R_OVERFLOW; + assign axi_r_underflow = AXI_R_UNDERFLOW; + assign axi_r_prog_full = AXI_R_PROG_FULL; + assign axi_r_prog_empty = AXI_R_PROG_EMPTY; + assign AXIS_INJECTSBITERR = axis_injectsbiterr; + assign AXIS_INJECTDBITERR = axis_injectdbiterr; + assign axis_sbiterr = AXIS_SBITERR; + assign axis_dbiterr = AXIS_DBITERR; + assign axis_overflow = AXIS_OVERFLOW; + assign axis_underflow = AXIS_UNDERFLOW; + assign axis_prog_full = AXIS_PROG_FULL; + assign axis_prog_empty = AXIS_PROG_EMPTY; + + + assign DIN = din; + assign PROG_EMPTY_THRESH = prog_empty_thresh; + assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert; + assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate; + assign PROG_FULL_THRESH = prog_full_thresh; + assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert; + assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate; + assign dout = DOUT; + assign data_count = DATA_COUNT; + assign rd_data_count = RD_DATA_COUNT; + assign wr_data_count = WR_DATA_COUNT; + assign S_AXI_AWID = s_axi_awid; + assign S_AXI_AWADDR = s_axi_awaddr; + assign S_AXI_AWLEN = s_axi_awlen; + assign S_AXI_AWSIZE = s_axi_awsize; + assign S_AXI_AWBURST = s_axi_awburst; + assign S_AXI_AWLOCK = s_axi_awlock; + assign S_AXI_AWCACHE = s_axi_awcache; + assign S_AXI_AWPROT = s_axi_awprot; + assign S_AXI_AWQOS = s_axi_awqos; + assign S_AXI_AWREGION = s_axi_awregion; + assign S_AXI_AWUSER = s_axi_awuser; + assign S_AXI_WID = s_axi_wid; + assign S_AXI_WDATA = s_axi_wdata; + assign S_AXI_WSTRB = s_axi_wstrb; + assign S_AXI_WUSER = s_axi_wuser; + assign s_axi_bid = S_AXI_BID; + assign s_axi_bresp = S_AXI_BRESP; + assign s_axi_buser = S_AXI_BUSER; + assign m_axi_awid = M_AXI_AWID; + assign m_axi_awaddr = M_AXI_AWADDR; + assign m_axi_awlen = M_AXI_AWLEN; + assign m_axi_awsize = M_AXI_AWSIZE; + assign m_axi_awburst = M_AXI_AWBURST; + assign m_axi_awlock = M_AXI_AWLOCK; + assign m_axi_awcache = M_AXI_AWCACHE; + assign m_axi_awprot = M_AXI_AWPROT; + assign m_axi_awqos = M_AXI_AWQOS; + assign m_axi_awregion = M_AXI_AWREGION; + assign m_axi_awuser = M_AXI_AWUSER; + assign m_axi_wid = M_AXI_WID; + assign m_axi_wdata = M_AXI_WDATA; + assign m_axi_wstrb = M_AXI_WSTRB; + assign m_axi_wuser = M_AXI_WUSER; + assign M_AXI_BID = m_axi_bid; + assign M_AXI_BRESP = m_axi_bresp; + assign M_AXI_BUSER = m_axi_buser; + assign S_AXI_ARID = s_axi_arid; + assign S_AXI_ARADDR = s_axi_araddr; + assign S_AXI_ARLEN = s_axi_arlen; + assign S_AXI_ARSIZE = s_axi_arsize; + assign S_AXI_ARBURST = s_axi_arburst; + assign S_AXI_ARLOCK = s_axi_arlock; + assign S_AXI_ARCACHE = s_axi_arcache; + assign S_AXI_ARPROT = s_axi_arprot; + assign S_AXI_ARQOS = s_axi_arqos; + assign S_AXI_ARREGION = s_axi_arregion; + assign S_AXI_ARUSER = s_axi_aruser; + assign s_axi_rid = S_AXI_RID; + assign s_axi_rdata = S_AXI_RDATA; + assign s_axi_rresp = S_AXI_RRESP; + assign s_axi_ruser = S_AXI_RUSER; + assign m_axi_arid = M_AXI_ARID; + assign m_axi_araddr = M_AXI_ARADDR; + assign m_axi_arlen = M_AXI_ARLEN; + assign m_axi_arsize = M_AXI_ARSIZE; + assign m_axi_arburst = M_AXI_ARBURST; + assign m_axi_arlock = M_AXI_ARLOCK; + assign m_axi_arcache = M_AXI_ARCACHE; + assign m_axi_arprot = M_AXI_ARPROT; + assign m_axi_arqos = M_AXI_ARQOS; + assign m_axi_arregion = M_AXI_ARREGION; + assign m_axi_aruser = M_AXI_ARUSER; + assign M_AXI_RID = m_axi_rid; + assign M_AXI_RDATA = m_axi_rdata; + assign M_AXI_RRESP = m_axi_rresp; + assign M_AXI_RUSER = m_axi_ruser; + assign S_AXIS_TDATA = s_axis_tdata; + assign S_AXIS_TSTRB = s_axis_tstrb; + assign S_AXIS_TKEEP = s_axis_tkeep; + assign S_AXIS_TID = s_axis_tid; + assign S_AXIS_TDEST = s_axis_tdest; + assign S_AXIS_TUSER = s_axis_tuser; + assign m_axis_tdata = M_AXIS_TDATA; + assign m_axis_tstrb = M_AXIS_TSTRB; + assign m_axis_tkeep = M_AXIS_TKEEP; + assign m_axis_tid = M_AXIS_TID; + assign m_axis_tdest = M_AXIS_TDEST; + assign m_axis_tuser = M_AXIS_TUSER; + assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh; + assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh; + assign axi_aw_data_count = AXI_AW_DATA_COUNT; + assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT; + assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT; + assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh; + assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh; + assign axi_w_data_count = AXI_W_DATA_COUNT; + assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT; + assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT; + assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh; + assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh; + assign axi_b_data_count = AXI_B_DATA_COUNT; + assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT; + assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT; + assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh; + assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh; + assign axi_ar_data_count = AXI_AR_DATA_COUNT; + assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT; + assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT; + assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh; + assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh; + assign axi_r_data_count = AXI_R_DATA_COUNT; + assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT; + assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT; + assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh; + assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh; + assign axis_data_count = AXIS_DATA_COUNT; + assign axis_wr_data_count = AXIS_WR_DATA_COUNT; + assign axis_rd_data_count = AXIS_RD_DATA_COUNT; + + + generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo + + fifo_generator_v13_2_4_CONV_VER + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_ECC (C_USE_ECC), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), + .C_AXI_TYPE (C_AXI_TYPE), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE) + ) + fifo_generator_v13_2_4_conv_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INT_CLK (INT_CLK), + .INJECTDBITERR (INJECTDBITERR), + .INJECTSBITERR (INJECTSBITERR), + + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (wr_data_count_in), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .wr_rst_busy_o (wr_rst_busy_o), + .wr_rst_busy (wr_rst_busy_i), + .rd_rst_busy (rd_rst_busy), + .wr_rst_i_out (wr_rst_int), + .rd_rst_i_out (rd_rst_int) + ); + end endgenerate + + + + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + localparam C_AXI_SIZE_WIDTH = 3; + localparam C_AXI_BURST_WIDTH = 2; + localparam C_AXI_CACHE_WIDTH = 4; + localparam C_AXI_PROT_WIDTH = 3; + localparam C_AXI_QOS_WIDTH = 4; + localparam C_AXI_REGION_WIDTH = 4; + localparam C_AXI_BRESP_WIDTH = 2; + localparam C_AXI_RRESP_WIDTH = 2; + + localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0; + localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS; + localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET; + localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET; + localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET; + localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET; + localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET; + localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS); + localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH); + + + function [LOG_DEPTH_AXIS-1:0] bin2gray; + input [LOG_DEPTH_AXIS-1:0] x; + begin + bin2gray = x ^ (x>>1); + end + endfunction + + function [LOG_DEPTH_AXIS-1:0] gray2bin; + input [LOG_DEPTH_AXIS-1:0] x; + integer i; + begin + gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1]; + for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin + gray2bin[i] = gray2bin[i+1] ^ x[i]; + end + end + endfunction + +wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last; +wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ; +wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ; +reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0; +reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0; +reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0; +reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0; +wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad; +wire [LOG_WR_DEPTH : 0] r_inv_pad; +wire [LOG_WR_DEPTH-1 : 0] d_cnt; +reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0; +reg adj_w_cnt_rd_pad_0 = 0; +reg r_inv_pad_0 = 0; + + + genvar l; + + generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage + fifo_generator_v13_2_4_sync_stage + #( + .C_WIDTH (LOG_WR_DEPTH) + ) + rd_stg_inst + ( + .RST (rd_rst_int), + .CLK (RD_CLK), + .DIN (w_q[l-1]), + .DOUT (w_q[l]) + ); + end endgenerate // gpkt_cnt_sync_stage + + + + generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter + assign wr_eop_ad = WR_EN & !(FULL); + assign rd_eop_ad = RD_EN & !(EMPTY); + + + always @ (posedge wr_rst_int or posedge WR_CLK) + begin + if (wr_rst_int) + w_cnt <= 1'b0; + else if (wr_eop_ad) + w_cnt <= w_cnt + 1; + end + + always @ (posedge wr_rst_int or posedge WR_CLK) + begin + if (wr_rst_int) + w_cnt_gc <= 1'b0; + else + w_cnt_gc <= bin2gray(w_cnt); + end + + + assign w_q[0] = w_cnt_gc; + assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE]; + + + + always @ (posedge rd_rst_int or posedge RD_CLK) + begin + if (rd_rst_int) + w_cnt_rd <= 1'b0; + else + w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last); + end + + always @ (posedge rd_rst_int or posedge RD_CLK) + begin + if (rd_rst_int) + r_cnt <= 1'b0; + else if (rd_eop_ad) + r_cnt <= r_cnt + 1; + end + + + // Take the difference of write and read packet count + // Logic is similar to rd_pe_as + assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd; + assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt; + assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0; + assign r_inv_pad[0] = r_inv_pad_0; + + + always @ ( rd_eop_ad ) + begin + if (!rd_eop_ad) begin + adj_w_cnt_rd_pad_0 <= 1'b1; + r_inv_pad_0 <= 1'b1; + end else begin + adj_w_cnt_rd_pad_0 <= 1'b0; + r_inv_pad_0 <= 1'b0; + end + end + + always @ (posedge rd_rst_int or posedge RD_CLK) + begin + if (rd_rst_int) + d_cnt_pad <= 1'b0; + else + d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ; + end + + assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ; + assign WR_DATA_COUNT = d_cnt; + + end endgenerate // fifo_ic_adapter + + generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter + assign WR_DATA_COUNT = wr_data_count_in; + + end endgenerate // fifo_icn_adapter + + + + wire inverted_reset = ~S_ARESETN; + wire axi_rs_rst; + wire [C_DIN_WIDTH_AXIS-1:0] axis_din ; + wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ; + wire axis_full ; + wire axis_almost_full ; + wire axis_empty ; + wire axis_s_axis_tready; + wire axis_m_axis_tvalid; + wire axis_wr_en ; + wire axis_rd_en ; + wire axis_we ; + wire axis_re ; + wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc; + reg axis_pkt_read = 1'b0; + wire axis_rd_rst; + wire axis_wr_rst; + + generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 || + C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst + reg rst_d1 = 0 ; + reg rst_d2 = 0 ; + reg [3:0] axi_rst = 4'h0 ; + always @ (posedge inverted_reset or posedge S_ACLK) begin + if (inverted_reset) begin + rst_d1 <= 1'b1; + rst_d2 <= 1'b1; + axi_rst <= 4'hf; + end else begin + rst_d1 <= #`TCQ 1'b0; + rst_d2 <= #`TCQ rst_d1; + axi_rst <= #`TCQ {axi_rst[2:0],1'b0}; + end + end + + assign axi_rs_rst = axi_rst[3];//rst_d2; + end endgenerate // gaxi_rs_rst + + generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming + + // Write protection when almost full or prog_full is high + assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : + (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID; + + // Read protection when almost empty or prog_empty is high + assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY : + (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY; + assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we; + assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re; + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_AXIS), + .C_WR_DEPTH (C_WR_DEPTH_AXIS), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), + .C_DOUT_WIDTH (C_DIN_WIDTH_AXIS), + .C_RD_DEPTH (C_WR_DEPTH_AXIS), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS), + .C_USE_ECC (C_USE_ECC_AXIS), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_axis_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (axis_wr_en), + .RD_EN (axis_rd_en), + .PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .INJECTDBITERR (AXIS_INJECTDBITERR), + .INJECTSBITERR (AXIS_INJECTSBITERR), + + .DIN (axis_din), + .DOUT (axis_dout), + .FULL (axis_full), + .EMPTY (axis_empty), + .ALMOST_FULL (axis_almost_full), + .PROG_FULL (AXIS_PROG_FULL), + .ALMOST_EMPTY (), + .PROG_EMPTY (AXIS_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (AXIS_OVERFLOW), + .VALID (), + .UNDERFLOW (AXIS_UNDERFLOW), + .DATA_COUNT (axis_dc), + .RD_DATA_COUNT (AXIS_RD_DATA_COUNT), + .WR_DATA_COUNT (AXIS_WR_DATA_COUNT), + .SBITERR (AXIS_SBITERR), + .DBITERR (AXIS_DBITERR), + .wr_rst_busy (wr_rst_busy_axis), + .rd_rst_busy (rd_rst_busy_axis), + .wr_rst_i_out (axis_wr_rst), + .rd_rst_i_out (axis_rd_rst), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full; + assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read; + assign S_AXIS_TREADY = axis_s_axis_tready; + assign M_AXIS_TVALID = axis_m_axis_tvalid; + + end endgenerate // axi_streaming + + wire axis_wr_eop; + reg axis_wr_eop_d1 = 1'b0; + wire axis_rd_eop; + integer axis_pkt_cnt; + + generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc + assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; + assign axis_rd_eop = axis_rd_en & axis_dout[0]; + + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_pkt_read <= 1'b0; + else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1) + axis_pkt_read <= 1'b0; + else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty)) + axis_pkt_read <= 1'b1; + end + + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_wr_eop_d1 <= 1'b0; + else + axis_wr_eop_d1 <= axis_wr_eop; + end + + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_pkt_cnt <= 0; + else if (axis_wr_eop_d1 && ~axis_rd_eop) + axis_pkt_cnt <= axis_pkt_cnt + 1; + else if (axis_rd_eop && ~axis_wr_eop_d1) + axis_pkt_cnt <= axis_pkt_cnt - 1; + end + end endgenerate // gaxis_pkt_fifo_cc + + +reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0; +wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last; +wire axis_rd_has_rst; +wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ; +wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ; +wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0; +wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ; +reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0; +reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0; +reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0; +wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad; +wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad; +wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt; +reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0; +reg adj_axis_wpkt_cnt_rd_pad_0 = 0; +reg rpkt_inv_pad_0 = 0; +wire axis_af_rd ; + +generate if (C_HAS_RST == 1) begin : rst_blk_has + assign axis_rd_has_rst = axis_rd_rst; +end endgenerate //rst_blk_has + +generate if (C_HAS_RST == 0) begin :rst_blk_no + assign axis_rd_has_rst = 1'b0; +end endgenerate //rst_blk_no + + genvar i; + + generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage + fifo_generator_v13_2_4_sync_stage + #( + .C_WIDTH (LOG_DEPTH_AXIS) + ) + rd_stg_inst + ( + .RST (axis_rd_has_rst), + .CLK (M_ACLK), + .DIN (wpkt_q[i-1]), + .DOUT (wpkt_q[i]) + ); + + fifo_generator_v13_2_4_sync_stage + #( + .C_WIDTH (1) + ) + wr_stg_inst + ( + .RST (axis_rd_has_rst), + .CLK (M_ACLK), + .DIN (axis_af_q[i-1]), + .DOUT (axis_af_q[i]) + ); + end endgenerate // gpkt_cnt_sync_stage + + + generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic + assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; + assign axis_rd_eop = axis_rd_en & axis_dout[0]; + + always @ (posedge axis_rd_has_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + axis_pkt_read <= 1'b0; + else if (axis_rd_eop && (diff_pkt_cnt == 1)) + axis_pkt_read <= 1'b0; + else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty)) + axis_pkt_read <= 1'b1; + end + + always @ (posedge axis_wr_rst or posedge S_ACLK) + begin + if (axis_wr_rst) + axis_wpkt_cnt <= 1'b0; + else if (axis_wr_eop) + axis_wpkt_cnt <= axis_wpkt_cnt + 1; + end + + always @ (posedge axis_wr_rst or posedge S_ACLK) + begin + if (axis_wr_rst) + axis_wpkt_cnt_gc <= 1'b0; + else + axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt); + end + + + assign wpkt_q[0] = axis_wpkt_cnt_gc; + assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE]; + assign axis_af_q[0] = axis_almost_full; + //assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE]; + assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE]; + + + + always @ (posedge axis_rd_has_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + axis_wpkt_cnt_rd <= 1'b0; + else + axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last); + end + + always @ (posedge axis_rd_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + axis_rpkt_cnt <= 1'b0; + else if (axis_rd_eop) + axis_rpkt_cnt <= axis_rpkt_cnt + 1; + end + + + // Take the difference of write and read packet count + // Logic is similar to rd_pe_as + assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd; + assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt; + assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0; + assign rpkt_inv_pad[0] = rpkt_inv_pad_0; + + + always @ ( axis_rd_eop ) + begin + if (!axis_rd_eop) begin + adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1; + rpkt_inv_pad_0 <= 1'b1; + end else begin + adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0; + rpkt_inv_pad_0 <= 1'b0; + end + end + + always @ (posedge axis_rd_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + diff_pkt_cnt_pad <= 1'b0; + else + diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ; + end + + assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ; + + + + + + end endgenerate // gaxis_pkt_fifo_ic + + + + + // Generate the accurate data count for axi stream packet fifo configuration + reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0; + generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_dc_pkt_fifo <= 0; + else if (axis_wr_en && (~axis_rd_en)) + axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1; + else if (~axis_wr_en && axis_rd_en) + axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1; + end + assign AXIS_DATA_COUNT = axis_dc_pkt_fifo; + end endgenerate // gdc_pkt + + generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt + assign AXIS_DATA_COUNT = 0; + end endgenerate // gndc_pkt + + generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc + assign AXIS_DATA_COUNT = axis_dc; + end endgenerate // gdc + + // Register Slice for Write Address Channel + generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice + assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID; + assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY; + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_AXIS), + .C_REG_CONFIG (C_REG_SLICE_MODE_AXIS) + ) + axis_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (axis_din), + .S_VALID (axis_wr_en), + .S_READY (S_AXIS_TREADY), + + // Master side + .M_PAYLOAD_DATA (axis_dout), + .M_VALID (M_AXIS_TVALID), + .M_READY (axis_rd_en) + ); + end endgenerate // gaxis_reg_slice + + + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata + assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA; + assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb + assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB; + assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep + assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP; + assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid + assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID; + assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest + assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST; + assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser + assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER; + assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast + assign axis_din[0] = S_AXIS_TLAST; + assign M_AXIS_TLAST = axis_dout[0]; + end endgenerate + + //########################################################################### + // AXI FULL Write Channel (axi_write_channel) + //########################################################################### + + localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0; + localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0; + + localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + + localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + + localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0; + localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0; + localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0; + localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0; + localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0; + + localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH; + localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH; + localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET; + localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET; + localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET; + localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET; + localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET; + localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH; + localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH; + localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET; + localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET; + + localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH; + localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH; + localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8; + localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET; + + localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH; + localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH; + localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET; + + + wire [C_DIN_WIDTH_WACH-1:0] wach_din ; + wire [C_DIN_WIDTH_WACH-1:0] wach_dout ; + wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ; + wire wach_full ; + wire wach_almost_full ; + wire wach_prog_full ; + wire wach_empty ; + wire wach_almost_empty ; + wire wach_prog_empty ; + wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ; + wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ; + wire wdch_full ; + wire wdch_almost_full ; + wire wdch_prog_full ; + wire wdch_empty ; + wire wdch_almost_empty ; + wire wdch_prog_empty ; + wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ; + wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ; + wire wrch_full ; + wire wrch_almost_full ; + wire wrch_prog_full ; + wire wrch_empty ; + wire wrch_almost_empty ; + wire wrch_prog_empty ; + wire axi_aw_underflow_i; + wire axi_w_underflow_i ; + wire axi_b_underflow_i ; + wire axi_aw_overflow_i ; + wire axi_w_overflow_i ; + wire axi_b_overflow_i ; + wire axi_wr_underflow_i; + wire axi_wr_overflow_i ; + wire wach_s_axi_awready; + wire wach_m_axi_awvalid; + wire wach_wr_en ; + wire wach_rd_en ; + wire wdch_s_axi_wready ; + wire wdch_m_axi_wvalid ; + wire wdch_wr_en ; + wire wdch_rd_en ; + wire wrch_s_axi_bvalid ; + wire wrch_m_axi_bready ; + wire wrch_wr_en ; + wire wrch_rd_en ; + wire txn_count_up ; + wire txn_count_down ; + wire awvalid_en ; + wire awvalid_pkt ; + wire awready_pkt ; + integer wr_pkt_count ; + wire wach_we ; + wire wach_re ; + wire wdch_we ; + wire wdch_re ; + wire wrch_we ; + wire wrch_re ; + + generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel + // Write protection when almost full or prog_full is high + assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID; + + // Read protection when almost empty or prog_empty is high + assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? + wach_m_axi_awvalid & awready_pkt & awvalid_en : + (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? + M_AXI_AWREADY && wach_m_axi_awvalid : + (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? + awready_pkt & awvalid_en : + (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? + M_AXI_AWREADY : 1'b0; + assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we; + assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re; + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_WACH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_WR_DEPTH (C_WR_DEPTH_WACH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), + .C_DOUT_WIDTH (C_DIN_WIDTH_WACH), + .C_RD_DEPTH (C_WR_DEPTH_WACH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH), + .C_USE_ECC (C_USE_ECC_WACH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0), + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_wach_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (wach_wr_en), + .RD_EN (wach_rd_en), + .PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .INJECTDBITERR (AXI_AW_INJECTDBITERR), + .INJECTSBITERR (AXI_AW_INJECTSBITERR), + + .DIN (wach_din), + .DOUT (wach_dout_pkt), + .FULL (wach_full), + .EMPTY (wach_empty), + .ALMOST_FULL (), + .PROG_FULL (AXI_AW_PROG_FULL), + .ALMOST_EMPTY (), + .PROG_EMPTY (AXI_AW_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_aw_overflow_i), + .VALID (), + .UNDERFLOW (axi_aw_underflow_i), + .DATA_COUNT (AXI_AW_DATA_COUNT), + .RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT), + .SBITERR (AXI_AW_SBITERR), + .DBITERR (AXI_AW_DBITERR), + .wr_rst_busy (wr_rst_busy_wach), + .rd_rst_busy (rd_rst_busy_wach), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full; + assign wach_m_axi_awvalid = ~wach_empty; + assign S_AXI_AWREADY = wach_s_axi_awready; + + assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0; + assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0; + + end endgenerate // axi_write_address_channel + + // Register Slice for Write Address Channel + generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WACH), + .C_REG_CONFIG (C_REG_SLICE_MODE_WACH) + ) + wach_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wach_din), + .S_VALID (S_AXI_AWVALID), + .S_READY (S_AXI_AWREADY), + + // Master side + .M_PAYLOAD_DATA (wach_dout), + .M_VALID (M_AXI_AWVALID), + .M_READY (M_AXI_AWREADY) + ); + end endgenerate // gwach_reg_slice + + generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WACH), + .C_REG_CONFIG (1) + ) + wach_pkt_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wach_dout_pkt), + .S_VALID (awvalid_pkt), + .S_READY (awready_pkt), + + // Master side + .M_PAYLOAD_DATA (wach_dout), + .M_VALID (M_AXI_AWVALID), + .M_READY (M_AXI_AWREADY) + ); + + assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en; + + assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; + assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en; + + always@(posedge S_ACLK or posedge inverted_reset) begin + if(inverted_reset == 1) begin + wr_pkt_count <= 0; + end else begin + if(txn_count_up == 1 && txn_count_down == 0) begin + wr_pkt_count <= wr_pkt_count + 1; + end else if(txn_count_up == 0 && txn_count_down == 1) begin + wr_pkt_count <= wr_pkt_count - 1; + end + end + end //Always end + assign awvalid_en = (wr_pkt_count > 0)?1:0; + end endgenerate + + generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr + assign awvalid_en = 1; + assign wach_dout = wach_dout_pkt; + assign M_AXI_AWVALID = wach_m_axi_awvalid; + end + endgenerate + + + + generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel + // Write protection when almost full or prog_full is high + assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID; + + // Read protection when almost empty or prog_empty is high + assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY; + assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we; + assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re; + + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_WDCH), + .C_WR_DEPTH (C_WR_DEPTH_WDCH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), + .C_DOUT_WIDTH (C_DIN_WIDTH_WDCH), + .C_RD_DEPTH (C_WR_DEPTH_WDCH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH), + .C_USE_ECC (C_USE_ECC_WDCH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_wdch_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (wdch_wr_en), + .RD_EN (wdch_rd_en), + .PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .INJECTDBITERR (AXI_W_INJECTDBITERR), + .INJECTSBITERR (AXI_W_INJECTSBITERR), + + .DIN (wdch_din), + .DOUT (wdch_dout), + .FULL (wdch_full), + .EMPTY (wdch_empty), + .ALMOST_FULL (), + .PROG_FULL (AXI_W_PROG_FULL), + .ALMOST_EMPTY (), + .PROG_EMPTY (AXI_W_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_w_overflow_i), + .VALID (), + .UNDERFLOW (axi_w_underflow_i), + .DATA_COUNT (AXI_W_DATA_COUNT), + .RD_DATA_COUNT (AXI_W_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_W_WR_DATA_COUNT), + .SBITERR (AXI_W_SBITERR), + .DBITERR (AXI_W_DBITERR), + .wr_rst_busy (wr_rst_busy_wdch), + .rd_rst_busy (rd_rst_busy_wdch), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full; + assign wdch_m_axi_wvalid = ~wdch_empty; + assign S_AXI_WREADY = wdch_s_axi_wready; + assign M_AXI_WVALID = wdch_m_axi_wvalid; + + assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0; + assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0; + + end endgenerate // axi_write_data_channel + + // Register Slice for Write Data Channel + generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WDCH), + .C_REG_CONFIG (C_REG_SLICE_MODE_WDCH) + ) + wdch_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wdch_din), + .S_VALID (S_AXI_WVALID), + .S_READY (S_AXI_WREADY), + + // Master side + .M_PAYLOAD_DATA (wdch_dout), + .M_VALID (M_AXI_WVALID), + .M_READY (M_AXI_WREADY) + ); + end endgenerate // gwdch_reg_slice + + generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel + // Write protection when almost full or prog_full is high + assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID; + + // Read protection when almost empty or prog_empty is high + assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY; + assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we; + assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re; + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_WRCH), + .C_WR_DEPTH (C_WR_DEPTH_WRCH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), + .C_DOUT_WIDTH (C_DIN_WIDTH_WRCH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_RD_DEPTH (C_WR_DEPTH_WRCH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH), + .C_USE_ECC (C_USE_ECC_WRCH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_wrch_dut + ( + .CLK (S_ACLK), + .WR_CLK (M_ACLK), + .RD_CLK (S_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (wrch_wr_en), + .RD_EN (wrch_rd_en), + .PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .INJECTDBITERR (AXI_B_INJECTDBITERR), + .INJECTSBITERR (AXI_B_INJECTSBITERR), + + .DIN (wrch_din), + .DOUT (wrch_dout), + .FULL (wrch_full), + .EMPTY (wrch_empty), + .ALMOST_FULL (), + .ALMOST_EMPTY (), + .PROG_FULL (AXI_B_PROG_FULL), + .PROG_EMPTY (AXI_B_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_b_overflow_i), + .VALID (), + .UNDERFLOW (axi_b_underflow_i), + .DATA_COUNT (AXI_B_DATA_COUNT), + .RD_DATA_COUNT (AXI_B_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_B_WR_DATA_COUNT), + .SBITERR (AXI_B_SBITERR), + .DBITERR (AXI_B_DBITERR), + .wr_rst_busy (wr_rst_busy_wrch), + .rd_rst_busy (rd_rst_busy_wrch), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign wrch_s_axi_bvalid = ~wrch_empty; + assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full; + assign S_AXI_BVALID = wrch_s_axi_bvalid; + assign M_AXI_BREADY = wrch_m_axi_bready; + + assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0; + assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0; + end endgenerate // axi_write_resp_channel + + // Register Slice for Write Response Channel + generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WRCH), + .C_REG_CONFIG (C_REG_SLICE_MODE_WRCH) + ) + wrch_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wrch_din), + .S_VALID (M_AXI_BVALID), + .S_READY (M_AXI_BREADY), + + // Master side + .M_PAYLOAD_DATA (wrch_dout), + .M_VALID (S_AXI_BVALID), + .M_READY (S_AXI_BREADY) + ); + end endgenerate // gwrch_reg_slice + + + assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0; + assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0; + + generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output + assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET]; + assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET]; + assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET]; + assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET]; + assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET]; + assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET]; + assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET]; + assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET]; + assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR; + assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN; + assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE; + assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST; + assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK; + assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE; + assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT; + assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS; + end endgenerate // axi_wach_output + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion + assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET]; + end endgenerate // axi_awregion + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion + assign M_AXI_AWREGION = 0; + end endgenerate // naxi_awregion + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser + assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET]; + end endgenerate // axi_awuser + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser + assign M_AXI_AWUSER = 0; + end endgenerate // naxi_awuser + + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid + assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET]; + end endgenerate //axi_awid + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid + assign M_AXI_AWID = 0; + end endgenerate //naxi_awid + + generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output + assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET]; + assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; + assign M_AXI_WLAST = wdch_dout[0]; + assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA; + assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB; + assign wdch_din[0] = S_AXI_WLAST; + end endgenerate // axi_wdch_output + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin + assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET]; + end endgenerate + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin + assign M_AXI_WID = 0; + end endgenerate + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin + assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET]; + end endgenerate + generate if (C_HAS_AXI_WUSER == 0) begin + assign M_AXI_WUSER = 0; + end endgenerate + + generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output + assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; + assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP; + end endgenerate // axi_wrch_output + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser + assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET]; + end endgenerate // axi_buser + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser + assign S_AXI_BUSER = 0; + end endgenerate // naxi_buser + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid + assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET]; + end endgenerate // axi_bid + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid + assign S_AXI_BID = 0 ; + end endgenerate // naxi_bid + + + generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1 + assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT}; + assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET]; + assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET]; + end endgenerate // axi_wach_output1 + + generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1 + assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB}; + assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET]; + assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; + end endgenerate // axi_wdch_output1 + + generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1 + assign wrch_din = M_AXI_BRESP; + assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; + end endgenerate // axi_wrch_output1 + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1 + assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER; + end endgenerate // gwach_din1 + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2 + assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID; + end endgenerate // gwach_din2 + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3 + assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION; + end endgenerate // gwach_din3 + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1 + assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER; + end endgenerate // gwdch_din1 + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2 + assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID; + end endgenerate // gwdch_din2 + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1 + assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER; + end endgenerate // gwrch_din1 + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2 + assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID; + end endgenerate // gwrch_din2 + + //end of axi_write_channel + + //########################################################################### + // AXI FULL Read Channel (axi_read_channel) + //########################################################################### + wire [C_DIN_WIDTH_RACH-1:0] rach_din ; + wire [C_DIN_WIDTH_RACH-1:0] rach_dout ; + wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ; + wire rach_full ; + wire rach_almost_full ; + wire rach_prog_full ; + wire rach_empty ; + wire rach_almost_empty ; + wire rach_prog_empty ; + wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ; + wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ; + wire rdch_full ; + wire rdch_almost_full ; + wire rdch_prog_full ; + wire rdch_empty ; + wire rdch_almost_empty ; + wire rdch_prog_empty ; + wire axi_ar_underflow_i ; + wire axi_r_underflow_i ; + wire axi_ar_overflow_i ; + wire axi_r_overflow_i ; + wire axi_rd_underflow_i ; + wire axi_rd_overflow_i ; + wire rach_s_axi_arready ; + wire rach_m_axi_arvalid ; + wire rach_wr_en ; + wire rach_rd_en ; + wire rdch_m_axi_rready ; + wire rdch_s_axi_rvalid ; + wire rdch_wr_en ; + wire rdch_rd_en ; + wire arvalid_pkt ; + wire arready_pkt ; + wire arvalid_en ; + wire rdch_rd_ok ; + wire accept_next_pkt ; + integer rdch_free_space ; + integer rdch_commited_space ; + wire rach_we ; + wire rach_re ; + wire rdch_we ; + wire rdch_re ; + + localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH; + localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH; + localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET; + localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET; + localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET; + localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET; + localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET; + localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH; + localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH; + localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET; + localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET; + + localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH; + localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH; + localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH; + localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET; + + + generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel + + // Write protection when almost full or prog_full is high + assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID; + + // Read protection when almost empty or prog_empty is high +// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en; + assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? + rach_m_axi_arvalid & arready_pkt & arvalid_en : + (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? + M_AXI_ARREADY && rach_m_axi_arvalid : + (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? + arready_pkt & arvalid_en : + (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? + M_AXI_ARREADY : 1'b0; + assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we; + assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re; + + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_RACH), + .C_WR_DEPTH (C_WR_DEPTH_RACH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_DOUT_WIDTH (C_DIN_WIDTH_RACH), + .C_RD_DEPTH (C_WR_DEPTH_RACH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH), + .C_USE_ECC (C_USE_ECC_RACH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_rach_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (rach_wr_en), + .RD_EN (rach_rd_en), + .PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .INJECTDBITERR (AXI_AR_INJECTDBITERR), + .INJECTSBITERR (AXI_AR_INJECTSBITERR), + + .DIN (rach_din), + .DOUT (rach_dout_pkt), + .FULL (rach_full), + .EMPTY (rach_empty), + .ALMOST_FULL (), + .ALMOST_EMPTY (), + .PROG_FULL (AXI_AR_PROG_FULL), + .PROG_EMPTY (AXI_AR_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_ar_overflow_i), + .VALID (), + .UNDERFLOW (axi_ar_underflow_i), + .DATA_COUNT (AXI_AR_DATA_COUNT), + .RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT), + .SBITERR (AXI_AR_SBITERR), + .DBITERR (AXI_AR_DBITERR), + .wr_rst_busy (wr_rst_busy_rach), + .rd_rst_busy (rd_rst_busy_rach), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full; + assign rach_m_axi_arvalid = ~rach_empty; + assign S_AXI_ARREADY = rach_s_axi_arready; + + assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0; + assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0; + + end endgenerate // axi_read_addr_channel + + // Register Slice for Read Address Channel + generate if (C_RACH_TYPE == 1) begin : grach_reg_slice + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_RACH), + .C_REG_CONFIG (C_REG_SLICE_MODE_RACH) + ) + rach_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (rach_din), + .S_VALID (S_AXI_ARVALID), + .S_READY (S_AXI_ARREADY), + + // Master side + .M_PAYLOAD_DATA (rach_dout), + .M_VALID (M_AXI_ARVALID), + .M_READY (M_AXI_ARREADY) + ); + end endgenerate // grach_reg_slice + + // Register Slice for Read Address Channel for MM Packet FIFO + generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_RACH), + .C_REG_CONFIG (1) + ) + reg_slice_mm_pkt_fifo_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (rach_dout_pkt), + .S_VALID (arvalid_pkt), + .S_READY (arready_pkt), + + // Master side + .M_PAYLOAD_DATA (rach_dout), + .M_VALID (M_AXI_ARVALID), + .M_READY (M_AXI_ARREADY) + ); + end endgenerate // grach_reg_slice_mm_pkt_fifo + + + generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid + assign M_AXI_ARVALID = rach_m_axi_arvalid; + assign rach_dout = rach_dout_pkt; + end endgenerate // grach_m_axi_arvalid + + + generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd + assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en; + assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en; + assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en; + + always@(posedge S_ACLK or posedge inverted_reset) begin + if(inverted_reset) begin + rdch_commited_space <= 0; + end else begin + if(rdch_rd_ok && !accept_next_pkt) begin + rdch_commited_space <= rdch_commited_space-1; + end else if(!rdch_rd_ok && accept_next_pkt) begin + rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1); + end else if(rdch_rd_ok && accept_next_pkt) begin + rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]); + end + end + end //Always end + + always@(*) begin + rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1)); + end + + assign arvalid_en = (rdch_free_space >= 0)?1:0; + end + endgenerate + + generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd + assign arvalid_en = 1; + end + endgenerate + + generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel + + // Write protection when almost full or prog_full is high + assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID; + + // Read protection when almost empty or prog_empty is high + assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY; + assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we; + assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re; + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_RDCH), + .C_WR_DEPTH (C_WR_DEPTH_RDCH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), + .C_DOUT_WIDTH (C_DIN_WIDTH_RDCH), + .C_RD_DEPTH (C_WR_DEPTH_RDCH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH), + .C_USE_ECC (C_USE_ECC_RDCH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_rdch_dut + ( + .CLK (S_ACLK), + .WR_CLK (M_ACLK), + .RD_CLK (S_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (rdch_wr_en), + .RD_EN (rdch_rd_en), + .PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .INJECTDBITERR (AXI_R_INJECTDBITERR), + .INJECTSBITERR (AXI_R_INJECTSBITERR), + + .DIN (rdch_din), + .DOUT (rdch_dout), + .FULL (rdch_full), + .EMPTY (rdch_empty), + .ALMOST_FULL (), + .ALMOST_EMPTY (), + .PROG_FULL (AXI_R_PROG_FULL), + .PROG_EMPTY (AXI_R_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_r_overflow_i), + .VALID (), + .UNDERFLOW (axi_r_underflow_i), + .DATA_COUNT (AXI_R_DATA_COUNT), + .RD_DATA_COUNT (AXI_R_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_R_WR_DATA_COUNT), + .SBITERR (AXI_R_SBITERR), + .DBITERR (AXI_R_DBITERR), + .wr_rst_busy (wr_rst_busy_rdch), + .rd_rst_busy (rd_rst_busy_rdch), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign rdch_s_axi_rvalid = ~rdch_empty; + assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full; + assign S_AXI_RVALID = rdch_s_axi_rvalid; + assign M_AXI_RREADY = rdch_m_axi_rready; + + assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0; + assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0; + + end endgenerate //axi_read_data_channel + + // Register Slice for read Data Channel + generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_RDCH), + .C_REG_CONFIG (C_REG_SLICE_MODE_RDCH) + ) + rdch_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (rdch_din), + .S_VALID (M_AXI_RVALID), + .S_READY (M_AXI_RREADY), + + // Master side + .M_PAYLOAD_DATA (rdch_dout), + .M_VALID (S_AXI_RVALID), + .M_READY (S_AXI_RREADY) + ); + end endgenerate // grdch_reg_slice + + + assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0; + assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0; + + + generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output + assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET]; + assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET]; + assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET]; + assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET]; + assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET]; + assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET]; + assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET]; + assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET]; + assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR; + assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN; + assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE; + assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST; + assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK; + assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE; + assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT; + assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS; + end endgenerate // axi_full_rach_output + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion + assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET]; + end endgenerate // axi_arregion + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion + assign M_AXI_ARREGION = 0; + end endgenerate // naxi_arregion + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser + assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET]; + end endgenerate // axi_aruser + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser + assign M_AXI_ARUSER = 0; + end endgenerate // naxi_aruser + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid + assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET]; + end endgenerate // axi_arid + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid + assign M_AXI_ARID = 0; + end endgenerate // naxi_arid + + generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output + assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET]; + assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; + assign S_AXI_RLAST = rdch_dout[0]; + assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA; + assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP; + assign rdch_din[0] = M_AXI_RLAST; + end endgenerate // axi_full_rdch_output + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output + assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET]; + end endgenerate // axi_full_ruser_output + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output + assign S_AXI_RUSER = 0; + end endgenerate // axi_full_nruser_output + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid + assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET]; + end endgenerate // axi_rid + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid + assign S_AXI_RID = 0; + end endgenerate // naxi_rid + + generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1 + assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT}; + assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET]; + assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET]; + end endgenerate // axi_lite_rach_output + + generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1 + assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP}; + assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET]; + assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; + end endgenerate // axi_lite_rdch_output + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1 + assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER; + end endgenerate // grach_din1 + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2 + assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID; + end endgenerate // grach_din2 + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin + assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION; + end endgenerate + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1 + assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER; + end endgenerate // grdch_din1 + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2 + assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID; + end endgenerate // grdch_din2 + + //end of axi_read_channel + + generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf + assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) : + (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i : + (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0; + end endgenerate // gaxi_comm_uf + + generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of + assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) : + (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i : + (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0; + end endgenerate // gaxi_comm_of + + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + // Pass Through Logic or Wiring Logic + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + + //------------------------------------------------------------------------- + // Pass Through Logic for Read Channel + //------------------------------------------------------------------------- + + // Wiring logic for Write Address Channel + generate if (C_WACH_TYPE == 2) begin : gwach_pass_through + assign M_AXI_AWID = S_AXI_AWID; + assign M_AXI_AWADDR = S_AXI_AWADDR; + assign M_AXI_AWLEN = S_AXI_AWLEN; + assign M_AXI_AWSIZE = S_AXI_AWSIZE; + assign M_AXI_AWBURST = S_AXI_AWBURST; + assign M_AXI_AWLOCK = S_AXI_AWLOCK; + assign M_AXI_AWCACHE = S_AXI_AWCACHE; + assign M_AXI_AWPROT = S_AXI_AWPROT; + assign M_AXI_AWQOS = S_AXI_AWQOS; + assign M_AXI_AWREGION = S_AXI_AWREGION; + assign M_AXI_AWUSER = S_AXI_AWUSER; + assign S_AXI_AWREADY = M_AXI_AWREADY; + assign M_AXI_AWVALID = S_AXI_AWVALID; + end endgenerate // gwach_pass_through; + + // Wiring logic for Write Data Channel + generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through + assign M_AXI_WID = S_AXI_WID; + assign M_AXI_WDATA = S_AXI_WDATA; + assign M_AXI_WSTRB = S_AXI_WSTRB; + assign M_AXI_WLAST = S_AXI_WLAST; + assign M_AXI_WUSER = S_AXI_WUSER; + assign S_AXI_WREADY = M_AXI_WREADY; + assign M_AXI_WVALID = S_AXI_WVALID; + end endgenerate // gwdch_pass_through; + + // Wiring logic for Write Response Channel + generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through + assign S_AXI_BID = M_AXI_BID; + assign S_AXI_BRESP = M_AXI_BRESP; + assign S_AXI_BUSER = M_AXI_BUSER; + assign M_AXI_BREADY = S_AXI_BREADY; + assign S_AXI_BVALID = M_AXI_BVALID; + end endgenerate // gwrch_pass_through; + + //------------------------------------------------------------------------- + // Pass Through Logic for Read Channel + //------------------------------------------------------------------------- + + // Wiring logic for Read Address Channel + generate if (C_RACH_TYPE == 2) begin : grach_pass_through + assign M_AXI_ARID = S_AXI_ARID; + assign M_AXI_ARADDR = S_AXI_ARADDR; + assign M_AXI_ARLEN = S_AXI_ARLEN; + assign M_AXI_ARSIZE = S_AXI_ARSIZE; + assign M_AXI_ARBURST = S_AXI_ARBURST; + assign M_AXI_ARLOCK = S_AXI_ARLOCK; + assign M_AXI_ARCACHE = S_AXI_ARCACHE; + assign M_AXI_ARPROT = S_AXI_ARPROT; + assign M_AXI_ARQOS = S_AXI_ARQOS; + assign M_AXI_ARREGION = S_AXI_ARREGION; + assign M_AXI_ARUSER = S_AXI_ARUSER; + assign S_AXI_ARREADY = M_AXI_ARREADY; + assign M_AXI_ARVALID = S_AXI_ARVALID; + end endgenerate // grach_pass_through; + + // Wiring logic for Read Data Channel + generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through + assign S_AXI_RID = M_AXI_RID; + assign S_AXI_RLAST = M_AXI_RLAST; + assign S_AXI_RUSER = M_AXI_RUSER; + assign S_AXI_RDATA = M_AXI_RDATA; + assign S_AXI_RRESP = M_AXI_RRESP; + assign S_AXI_RVALID = M_AXI_RVALID; + assign M_AXI_RREADY = S_AXI_RREADY; + end endgenerate // grdch_pass_through; + + // Wiring logic for AXI Streaming + generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through + assign M_AXIS_TDATA = S_AXIS_TDATA; + assign M_AXIS_TSTRB = S_AXIS_TSTRB; + assign M_AXIS_TKEEP = S_AXIS_TKEEP; + assign M_AXIS_TID = S_AXIS_TID; + assign M_AXIS_TDEST = S_AXIS_TDEST; + assign M_AXIS_TUSER = S_AXIS_TUSER; + assign M_AXIS_TLAST = S_AXIS_TLAST; + assign S_AXIS_TREADY = M_AXIS_TREADY; + assign M_AXIS_TVALID = S_AXIS_TVALID; + end endgenerate // gaxis_pass_through; + + +endmodule //fifo_generator_v13_2_4 + + + +/******************************************************************************* + * Declaration of top-level module for Conventional FIFO + ******************************************************************************/ +module fifo_generator_v13_2_4_CONV_VER + #( + parameter C_COMMON_CLOCK = 0, + parameter C_INTERFACE_TYPE = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_COUNT_TYPE = 0, + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DEFAULT_VALUE = "", + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_ENABLE_RLOCS = 0, + parameter C_FAMILY = "virtex7", //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_BACKUP = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_INT_CLK = 0, + parameter C_HAS_MEMINIT_FILE = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RD_RST = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_HAS_WR_RST = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_INIT_WR_PNTR_VAL = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_MIF_FILE_NAME = "", + parameter C_OPTIMIZATION_MODE = 0, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PRIM_FIFO_TYPE = "", + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_FREQ = 1, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FIFO16_FLAGS = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_FREQ = 1, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_WR_RESPONSE_LATENCY = 1, + parameter C_MSGON_VAL = 1, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_FIFO_TYPE = 0, + parameter C_SYNCHRONIZER_STAGE = 2, + parameter C_AXI_TYPE = 0 + ) + + ( + input BACKUP, + input BACKUP_MARKER, + input CLK, + input RST, + input SRST, + input WR_CLK, + input WR_RST, + input RD_CLK, + input RD_RST, + input [C_DIN_WIDTH-1:0] DIN, + input WR_EN, + input RD_EN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input INT_CLK, + input INJECTDBITERR, + input INJECTSBITERR, + + output [C_DOUT_WIDTH-1:0] DOUT, + output FULL, + output ALMOST_FULL, + output WR_ACK, + output OVERFLOW, + output EMPTY, + output ALMOST_EMPTY, + output VALID, + output UNDERFLOW, + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output PROG_FULL, + output PROG_EMPTY, + output SBITERR, + output DBITERR, + output wr_rst_busy_o, + output wr_rst_busy, + output rd_rst_busy, + output wr_rst_i_out, + output rd_rst_i_out + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : Used for error injection purpose + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST + * 1 = Use RST + * C_ERROR_INJECTION_TYPE : 0 = No error injection + * 1 = Single bit error injection only + * 2 = Double bit error injection only + * 3 = Single and double bit error injection + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Read Reset + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Write Reset + * INT_CLK : Internal Clock + * INJECTSBITERR: Inject Signle bit error + * INJECTDBITERR: Inject Double bit error + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + //---------------------------------------------------------------------------- + //- Internal Signals for delayed input signals + //- All the input signals except Clock are delayed by 100 ps and then given to + //- the models. + //---------------------------------------------------------------------------- + + reg rst_delayed ; + reg empty_fb ; + reg srst_delayed ; + reg wr_rst_delayed ; + reg rd_rst_delayed ; + reg wr_en_delayed ; + reg rd_en_delayed ; + reg [C_DIN_WIDTH-1:0] din_delayed ; + reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ; + reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ; + reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ; + reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ; + reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ; + reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ; + reg injectdbiterr_delayed ; + reg injectsbiterr_delayed ; + wire empty_p0_out; + + always @* rst_delayed <= #`TCQ RST ; + always @* empty_fb <= #`TCQ empty_p0_out ; + always @* srst_delayed <= #`TCQ SRST ; + always @* wr_rst_delayed <= #`TCQ WR_RST ; + always @* rd_rst_delayed <= #`TCQ RD_RST ; + always @* din_delayed <= #`TCQ DIN ; + always @* wr_en_delayed <= #`TCQ WR_EN ; + always @* rd_en_delayed <= #`TCQ RD_EN ; + always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ; + always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; + always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; + always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ; + always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ; + always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ; + always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ; + always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ; + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + // 2 = Low Latency Synchronous FIFO + // 3 = Low Latency Asynchronous FIFO + localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 : + (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + + //Internal reset signals + reg rd_rst_asreg = 1'b0; + reg rd_rst_asreg_d1 = 1'b0; + reg rd_rst_asreg_d2 = 1'b0; + reg rd_rst_asreg_d3 = 1'b0; + reg rd_rst_reg = 1'b0; + reg rd_rst_comb = 1'b1; + reg rd_rst_comb_d1 = 1'b0; + reg wr_rst_d0 = 1'b0; + reg wr_rst_d1 = 1'b0; + reg wr_rst_d2 = 1'b0; + reg rd_rst_d0 = 1'b0; + reg rd_rst_d1 = 1'b0; + reg rd_rst_d2 = 1'b0; + reg rd_rst_d3 = 1'b0; + reg wrrst_done = 1'b0; + reg rdrst_done = 1'b0; + reg wr_rst_asreg = 1'b0; + reg wr_rst_asreg_d1 = 1'b0; + reg wr_rst_asreg_d2 = 1'b0; + reg wr_rst_asreg_d3 = 1'b0; + reg rd_rst_wr_d0 = 1'b0; + reg rd_rst_wr_d1 = 1'b0; + reg rd_rst_wr_d2 = 1'b0; + reg wr_rst_reg = 1'b0; + reg rst_active_i = 1'b1; + reg rst_delayed_d1 = 1'b1; + reg rst_delayed_d2 = 1'b1; + reg wr_rst_comb = 1'b1; + reg wr_rst_comb_d1 = 1'b0; + wire wr_rst_i; + wire rd_rst_i; + wire rst_i; + + //Internal reset signals + reg rst_asreg = 1'b0; + reg srst_asreg = 1'b0; + reg rst_asreg_d1 = 1'b0; + reg rst_asreg_d2 = 1'b0; + reg srst_asreg_d1 = 1'b0; + reg srst_asreg_d2 = 1'b0; + reg rst_reg = 1'b0; + reg srst_reg = 1'b0; + reg rst_comb = 1'b1; + reg rst_comb_d1 = 1'b0; + wire srst_comb; + reg rst_full_gen_i = 0; + reg rst_full_ff_i = 0; + reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}}; + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire fifo_empty_fb; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + wire sbiterr_fifo_out; + wire dbiterr_fifo_out; + wire inject_sbit_err; + wire inject_dbit_err; + wire sckt_wr_rst_i; + wire sckt_rd_rst_i; + reg sckt_wr_rst_i_q = 1'b0; + + wire w_fab_read_data_valid_i; + wire w_read_data_valid_i; + wire w_ram_valid_i; + // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. + assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? + injectsbiterr_delayed : 0; + assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? + injectdbiterr_delayed : 0; + + assign wr_rst_i_out = wr_rst_i; + assign rd_rst_i_out = rd_rst_i; + assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2]; + generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o + wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK; + always @ (posedge clk_i) + sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; + end endgenerate +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) + + localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; +generate +case (C_VERILOG_IMPL) +0 : begin : block1_ss + //Common Clock Behavioral Model + fifo_generator_v13_2_4_bhv_ver_ss + #( + .C_FAMILY (C_FAMILY), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST), + .C_HAS_SRST (C_EN_SAFETY_CKT?1:C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_USE_ECC (C_USE_ECC), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), + .C_FIFO_TYPE (C_FIFO_TYPE) + ) + gen_ss + ( + .SAFETY_CKT_WR_RST (sckt_wr_rst_i), + .CLK (CLK), + .RST (C_EN_SAFETY_CKT?1'b0:rst_i), + .SRST (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .DIN (din_delayed), + .WR_EN (wr_en_delayed), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (rd_en_delayed), + .USER_EMPTY_FB (empty_fb), + .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), + .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), + .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), + .PROG_FULL_THRESH (prog_full_thresh_delayed), + .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), + .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .EMPTY_FB (fifo_empty_fb), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .WR_RST_BUSY (wr_rst_busy), + .RD_RST_BUSY (rd_rst_busy), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end +1 : begin : block1_as + //Independent Clocks Behavioral Model + fifo_generator_v13_2_4_bhv_ver_as + #( + .C_FAMILY (C_FAMILY), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_USE_ECC (C_USE_ECC), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + gen_as + ( + .SAFETY_CKT_WR_RST (sckt_wr_rst_i), + .SAFETY_CKT_RD_RST (sckt_rd_rst_i), + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (din_delayed), + .WR_EN (wr_en_delayed), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (rd_en_delayed), + .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), + .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), + .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), + .PROG_FULL_THRESH (prog_full_thresh_delayed), + .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), + .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .EMPTY_FB (fifo_empty_fb), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .fab_read_data_valid_i (w_fab_read_data_valid_i), + .read_data_valid_i (w_read_data_valid_i), + .ram_valid_i (w_ram_valid_i), + .DBITERR (dbiterr_fifo_out) + ); +end + +2 : begin : ll_afifo_inst + fifo_generator_v13_2_4_beh_ver_ll_afifo + #( + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_FIFO_TYPE (C_FIFO_TYPE) + ) + gen_ll_afifo + ( + .DIN (din_delayed), + .RD_CLK (RD_CLK), + .RD_EN (rd_en_delayed), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .WR_CLK (WR_CLK), + .WR_EN (wr_en_delayed), + .DOUT (DOUT), + .EMPTY (EMPTY), + .FULL (FULL) + ); +end +default : begin : block1_as + //Independent Clocks Behavioral Model + fifo_generator_v13_2_4_bhv_ver_as + #( + .C_FAMILY (C_FAMILY), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_USE_ECC (C_USE_ECC), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + gen_as + ( + .SAFETY_CKT_WR_RST (sckt_wr_rst_i), + .SAFETY_CKT_RD_RST (sckt_rd_rst_i), + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (din_delayed), + .WR_EN (wr_en_delayed), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (rd_en_delayed), + .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), + .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), + .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), + .PROG_FULL_THRESH (prog_full_thresh_delayed), + .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), + .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .EMPTY_FB (fifo_empty_fb), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + wire rd_en_to_fwft_fifo; + wire sbiterr_fwft; + wire dbiterr_fwft; + wire [C_DOUT_WIDTH-1:0] dout_fwft; + wire empty_fwft; + wire rd_en_fifo_in; + wire stage2_reg_en_i; + wire [1:0] valid_stages_i; + wire rst_fwft; + //wire empty_p0_out; + reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1; + + localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; + localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0; + localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0; + assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0; + + generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft + + + fifo_generator_v13_2_4_bhv_ver_preload0 + #( + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_HAS_RST (C_HAS_RST), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_HAS_SRST (C_HAS_SRST), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_USE_ECC (C_USE_ECC), + .C_USERVALID_LOW (C_VALID_LOW), + .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_FIFO_TYPE (C_FIFO_TYPE) + ) + fgpl0 + ( + .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (srst_delayed), + .WR_RST_BUSY (wr_rst_busy), + .RD_RST_BUSY (rd_rst_busy), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .FIFOSBITERR (sbiterr_fifo_out), + .FIFODBITERR (dbiterr_fifo_out), + // Output + .USERDATA (dout_fwft), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (empty_fwft), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (), + .FIFORDEN (rd_en_fifo_in), + .USERSBITERR (sbiterr_fwft), + .USERDBITERR (dbiterr_fwft), + .STAGE2_REG_EN (stage2_reg_en_i), + .fab_read_data_valid_i_o (w_fab_read_data_valid_i), + .read_data_valid_i_o (w_read_data_valid_i), + .ram_valid_i_o (w_ram_valid_i), + .VALID_STAGES (valid_stages_i) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; + assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; + assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign VALID = VALID_P0_OUT ; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = rd_en_fifo_in; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + EMPTY_P0_OUT_Q <= 1; + ALMOSTEMPTY_P0_OUT_Q <= 1; + end else begin + EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out; +// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin + if (C_VALID_LOW == 1) begin + SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ; + end else begin + SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ; + end + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + DATA_COUNT_FWFT <= 0; + end else begin + //if (srst_delayed && (C_HAS_SRST == 1) ) begin + if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + end endgenerate // : block2 + + // AXI Streaming Packet FIFO + reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0; + reg partial_packet = 0; + reg stage1_eop_d1 = 0; + reg rd_en_fifo_in_d1 = 0; + reg eop_at_stage2 = 0; + reg ram_pkt_empty = 0; + reg ram_pkt_empty_d1 = 0; + + wire [C_DOUT_WIDTH-1:0] dout_p0_out; + wire packet_empty_wr; + wire wr_rst_fwft_pkt_fifo; + wire dummy_wr_eop; + wire ram_wr_en_pkt_fifo; + wire wr_eop; + wire ram_rd_en_compare; + wire stage1_eop; + wire pkt_ready_to_read; + wire rd_en_2_stage2; + + // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming) + // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP + // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of + // write packet count + generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + partial_packet <= 1'b0; + else begin + if (srst_delayed | wr_rst_busy | rd_rst_busy) + partial_packet <= #`TCQ 1'b0; + else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0])) + partial_packet <= #`TCQ 1'b1; + else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo) + partial_packet <= #`TCQ 1'b0; + end + end + end endgenerate // gdummy_wr_eop + + generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft + assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0; + assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet); + assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1]; + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + stage1_eop_d1 <= 1'b0; + rd_en_fifo_in_d1 <= 1'b0; + end else begin + if (srst_delayed | wr_rst_busy | rd_rst_busy) begin + stage1_eop_d1 <= #`TCQ 1'b0; + rd_en_fifo_in_d1 <= #`TCQ 1'b0; + end else begin + stage1_eop_d1 <= #`TCQ stage1_eop; + rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in; + end + end + end + assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1; + assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT); + assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop); + assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop; + + + fifo_generator_v13_2_4_bhv_ver_preload0 + #( + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_ECC (C_USE_ECC), + .C_USERVALID_LOW (C_VALID_LOW), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_FIFO_TYPE (2) // Enable low latency fwft logic + ) + pkt_fifo_fwft + ( + .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (rst_fwft), + .SRST (srst_delayed), + .WR_RST_BUSY (wr_rst_busy), + .RD_RST_BUSY (rd_rst_busy), + .RD_EN (rd_en_delayed), + .FIFOEMPTY (pkt_ready_to_read), + .FIFODATA (dout_fwft), + .FIFOSBITERR (sbiterr_fwft), + .FIFODBITERR (dbiterr_fwft), + // Output + .USERDATA (dout_p0_out), + .USERVALID (), + .USEREMPTY (empty_p0_out), + .USERALMOSTEMPTY (), + .USERUNDERFLOW (), + .RAMVALID (), + .FIFORDEN (rd_en_2_stage2), + .USERSBITERR (SBITERR), + .USERDBITERR (DBITERR), + .STAGE2_REG_EN (), + .VALID_STAGES () + ); + + assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2)); + assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2; + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) + eop_at_stage2 <= 1'b0; + else if (stage2_reg_en_i) + eop_at_stage2 <= #`TCQ stage1_eop; + end + + //--------------------------------------------------------------------------- + // Write and Read Packet Count + //--------------------------------------------------------------------------- + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + wr_pkt_count <= 0; + else if (srst_delayed | wr_rst_busy | rd_rst_busy) + wr_pkt_count <= #`TCQ 0; + else if (wr_eop) + wr_pkt_count <= #`TCQ wr_pkt_count + 1; + end + + end endgenerate //: gpkt_fifo_fwft + + assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out; + assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out; + + generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + rd_pkt_count <= 0; + rd_pkt_count_plus1 <= 1; + end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin + rd_pkt_count <= #`TCQ 0; + rd_pkt_count_plus1 <= #`TCQ 1; + end else if (stage2_reg_en_i && stage1_eop) begin + rd_pkt_count <= #`TCQ rd_pkt_count + 1; + rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1; + end + end + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + ram_pkt_empty <= 1'b1; + ram_pkt_empty_d1 <= 1'b1; + end else if (SRST | wr_rst_busy | rd_rst_busy) begin + ram_pkt_empty <= #`TCQ 1'b1; + ram_pkt_empty_d1 <= #`TCQ 1'b1; + end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin + ram_pkt_empty <= #`TCQ 1'b0; + ram_pkt_empty_d1 <= #`TCQ 1'b0; + end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin + ram_pkt_empty <= #`TCQ 1'b1; + end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin + ram_pkt_empty_d1 <= #`TCQ 1'b1; + end + end + end endgenerate //grss_pkt_cnt + + localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH; + reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0; + wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd; + generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt + // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + wr_pkt_count_b2g <= 0; + else + wr_pkt_count_b2g <= #`TCQ wr_pkt_count; + end + + // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) + wr_pkt_count_q <= 0; + else + wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g}; + end + + always @* begin + if (stage1_eop) + rd_pkt_count <= rd_pkt_count_reg + 1; + else + rd_pkt_count <= rd_pkt_count_reg; + end + + assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH]; + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) + rd_pkt_count_reg <= 0; + else if (rd_en_fifo_in) + rd_pkt_count_reg <= #`TCQ rd_pkt_count; + end + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + ram_pkt_empty <= 1'b1; + ram_pkt_empty_d1 <= 1'b1; + end else if (rd_pkt_count != wr_pkt_count_rd) begin + ram_pkt_empty <= #`TCQ 1'b0; + ram_pkt_empty_d1 <= #`TCQ 1'b0; + end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin + ram_pkt_empty <= #`TCQ 1'b1; + end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin + ram_pkt_empty_d1 <= #`TCQ 1'b1; + end + end + + // Synchronize the empty in write domain + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + pkt_empty_sync <= 'b1; + else + pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out}; + end + + end endgenerate //gras_pkt_cnt + + generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = rd_en_delayed; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + assign SBITERR = sbiterr_fifo_out; + assign DBITERR = dbiterr_fifo_out; + + end endgenerate // STD_FIFO + + generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO + assign empty_p0_out = empty_fwft; + assign SBITERR = sbiterr_fwft; + assign DBITERR = dbiterr_fwft; + assign DOUT = dout_fwft; + assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; + + end endgenerate // NO_PKT_FIFO + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3 + if (C_COMMON_CLOCK == 0) begin : block_ic + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block_ic + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30 + if (C_COMMON_CLOCK == 0) begin : block_ic + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block30 + endgenerate + + + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both + if (C_COMMON_CLOCK == 0) begin : block_ic_both + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT)); + end + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block30_both + endgenerate + + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both + if (C_COMMON_CLOCK == 0) begin : block_ic_both + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT)); + end //block_ic_both + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block3_both + endgenerate + + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + /************************************************************************** + * find_log2 + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function integer find_log2; + input integer int_val; + integer i,j; + begin + i = 1; + j = 0; + for (i = 1; i < int_val; i = i*2) begin + j = j + 1; + end + find_log2 = j; + end + endfunction + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information."); + end else if (C_MEMORY_TYPE == 4) begin + $display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado."); + $finish; + end + + if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin + $display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH."); + $finish; + end + + if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin + $display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH."); + $finish; + end + + if (C_USE_ECC == 1) begin + if (C_DIN_WIDTH != C_DOUT_WIDTH) begin + $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration."); + $finish; + end + if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin + $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection."); + $finish; + end + end + + end //initial + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0; + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0; + assign rst_i = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0; + + wire rst_2_sync; + wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; + + localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5; + localparam RST_BUSY_LEN = 4; + reg wr_rst_busy_i = 0; + reg rd_rst_busy_i = 0; + generate + if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync + always @* begin + wr_rst_reg <= wr_rst_delayed; + rd_rst_reg <= rd_rst_delayed; + rst_reg <= 1'b0; + srst_reg <= 1'b0; + end + assign rst_2_sync = wr_rst_delayed; + assign wr_rst_busy = 1'b0; + assign wr_rst_busy_o = 1'b0; + assign rd_rst_busy = 1'b0; + assign sckt_wr_rst_i = 1'b0; + assign sckt_rd_rst_i = 1'b0; + end // gnrst_sync + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt + reg [1:0] arst_sync_wr = 2'b11; + reg [1:0] arst_sync_rd = 2'b11; + reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0; + reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0; + reg [3:0] rd_rst_wr_ext = 0; + reg [1:0] wr_rst_rd_ext = 0; + reg sckt_wr_rst_ic = 0; + reg sckt_rd_rst_ic = 0; + + assign rst_2_sync = arst_sync_wr[1]; + + always @(posedge WR_CLK or posedge rst_delayed) begin + if (rst_delayed == 1'b1) + arst_sync_wr <= #`TCQ 2'b11; + else + arst_sync_wr <= #`TCQ {arst_sync_wr[0], rst_delayed}; + end + + always @(posedge RD_CLK or posedge rst_delayed) begin + if (rst_delayed == 1'b1) + arst_sync_rd <= #`TCQ 2'b11; + else + arst_sync_rd <= #`TCQ {arst_sync_rd[0], rst_delayed}; + end + always @(posedge WR_CLK) begin + sckt_rd_rst_wr <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic}; + end + always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin + if (arst_sync_wr[1]) begin + sckt_wr_rst_ic <= #`TCQ 1'b1; + wr_rst_busy_i <= #`TCQ 1'b1; + rd_rst_wr_ext <= #`TCQ {RST_SYNC_STAGES{1'b0}}; + end else begin + rd_rst_wr_ext <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]}; + if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0]) + sckt_wr_rst_ic <= #`TCQ 1'b0; + else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2]) + wr_rst_busy_i <= #`TCQ 1'b0; + end + end + always @(posedge RD_CLK) begin + sckt_wr_rst_rd <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic}; + end + always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin + if (arst_sync_rd[1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b1; + rd_rst_busy_i <= #`TCQ 1'b1; + wr_rst_rd_ext <= #`TCQ {RST_SYNC_STAGES{1'b0}}; + end else begin + wr_rst_rd_ext <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]}; + if (wr_rst_rd_ext[1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b0; + rd_rst_busy_i <= #`TCQ 1'b0; + end + end + end + + assign rd_rst_busy = rd_rst_busy_i; + assign wr_rst_busy = wr_rst_busy_i; + assign wr_rst_busy_o = wr_rst_busy_i; + assign sckt_wr_rst_i = sckt_wr_rst_ic|arst_sync_wr[1]; + assign sckt_rd_rst_i = sckt_rd_rst_ic|arst_sync_rd[1]; + end // g7s_ic_rst_nsckt + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt + reg [RST_SYNC_STAGES-1:0] arst_sync_wr = {RST_SYNC_STAGES{1'b1}}; + reg [RST_SYNC_STAGES-1:0] arst_sync_rd = {RST_SYNC_STAGES{1'b1}}; + reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0; + reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0; + reg [3:0] rd_rst_wr_ext = 0; + reg [1:0] wr_rst_rd_ext = 0; + reg sckt_wr_rst_ic = 0; + reg sckt_rd_rst_ic = 0; + + always @(posedge WR_CLK) begin + arst_sync_wr <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed}; + sckt_rd_rst_wr <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic}; + rd_rst_wr_ext <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]}; + if (arst_sync_wr[RST_SYNC_STAGES-1]) begin + sckt_wr_rst_ic <= #`TCQ 1'b1; + wr_rst_busy_i <= #`TCQ 1'b1; + end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0]) + sckt_wr_rst_ic <= #`TCQ 1'b0; + else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2]) + wr_rst_busy_i <= #`TCQ 1'b0; + end + always @(posedge RD_CLK) begin + arst_sync_rd <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed}; + sckt_wr_rst_rd <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]}; + wr_rst_rd_ext <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]}; + if (arst_sync_rd[RST_SYNC_STAGES-1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b1; + rd_rst_busy_i <= #`TCQ 1'b1; + end else if (wr_rst_rd_ext[1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b0; + rd_rst_busy_i <= #`TCQ 1'b0; + end + end + + assign rd_rst_busy = rd_rst_busy_i; + assign wr_rst_busy = wr_rst_busy_i; + assign wr_rst_busy_o = wr_rst_busy_i; + assign sckt_wr_rst_i = sckt_wr_rst_ic; + assign sckt_rd_rst_i = sckt_rd_rst_ic; + end // g7s_ic_rst_sckt + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt + reg [1:0] arst_sync_wr = 0; + reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0; + assign rst_2_sync = arst_sync_wr[1]; + + always @(posedge CLK or posedge rst_delayed) begin + if (rst_delayed == 1'b1) + arst_sync_wr <= #`TCQ 2'b11; + else + arst_sync_wr <= #`TCQ {arst_sync_wr[0], rst_delayed}; + end + + always @(posedge CLK) begin + sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]}; + end + + assign sckt_wr_rst_i = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; + assign sckt_rd_rst_i = sckt_wr_rst_i; + assign wr_rst_busy = |sckt_wr_rst_cc | arst_sync_wr[1]; + assign rd_rst_busy = |sckt_wr_rst_cc; + assign wr_rst_busy_o = |sckt_wr_rst_cc; + end // g7s_cc_rst_nsckt + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt + reg [RST_SYNC_STAGES-1:0] arst_sync_wr = 0; + reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0; + + always @(posedge CLK) begin + arst_sync_wr <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed}; + sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]}; + end + + assign sckt_wr_rst_i = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; + assign sckt_rd_rst_i = sckt_wr_rst_i; + assign wr_rst_busy = |sckt_wr_rst_cc; + assign rd_rst_busy = |sckt_wr_rst_cc; + assign wr_rst_busy_o = |sckt_wr_rst_cc; + end // g7s_cc_rst_sckt + else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst + assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i; + assign rd_rst_busy = rst_reg; + assign rst_2_sync = srst_delayed; + assign sckt_wr_rst_i = rst_reg; + always @* rst_full_ff_i <= 1'b0; + always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0; + + always @(posedge CLK) begin + rst_delayed_d1 <= #`TCQ srst_delayed; + rst_delayed_d2 <= #`TCQ rst_delayed_d1; + if (rst_reg || rst_delayed_d2) begin + rst_active_i <= #`TCQ 1'b1; + end else begin + rst_active_i <= #`TCQ rst_reg; + end + end + always @(posedge CLK) begin + if (~rst_reg && srst_delayed) begin + rst_reg <= #`TCQ 1'b1; + end else if (rst_reg) begin + rst_reg <= #`TCQ 1'b0; + end else begin + rst_reg <= #`TCQ rst_reg; + end + end + end // g8s_cc_rst + else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst + assign wr_rst_busy = srst_delayed; + assign rd_rst_busy = srst_delayed; + assign rst_2_sync = srst_delayed; + assign sckt_wr_rst_i = srst_delayed; + always @* rst_full_ff_i <= 1'b0; + end // g7s_cc_srst + endgenerate + + reg rst_d1 = 1'b0; + reg rst_d2 = 1'b0; + reg rst_d3 = 1'b0; + reg rst_d4 = 1'b0; + generate + if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 + // RST_FULL_GEN replaces the reset falling edge detection used to de-assert + // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. + + // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & + // PROG_FULL + + always @ (posedge rst_2_sync or posedge clk_2_sync) begin + if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin + rst_d1 <= 1'b1; + rst_d2 <= 1'b1; + rst_d3 <= 1'b1; + rst_d4 <= 1'b0; + end else begin + if (srst_delayed) begin + rst_d1 <= #`TCQ 1'b1; + rst_d2 <= #`TCQ 1'b1; + rst_d3 <= #`TCQ 1'b1; + rst_d4 <= #`TCQ 1'b0; + end else begin + rst_d1 <= #`TCQ wr_rst_busy;//1'b0; + rst_d2 <= #`TCQ rst_d1; + rst_d3 <= #`TCQ rst_d2 | sckt_wr_rst_i; + rst_d4 <= #`TCQ rst_d3; + end + end + end + + always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i; + always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3; + + end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt + always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; + always @* rst_full_gen_i <= 1'b0; + end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full + always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; + always @* rst_full_gen_i <= 1'b0; + end + endgenerate // grstd1 + +endmodule //fifo_generator_v13_2_4_CONV_VER + + +module fifo_generator_v13_2_4_sync_stage + #( + parameter C_WIDTH = 10 + ) + ( + input RST, + input CLK, + input [C_WIDTH-1:0] DIN, + output reg [C_WIDTH-1:0] DOUT = 0 + ); + always @ (posedge RST or posedge CLK) begin + if (RST) + DOUT <= 0; + else + DOUT <= #`TCQ DIN; + end +endmodule // fifo_generator_v13_2_4_sync_stage + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v13_2_4_bhv_ver_as + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + #( + parameter C_FAMILY = "virtex7", + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_SYNCHRONIZER_STAGE = 2 + ) + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + ( + input SAFETY_CKT_WR_RST, + input SAFETY_CKT_RD_RST, + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_CLK, + input RD_EN, + input RD_EN_USER, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input WR_RST, + input RD_RST, + input WR_CLK, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + input USER_EMPTY_FB, + input fab_read_data_valid_i, + input read_data_valid_i, + input ram_valid_i, + output reg ALMOST_EMPTY = 1'b1, + output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, + output [C_DOUT_WIDTH-1:0] DOUT, + output reg EMPTY = 1'b1, + output reg EMPTY_FB = 1'b1, + output reg FULL = C_FULL_FLAGS_RST_VAL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output UNDERFLOW, + output WR_ACK, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output SBITERR, + output DBITERR + ); + + + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + localparam C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + localparam C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); + + localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + wire wr_rst_i = WR_RST; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + wire rd_rst_i = RD_RST; + wire ram_rd_en; + wire empty_int; + wire almost_empty_int; + wire ram_wr_en; + wire full_int; + wire almost_full_int; + reg ram_rd_en_d1 = 1'b0; + reg fab_rd_en_d1 = 1'b0; + + + + // Delayed ram_rd_en is needed only for STD Embedded register option + generate + if (C_PRELOAD_LATENCY == 2) begin : grd_d + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + end + endgenerate + + generate + if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1 + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; + end + end + endgenerate + + + + // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; + end else begin : rdl // Read depth lesser than or equal to write depth + assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + endgenerate + + // Generate Empty and Almost Empty + // ram_rd_en used to determine EMPTY should depend on the EMPTY. + assign ram_rd_en = RD_EN & !EMPTY; + assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); + assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); + + // Register Empty and Almost Empty + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin + EMPTY <= 1'b1; + ALMOST_EMPTY <= 1'b1; + rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}}; + end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin + EMPTY <= 1'b1; + ALMOST_EMPTY <= 1'b1; + rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}}; + end else begin + rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; + + if (empty_int) + EMPTY <= #`TCQ 1'b1; + else + EMPTY <= #`TCQ 1'b0; + + if (!EMPTY) begin + if (almost_empty_int) + ALMOST_EMPTY <= #`TCQ 1'b1; + else + ALMOST_EMPTY <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin + EMPTY_FB <= 1'b1; + end else begin + if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) + EMPTY_FB <= #`TCQ 1'b1; + else if (empty_int) + EMPTY_FB <= #`TCQ 1'b1; + else + EMPTY_FB <= #`TCQ 1'b0; + end // rd_rst_i + end // always + + // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; + end else begin : wdl // Write depth lesser than or equal to read depth + assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end + endgenerate + + // Generate FULL and ALMOST_FULL + // ram_wr_en used to determine FULL should depend on the FULL. + assign ram_wr_en = WR_EN & !FULL; + assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); + assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); + + // Register FULL and ALMOST_FULL Empty + always @ (posedge WR_CLK or posedge RST_FULL_FF) + begin + if (RST_FULL_FF & C_HAS_RST) begin + FULL <= C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= C_FULL_FLAGS_RST_VAL; + end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin + FULL <= C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= C_FULL_FLAGS_RST_VAL; + end else begin + if (full_int) begin + FULL <= #`TCQ 1'b1; + end else begin + FULL <= #`TCQ 1'b0; + end + + if (RST_FULL_GEN) begin + ALMOST_FULL <= #`TCQ 1'b0; + end else if (!FULL) begin + if (almost_full_int) + ALMOST_FULL <= #`TCQ 1'b1; + else + ALMOST_FULL <= #`TCQ 1'b0; + end + end // wr_rst_i + end // always + always @ (posedge WR_CLK or posedge wr_rst_i) + begin + if (wr_rst_i) begin + wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}}; + end else begin + wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; + end // wr_rst_i + end // always + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + stage1_valid <= 0; + stage2_valid <= 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out1; + wire valid_out2; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [1:0] err_type_both = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = C_OVERFLOW_LOW; + reg ideal_underflow = C_UNDERFLOW_LOW; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + reg valid_d2 = 0; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) begin + $display("FAILURE : Data width must be >= 2 for double bit error injection."); + $finish; + end else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + err_type_d1 = 0; + err_type_both = 0; + ideal_dout_d1 = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + valid_d2 = 1'b0; + ideal_overflow = C_OVERFLOW_LOW; + ideal_underflow = C_UNDERFLOW_LOW; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //*************************************************************************** + // Dout may change behavior based on latency + //*************************************************************************** + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + //*************************************************************************** + // Assign SBITERR and DBITERR based on latency + //*************************************************************************** + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY == 2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + //*************************************************************************** + // Safety-ckt logic with embedded reg/fabric reg + //*************************************************************************** + generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + // if (C_HAS_VALID == 1) begin + // assign valid_out = valid_d1; + // end + + always@(posedge RD_CLK) + begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) + begin + if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) + ram_rd_en_d1 <= #`TCQ 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + + always@(posedge rst_delayed_sft2 or posedge RD_CLK) + begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + else begin + if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1[0] <= #`TCQ err_type[0]; + err_type_d1[1] <= #`TCQ err_type[1]; + end + end + end + end + endgenerate + +//*************************************************************************** + // Safety-ckt logic with embedded reg + fabric reg + //*************************************************************************** + generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge RD_CLK) begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin + if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) + ram_rd_en_d1 <= #`TCQ 1'b0; + else begin + ram_rd_en_d1 <= #`TCQ ram_rd_en; + fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; + end + end + + always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + end else begin + if (ram_rd_en_d1) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both[0] <= #`TCQ err_type[0]; + err_type_both[1] <= #`TCQ err_type[1]; + end + + if (fab_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1[0] <= #`TCQ err_type_both[0]; + err_type_d1[1] <= #`TCQ err_type_both[1]; + end + end + end + end + endgenerate + + //*************************************************************************** + // Overflow may be active-low + //*************************************************************************** + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //*************************************************************************** + // Valid may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out1 = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)? + valid_d1: valid_i; + assign valid_out2 = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)? + valid_d2: valid_i; + assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + + //*************************************************************************** + // Underflow may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //*************************************************************************** + // Write acknowledge may be active low + //*************************************************************************** + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext + + reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; + reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; + wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; + wire [C_PNTR_WIDTH:0] diff_wr_rd; + reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; + always @* begin + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = 0; + adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin + adjusted_rd_pntr = rd_pntr_wr; + adjusted_wr_pntr = 0; + adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + end else begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = rd_pntr_wr; + end + end // always @* + + assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; + assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; + + always @ (posedge wr_rst_i or posedge WR_CLK) + begin + if (wr_rst_i) + wr_data_count_i <= 0; + else + wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; + end // always @ (posedge WR_CLK or posedge WR_CLK) + + always @* begin + if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; + else + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end // always @* + end // wdc_fwft_ext + endgenerate + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; + + generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= 0; + end else begin + if (!stage2_valid) + rdc_fwft_ext_as <= #`TCQ 0; + else if (!stage1_valid && stage2_valid) + rdc_fwft_ext_as <= #`TCQ 1; + else + rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; + end + end // always @ (posedge WR_CLK or posedge WR_CLK) + end // rdc_fwft_ext + end + endgenerate + + + generate if (C_USE_EMBEDDED_REG == 3) begin + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1; + // assign diff_rd_wr_1 = diff_rd_wr +2'h2; + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= #`TCQ 0; + end else begin + //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1))) + // rdc_fwft_ext_as <= 1'b0; + //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) + // rdc_fwft_ext_as <= 1'b1; + //else + rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ; + end + + + +end +end +end +endgenerate + + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? + rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : + rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? + wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : + wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= 1'b0; + valid_d2 <= 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + valid_d2 <= #`TCQ valid_d1; + end +// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin + // valid_d2 <= #`TCQ valid_d1; + // end + end + end + endgenerate + + //Capture delayed version of dout + /************************************************************************** + *embedded/fabric reg with no safety ckt + **************************************************************************/ + generate + if (C_USE_EMBEDDED_REG < 3) begin + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout <= #`TCQ dout_reset_val; + end + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + +end +endgenerate +/************************************************************************** + *embedded + fabric reg with no safety ckt + **************************************************************************/ + +generate + if (C_USE_EMBEDDED_REG == 3) begin + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + end else begin + if (ram_rd_en_d1) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both <= #`TCQ err_type; + end + if (fab_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1 <= #`TCQ err_type_both; + end + end + end + end +endgenerate + + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw + always @(posedge WR_CLK) begin + ideal_overflow <= #`TCQ WR_EN & FULL; + end + end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw + always @(posedge WR_CLK) begin + //ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i); + ideal_overflow <= #`TCQ WR_EN & (FULL ); + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ EMPTY & RD_EN; + end + end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ (EMPTY) & RD_EN; + //ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write/Read Pointer Synchronization + **************************************************************************/ + localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1; + wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; + wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; + genvar gss; + + generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst + fifo_generator_v13_2_4_sync_stage + #( + .C_WIDTH (C_WR_PNTR_WIDTH) + ) + rd_stg_inst + ( + .RST (rd_rst_i), + .CLK (RD_CLK), + .DIN (wr_pntr_sync_stgs[gss-1]), + .DOUT (wr_pntr_sync_stgs[gss]) + ); + + fifo_generator_v13_2_4_sync_stage + #( + .C_WIDTH (C_RD_PNTR_WIDTH) + ) + wr_stg_inst + ( + .RST (wr_rst_i), + .CLK (WR_CLK), + .DIN (rd_pntr_sync_stgs[gss-1]), + .DOUT (rd_pntr_sync_stgs[gss]) + ); + end endgenerate // Sync_stage_inst + + assign wr_pntr_sync_stgs[0] = wr_pntr_rd1; + assign rd_pntr_sync_stgs[0] = rd_pntr_wr1; + always@* begin + wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; + rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; + end + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp + if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0) + wr_pntr <= 0; + else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1) + wr_pntr <= #`TCQ 0; + end + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= 0; + next_num_wr_bits = 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr_wrclk <= C_RD_DEPTH - 1; + ideal_wr_ack <= 0; + ideal_wr_count <= 0; + tmp_wr_listsize = 0; + rd_ptr_wrclk_next <= 0; + wr_pntr_rd1 <= 0; + + end else begin //wr_rst_i==0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //With DEPTH-1 words in the FIFO, it is almost_full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //FIFO is really not close to full, so change flag status. + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //This write is CAUSING the FIFO to go full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Still 2 from full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //wr_rst_i==0 + end // gen_fifo_w + + + /*************************************************************************** + * Programmable FULL flags + ***************************************************************************/ + + wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val; + wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val; + + generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT + assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC; + assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC; + end else begin // STD + assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL; + assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL; + end endgenerate + + always @(posedge WR_CLK or posedge wr_rst_i) begin + + if (wr_rst_i == 1'b1) begin + diff_pntr <= 0; + end else begin + if (ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); + else if (!ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); + end + end + + + always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf + + if (RST_FULL_FF & C_HAS_RST) begin + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + end else begin + + if (RST_FULL_GEN) + ideal_prog_full <= #`TCQ 0; + //Single Programmable Full Constant Threshold + else if (C_PROG_FULL_TYPE == 1) begin + if (FULL == 0) begin + if (diff_pntr >= pf_thr_assert_val) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if (FULL == 0) begin + if (diff_pntr >= pf_thr_assert_val) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < pf_thr_negate_val) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE == 3) begin + if (FULL == 0) begin + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else begin // STD + if (diff_pntr >= PROG_FULL_THRESH) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE == 4) begin + if (FULL == 0) begin + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else begin // STD + if (diff_pntr >= PROG_FULL_THRESH_ASSERT) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < PROG_FULL_THRESH_NEGATE) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + end // C_PROG_FULL_TYPE + + end //wr_rst_i==0 + end // + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + + wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val; + wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe + + if (rd_rst_i & C_HAS_RST) begin + diff_pntr_rd <= 0; + ideal_prog_empty <= 1'b1; + end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin + diff_pntr_rd <= 0; + ideal_prog_empty <= 1'b1; + end else begin + if (ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; + else if (!ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); + else + diff_pntr_rd <= #`TCQ diff_pntr_rd; + + if (C_PROG_EMPTY_TYPE == 1) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 2) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 3) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 4) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end //C_PROG_EMPTY_TYPE + end + end // gen_pe + + generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input + assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH; + end endgenerate // single_pe_thr_input + + generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input + assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT; + assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE; + end endgenerate // multiple_pe_thr_input + + generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const + assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL; + assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL; + end endgenerate // single_multiple_pe_thr_const + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp + if (rd_rst_i && C_EN_SAFETY_CKT == 0) + rd_pntr <= 0; + else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1) + rd_pntr <= #`TCQ 0; + end + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i & C_HAS_RST) begin + num_rd_bits <= 0; + next_num_rd_bits = 0; + rd_ptr <= C_RD_DEPTH -1; + rd_pntr_wr1 <= 0; + wr_ptr_rdclk <= C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= 0; + err_type_d1 <= 0; + err_type_both <= 0; + end + ideal_valid <= 1'b0; + ideal_rd_count <= 0; + + end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin + num_rd_bits <= 0; + next_num_rd_bits = 0; + rd_ptr <= C_RD_DEPTH -1; + rd_pntr_wr1 <= 0; + wr_ptr_rdclk <= C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= 0; + err_type_d1 <= 0; + err_type_both <= 0; + end + ideal_valid <= 1'b0; + ideal_rd_count <= 0; + end else begin //rd_rst_i==0 + + rd_pntr_wr1 <= #`TCQ rd_pntr; + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + ideal_valid <= #`TCQ 1'b0; + + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + ideal_valid <= #`TCQ 1'b0; + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //rd_rst_i==0 + end //always gen_fifo_r_as + +endmodule // fifo_generator_v13_2_4_bhv_ver_as + + +/******************************************************************************* + * Declaration of Low Latency Asynchronous FIFO + ******************************************************************************/ +module fifo_generator_v13_2_4_beh_ver_ll_afifo + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + #( + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_USE_DOUT_RST = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_FIFO_TYPE = 0 + ) + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + ( + input [C_DIN_WIDTH-1:0] DIN, + input RD_CLK, + input RD_EN, + input WR_RST, + input RD_RST, + input WR_CLK, + input WR_EN, + output reg [C_DOUT_WIDTH-1:0] DOUT = 0, + output reg EMPTY = 1'b1, + output reg FULL = C_FULL_FLAGS_RST_VAL + ); + + //----------------------------------------------------------------------------- + // Low Latency Asynchronous FIFO + //----------------------------------------------------------------------------- + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + integer i; + initial begin + for (i = 0; i < C_WR_DEPTH; i = i + 1) + memory[i] = 0; + end + + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0; + wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0; + reg ll_afifo_full = 1'b0; + reg ll_afifo_empty = 1'b1; + wire write_allow; + wire read_allow; + + assign write_allow = WR_EN & ~ll_afifo_full; + assign read_allow = RD_EN & ~ll_afifo_empty; + + //----------------------------------------------------------------------------- + // Write Pointer Generation + //----------------------------------------------------------------------------- + always @(posedge WR_CLK or posedge WR_RST) begin + if (WR_RST) + wr_pntr_ll_afifo <= 0; + else if (write_allow) + wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1; + end + + //----------------------------------------------------------------------------- + // Read Pointer Generation + //----------------------------------------------------------------------------- + always @(posedge RD_CLK or posedge RD_RST) begin + if (RD_RST) + rd_pntr_ll_afifo_q <= 0; + else + rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo; + end + assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q; + + //----------------------------------------------------------------------------- + // Fill the Memory + //----------------------------------------------------------------------------- + always @(posedge WR_CLK) begin + if (write_allow) + memory[wr_pntr_ll_afifo] <= #`TCQ DIN; + end + + //----------------------------------------------------------------------------- + // Generate DOUT + //----------------------------------------------------------------------------- + always @(posedge RD_CLK) begin + DOUT <= #`TCQ memory[rd_pntr_ll_afifo]; + end + + //----------------------------------------------------------------------------- + // Generate EMPTY + //----------------------------------------------------------------------------- + always @(posedge RD_CLK or posedge RD_RST) begin + if (RD_RST) + ll_afifo_empty <= 1'b1; + else + ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | + (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1)))); + end + + //----------------------------------------------------------------------------- + // Generate FULL + //----------------------------------------------------------------------------- + always @(posedge WR_CLK or posedge WR_RST) begin + if (WR_RST) + ll_afifo_full <= 1'b1; + else + ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | + (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2)))); + end + + always @* begin + FULL <= ll_afifo_full; + EMPTY <= ll_afifo_empty; + end + +endmodule // fifo_generator_v13_2_4_beh_ver_ll_afifo + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v13_2_4_bhv_ver_ss + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + #( + parameter C_FAMILY = "virtex7", + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_FIFO_TYPE = 0 + ) + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + ( + //Inputs + input SAFETY_CKT_WR_RST, + input CLK, + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_EN, + input RD_EN_USER, + input USER_EMPTY_FB, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input SRST, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + input WR_RST_BUSY, + input RD_RST_BUSY, + + //Outputs + output ALMOST_EMPTY, + output ALMOST_FULL, + output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0, + output [C_DOUT_WIDTH-1:0] DOUT, + output EMPTY, + output reg EMPTY_FB = 1'b1, + output FULL, + output OVERFLOW, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output UNDERFLOW, + output WR_ACK, + output SBITERR, + output DBITERR + ); + + + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss; + wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + localparam C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + localparam C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; + + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); + localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + //localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); + + localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); + + localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + localparam C_HAS_FAST_FIFO = 0; + localparam C_FIFO_WR_DEPTH = C_WR_DEPTH; + localparam C_FIFO_RD_DEPTH = C_RD_DEPTH; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH; + localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1; + localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; + localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + + wire ram_rd_en; + wire empty_int; + wire almost_empty_int; + wire ram_wr_en; + wire full_int; + wire almost_full_int; + reg ram_rd_en_reg = 1'b0; + reg ram_rd_en_d1 = 1'b0; + reg fab_rd_en_d1 = 1'b0; + wire srst_rrst_busy; + + + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [1:0] err_type_both = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = C_OVERFLOW_LOW; + reg ideal_underflow = C_UNDERFLOW_LOW; + + reg full_i = C_FULL_FLAGS_RST_VAL; + reg full_i_temp = 0; + reg empty_i = 1; + reg almost_full_i = 0; + reg almost_empty_i = 1; + reg prog_full_i = 0; + reg prog_empty_i = 1; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0; + + reg write_allow_q = 0; + reg read_allow_q = 0; + reg valid_d1 = 0; + reg valid_both = 0; + reg valid_d2 = 0; + wire rst_i; + wire srst_i; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin + case (def_data[7:0]) + 8'b00000000 : begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) begin + if ((index*4)+j < C_DOUT_WIDTH) begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + //reg valid_d1 = 0; + + + //user specified value for reseting the size of the fifo + //reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) begin + $display("FAILURE : Data width must be >= 2 for double bit error injection."); + $finish; + end else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + + end + endtask + + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + err_type_d1 = 0; + err_type_both = 0; + ideal_dout_d1 = dout_reset_val; + ideal_dout_both = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + valid_both = 1'b0; + ideal_overflow = C_OVERFLOW_LOW; + ideal_underflow = C_UNDERFLOW_LOW; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + // Assign ALMOST_EPMTY + generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae + assign ALMOST_EMPTY = almost_empty_i; + end else begin : gnae + assign ALMOST_EMPTY = 0; + end endgenerate // gae + + // Assign ALMOST_FULL + generate if (C_HAS_ALMOST_FULL==1) begin : gaf + assign ALMOST_FULL = almost_full_i; + end else begin : gnaf + assign ALMOST_FULL = 0; + end endgenerate // gaf + + // Dout may change behavior based on latency + localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = empty_i; + assign FULL = full_i; + //saftey_ckt with one register + + generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge CLK) + begin + rst_delayed_sft1 <= #`TCQ rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) + begin + if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + valid_d1 <= #`TCQ 1'b0; + end + else begin + ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); + valid_d1 <= #`TCQ valid_i; + end + end + + always@(posedge rst_delayed_sft2 or posedge CLK) + begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + else if (srst_rrst_busy == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1[0] <= #`TCQ err_type[0]; + err_type_d1[1] <= #`TCQ err_type[1]; + end + end + end //if + endgenerate + +//safety ckt with both registers + +generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge CLK) begin + rst_delayed_sft1 <= #`TCQ rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin + if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + valid_d1 <= #`TCQ 1'b0; + end else begin + ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); + fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; + valid_both <= #`TCQ valid_i; + valid_d1 <= #`TCQ valid_both; + end + end + + always@(posedge rst_delayed_sft2 or posedge CLK) begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else if (srst_rrst_busy == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + if (ram_rd_en_d1) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both[0] <= #`TCQ err_type[0]; + err_type_both[1] <= #`TCQ err_type[1]; + end + if (fab_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1[0] <= #`TCQ err_type_both[0]; + err_type_d1[1] <= #`TCQ err_type_both[1]; + end + end + end + end //if + endgenerate + + + //Overflow may be active-low + generate if (C_HAS_OVERFLOW==1) begin : gof + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end else begin : gnof + assign OVERFLOW = 0; + end endgenerate // gof + + assign PROG_EMPTY = prog_empty_i; + assign PROG_FULL = prog_full_i; + + //Valid may change behavior based on latency or active-low + generate if (C_HAS_VALID==1) begin : gvalid + assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ? + valid_d1 : valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end else begin : gnvalid + assign VALID = 0; + end endgenerate // gvalid + + //Trim data count differently depending on set widths + generate if (C_HAS_DATA_COUNT == 1) begin : gdc + always @* begin + diff_count <= wr_pntr - rd_pntr; + if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin + DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count; + DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; + end else begin + DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end + end +// end else begin : gndc +// always @* DATA_COUNT <= 0; + end endgenerate // gdc + + //Underflow may change behavior based on latency or active-low + generate if (C_HAS_UNDERFLOW==1) begin : guf + assign underflow_i = ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end else begin : gnuf + assign UNDERFLOW = 0; + end endgenerate // guf + + + //Write acknowledge may be active low + generate if (C_HAS_WR_ACK==1) begin : gwr_ack + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end else begin : gnwr_ack + assign WR_ACK = 0; + end endgenerate // gwr_ack + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0; + assign rst_i = C_HAS_RST ? RST : 0; + assign srst_wrst_busy = srst_i; + assign srst_rrst_busy = srst_i; + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + if (srst_rrst_busy) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate // blockVL20 + + generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= 1'b0; + valid_both <= 1'b0; + end else begin + if (srst_rrst_busy) begin + valid_d1 <= #`TCQ 1'b0; + valid_both <= #`TCQ 1'b0; + + end else begin + valid_both <= #`TCQ valid_i; + valid_d1 <= #`TCQ valid_both; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate // blockVL20 + + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge CLK or posedge rst_i) begin + if (rst_i) begin + stage1_valid <= #`TCQ 0; + stage2_valid <= #`TCQ 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + //reg ram_rd_en_d1 = 1'b0; + //Capture delayed version of dout + generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + ram_rd_en_d1 <= #`TCQ 1'b0; + if (C_USE_DOUT_RST == 1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; + if (srst_rrst_busy) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + if (C_USE_DOUT_RST == 1) begin + // @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + if (ram_rd_en_d1 ) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + end + end // always +end +endgenerate + +//no safety ckt with both registers + generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + fab_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + + end + if (C_USE_DOUT_RST == 1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + end else begin + if (srst_rrst_busy) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + fab_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + if (C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; + fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1); + if (ram_rd_en_d1 ) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both <= #`TCQ err_type; + end + if (fab_rd_en_d1 ) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1 <= #`TCQ err_type_both; + end + end + end + end // always +end +endgenerate + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw + always @(posedge CLK) begin + ideal_overflow <= #`TCQ WR_EN & full_i; + end + end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw + always @(posedge CLK) begin + //ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i); + ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i); + end + end endgenerate // blockOF20 + + generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw + always @(posedge CLK) begin + ideal_underflow <= #`TCQ empty_i & RD_EN; + end + end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw + always @(posedge CLK) begin + //ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN; + ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN; + end + end endgenerate // blockUF20 + + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + wire write_allow; + wire read_allow; + wire read_allow_dc; + wire write_only; + wire read_only; + //wire write_only_q; + reg write_only_q; + //wire read_only_q; + reg read_only_q; + reg full_reg; + reg rst_full_ff_reg1; + reg rst_full_ff_reg2; + wire ram_full_comb; + wire carry; + + assign write_allow = WR_EN & ~full_i; + assign read_allow = RD_EN & ~empty_i; + assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB; + //assign write_only = write_allow & ~read_allow; + //assign write_only_q = write_allow_q; + //assign read_only = read_allow & ~write_allow; + //assign read_only_q = read_allow_q ; + wire [C_WR_PNTR_WIDTH-1:0] diff_pntr; + wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe; + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0; + reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0; + wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ; + wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym; + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max; + wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max; + + assign diff_pntr_pe_max = DIFF_MAX_RD; + assign diff_pntr_max = DIFF_MAX_WR; + + + + generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym + assign write_only = write_allow & ~read_allow; + assign read_only = read_allow & ~write_allow; + end endgenerate + generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd + assign read_only = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow; + assign write_only = write_allow & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])); + end endgenerate + generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr + assign read_only = read_allow & ~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); + assign write_only = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow; + end endgenerate + + + //----------------------------------------------------------------------------- + // Write and Read pointer generation + //----------------------------------------------------------------------------- + always @(posedge CLK or posedge rst_i) begin + if (rst_i && C_EN_SAFETY_CKT == 0) begin + wr_pntr <= 0; + rd_pntr <= 0; + end else begin + if (srst_i) begin + wr_pntr <= #`TCQ 0; + rd_pntr <= #`TCQ 0; + end else begin + if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1; + if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1; + end + end + end + + generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout + always @(posedge CLK) begin + if (write_allow) begin + if (ENABLE_ERR_INJECTION == 1) + memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN}; + else + memory[wr_pntr] <= #`TCQ DIN; + end + end + + reg [C_DATA_WIDTH-1:0] dout_tmp_q; + reg [C_DATA_WIDTH-1:0] dout_tmp = 0; + reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0; + always @(posedge CLK) begin + dout_tmp_q <= #`TCQ ideal_dout; + end + + + + always @* begin + if (read_allow) + ideal_dout <= memory[rd_pntr]; + else + ideal_dout <= dout_tmp_q; + end + end endgenerate // gll_dm_dout + + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + assign ram_rd_en = RD_EN & !EMPTY; + + //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + generate if (C_FIFO_TYPE != 2) begin : gnll_din + always @(posedge CLK or posedge rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (rst_i == 1'b1) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + + end else begin //rst_i==0 + if (srst_wrst_busy) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + end else begin//srst_i=0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + end else begin + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + ideal_wr_count <= num_write_words_sized_i; + + //end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //srst_i==0 + end //wr_rst_i==0 + end // gen_fifo_w + end endgenerate + + generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout + always @(posedge CLK) begin + if (rst_i || srst_rrst_busy) begin + if (C_USE_DOUT_RST == 1) begin + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + end + end + end endgenerate + + + + + generate if (C_FIFO_TYPE != 2) begin : gnll_dout + always @(posedge CLK or posedge rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rst_i) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + //rd_pntr_wr1 <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= #`TCQ 0; + err_type_d1 <= 0; + err_type_both <= 0; + end + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + + end else begin //rd_rst_i==0 + if (srst_rrst_busy) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + //rd_pntr_wr1 <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets synchronously + if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= #`TCQ 0; + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + end //srst_i + else begin + + //rd_pntr_wr1 <= #`TCQ rd_pntr; + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + if (RD_EN == 1'b1) begin + + if (EMPTY == 1'b1) begin + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end + else + begin + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + end + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //s_rst_i==0 + end //rd_rst_i==0 + end //always + end endgenerate + + //----------------------------------------------------------------------------- + // Generate diff_pntr for PROG_FULL generation + // Generate diff_pntr_pe for PROG_EMPTY generation + //----------------------------------------------------------------------------- + generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow + always @(posedge CLK ) begin + if (rst_i) begin + write_only_q <= 1'b0; + read_only_q <= 1'b0; + diff_pntr_reg1 <= 0; + diff_pntr_pe_reg1 <= 0; + diff_pntr_reg2 <= 0; + diff_pntr_pe_reg2 <= 0; + end else begin + if (srst_i || srst_wrst_busy || srst_rrst_busy) begin + if (srst_rrst_busy) begin + read_only_q <= #`TCQ 1'b0; + diff_pntr_pe_reg1 <= #`TCQ 0; + diff_pntr_pe_reg2 <= #`TCQ 0; + end + if (srst_wrst_busy) begin + write_only_q <= #`TCQ 1'b0; + diff_pntr_reg1 <= #`TCQ 0; + diff_pntr_reg2 <= #`TCQ 0; + end + end else begin + write_only_q <= #`TCQ write_only; + read_only_q <= #`TCQ read_only; + diff_pntr_reg2 <= #`TCQ diff_pntr_reg1; + diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1; + + // Add 1 to the difference pointer value when only write happens. + if (write_only) + diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1; + else + diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; + + // Add 1 to the difference pointer value when write or both write & read or no write & read happen. + if (read_only) + diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1; + else + diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr; + end + end + end + assign diff_pntr_pe = diff_pntr_pe_reg1; + assign diff_pntr = diff_pntr_reg1; + end endgenerate // reg_write_allow + + generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym + assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1}; + assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1}; + always @(posedge CLK ) begin + if (rst_i) begin + diff_pntr_pe_asym <= 0; + diff_pntr_reg1 <= 0; + full_reg <= 0; + rst_full_ff_reg1 <= 1; + rst_full_ff_reg2 <= 1; + diff_pntr_pe_reg1 <= 0; + end else begin + if (srst_i || srst_wrst_busy || srst_rrst_busy) begin + if (srst_wrst_busy) + diff_pntr_reg1 <= #`TCQ 0; + if (srst_rrst_busy) + full_reg <= #`TCQ 0; + rst_full_ff_reg1 <= #`TCQ 1; + rst_full_ff_reg2 <= #`TCQ 1; + diff_pntr_pe_asym <= #`TCQ 0; + diff_pntr_pe_reg1 <= #`TCQ 0; + end else begin + diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym; + full_reg <= #`TCQ full_i; + rst_full_ff_reg1 <= #`TCQ RST_FULL_FF; + rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1; + if (~full_i) begin + diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; + end + end + end + end + assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1]))); + assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1]; + assign diff_pntr = diff_pntr_reg1; + end endgenerate // reg_write_allow_asym + + + //----------------------------------------------------------------------------- + // Generate FULL flag + //----------------------------------------------------------------------------- + wire comp0; + wire comp1; + wire going_full; + wire leaving_full; + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad + assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0; + end endgenerate + + generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim + assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end endgenerate + + assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1)); + assign comp0 = (adj_rd_pntr_wr == wr_pntr); + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp + assign going_full = (comp1 & write_allow & ~read_allow); + assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN; + end endgenerate + + // Write data width is bigger than read data width + // Write depth is smaller than read depth + // One write could be equal to 2 or 4 or 8 reads + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym + assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); + assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp + assign going_full = (comp1 & write_allow & ~read_allow); + assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN; + end endgenerate + + + assign ram_full_comb = going_full | (~leaving_full & full_i); + + generate if (C_HAS_RST == 1) begin : grst_full + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF & C_HAS_RST) + full_i <= C_FULL_FLAGS_RST_VAL; + else + full_i <= #`TCQ ram_full_comb; + end + end endgenerate + + generate if (C_HAS_SRST == 1) begin : gsrst_full + always @(posedge CLK) begin + if (srst_wrst_busy) + full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else + full_i <= #`TCQ ram_full_comb; + end + end endgenerate + + generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full + always @(posedge CLK) begin + full_i <= #`TCQ ram_full_comb; + end + end endgenerate + + //----------------------------------------------------------------------------- + // Generate EMPTY flag + //----------------------------------------------------------------------------- + wire ecomp0; + wire ecomp1; + wire going_empty; + wire leaving_empty; + wire ram_empty_comb; + + + generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad + assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0; + end endgenerate + + generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim + assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end endgenerate + + assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1)); + assign ecomp0 = (adj_wr_pntr_rd == rd_pntr); + + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp + assign going_empty = (ecomp1 & ~write_allow & read_allow); + assign leaving_empty = (ecomp0 & write_allow); + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp + assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); + assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); + end endgenerate + + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp + assign going_empty = (ecomp1 & ~write_allow & read_allow); + assign leaving_empty =(ecomp0 & write_allow); + end endgenerate + + + + assign ram_empty_comb = going_empty | (~leaving_empty & empty_i); + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + empty_i <= 1'b1; + else if (srst_rrst_busy) + empty_i <= #`TCQ 1'b1; + else + empty_i <= #`TCQ ram_empty_comb; + end + always @(posedge CLK or posedge rst_i) begin + if (rst_i && C_EN_SAFETY_CKT == 0) begin + EMPTY_FB <= 1'b1; + end else begin + if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT)) + EMPTY_FB <= #`TCQ 1'b1; + else + EMPTY_FB <= #`TCQ ram_empty_comb; + end + end // always + + //----------------------------------------------------------------------------- + // Generate Read and write data counts for asymmetic common clock + //----------------------------------------------------------------------------- + + reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; + wire [C_GRTR_PNTR_WIDTH :0] ratio; + wire decr_by_one; + wire incr_by_ratio; + wire incr_by_one; + wire decr_by_ratio; + + localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; + + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr + assign ratio = C_DEPTH_RATIO_RD; + assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow; + assign incr_by_ratio = write_allow; + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + count_dc <= #`TCQ 0; + else if (srst_wrst_busy) + count_dc <= #`TCQ 0; + else begin + if (decr_by_one) begin + if (!incr_by_ratio) + count_dc <= #`TCQ count_dc - 1; + else + count_dc <= #`TCQ count_dc - 1 + ratio ; + end + else begin + if (!incr_by_ratio) + count_dc <= #`TCQ count_dc ; + else + count_dc <= #`TCQ count_dc + ratio ; + end + end + end + + assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc; + assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + + end endgenerate + + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd + assign ratio = C_DEPTH_RATIO_WR; + assign incr_by_one = write_allow; + assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow; + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + count_dc <= #`TCQ 0; + else if (srst_wrst_busy) + count_dc <= #`TCQ 0; + else begin + if (incr_by_one) begin + if (!decr_by_ratio) + count_dc <= #`TCQ count_dc + 1; + else + count_dc <= #`TCQ count_dc + 1 - ratio ; + end + else begin + if (!decr_by_ratio) + count_dc <= #`TCQ count_dc ; + else + count_dc <= #`TCQ count_dc - ratio ; + end + end + end + + assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc; + assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + + end endgenerate + + + + + + + //----------------------------------------------------------------------------- + // Generate WR_ACK flag + //----------------------------------------------------------------------------- + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + ideal_wr_ack <= 1'b0; + else if (srst_wrst_busy) + ideal_wr_ack <= #`TCQ 1'b0; + else if (WR_EN & ~full_i) + ideal_wr_ack <= #`TCQ 1'b1; + else + ideal_wr_ack <= #`TCQ 1'b0; + end + + //----------------------------------------------------------------------------- + // Generate VALID flag + //----------------------------------------------------------------------------- + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + ideal_valid <= 1'b0; + else if (srst_rrst_busy) + ideal_valid <= #`TCQ 1'b0; + else if (RD_EN & ~empty_i) + ideal_valid <= #`TCQ 1'b1; + else + ideal_valid <= #`TCQ 1'b0; + end + + + //----------------------------------------------------------------------------- + // Generate ALMOST_FULL flag + //----------------------------------------------------------------------------- + //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss + + wire fcomp2; + wire going_afull; + wire leaving_afull; + wire ram_afull_comb; + + + assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2)); + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp + assign going_afull = (fcomp2 & write_allow & ~read_allow); + assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN; + end endgenerate + + // Write data width is bigger than read data width + // Write depth is smaller than read depth + // One write could be equal to 2 or 4 or 8 reads + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym + assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); + assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp + assign going_afull = (fcomp2 & write_allow & ~read_allow); + assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN; + end endgenerate + + assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i); + + + generate if (C_HAS_RST == 1) begin : grst_afull + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF & C_HAS_RST) + almost_full_i <= C_FULL_FLAGS_RST_VAL; + else + almost_full_i <= #`TCQ ram_afull_comb; + end + end endgenerate + + generate if (C_HAS_SRST == 1) begin : gsrst_afull + always @(posedge CLK) begin + if (srst_wrst_busy) + almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else + almost_full_i <= #`TCQ ram_afull_comb; + end + end endgenerate + + generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull + always @(posedge CLK) begin + almost_full_i <= #`TCQ ram_afull_comb; + end + end endgenerate + + //----------------------------------------------------------------------------- + // Generate ALMOST_EMPTY flag + //----------------------------------------------------------------------------- + //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss + + wire ecomp2; + wire going_aempty; + wire leaving_aempty; + wire ram_aempty_comb; + + assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2)); + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp + assign going_aempty = (ecomp2 & ~write_allow & read_allow); + assign leaving_aempty = (ecomp1 & write_allow & ~read_allow); + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp + assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); + assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); + end endgenerate + + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp + assign going_aempty = (ecomp2 & ~write_allow & read_allow); + assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow); + end endgenerate + + + assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i); + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + almost_empty_i <= 1'b1; + else if (srst_rrst_busy) + almost_empty_i <= #`TCQ 1'b1; + else + almost_empty_i <= #`TCQ ram_aempty_comb; + end + // end endgenerate // gae_ss + + //----------------------------------------------------------------------------- + // Generate PROG_FULL + //----------------------------------------------------------------------------- + + localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT + C_PROG_FULL_THRESH_ASSERT_VAL; // STD + localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT + C_PROG_FULL_THRESH_NEGATE_VAL; // STD + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for single programmable threshold constant + //----------------------------------------------------------------------------- + wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL; + generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~RST_FULL_GEN ) begin + if (diff_pntr>= C_PF_ASSERT_VAL ) + prog_full_i <= #`TCQ 1'b1; + else if ((diff_pntr) < C_PF_ASSERT_VAL ) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ 1'b0; + end + else + prog_full_i <= #`TCQ prog_full_i; + end + end + end + end endgenerate // single_pf_const + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for multiple programmable threshold constants + //----------------------------------------------------------------------------- + generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const + always @(posedge CLK or posedge RST_FULL_FF) begin + //if (RST_FULL_FF) + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~RST_FULL_GEN ) begin + if (diff_pntr >= C_PF_ASSERT_VAL ) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr < C_PF_NEGATE_VAL) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else + prog_full_i <= #`TCQ prog_full_i; + end + end + end + end endgenerate //multiple_pf_const + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for single programmable threshold input port + //----------------------------------------------------------------------------- + wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? + PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT + PROG_FULL_THRESH; // STD + generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input + + always @(posedge CLK or posedge RST_FULL_FF) begin//0 + //if (RST_FULL_FF) + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin //1 + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin//2 + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~almost_full_i) begin//3 + if (diff_pntr > pf3_assert_val) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr == pf3_assert_val) begin//4 + if (read_only_q) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ 1'b1; + end else//4 + prog_full_i <= #`TCQ 1'b0; + end else//3 + prog_full_i <= #`TCQ prog_full_i; + end //2 + else begin//5 + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~full_i ) begin//6 + if (diff_pntr >= pf3_assert_val ) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr < pf3_assert_val) begin//7 + prog_full_i <= #`TCQ 1'b0; + end//7 + end//6 + else + prog_full_i <= #`TCQ prog_full_i; + end//5 + end//1 + end//0 + end endgenerate //single_pf_input + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for multiple programmable threshold input ports + //----------------------------------------------------------------------------- + wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT + PROG_FULL_THRESH_ASSERT; // STD + wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT + PROG_FULL_THRESH_NEGATE; // STD + + generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~almost_full_i) begin + if (diff_pntr >= pf_assert_val) + prog_full_i <= #`TCQ 1'b1; + else if ((diff_pntr == pf_negate_val && read_only_q) || + diff_pntr < pf_negate_val) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end else + prog_full_i <= #`TCQ prog_full_i; + end + else begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~full_i ) begin + if (diff_pntr >= pf_assert_val ) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr < pf_negate_val) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else + prog_full_i <= #`TCQ prog_full_i; + end + + end + end + end endgenerate //multiple_pf_inputs + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY + //----------------------------------------------------------------------------- + localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT + C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD + localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT + C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for single programmable threshold constant + //----------------------------------------------------------------------------- + generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (~rst_i ) begin + if (diff_pntr_pe <= C_PE_ASSERT_VAL) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > C_PE_ASSERT_VAL) + prog_empty_i <= #`TCQ 1'b0; + end + else + prog_empty_i <= #`TCQ prog_empty_i; + end + end + end + end endgenerate // single_pe_const + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for multiple programmable threshold constants + //----------------------------------------------------------------------------- + generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (~rst_i ) begin + if (diff_pntr_pe <= C_PE_ASSERT_VAL ) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > C_PE_NEGATE_VAL) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + else + prog_empty_i <= #`TCQ prog_empty_i; + end + + end + + end + end endgenerate //multiple_pe_const + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for single programmable threshold input port + //----------------------------------------------------------------------------- + wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_EMPTY_THRESH -2) : // FWFT + PROG_EMPTY_THRESH; // STD + generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (~almost_full_i) begin + if (diff_pntr_pe < pe3_assert_val) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe == pe3_assert_val) begin + if (write_only_q) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ 1'b1; + end else + prog_empty_i <= #`TCQ 1'b0; + end else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (diff_pntr_pe <= pe3_assert_val ) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > pe3_assert_val) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + end + + end + end endgenerate // single_pe_input + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for multiple programmable threshold input ports + //----------------------------------------------------------------------------- + wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT + PROG_EMPTY_THRESH_ASSERT; // STD + wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT + PROG_EMPTY_THRESH_NEGATE; // STD + generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (~almost_full_i) begin + if (diff_pntr_pe <= pe4_assert_val) + prog_empty_i <= #`TCQ 1'b1; + else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || + (diff_pntr_pe > pe4_negate_val)) begin + prog_empty_i <= #`TCQ 1'b0; + end else + prog_empty_i <= #`TCQ prog_empty_i; + end else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (diff_pntr_pe <= pe4_assert_val ) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > pe4_negate_val) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + end + end + end endgenerate // multiple_pe_inputs + +endmodule // fifo_generator_v13_2_4_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v13_2_4_bhv_ver_preload0 + #( + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_HAS_RST = 0, + parameter C_ENABLE_RST_SYNC = 0, + parameter C_HAS_SRST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USERVALID_LOW = 0, + parameter C_USERUNDERFLOW_LOW = 0, + parameter C_MEMORY_TYPE = 0, + parameter C_FIFO_TYPE = 0 + ) + ( + //Inputs + input SAFETY_CKT_RD_RST, + input RD_CLK, + input RD_RST, + input SRST, + input WR_RST_BUSY, + input RD_RST_BUSY, + input RD_EN, + input FIFOEMPTY, + input [C_DOUT_WIDTH-1:0] FIFODATA, + input FIFOSBITERR, + input FIFODBITERR, + + //Outputs + output reg [C_DOUT_WIDTH-1:0] USERDATA, + output USERVALID, + output USERUNDERFLOW, + output USEREMPTY, + output USERALMOSTEMPTY, + output RAMVALID, + output FIFORDEN, + output reg USERSBITERR, + output reg USERDBITERR, + output reg STAGE2_REG_EN, + output fab_read_data_valid_i_o, + output read_data_valid_i_o, + output ram_valid_i_o, + output [1:0] VALID_STAGES + ); + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg fab_valid; + reg read_data_valid_i; + reg fab_read_data_valid_i; + reg fab_read_data_valid_i_1; + reg ram_valid_i_d; + reg read_data_valid_i_d; + reg fab_read_data_valid_i_d; + wire ram_regout_en; + reg ram_regout_en_d1; + reg ram_regout_en_d2; + wire fab_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_sckt = 1'b1; + reg sckt_rrst_q = 1'b0; + reg sckt_rrst_done = 1'b0; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + reg [C_DOUT_WIDTH-1:0] userdata_both; + wire uservalid_both; + wire uservalid_one; + reg user_sbiterr_both = 1'b0; + reg user_dbiterr_both = 1'b0; + +assign ram_valid_i_o = ram_valid_i; +assign read_data_valid_i_o = read_data_valid_i; +assign fab_read_data_valid_i_o = fab_read_data_valid_i; + + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + fab_valid = 1'b0; + read_data_valid_i = 1'b0; + fab_read_data_valid_i = 1'b0; + fab_read_data_valid_i_1 = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + userdata_both = hexstr_conv(C_DOUT_RST_VAL); + USERSBITERR = 1'b0; + USERDBITERR = 1'b0; + user_sbiterr_both = 1'b0; + user_dbiterr_both = 1'b0; + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; + assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0; + + reg sckt_rd_rst_fwft = 1'b0; + reg fwft_rst_done_i = 1'b0; + wire fwft_rst_done; + assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1; + always @ (posedge RD_CLK) begin + sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST; + end + + always @ (posedge rd_rst_i or posedge RD_CLK) begin + if (rd_rst_i) + fwft_rst_done_i <= 1'b0; + else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST) + fwft_rst_done_i <= #`TCQ 1'b1; + end + + localparam INVALID = 0; + localparam STAGE1_VALID = 2; + localparam STAGE2_VALID = 1; + localparam BOTH_STAGES_VALID = 3; + + reg [1:0] curr_fwft_state = INVALID; + reg [1:0] next_fwft_state = INVALID; + + +generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin + always @* begin + case (curr_fwft_state) + INVALID: begin + if (~FIFOEMPTY) + next_fwft_state <= STAGE1_VALID; + else + next_fwft_state <= INVALID; + end + STAGE1_VALID: begin + if (FIFOEMPTY) + next_fwft_state <= STAGE2_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + STAGE2_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= INVALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE1_VALID; + else if (~FIFOEMPTY && ~RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= STAGE2_VALID; + end + BOTH_STAGES_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE2_VALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + default: next_fwft_state <= INVALID; + endcase + end + + always @ (posedge rd_rst_i or posedge RD_CLK) begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) + curr_fwft_state <= INVALID; + else if (srst_i) + curr_fwft_state <= #`TCQ INVALID; + else + curr_fwft_state <= #`TCQ next_fwft_state; + end + + always @* begin + case (curr_fwft_state) + INVALID: STAGE2_REG_EN <= 1'b0; + STAGE1_VALID: STAGE2_REG_EN <= 1'b1; + STAGE2_VALID: STAGE2_REG_EN <= 1'b0; + BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; + default: STAGE2_REG_EN <= 1'b0; + endcase + end + + + assign VALID_STAGES = curr_fwft_state; + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); + + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + end +endgenerate // gnll_fifo + + reg curr_state = 0; + reg next_state = 0; + reg leaving_empty_fwft = 0; + reg going_empty_fwft = 0; + reg empty_i_q = 0; + reg ram_rd_en_fwft = 0; + generate if (C_FIFO_TYPE == 2) begin : gll_fifo + always @* begin // FSM fo FWFT + case (curr_state) + 1'b0: begin + if (~FIFOEMPTY) + next_state <= 1'b1; + else + next_state <= 1'b0; + end + 1'b1: begin + if (FIFOEMPTY && RD_EN) + next_state <= 1'b0; + else + next_state <= 1'b1; + end + default: next_state <= 1'b0; + endcase + end + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + empty_i <= 1'b1; + empty_i_q <= 1'b1; + ram_valid_i <= 1'b0; + end else if (srst_i) begin + empty_i <= #`TCQ 1'b1; + empty_i_q <= #`TCQ 1'b1; + ram_valid_i <= #`TCQ 1'b0; + end else begin + empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i); + empty_i_q <= #`TCQ FIFOEMPTY; + ram_valid_i <= #`TCQ next_state; + end + end //always + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin + curr_state <= 1'b0; + end else if (srst_i) begin + curr_state <= #`TCQ 1'b0; + end else begin + curr_state <= #`TCQ next_state; + end + end //always + + wire fe_of_empty; + assign fe_of_empty = empty_i_q & ~FIFOEMPTY; + + always @* begin // Finding leaving empty + case (curr_state) + 1'b0: leaving_empty_fwft <= fe_of_empty; + 1'b1: leaving_empty_fwft <= 1'b1; + default: leaving_empty_fwft <= 1'b0; + endcase + end + + always @* begin // Finding going empty + case (curr_state) + 1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN; + default: going_empty_fwft <= 1'b0; + endcase + end + + always @* begin // Generating FWFT rd_en + case (curr_state) + 1'b0: ram_rd_en_fwft <= ~FIFOEMPTY; + 1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN; + default: ram_rd_en_fwft <= 1'b0; + endcase + end + + assign ram_regout_en = ram_rd_en_fwft; + //assign ram_regout_en_d1 = ram_rd_en_fwft; + //assign ram_regout_en_d2 = ram_rd_en_fwft; + assign ram_rd_en = ram_rd_en_fwft; + end endgenerate // gll_fifo + + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= #`TCQ 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= #`TCQ 1'b0; + else + ram_valid_i <= #`TCQ ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + end endgenerate // gnll_fifo_ram_valid + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + + generate if(C_USE_EMBEDDED_REG < 3) begin + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always +end +endgenerate + + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + end + end + end //always + end endgenerate // gnll_fifo_empty + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + generate if ( C_USE_EMBEDDED_REG < 3) begin + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ FIFOEMPTY; + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always +end +endgenerate + + + + // BRAM resets synchronously + generate + if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin + always @ ( posedge rd_rst_i) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1) begin + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else if (fwft_rst_done) begin + if (ram_regout_en) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + end //if + endgenerate +//safety ckt with one register +generate + if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge RD_CLK) + begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin + @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end + end //always + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) + //@(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end + else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1) begin + // @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else if (fwft_rst_done) begin + if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + end //if +endgenerate + + +generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin + + + always @* begin + case (curr_fwft_state) + INVALID: begin + if (~FIFOEMPTY) + next_fwft_state <= STAGE1_VALID; + else + next_fwft_state <= INVALID; + end + STAGE1_VALID: begin + if (FIFOEMPTY) + next_fwft_state <= STAGE2_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + STAGE2_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= INVALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE1_VALID; + else if (~FIFOEMPTY && ~RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= STAGE2_VALID; + end + BOTH_STAGES_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE2_VALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + default: next_fwft_state <= INVALID; + endcase + end + + always @ (posedge rd_rst_i or posedge RD_CLK) begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) + curr_fwft_state <= INVALID; + else if (srst_i) + curr_fwft_state <= #`TCQ INVALID; + else + curr_fwft_state <= #`TCQ next_fwft_state; + end + + always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay + if (rd_rst_i == 1) begin + ram_regout_en_d1 <= #`TCQ 1'b0; + end + else begin + if (srst_i == 1'b1) + ram_regout_en_d1 <= #`TCQ 1'b0; + else + ram_regout_en_d1 <= #`TCQ ram_regout_en; + end + end //always + // assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i)); + assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0; + + always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1 + if (rd_rst_i == 1) begin + ram_regout_en_d2 <= #`TCQ 1'b0; + end + else begin + if (srst_i == 1'b1) + ram_regout_en_d2 <= #`TCQ 1'b0; + else + ram_regout_en_d2 <= #`TCQ ram_regout_en_d1; + end + end //always + + + + always @* begin + case (curr_fwft_state) + INVALID: STAGE2_REG_EN <= 1'b0; + STAGE1_VALID: STAGE2_REG_EN <= 1'b1; + STAGE2_VALID: STAGE2_REG_EN <= 1'b0; + BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; + default: STAGE2_REG_EN <= 1'b0; + endcase + end + + always @ (posedge RD_CLK) begin + ram_valid_i_d <= #`TCQ ram_valid_i; + read_data_valid_i_d <= #`TCQ read_data_valid_i; + fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i; + + end + assign VALID_STAGES = curr_fwft_state; + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1; + end + endgenerate // gnll_fifo + + + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid + + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + fab_valid <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + fab_valid <= #`TCQ 1'b0; + end else begin + if (ram_regout_en == 1'b1) begin + fab_valid <= #`TCQ 1'b1; + end else begin + if (fab_regout_en == 1'b1) + fab_valid <= #`TCQ 1'b0; + else + fab_valid <= #`TCQ fab_valid; + end + end //srst_i + end //rd_rst_i + end //always + end endgenerate // gnll_fifo_fab_valid + + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + generate if(C_USE_EMBEDDED_REG == 3) begin + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else begin + if (ram_regout_en == 1'b1) begin + read_data_valid_i <= #`TCQ 1'b1; + end else begin + if (fab_regout_en == 1'b1) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ read_data_valid_i; + end + end + end //always +end +endgenerate + +//generate if(C_USE_EMBEDDED_REG == 3) begin +// always @ (posedge RD_CLK or posedge rd_rst_i) begin +// if (rd_rst_i) +// read_data_valid_i <= #`TCQ 1'b0; +// else if (srst_i) +// read_data_valid_i <= #`TCQ 1'b0; +// +// if (ram_regout_en == 1'b1) begin +// fab_read_data_valid_i <= #`TCQ 1'b0; +// end else begin +// if (fab_regout_en == 1'b1) +// fab_read_data_valid_i <= #`TCQ 1'b1; +// else +// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i; +// end +// end //always +//end +//endgenerate + + generate if(C_USE_EMBEDDED_REG == 3 ) begin + always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid + if (rd_rst_i) + fab_read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + fab_read_data_valid_i <= #`TCQ 1'b0; + else + fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN); + end //always +end +endgenerate + +always @ (posedge RD_CLK ) begin : proc_del1 + begin + fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i; + end + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN); + end + end + end //always + end endgenerate // gnll_fifo_empty_both + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + reg FIFOEMPTY_1; + generate if (C_USE_EMBEDDED_REG == 3 ) begin + always @(posedge RD_CLK) begin + FIFOEMPTY_1 <= #`TCQ FIFOEMPTY; + end + end +endgenerate + generate if (C_USE_EMBEDDED_REG == 3 ) begin + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ (~ram_valid_i); + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always +end +endgenerate + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + empty_sckt <= #`TCQ 1'b1; + sckt_rrst_q <= #`TCQ 1'b0; + sckt_rrst_done <= #`TCQ 1'b0; + end else begin + sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST; + if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin + sckt_rrst_done <= #`TCQ 1'b1; + end else if (sckt_rrst_done) begin + // rising clock edge + empty_sckt <= #`TCQ 1'b0; + end + end + end //always + + +// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i; + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i; + assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0); + assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0); + assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; +//no safety ckt with both reg +generate + if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end else begin + if (fwft_rst_done) begin + if (ram_regout_en) begin + userdata_both <= #`TCQ FIFODATA; + user_dbiterr_both <= #`TCQ FIFODBITERR; + user_sbiterr_both <= #`TCQ FIFOSBITERR; + end + if (fab_regout_en) begin + USERDATA <= #`TCQ userdata_both; + USERDBITERR <= #`TCQ user_dbiterr_both; + USERSBITERR <= #`TCQ user_sbiterr_both; + end + end + end + end + end //always + end //if + endgenerate + +//safety_ckt with both registers + generate + if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge RD_CLK) begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always @ (posedge RD_CLK) begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin + @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end + end //always + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else if (fwft_rst_done) begin + if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin + userdata_both <= #`TCQ FIFODATA; + user_dbiterr_both <= #`TCQ FIFODBITERR; + user_sbiterr_both <= #`TCQ FIFOSBITERR; + end + if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin + USERDATA <= #`TCQ userdata_both; + USERDBITERR <= #`TCQ user_dbiterr_both; + USERSBITERR <= #`TCQ user_sbiterr_both; + end + end + end + end //always + end //if +endgenerate + +endmodule //fifo_generator_v13_2_4_bhv_ver_preload0 + + +//----------------------------------------------------------------------------- +// +// Register Slice +// Register one AXI channel on forward and/or reverse signal path +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// reg_slice +// +//-------------------------------------------------------------------------- + +module fifo_generator_v13_2_4_axic_reg_slice # + ( + parameter C_FAMILY = "virtex7", + parameter C_DATA_WIDTH = 32, + parameter C_REG_CONFIG = 32'h00000000 + ) + ( + // System Signals + input wire ACLK, + input wire ARESET, + + // Slave side + input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, + input wire S_VALID, + output wire S_READY, + + // Master side + output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, + output wire M_VALID, + input wire M_READY + ); + + localparam RST_SYNC_STAGES = 5; + localparam RST_BUSY_LEN = 6; + reg [1:0] arst_sync_wr = 2'b11; + reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0; + wire sync_reset; + wire extnd_reset; + + + always @(posedge ARESET or posedge ACLK) begin + if (ARESET) + arst_sync_wr <= 2'b11; + else + arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0}; + end + + always @(posedge ACLK) begin + sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]}; + end + + assign sync_reset = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; + assign extnd_reset = |sckt_wr_rst_cc | arst_sync_wr[1]; + generate + //////////////////////////////////////////////////////////////////// + // + // Both FWD and REV mode + // + //////////////////////////////////////////////////////////////////// + if (C_REG_CONFIG == 32'h00000000) + begin + reg [1:0] state; + localparam [1:0] + ZERO = 2'b10, + ONE = 2'b11, + TWO = 2'b01; + + reg [C_DATA_WIDTH-1:0] storage_data1 = 0; + reg [C_DATA_WIDTH-1:0] storage_data2 = 0; + reg load_s1; + wire load_s2; + wire load_s1_from_s2; + reg s_ready_i; //local signal of output + wire m_valid_i; //local signal of output + + // assign local signal to its output signal + assign S_READY = s_ready_i; + assign M_VALID = m_valid_i; + + reg areset_d1; // Reset delay register + always @(posedge ACLK) begin + areset_d1 <= extnd_reset; + end + + // Load storage1 with either slave side data or from storage2 + always @(posedge ACLK) + begin + if (load_s1) + if (load_s1_from_s2) + storage_data1 <= storage_data2; + else + storage_data1 <= S_PAYLOAD_DATA; + end + + // Load storage2 with slave side data + always @(posedge ACLK) + begin + if (load_s2) + storage_data2 <= S_PAYLOAD_DATA; + end + + assign M_PAYLOAD_DATA = storage_data1; + + // Always load s2 on a valid transaction even if it's unnecessary + assign load_s2 = S_VALID & s_ready_i; + + // Loading s1 + always @ * + begin + if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction + // Load when ONE if we both have read and write at the same time + ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) || + // Load when TWO and we have a transaction on Master side + ((state == TWO) && (M_READY == 1))) + load_s1 = 1'b1; + else + load_s1 = 1'b0; + end // always @ * + + assign load_s1_from_s2 = (state == TWO); + + // State Machine for handling output signals + always @(posedge ACLK) begin + if (sync_reset || extnd_reset) begin + s_ready_i <= 1'b0; + state <= ZERO; + end else if (areset_d1 && ~extnd_reset) begin + s_ready_i <= 1'b1; + end else begin + case (state) + // No transaction stored locally + ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE + + // One transaction stored locally + ONE: begin + if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO + if (~M_READY & S_VALID) begin + state <= TWO; // Got another one so move to TWO + s_ready_i <= 1'b0; + end + end + + // TWO transaction stored locally + TWO: if (M_READY) begin + state <= ONE; // Read out one so move to ONE + s_ready_i <= 1'b1; + end + endcase // case (state) + end + end // always @ (posedge ACLK) + + assign m_valid_i = state[0]; + + end // if (C_REG_CONFIG == 1) + //////////////////////////////////////////////////////////////////// + // + // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining + // Operates same as 1-deep FIFO + // + //////////////////////////////////////////////////////////////////// + else if (C_REG_CONFIG == 32'h00000001) + begin + reg [C_DATA_WIDTH-1:0] storage_data1 = 0; + reg s_ready_i; //local signal of output + reg m_valid_i; //local signal of output + + // assign local signal to its output signal + assign S_READY = s_ready_i; + assign M_VALID = m_valid_i; + + reg areset_d1; // Reset delay register + always @(posedge ACLK) begin + areset_d1 <= extnd_reset; + end + + // Load storage1 with slave side data + always @(posedge ACLK) + begin + if (sync_reset || extnd_reset) begin + s_ready_i <= 1'b0; + m_valid_i <= 1'b0; + end else if (areset_d1 && ~extnd_reset) begin + s_ready_i <= 1'b1; + end else if (m_valid_i & M_READY) begin + s_ready_i <= 1'b1; + m_valid_i <= 1'b0; + end else if (S_VALID & s_ready_i) begin + s_ready_i <= 1'b0; + m_valid_i <= 1'b1; + end + if (~m_valid_i) begin + storage_data1 <= S_PAYLOAD_DATA; + end + end + assign M_PAYLOAD_DATA = storage_data1; + end // if (C_REG_CONFIG == 7) + + else begin : default_case + // Passthrough + assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; + assign M_VALID = S_VALID; + assign S_READY = M_READY; + end + + endgenerate +endmodule // reg_slice diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/mem_init_files/fir_prbs10_invert_rep2.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/mem_init_files/fir_prbs10_invert_rep2.mif new file mode 100644 index 00000000..f8d26256 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/mem_init_files/fir_prbs10_invert_rep2.mif @@ -0,0 +1,2048 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 0 0 0 4 0 +00000001 0 0 0 0 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b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/mem_init_files/rom_freq_word.mif @@ -1,81 +1,81 @@ -0000010000110100 -0000010001000000 -0000010001001100 -0000010001011000 -0000010001100100 -0000010001110000 -0000010001111100 -0000010010001000 -0000010010010100 -0000010010100000 -0000010010101100 -0000010010111000 -0000010011000100 -0000010011010000 -0000010011011100 -0000010011101000 -0000010011110100 -0000010100000000 -0000010100001100 -0000010100011000 -0000010100100100 -0000010100110000 -0000010100111100 -0000010101001000 -0000010101010100 -0000010101100000 -0000010101101100 -0000010101111000 -0000010110000100 -0000010110010000 -0000010110011100 -0000010110101000 -0000010110110100 -0000010111000000 -0000010111001100 -0000010111011000 -0000010111100100 -0000010111110000 -0000010111111100 -0000011000001000 -0000011000010100 -0000011000100000 -0000011000101100 -0000011000111000 -0000011001000100 -0000011001010000 -0000011001011100 -0000011001101000 -0000011001110100 -0000011010000000 -0000011010001100 -0000011010011000 -0000011010100100 -0000011010110000 -0000011010111100 -0000011011001000 -0000011011010100 -0000011011100000 -0000011011101100 -0000011011111000 -0000011100000100 -0000011100010000 -0000011100011100 -0000011100101000 -0000011100110100 -0000011101000000 -0000011101001100 -0000011101011000 -0000011101100100 -0000011101110000 +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 0000011101111100 -0000011110001000 -0000011110010100 -0000011110100000 -0000011110101100 -0000011110111000 -0000011111000100 -0000011111010000 -0000011111011100 -0000011111101000 -0000011111110100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/compile.do deleted file mode 100644 index ea5e2851..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/compile.do +++ /dev/null @@ -1,67 +0,0 @@ -vlib work -vlib activehdl - -vlib activehdl/xil_defaultlib -vlib activehdl/xpm -vlib activehdl/xbip_utils_v3_0_10 -vlib activehdl/axi_utils_v2_0_6 -vlib activehdl/xbip_pipe_v3_0_6 -vlib activehdl/xbip_bram18k_v3_0_6 -vlib activehdl/mult_gen_v12_0_15 -vlib activehdl/xbip_dsp48_wrapper_v3_0_4 -vlib activehdl/xbip_dsp48_addsub_v3_0_6 -vlib activehdl/xbip_dsp48_multadd_v3_0_6 -vlib activehdl/dds_compiler_v6_0_18 - -vmap xil_defaultlib activehdl/xil_defaultlib -vmap xpm activehdl/xpm -vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10 -vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6 -vmap xbip_pipe_v3_0_6 activehdl/xbip_pipe_v3_0_6 -vmap xbip_bram18k_v3_0_6 activehdl/xbip_bram18k_v3_0_6 -vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15 -vmap xbip_dsp48_wrapper_v3_0_4 activehdl/xbip_dsp48_wrapper_v3_0_4 -vmap xbip_dsp48_addsub_v3_0_6 activehdl/xbip_dsp48_addsub_v3_0_6 -vmap xbip_dsp48_multadd_v3_0_6 activehdl/xbip_dsp48_multadd_v3_0_6 -vmap dds_compiler_v6_0_18 activehdl/dds_compiler_v6_0_18 - -vlog -work xil_defaultlib -sv2k12 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vcom -work xbip_utils_v3_0_10 -93 \ -"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - -vcom -work axi_utils_v2_0_6 -93 \ -"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - -vcom -work xbip_pipe_v3_0_6 -93 \ -"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ - -vcom -work xbip_bram18k_v3_0_6 -93 \ -"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ - -vcom -work mult_gen_v12_0_15 -93 \ -"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ - -vcom -work xbip_dsp48_wrapper_v3_0_4 -93 \ -"../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \ - -vcom -work xbip_dsp48_addsub_v3_0_6 -93 \ -"../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \ - -vcom -work xbip_dsp48_multadd_v3_0_6 -93 \ -"../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \ - -vcom -work dds_compiler_v6_0_18 -93 \ -"../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \ - -vcom -work xil_defaultlib -93 \ -"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/file_info.txt deleted file mode 100644 index a8155a29..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/file_info.txt +++ /dev/null @@ -1,14 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, -xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, -xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, -mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, -xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, -xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd, -xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd, -dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd, -dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/simulate.do deleted file mode 100644 index bd592544..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+dds_32b_8b_comp -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dds_32b_8b_comp xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {dds_32b_8b_comp.udo} - -run -all - -endsim - -quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/file_info.txt deleted file mode 100644 index a8155a29..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/file_info.txt +++ /dev/null @@ -1,14 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, -xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, -xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, -mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, -xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, -xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd, -xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd, -dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd, -dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/run.f deleted file mode 100644 index be38ce1a..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/run.f +++ /dev/null @@ -1,41 +0,0 @@ --makelib ies_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib ies_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib ies_lib/xbip_utils_v3_0_10 \ - "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/axi_utils_v2_0_6 \ - "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/xbip_pipe_v3_0_6 \ - "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/xbip_bram18k_v3_0_6 \ - "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/mult_gen_v12_0_15 \ - "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/xbip_dsp48_wrapper_v3_0_4 \ - "../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/xbip_dsp48_addsub_v3_0_6 \ - "../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/xbip_dsp48_multadd_v3_0_6 \ - "../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/dds_compiler_v6_0_18 \ - "../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - "../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/file_info.txt deleted file mode 100644 index a3c88400..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/simulate.do deleted file mode 100644 index f9660524..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.dds_32b_8b_comp xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure -view signals - -do {dds_32b_8b_comp.udo} - -run -all - -quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/compile.do deleted file mode 100644 index a8cf2a38..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/compile.do +++ /dev/null @@ -1,67 +0,0 @@ -vlib questa_lib/work -vlib questa_lib/msim - -vlib questa_lib/msim/xil_defaultlib -vlib questa_lib/msim/xpm -vlib questa_lib/msim/xbip_utils_v3_0_10 -vlib questa_lib/msim/axi_utils_v2_0_6 -vlib questa_lib/msim/xbip_pipe_v3_0_6 -vlib questa_lib/msim/xbip_bram18k_v3_0_6 -vlib questa_lib/msim/mult_gen_v12_0_15 -vlib questa_lib/msim/xbip_dsp48_wrapper_v3_0_4 -vlib questa_lib/msim/xbip_dsp48_addsub_v3_0_6 -vlib questa_lib/msim/xbip_dsp48_multadd_v3_0_6 -vlib questa_lib/msim/dds_compiler_v6_0_18 - -vmap xil_defaultlib questa_lib/msim/xil_defaultlib -vmap xpm questa_lib/msim/xpm -vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10 -vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6 -vmap xbip_pipe_v3_0_6 questa_lib/msim/xbip_pipe_v3_0_6 -vmap xbip_bram18k_v3_0_6 questa_lib/msim/xbip_bram18k_v3_0_6 -vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15 -vmap xbip_dsp48_wrapper_v3_0_4 questa_lib/msim/xbip_dsp48_wrapper_v3_0_4 -vmap xbip_dsp48_addsub_v3_0_6 questa_lib/msim/xbip_dsp48_addsub_v3_0_6 -vmap xbip_dsp48_multadd_v3_0_6 questa_lib/msim/xbip_dsp48_multadd_v3_0_6 -vmap dds_compiler_v6_0_18 questa_lib/msim/dds_compiler_v6_0_18 - -vlog -work xil_defaultlib -64 -sv \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vcom -work xbip_utils_v3_0_10 -64 -93 \ -"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - -vcom -work axi_utils_v2_0_6 -64 -93 \ -"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - -vcom -work xbip_pipe_v3_0_6 -64 -93 \ -"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ - -vcom -work xbip_bram18k_v3_0_6 -64 -93 \ -"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ - -vcom -work mult_gen_v12_0_15 -64 -93 \ -"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ - -vcom -work xbip_dsp48_wrapper_v3_0_4 -64 -93 \ -"../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \ - -vcom -work xbip_dsp48_addsub_v3_0_6 -64 -93 \ -"../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \ - -vcom -work xbip_dsp48_multadd_v3_0_6 -64 -93 \ -"../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \ - -vcom -work dds_compiler_v6_0_18 -64 -93 \ -"../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \ - -vcom -work xil_defaultlib -64 -93 \ -"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/elaborate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/elaborate.do deleted file mode 100644 index 52c7371f..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/elaborate.do +++ /dev/null @@ -1 +0,0 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.dds_32b_8b_comp xil_defaultlib.glbl -o dds_32b_8b_comp_opt diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/file_info.txt deleted file mode 100644 index a8155a29..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/file_info.txt +++ /dev/null @@ -1,14 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, -xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, -xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, -mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, -xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, -xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd, -xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd, -dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd, -dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/compile.do deleted file mode 100644 index 321b71cd..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/compile.do +++ /dev/null @@ -1,67 +0,0 @@ -vlib work -vlib riviera - -vlib riviera/xil_defaultlib -vlib riviera/xpm -vlib riviera/xbip_utils_v3_0_10 -vlib riviera/axi_utils_v2_0_6 -vlib riviera/xbip_pipe_v3_0_6 -vlib riviera/xbip_bram18k_v3_0_6 -vlib riviera/mult_gen_v12_0_15 -vlib riviera/xbip_dsp48_wrapper_v3_0_4 -vlib riviera/xbip_dsp48_addsub_v3_0_6 -vlib riviera/xbip_dsp48_multadd_v3_0_6 -vlib riviera/dds_compiler_v6_0_18 - -vmap xil_defaultlib riviera/xil_defaultlib -vmap xpm riviera/xpm -vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10 -vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6 -vmap xbip_pipe_v3_0_6 riviera/xbip_pipe_v3_0_6 -vmap xbip_bram18k_v3_0_6 riviera/xbip_bram18k_v3_0_6 -vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15 -vmap xbip_dsp48_wrapper_v3_0_4 riviera/xbip_dsp48_wrapper_v3_0_4 -vmap xbip_dsp48_addsub_v3_0_6 riviera/xbip_dsp48_addsub_v3_0_6 -vmap xbip_dsp48_multadd_v3_0_6 riviera/xbip_dsp48_multadd_v3_0_6 -vmap dds_compiler_v6_0_18 riviera/dds_compiler_v6_0_18 - -vlog -work xil_defaultlib -sv2k12 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vcom -work xbip_utils_v3_0_10 -93 \ -"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - -vcom -work axi_utils_v2_0_6 -93 \ -"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - -vcom -work xbip_pipe_v3_0_6 -93 \ -"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ - -vcom -work xbip_bram18k_v3_0_6 -93 \ -"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ - -vcom -work mult_gen_v12_0_15 -93 \ -"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ - -vcom -work xbip_dsp48_wrapper_v3_0_4 -93 \ -"../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \ - -vcom -work xbip_dsp48_addsub_v3_0_6 -93 \ -"../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \ - -vcom -work xbip_dsp48_multadd_v3_0_6 -93 \ -"../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \ - -vcom -work dds_compiler_v6_0_18 -93 \ -"../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \ - -vcom -work xil_defaultlib -93 \ -"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/file_info.txt deleted file mode 100644 index a8155a29..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/file_info.txt +++ /dev/null @@ -1,14 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, -xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, -xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, -mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, -xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, -xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd, -xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd, -dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd, -dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/simulate.do deleted file mode 100644 index bd592544..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+dds_32b_8b_comp -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dds_32b_8b_comp xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {dds_32b_8b_comp.udo} - -run -all - -endsim - -quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/README.txt deleted file mode 100644 index 8d80168b..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Mon May 08 00:28:50 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./dds_32b_8b_comp.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './dds_32b_8b_comp.sh' script. - -./dds_32b_8b_comp.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./dds_32b_8b_comp.sh -noclean_files - -For more information on the script, please type './dds_32b_8b_comp.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/file_info.txt deleted file mode 100644 index a3c88400..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/file_info.txt deleted file mode 100644 index a8155a29..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/file_info.txt +++ /dev/null @@ -1,14 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd, -xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd, -xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd, -mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd, -xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, -xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd, -xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd, -dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd, -dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/run.f deleted file mode 100644 index 67c033df..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/run.f +++ /dev/null @@ -1,41 +0,0 @@ --makelib xcelium_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib xcelium_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib xcelium_lib/xbip_utils_v3_0_10 \ - "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/axi_utils_v2_0_6 \ - "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/xbip_pipe_v3_0_6 \ - "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/xbip_bram18k_v3_0_6 \ - "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/mult_gen_v12_0_15 \ - "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/xbip_dsp48_wrapper_v3_0_4 \ - "../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/xbip_dsp48_addsub_v3_0_6 \ - "../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/xbip_dsp48_multadd_v3_0_6 \ - "../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/dds_compiler_v6_0_18 \ - "../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - "../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/README.txt deleted file mode 100644 index 8d80168b..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Mon May 08 00:28:50 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./dds_32b_8b_comp.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './dds_32b_8b_comp.sh' script. - -./dds_32b_8b_comp.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./dds_32b_8b_comp.sh -noclean_files - -For more information on the script, please type './dds_32b_8b_comp.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/file_info.txt deleted file mode 100644 index a3c88400..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/vhdl.prj b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/vhdl.prj deleted file mode 100644 index f4a04b58..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/vhdl.prj +++ /dev/null @@ -1,4 +0,0 @@ -vhdl xil_defaultlib \ -"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \ - -nosort diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/README.txt similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/README.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/README.txt diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/README.txt similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/README.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/README.txt index 8d80168b..32dddaa4 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 00:28:50 CST 2023 +# Generated by export_simulation on Fri May 12 16:07:36 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./dds_32b_8b_comp.sh +./fifo_rx_data.sh This command will launch the 'compile', 'elaborate' and 'simulate' functions implemented in the script file for the 3-step flow. These functions are called @@ -26,16 +26,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './dds_32b_8b_comp.sh' script. +'-reset_run' switch to the './fifo_rx_data.sh' script. -./dds_32b_8b_comp.sh -reset_run +./fifo_rx_data.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./dds_32b_8b_comp.sh -noclean_files +./fifo_rx_data.sh -noclean_files -For more information on the script, please type './dds_32b_8b_comp.sh -help'. +For more information on the script, please type './fifo_rx_data.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/compile.do new file mode 100644 index 00000000..20ae9abf --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/compile.do @@ -0,0 +1,33 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/fifo_generator_v13_2_4 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap fifo_generator_v13_2_4 activehdl/fifo_generator_v13_2_4 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_4 -v2k5 \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_4 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_4 -v2k5 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/fifo_rx_data.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/fifo_rx_data.sh new file mode 100755 index 00000000..e32f1056 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/fifo_rx_data.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_rx_data.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:07:36 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_rx_data.sh [-help] +# usage: fifo_rx_data.sh [-lib_map_path] +# usage: fifo_rx_data.sh [-noclean_files] +# usage: fifo_rx_data.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_rx_data.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_rx_data.sh [-help]\n\ +Usage: fifo_rx_data.sh [-lib_map_path]\n\ +Usage: fifo_rx_data.sh [-reset_run]\n\ +Usage: fifo_rx_data.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/dds_32b_8b_comp.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/fifo_rx_data.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/dds_32b_8b_comp.udo rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/fifo_rx_data.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/file_info.txt new file mode 100644 index 00000000..c409d183 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/simulate.do new file mode 100644 index 00000000..d5f8b47e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+fifo_rx_data -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fifo_rx_data xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {fifo_rx_data.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/wave.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/wave.do diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/README.txt similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/README.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/README.txt index bb369b49..fc756dbd 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 00:28:50 CST 2023 +# Generated by export_simulation on Fri May 12 16:07:36 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./dds_32b_8b_comp.sh +./fifo_rx_data.sh This command will launch the 'execute' function for the single-step flow. This function is called from the main 'run' function in the script file. @@ -25,16 +25,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './dds_32b_8b_comp.sh' script. +'-reset_run' switch to the './fifo_rx_data.sh' script. -./dds_32b_8b_comp.sh -reset_run +./fifo_rx_data.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./dds_32b_8b_comp.sh -noclean_files +./fifo_rx_data.sh -noclean_files -For more information on the script, please type './dds_32b_8b_comp.sh -help'. +For more information on the script, please type './fifo_rx_data.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/fifo_rx_data.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/fifo_rx_data.sh new file mode 100755 index 00000000..64085833 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/fifo_rx_data.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_rx_data.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:07:36 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_rx_data.sh [-help] +# usage: fifo_rx_data.sh [-lib_map_path] +# usage: fifo_rx_data.sh [-noclean_files] +# usage: fifo_rx_data.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_rx_data.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.fifo_rx_data \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_rx_data.sh [-help]\n\ +Usage: fifo_rx_data.sh [-lib_map_path]\n\ +Usage: fifo_rx_data.sh [-reset_run]\n\ +Usage: fifo_rx_data.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/file_info.txt new file mode 100644 index 00000000..c409d183 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/run.f new file mode 100644 index 00000000..c74416b9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/run.f @@ -0,0 +1,23 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/README.txt similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/README.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/README.txt index 8d80168b..32dddaa4 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 00:28:50 CST 2023 +# Generated by export_simulation on Fri May 12 16:07:36 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./dds_32b_8b_comp.sh +./fifo_rx_data.sh This command will launch the 'compile', 'elaborate' and 'simulate' functions implemented in the script file for the 3-step flow. These functions are called @@ -26,16 +26,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './dds_32b_8b_comp.sh' script. +'-reset_run' switch to the './fifo_rx_data.sh' script. -./dds_32b_8b_comp.sh -reset_run +./fifo_rx_data.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./dds_32b_8b_comp.sh -noclean_files +./fifo_rx_data.sh -noclean_files -For more information on the script, please type './dds_32b_8b_comp.sh -help'. +For more information on the script, please type './fifo_rx_data.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/compile.do new file mode 100644 index 00000000..2b4e0ab2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr \ +"../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/fifo_rx_data.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/fifo_rx_data.sh new file mode 100755 index 00000000..114404d5 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/fifo_rx_data.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_rx_data.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:07:36 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_rx_data.sh [-help] +# usage: fifo_rx_data.sh [-lib_map_path] +# usage: fifo_rx_data.sh [-noclean_files] +# usage: fifo_rx_data.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_rx_data.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_rx_data.sh [-help]\n\ +Usage: fifo_rx_data.sh [-lib_map_path]\n\ +Usage: fifo_rx_data.sh [-reset_run]\n\ +Usage: fifo_rx_data.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/dds_32b_8b_comp.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/fifo_rx_data.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/dds_32b_8b_comp.udo rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/fifo_rx_data.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/file_info.txt new file mode 100644 index 00000000..aba78f72 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/file_info.txt @@ -0,0 +1,2 @@ +fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/simulate.do new file mode 100644 index 00000000..4dc77b43 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L fifo_generator_v13_2_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.fifo_rx_data xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {fifo_rx_data.udo} + +run -all + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/wave.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/wave.do diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/README.txt similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/README.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/README.txt index 8d80168b..32dddaa4 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 00:28:50 CST 2023 +# Generated by export_simulation on Fri May 12 16:07:36 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./dds_32b_8b_comp.sh +./fifo_rx_data.sh This command will launch the 'compile', 'elaborate' and 'simulate' functions implemented in the script file for the 3-step flow. These functions are called @@ -26,16 +26,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './dds_32b_8b_comp.sh' script. +'-reset_run' switch to the './fifo_rx_data.sh' script. -./dds_32b_8b_comp.sh -reset_run +./fifo_rx_data.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./dds_32b_8b_comp.sh -noclean_files +./fifo_rx_data.sh -noclean_files -For more information on the script, please type './dds_32b_8b_comp.sh -help'. +For more information on the script, please type './fifo_rx_data.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/compile.do new file mode 100644 index 00000000..75f343d1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/compile.do @@ -0,0 +1,33 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/fifo_generator_v13_2_4 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap fifo_generator_v13_2_4 questa_lib/msim/fifo_generator_v13_2_4 + +vlog -work xil_defaultlib -64 -sv \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_4 -64 \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_4 -64 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_4 -64 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/elaborate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/elaborate.do new file mode 100644 index 00000000..637ff613 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.fifo_rx_data xil_defaultlib.glbl -o fifo_rx_data_opt diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/fifo_rx_data.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/fifo_rx_data.sh new file mode 100755 index 00000000..80623566 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/fifo_rx_data.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_rx_data.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:07:36 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_rx_data.sh [-help] +# usage: fifo_rx_data.sh [-lib_map_path] +# usage: fifo_rx_data.sh [-noclean_files] +# usage: fifo_rx_data.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_rx_data.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_rx_data.sh [-help]\n\ +Usage: fifo_rx_data.sh [-lib_map_path]\n\ +Usage: fifo_rx_data.sh [-reset_run]\n\ +Usage: fifo_rx_data.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/dds_32b_8b_comp.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/fifo_rx_data.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/dds_32b_8b_comp.udo rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/fifo_rx_data.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/file_info.txt new file mode 100644 index 00000000..c409d183 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/simulate.do similarity index 59% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/simulate.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/simulate.do index 65b86389..59826520 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/simulate.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/simulate.do @@ -1,7 +1,7 @@ onbreak {quit -f} onerror {quit -f} -vsim -t 1ps -lib xil_defaultlib dds_32b_8b_comp_opt +vsim -t 1ps -lib xil_defaultlib fifo_rx_data_opt do {wave.do} @@ -9,7 +9,7 @@ view wave view structure view signals -do {dds_32b_8b_comp.udo} +do {fifo_rx_data.udo} run -all diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/wave.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/wave.do diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/README.txt similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/README.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/README.txt index 8d80168b..32dddaa4 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 00:28:50 CST 2023 +# Generated by export_simulation on Fri May 12 16:07:36 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./dds_32b_8b_comp.sh +./fifo_rx_data.sh This command will launch the 'compile', 'elaborate' and 'simulate' functions implemented in the script file for the 3-step flow. These functions are called @@ -26,16 +26,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './dds_32b_8b_comp.sh' script. +'-reset_run' switch to the './fifo_rx_data.sh' script. -./dds_32b_8b_comp.sh -reset_run +./fifo_rx_data.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./dds_32b_8b_comp.sh -noclean_files +./fifo_rx_data.sh -noclean_files -For more information on the script, please type './dds_32b_8b_comp.sh -help'. +For more information on the script, please type './fifo_rx_data.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/compile.do new file mode 100644 index 00000000..93ed00f9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/compile.do @@ -0,0 +1,33 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/fifo_generator_v13_2_4 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap fifo_generator_v13_2_4 riviera/fifo_generator_v13_2_4 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_4 -v2k5 \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_4 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_4 -v2k5 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/fifo_rx_data.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/fifo_rx_data.sh new file mode 100755 index 00000000..5612e228 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/fifo_rx_data.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_rx_data.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:07:36 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_rx_data.sh [-help] +# usage: fifo_rx_data.sh [-lib_map_path] +# usage: fifo_rx_data.sh [-noclean_files] +# usage: fifo_rx_data.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_rx_data.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_rx_data.sh [-help]\n\ +Usage: fifo_rx_data.sh [-lib_map_path]\n\ +Usage: fifo_rx_data.sh [-reset_run]\n\ +Usage: fifo_rx_data.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/dds_32b_8b_comp.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/fifo_rx_data.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/dds_32b_8b_comp.udo rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/fifo_rx_data.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/file_info.txt new file mode 100644 index 00000000..c409d183 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/simulate.do new file mode 100644 index 00000000..d5f8b47e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+fifo_rx_data -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fifo_rx_data xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {fifo_rx_data.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/wave.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/wave.do diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/README.txt new file mode 100644 index 00000000..32dddaa4 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:07:36 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fifo_rx_data.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fifo_rx_data.sh' script. + +./fifo_rx_data.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fifo_rx_data.sh -noclean_files + +For more information on the script, please type './fifo_rx_data.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/fifo_rx_data.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/fifo_rx_data.sh new file mode 100755 index 00000000..04282927 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/fifo_rx_data.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_rx_data.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:07:36 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_rx_data.sh [-help] +# usage: fifo_rx_data.sh [-lib_map_path] +# usage: fifo_rx_data.sh [-noclean_files] +# usage: fifo_rx_data.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_rx_data.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.fifo_rx_data xil_defaultlib.glbl -o fifo_rx_data_simv +} + +# RUN_STEP: +simulate() +{ + ./fifo_rx_data_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key fifo_rx_data_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc fifo_rx_data_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_rx_data.sh [-help]\n\ +Usage: fifo_rx_data.sh [-lib_map_path]\n\ +Usage: fifo_rx_data.sh [-reset_run]\n\ +Usage: fifo_rx_data.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/file_info.txt new file mode 100644 index 00000000..aba78f72 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/file_info.txt @@ -0,0 +1,2 @@ +fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/simulate.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/simulate.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/simulate.do diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/README.txt similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/README.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/README.txt index bb369b49..fc756dbd 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 00:28:50 CST 2023 +# Generated by export_simulation on Fri May 12 16:07:36 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./dds_32b_8b_comp.sh +./fifo_rx_data.sh This command will launch the 'execute' function for the single-step flow. This function is called from the main 'run' function in the script file. @@ -25,16 +25,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './dds_32b_8b_comp.sh' script. +'-reset_run' switch to the './fifo_rx_data.sh' script. -./dds_32b_8b_comp.sh -reset_run +./fifo_rx_data.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./dds_32b_8b_comp.sh -noclean_files +./fifo_rx_data.sh -noclean_files -For more information on the script, please type './dds_32b_8b_comp.sh -help'. +For more information on the script, please type './fifo_rx_data.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/fifo_rx_data.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/fifo_rx_data.sh new file mode 100755 index 00000000..65ec89e1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/fifo_rx_data.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_rx_data.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:07:36 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_rx_data.sh [-help] +# usage: fifo_rx_data.sh [-lib_map_path] +# usage: fifo_rx_data.sh [-noclean_files] +# usage: fifo_rx_data.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_rx_data.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.fifo_rx_data \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_rx_data.sh [-help]\n\ +Usage: fifo_rx_data.sh [-lib_map_path]\n\ +Usage: fifo_rx_data.sh [-reset_run]\n\ +Usage: fifo_rx_data.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/file_info.txt new file mode 100644 index 00000000..c409d183 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/run.f new file mode 100644 index 00000000..80c63e1b --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/run.f @@ -0,0 +1,23 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/README.txt new file mode 100644 index 00000000..32dddaa4 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:07:36 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fifo_rx_data.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fifo_rx_data.sh' script. + +./fifo_rx_data.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fifo_rx_data.sh -noclean_files + +For more information on the script, please type './fifo_rx_data.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/cmd.tcl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/cmd.tcl similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/cmd.tcl rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/cmd.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/fifo_rx_data.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/fifo_rx_data.sh new file mode 100755 index 00000000..fbfd3615 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/fifo_rx_data.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_rx_data.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:07:36 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_rx_data.sh [-help] +# usage: fifo_rx_data.sh [-lib_map_path] +# usage: fifo_rx_data.sh [-noclean_files] +# usage: fifo_rx_data.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" +xvhdl_opts="--relax" + + +# Script info +echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L fifo_generator_v13_2_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot fifo_rx_data xil_defaultlib.fifo_rx_data xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim fifo_rx_data -key {Behavioral:sim_1:Functional:fifo_rx_data} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb fifo_rx_data.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_rx_data.sh [-help]\n\ +Usage: fifo_rx_data.sh [-lib_map_path]\n\ +Usage: fifo_rx_data.sh [-reset_run]\n\ +Usage: fifo_rx_data.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/file_info.txt new file mode 100644 index 00000000..aba78f72 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/file_info.txt @@ -0,0 +1,2 @@ +fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/vhdl.prj b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/vhdl.prj new file mode 100644 index 00000000..359cbd5e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/vhdl.prj @@ -0,0 +1,2 @@ + +nosort diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/vlog.prj b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/vlog.prj new file mode 100644 index 00000000..e0191c94 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/README.txt similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/README.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/README.txt diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/README.txt new file mode 100644 index 00000000..275ac2f2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:04:30 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs10_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs10_invert_rep2.sh' script. + +./fir_prbs10_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs10_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs10_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/compile.do similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/compile.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/compile.do index 928c972d..a333d8ad 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/compile.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/compile.do @@ -13,7 +13,8 @@ vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10 vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6 vmap fir_compiler_v7_2_12 activehdl/fir_compiler_v7_2_12 -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/fir_prbs7_invert_rep4/cmodel" \ +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/fir_prbs10_invert_rep2/cmodel" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ @@ -29,8 +30,7 @@ vcom -work fir_compiler_v7_2_12 -93 \ "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ vcom -work xil_defaultlib -93 \ -"../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd" \ - +"../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd" \ vlog -work xil_defaultlib \ "glbl.v" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/file_info.txt new file mode 100644 index 00000000..7765cc34 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +fir_prbs10_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/fir_prbs10_invert_rep2.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/fir_prbs10_invert_rep2.mif new file mode 100644 index 00000000..f8d26256 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/fir_prbs10_invert_rep2.mif @@ -0,0 +1,2048 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 0 0 0 4 0 +00000001 0 0 0 0 5 0 +00000001 0 0 0 0 6 0 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127 0 0 2036 0 +00000001 0 127 0 0 2037 0 +00000001 0 127 0 0 2038 0 +00000001 0 127 0 0 2039 0 +00000001 0 127 0 0 2040 0 +00000001 0 127 0 0 2041 0 +00000001 0 127 0 0 2042 0 +00000001 0 127 0 0 2043 0 +00000001 0 127 0 0 2044 0 +00000001 0 127 0 0 2045 0 +ffffffff 0 127 0 0 2046 0 +ffffffff 0 127 0 0 2047 0 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/fir_prbs7_invert_rep4.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/fir_prbs10_invert_rep2.sh similarity index 82% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/fir_prbs7_invert_rep4.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/fir_prbs10_invert_rep2.sh index d6a31b84..b2af05a3 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/fir_prbs7_invert_rep4.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/fir_prbs10_invert_rep2.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : fir_prbs7_invert_rep4.sh +# Filename : fir_prbs10_invert_rep2.sh # Simulator : Aldec Active-HDL Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 11:00:01 CST 2023 +# Generated by Vivado on Fri May 12 16:04:30 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: fir_prbs7_invert_rep4.sh [-help] -# usage: fir_prbs7_invert_rep4.sh [-lib_map_path] -# usage: fir_prbs7_invert_rep4.sh [-noclean_files] -# usage: fir_prbs7_invert_rep4.sh [-reset_run] +# usage: fir_prbs10_invert_rep2.sh [-help] +# usage: fir_prbs10_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs10_invert_rep2.sh [-noclean_files] +# usage: fir_prbs10_invert_rep2.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'fir_prbs7_invert_rep4.sh -help' for more information. +# executing this script. Please type 'fir_prbs10_invert_rep2.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "fir_prbs7_invert_rep4.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "fir_prbs10_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -66,7 +66,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi map_setup_file $2 @@ -121,7 +121,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi @@ -133,10 +133,10 @@ check_args() # Script usage usage() { - msg="Usage: fir_prbs7_invert_rep4.sh [-help]\n\ -Usage: fir_prbs7_invert_rep4.sh [-lib_map_path]\n\ -Usage: fir_prbs7_invert_rep4.sh [-reset_run]\n\ -Usage: fir_prbs7_invert_rep4.sh [-noclean_files]\n\n\ + msg="Usage: fir_prbs10_invert_rep2.sh [-help]\n\ +Usage: fir_prbs10_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs10_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs10_invert_rep2.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/fir_prbs7_invert_rep4.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/fir_prbs10_invert_rep2.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/fir_prbs7_invert_rep4.udo rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/fir_prbs10_invert_rep2.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/prbs10_invert_rep2.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/prbs10_invert_rep2.coe new file mode 100755 index 00000000..0ab98031 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/prbs10_invert_rep2.coe @@ -0,0 +1,2050 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, 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+-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/simulate.do new file mode 100644 index 00000000..0479d5b8 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+fir_prbs10_invert_rep2 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fir_prbs10_invert_rep2 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {fir_prbs10_invert_rep2.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/wave.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/activehdl/wave.do diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/README.txt new file mode 100644 index 00000000..ff2b424a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:04:30 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs10_invert_rep2.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs10_invert_rep2.sh' script. + +./fir_prbs10_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs10_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs10_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/file_info.txt new file mode 100644 index 00000000..7765cc34 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +fir_prbs10_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/fir_prbs10_invert_rep2.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/fir_prbs10_invert_rep2.mif new file mode 100644 index 00000000..f8d26256 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/fir_prbs10_invert_rep2.mif @@ -0,0 +1,2048 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 0 0 0 4 0 +00000001 0 0 0 0 5 0 +00000001 0 0 0 0 6 0 +00000001 0 0 0 0 7 0 +00000001 0 0 0 0 8 0 +00000001 0 0 0 0 9 0 +00000001 0 0 0 0 10 0 +00000001 0 0 0 0 11 0 +00000001 0 0 0 0 12 0 +00000001 0 0 0 0 13 0 +ffffffff 0 0 0 0 14 0 +ffffffff 0 0 0 0 15 0 +00000001 0 1 0 0 16 0 +00000001 0 1 0 0 17 0 +00000001 0 1 0 0 18 0 +00000001 0 1 0 0 19 0 +ffffffff 0 1 0 0 20 0 +ffffffff 0 1 0 0 21 0 +00000001 0 1 0 0 22 0 +00000001 0 1 0 0 23 0 +00000001 0 1 0 0 24 0 +00000001 0 1 0 0 25 0 +00000001 0 1 0 0 26 0 +00000001 0 1 0 0 27 0 +ffffffff 0 1 0 0 28 0 +ffffffff 0 1 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b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/fir_prbs10_invert_rep2.sh similarity index 83% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/fir_prbs7_invert_rep4.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/fir_prbs10_invert_rep2.sh index d9faf6b2..69212636 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/fir_prbs7_invert_rep4.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/fir_prbs10_invert_rep2.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : fir_prbs7_invert_rep4.sh +# Filename : fir_prbs10_invert_rep2.sh # Simulator : Cadence Incisive Enterprise Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 11:00:01 CST 2023 +# Generated by Vivado on Fri May 12 16:04:30 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: fir_prbs7_invert_rep4.sh [-help] -# usage: fir_prbs7_invert_rep4.sh [-lib_map_path] -# usage: fir_prbs7_invert_rep4.sh [-noclean_files] -# usage: fir_prbs7_invert_rep4.sh [-reset_run] +# usage: fir_prbs10_invert_rep2.sh [-help] +# usage: fir_prbs10_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs10_invert_rep2.sh [-noclean_files] +# usage: fir_prbs10_invert_rep2.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'fir_prbs7_invert_rep4.sh -help' for more information. +# executing this script. Please type 'fir_prbs10_invert_rep2.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler sim_lib_dir="ies_lib" # Script info -echo -e "fir_prbs7_invert_rep4.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "fir_prbs10_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,11 +73,11 @@ execute() -reflib "$ref_lib_dir/secureip:secureip" \ -reflib "$ref_lib_dir/unimacro:unimacro" \ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.fir_prbs7_invert_rep4 \ + -top xil_defaultlib.fir_prbs10_invert_rep2 \ -f run.f \ -top glbl \ glbl.v \ - +incdir+"../../../ip/fir_prbs7_invert_rep4/cmodel" + +incdir+"../../../ip/fir_prbs10_invert_rep2/cmodel" } # STEP: setup @@ -86,7 +86,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 else ref_lib_dir=$2 @@ -145,7 +145,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi @@ -157,10 +157,10 @@ check_args() # Script usage usage() { - msg="Usage: fir_prbs7_invert_rep4.sh [-help]\n\ -Usage: fir_prbs7_invert_rep4.sh [-lib_map_path]\n\ -Usage: fir_prbs7_invert_rep4.sh [-reset_run]\n\ -Usage: fir_prbs7_invert_rep4.sh [-noclean_files]\n\n\ + msg="Usage: fir_prbs10_invert_rep2.sh [-help]\n\ +Usage: fir_prbs10_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs10_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs10_invert_rep2.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/prbs10_invert_rep2.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/prbs10_invert_rep2.coe new file mode 100755 index 00000000..0ab98031 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/prbs10_invert_rep2.coe @@ -0,0 +1,2050 @@ +RADIX = 10; +COEFDATA = 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+-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/run.f similarity index 81% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/run.f rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/run.f index 4b6214fa..4cf3071d 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/run.f +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/ies/run.f @@ -1,4 +1,5 @@ -makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib ies_lib/xpm \ @@ -14,7 +15,7 @@ "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ -endlib -makelib ies_lib/xil_defaultlib \ - "../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd" \ + "../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd" \ -endlib -makelib ies_lib/xil_defaultlib \ glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/README.txt new file mode 100644 index 00000000..275ac2f2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:04:30 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs10_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs10_invert_rep2.sh' script. + +./fir_prbs10_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs10_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs10_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/compile.do similarity index 75% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/compile.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/compile.do index 68721efe..a69cff6f 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/compile.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/compile.do @@ -6,7 +6,7 @@ vlib modelsim_lib/msim/xil_defaultlib vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib vcom -work xil_defaultlib -64 -93 \ -"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \ +"../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd" \ vlog -work xil_defaultlib \ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/file_info.txt new file mode 100644 index 00000000..218339e1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/file_info.txt @@ -0,0 +1,2 @@ +fir_prbs10_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/fir_prbs10_invert_rep2.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/fir_prbs10_invert_rep2.mif new file mode 100644 index 00000000..f8d26256 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/fir_prbs10_invert_rep2.mif @@ -0,0 +1,2048 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 0 0 0 4 0 +00000001 0 0 0 0 5 0 +00000001 0 0 0 0 6 0 +00000001 0 0 0 0 7 0 +00000001 0 0 0 0 8 0 +00000001 0 0 0 0 9 0 +00000001 0 0 0 0 10 0 +00000001 0 0 0 0 11 0 +00000001 0 0 0 0 12 0 +00000001 0 0 0 0 13 0 +ffffffff 0 0 0 0 14 0 +ffffffff 0 0 0 0 15 0 +00000001 0 1 0 0 16 0 +00000001 0 1 0 0 17 0 +00000001 0 1 0 0 18 0 +00000001 0 1 0 0 19 0 +ffffffff 0 1 0 0 20 0 +ffffffff 0 1 0 0 21 0 +00000001 0 1 0 0 22 0 +00000001 0 1 0 0 23 0 +00000001 0 1 0 0 24 0 +00000001 0 1 0 0 25 0 +00000001 0 1 0 0 26 0 +00000001 0 1 0 0 27 0 +ffffffff 0 1 0 0 28 0 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b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/fir_prbs10_invert_rep2.sh similarity index 83% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/fir_prbs7_invert_rep4.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/fir_prbs10_invert_rep2.sh index 679b2814..a2a01741 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/fir_prbs7_invert_rep4.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/fir_prbs10_invert_rep2.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : fir_prbs7_invert_rep4.sh +# Filename : fir_prbs10_invert_rep2.sh # Simulator : Mentor Graphics ModelSim Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 11:00:01 CST 2023 +# Generated by Vivado on Fri May 12 16:04:30 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: fir_prbs7_invert_rep4.sh [-help] -# usage: fir_prbs7_invert_rep4.sh [-lib_map_path] -# usage: fir_prbs7_invert_rep4.sh [-noclean_files] -# usage: fir_prbs7_invert_rep4.sh [-reset_run] +# usage: fir_prbs10_invert_rep2.sh [-help] +# usage: fir_prbs10_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs10_invert_rep2.sh [-noclean_files] +# usage: fir_prbs10_invert_rep2.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'fir_prbs7_invert_rep4.sh -help' for more information. +# executing this script. Please type 'fir_prbs10_invert_rep2.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "fir_prbs7_invert_rep4.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "fir_prbs10_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -66,7 +66,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi copy_setup_file $2 @@ -136,7 +136,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi @@ -148,10 +148,10 @@ check_args() # Script usage usage() { - msg="Usage: fir_prbs7_invert_rep4.sh [-help]\n\ -Usage: fir_prbs7_invert_rep4.sh [-lib_map_path]\n\ -Usage: fir_prbs7_invert_rep4.sh [-reset_run]\n\ -Usage: fir_prbs7_invert_rep4.sh [-noclean_files]\n\n\ + msg="Usage: fir_prbs10_invert_rep2.sh [-help]\n\ +Usage: fir_prbs10_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs10_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs10_invert_rep2.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/fir_prbs7_invert_rep4.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/fir_prbs10_invert_rep2.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/fir_prbs7_invert_rep4.udo rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/fir_prbs10_invert_rep2.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/prbs10_invert_rep2.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/prbs10_invert_rep2.coe new file mode 100755 index 00000000..0ab98031 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/prbs10_invert_rep2.coe @@ -0,0 +1,2050 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, 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b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/simulate.do new file mode 100644 index 00000000..f628ab39 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.fir_prbs10_invert_rep2 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {fir_prbs10_invert_rep2.udo} + +run -all + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/wave.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/modelsim/wave.do diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/README.txt new file mode 100644 index 00000000..275ac2f2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:04:30 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs10_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs10_invert_rep2.sh' script. + +./fir_prbs10_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs10_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs10_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/compile.do similarity index 81% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/compile.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/compile.do index da87cfb5..318c47e6 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/compile.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/compile.do @@ -13,7 +13,8 @@ vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10 vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6 vmap fir_compiler_v7_2_12 questa_lib/msim/fir_compiler_v7_2_12 -vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/fir_prbs7_invert_rep4/cmodel" \ +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/fir_prbs10_invert_rep2/cmodel" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ @@ -29,8 +30,7 @@ vcom -work fir_compiler_v7_2_12 -64 -93 \ "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ vcom -work xil_defaultlib -64 -93 \ -"../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd" \ - +"../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd" \ vlog -work xil_defaultlib \ "glbl.v" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/elaborate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/elaborate.do similarity index 70% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/elaborate.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/elaborate.do index 26d92900..398bf335 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/elaborate.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/elaborate.do @@ -1 +1 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.fir_prbs7_invert_rep4 xil_defaultlib.glbl -o fir_prbs7_invert_rep4_opt +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.fir_prbs10_invert_rep2 xil_defaultlib.glbl -o fir_prbs10_invert_rep2_opt diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/file_info.txt new file mode 100644 index 00000000..7765cc34 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +fir_prbs10_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/fir_prbs10_invert_rep2.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/fir_prbs10_invert_rep2.mif new file mode 100644 index 00000000..f8d26256 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/fir_prbs10_invert_rep2.mif @@ -0,0 +1,2048 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 0 0 0 4 0 +00000001 0 0 0 0 5 0 +00000001 0 0 0 0 6 0 +00000001 0 0 0 0 7 0 +00000001 0 0 0 0 8 0 +00000001 0 0 0 0 9 0 +00000001 0 0 0 0 10 0 +00000001 0 0 0 0 11 0 +00000001 0 0 0 0 12 0 +00000001 0 0 0 0 13 0 +ffffffff 0 0 0 0 14 0 +ffffffff 0 0 0 0 15 0 +00000001 0 1 0 0 16 0 +00000001 0 1 0 0 17 0 +00000001 0 1 0 0 18 0 +00000001 0 1 0 0 19 0 +ffffffff 0 1 0 0 20 0 +ffffffff 0 1 0 0 21 0 +00000001 0 1 0 0 22 0 +00000001 0 1 0 0 23 0 +00000001 0 1 0 0 24 0 +00000001 0 1 0 0 25 0 +00000001 0 1 0 0 26 0 +00000001 0 1 0 0 27 0 +ffffffff 0 1 0 0 28 0 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+00000001 0 126 0 0 2018 0 +00000001 0 126 0 0 2019 0 +ffffffff 0 126 0 0 2020 0 +ffffffff 0 126 0 0 2021 0 +00000001 0 126 0 0 2022 0 +00000001 0 126 0 0 2023 0 +00000001 0 126 0 0 2024 0 +00000001 0 126 0 0 2025 0 +ffffffff 0 126 0 0 2026 0 +ffffffff 0 126 0 0 2027 0 +00000001 0 126 0 0 2028 0 +00000001 0 126 0 0 2029 0 +00000001 0 126 0 0 2030 0 +00000001 0 126 0 0 2031 0 +00000001 0 127 0 0 2032 0 +00000001 0 127 0 0 2033 0 +00000001 0 127 0 0 2034 0 +00000001 0 127 0 0 2035 0 +00000001 0 127 0 0 2036 0 +00000001 0 127 0 0 2037 0 +00000001 0 127 0 0 2038 0 +00000001 0 127 0 0 2039 0 +00000001 0 127 0 0 2040 0 +00000001 0 127 0 0 2041 0 +00000001 0 127 0 0 2042 0 +00000001 0 127 0 0 2043 0 +00000001 0 127 0 0 2044 0 +00000001 0 127 0 0 2045 0 +ffffffff 0 127 0 0 2046 0 +ffffffff 0 127 0 0 2047 0 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/fir_prbs7_invert_rep4.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/fir_prbs10_invert_rep2.sh similarity index 84% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/fir_prbs7_invert_rep4.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/fir_prbs10_invert_rep2.sh index 6609c7d0..d7e4c93c 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/fir_prbs7_invert_rep4.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/fir_prbs10_invert_rep2.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : fir_prbs7_invert_rep4.sh +# Filename : fir_prbs10_invert_rep2.sh # Simulator : Mentor Graphics Questa Advanced Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 11:00:01 CST 2023 +# Generated by Vivado on Fri May 12 16:04:30 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: fir_prbs7_invert_rep4.sh [-help] -# usage: fir_prbs7_invert_rep4.sh [-lib_map_path] -# usage: fir_prbs7_invert_rep4.sh [-noclean_files] -# usage: fir_prbs7_invert_rep4.sh [-reset_run] +# usage: fir_prbs10_invert_rep2.sh [-help] +# usage: fir_prbs10_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs10_invert_rep2.sh [-noclean_files] +# usage: fir_prbs10_invert_rep2.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'fir_prbs7_invert_rep4.sh -help' for more information. +# executing this script. Please type 'fir_prbs10_invert_rep2.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "fir_prbs7_invert_rep4.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "fir_prbs10_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,7 +73,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi copy_setup_file $2 @@ -143,7 +143,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi @@ -155,10 +155,10 @@ check_args() # Script usage usage() { - msg="Usage: fir_prbs7_invert_rep4.sh [-help]\n\ -Usage: fir_prbs7_invert_rep4.sh [-lib_map_path]\n\ -Usage: fir_prbs7_invert_rep4.sh [-reset_run]\n\ -Usage: fir_prbs7_invert_rep4.sh [-noclean_files]\n\n\ + msg="Usage: fir_prbs10_invert_rep2.sh [-help]\n\ +Usage: fir_prbs10_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs10_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs10_invert_rep2.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/fir_prbs7_invert_rep4.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/fir_prbs10_invert_rep2.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/fir_prbs7_invert_rep4.udo rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/fir_prbs10_invert_rep2.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/prbs10_invert_rep2.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/prbs10_invert_rep2.coe new file mode 100755 index 00000000..0ab98031 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/prbs10_invert_rep2.coe @@ -0,0 +1,2050 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, 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b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/simulate.do new file mode 100644 index 00000000..cb84093b --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib fir_prbs10_invert_rep2_opt + +do {wave.do} + +view wave +view structure +view signals + +do {fir_prbs10_invert_rep2.udo} + +run -all + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/wave.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/questa/wave.do diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/README.txt new file mode 100644 index 00000000..275ac2f2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:04:30 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs10_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs10_invert_rep2.sh' script. + +./fir_prbs10_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs10_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs10_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/compile.do similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/compile.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/compile.do index 97bc4483..db6fcd5b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/compile.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/compile.do @@ -13,7 +13,8 @@ vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10 vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6 vmap fir_compiler_v7_2_12 riviera/fir_compiler_v7_2_12 -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/fir_prbs7_invert_rep4/cmodel" \ +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/fir_prbs10_invert_rep2/cmodel" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ @@ -29,8 +30,7 @@ vcom -work fir_compiler_v7_2_12 -93 \ "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ vcom -work xil_defaultlib -93 \ -"../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd" \ - +"../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd" \ vlog -work xil_defaultlib \ "glbl.v" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/file_info.txt new file mode 100644 index 00000000..7765cc34 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +fir_prbs10_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/fir_prbs10_invert_rep2.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/fir_prbs10_invert_rep2.mif new file mode 100644 index 00000000..f8d26256 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/fir_prbs10_invert_rep2.mif @@ -0,0 +1,2048 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 0 0 0 4 0 +00000001 0 0 0 0 5 0 +00000001 0 0 0 0 6 0 +00000001 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a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/fir_prbs7_invert_rep4.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/fir_prbs10_invert_rep2.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : fir_prbs7_invert_rep4.sh +# Filename : fir_prbs10_invert_rep2.sh # Simulator : Aldec Riviera-PRO Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 11:00:01 CST 2023 +# Generated by Vivado on Fri May 12 16:04:30 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: fir_prbs7_invert_rep4.sh [-help] -# usage: fir_prbs7_invert_rep4.sh [-lib_map_path] -# usage: fir_prbs7_invert_rep4.sh [-noclean_files] -# usage: fir_prbs7_invert_rep4.sh [-reset_run] +# usage: fir_prbs10_invert_rep2.sh [-help] +# usage: fir_prbs10_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs10_invert_rep2.sh [-noclean_files] +# usage: fir_prbs10_invert_rep2.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'fir_prbs7_invert_rep4.sh -help' for more information. +# executing this script. Please type 'fir_prbs10_invert_rep2.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "fir_prbs7_invert_rep4.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "fir_prbs10_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -66,7 +66,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi map_setup_file $2 @@ -122,7 +122,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi @@ -134,10 +134,10 @@ check_args() # Script usage usage() { - msg="Usage: fir_prbs7_invert_rep4.sh [-help]\n\ -Usage: fir_prbs7_invert_rep4.sh [-lib_map_path]\n\ -Usage: fir_prbs7_invert_rep4.sh [-reset_run]\n\ -Usage: fir_prbs7_invert_rep4.sh [-noclean_files]\n\n\ + msg="Usage: fir_prbs10_invert_rep2.sh [-help]\n\ +Usage: fir_prbs10_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs10_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs10_invert_rep2.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/fir_prbs7_invert_rep4.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/fir_prbs10_invert_rep2.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/fir_prbs7_invert_rep4.udo rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/fir_prbs10_invert_rep2.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/glbl.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/prbs10_invert_rep2.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/prbs10_invert_rep2.coe new file mode 100755 index 00000000..0ab98031 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/prbs10_invert_rep2.coe @@ -0,0 +1,2050 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, 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b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/simulate.do new file mode 100644 index 00000000..0479d5b8 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+fir_prbs10_invert_rep2 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fir_prbs10_invert_rep2 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {fir_prbs10_invert_rep2.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/README.txt new file mode 100644 index 00000000..275ac2f2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:04:30 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs10_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs10_invert_rep2.sh' script. + +./fir_prbs10_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs10_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs10_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/file_info.txt new file mode 100644 index 00000000..218339e1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/file_info.txt @@ -0,0 +1,2 @@ +fir_prbs10_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/fir_prbs10_invert_rep2.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/fir_prbs10_invert_rep2.mif new file mode 100644 index 00000000..f8d26256 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/fir_prbs10_invert_rep2.mif @@ -0,0 +1,2048 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 0 0 0 4 0 +00000001 0 0 0 0 5 0 +00000001 0 0 0 0 6 0 +00000001 0 0 0 0 7 0 +00000001 0 0 0 0 8 0 +00000001 0 0 0 0 9 0 +00000001 0 0 0 0 10 0 +00000001 0 0 0 0 11 0 +00000001 0 0 0 0 12 0 +00000001 0 0 0 0 13 0 +ffffffff 0 0 0 0 14 0 +ffffffff 0 0 0 0 15 0 +00000001 0 1 0 0 16 0 +00000001 0 1 0 0 17 0 +00000001 0 1 0 0 18 0 +00000001 0 1 0 0 19 0 +ffffffff 0 1 0 0 20 0 +ffffffff 0 1 0 0 21 0 +00000001 0 1 0 0 22 0 +00000001 0 1 0 0 23 0 +00000001 0 1 0 0 24 0 +00000001 0 1 0 0 25 0 +00000001 0 1 0 0 26 0 +00000001 0 1 0 0 27 0 +ffffffff 0 1 0 0 28 0 +ffffffff 0 1 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2018 0 +00000001 0 126 0 0 2019 0 +ffffffff 0 126 0 0 2020 0 +ffffffff 0 126 0 0 2021 0 +00000001 0 126 0 0 2022 0 +00000001 0 126 0 0 2023 0 +00000001 0 126 0 0 2024 0 +00000001 0 126 0 0 2025 0 +ffffffff 0 126 0 0 2026 0 +ffffffff 0 126 0 0 2027 0 +00000001 0 126 0 0 2028 0 +00000001 0 126 0 0 2029 0 +00000001 0 126 0 0 2030 0 +00000001 0 126 0 0 2031 0 +00000001 0 127 0 0 2032 0 +00000001 0 127 0 0 2033 0 +00000001 0 127 0 0 2034 0 +00000001 0 127 0 0 2035 0 +00000001 0 127 0 0 2036 0 +00000001 0 127 0 0 2037 0 +00000001 0 127 0 0 2038 0 +00000001 0 127 0 0 2039 0 +00000001 0 127 0 0 2040 0 +00000001 0 127 0 0 2041 0 +00000001 0 127 0 0 2042 0 +00000001 0 127 0 0 2043 0 +00000001 0 127 0 0 2044 0 +00000001 0 127 0 0 2045 0 +ffffffff 0 127 0 0 2046 0 +ffffffff 0 127 0 0 2047 0 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/fir_prbs7_invert_rep4.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/fir_prbs10_invert_rep2.sh similarity index 78% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/fir_prbs7_invert_rep4.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/fir_prbs10_invert_rep2.sh index a0fed676..a26d5735 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/fir_prbs7_invert_rep4.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/fir_prbs10_invert_rep2.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : fir_prbs7_invert_rep4.sh +# Filename : fir_prbs10_invert_rep2.sh # Simulator : Synopsys Verilog Compiler Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 11:00:01 CST 2023 +# Generated by Vivado on Fri May 12 16:04:30 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: fir_prbs7_invert_rep4.sh [-help] -# usage: fir_prbs7_invert_rep4.sh [-lib_map_path] -# usage: fir_prbs7_invert_rep4.sh [-noclean_files] -# usage: fir_prbs7_invert_rep4.sh [-reset_run] +# usage: fir_prbs10_invert_rep2.sh [-help] +# usage: fir_prbs10_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs10_invert_rep2.sh [-noclean_files] +# usage: fir_prbs10_invert_rep2.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'fir_prbs7_invert_rep4.sh -help' for more information. +# executing this script. Please type 'fir_prbs10_invert_rep2.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib) sim_lib_dir="vcs_lib" # Script info -echo -e "fir_prbs7_invert_rep4.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "fir_prbs10_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -71,23 +71,26 @@ compile() { # Compile design files vhdlan -work xil_defaultlib $vhdlan_opts \ - "$ref_dir/../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd" \ + "$ref_dir/../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd" \ 2>&1 | tee -a vhdlan.log + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log } # RUN_STEP: elaborate() { - vcs $vcs_elab_opts xil_defaultlib.fir_prbs7_invert_rep4 -o fir_prbs7_invert_rep4_simv + vcs $vcs_elab_opts xil_defaultlib.fir_prbs10_invert_rep2 xil_defaultlib.glbl -o fir_prbs10_invert_rep2_simv } # RUN_STEP: simulate() { - ./fir_prbs7_invert_rep4_simv $vcs_sim_opts -do simulate.do + ./fir_prbs10_invert_rep2_simv $vcs_sim_opts -do simulate.do } # STEP: setup @@ -96,7 +99,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi create_lib_mappings $2 @@ -172,7 +175,7 @@ create_lib_dir() # Delete generated data from the previous run reset_run() { - files_to_remove=(ucli.key fir_prbs7_invert_rep4_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc fir_prbs7_invert_rep4_simv.daidir) + files_to_remove=(ucli.key fir_prbs10_invert_rep2_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc fir_prbs10_invert_rep2_simv.daidir) for (( i=0; i<${#files_to_remove[*]}; i++ )); do file="${files_to_remove[i]}" if [[ -e $file ]]; then @@ -187,7 +190,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi @@ -199,10 +202,10 @@ check_args() # Script usage usage() { - msg="Usage: fir_prbs7_invert_rep4.sh [-help]\n\ -Usage: fir_prbs7_invert_rep4.sh [-lib_map_path]\n\ -Usage: fir_prbs7_invert_rep4.sh [-reset_run]\n\ -Usage: fir_prbs7_invert_rep4.sh [-noclean_files]\n\n\ + msg="Usage: fir_prbs10_invert_rep2.sh [-help]\n\ +Usage: fir_prbs10_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs10_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs10_invert_rep2.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/prbs10_invert_rep2.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/prbs10_invert_rep2.coe new file mode 100755 index 00000000..0ab98031 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/prbs10_invert_rep2.coe @@ -0,0 +1,2050 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, 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projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/simulate.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/vcs/simulate.do diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/README.txt new file mode 100644 index 00000000..ff2b424a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:04:30 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs10_invert_rep2.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs10_invert_rep2.sh' script. + +./fir_prbs10_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs10_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs10_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/file_info.txt new file mode 100644 index 00000000..7765cc34 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +fir_prbs10_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/fir_prbs10_invert_rep2.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/fir_prbs10_invert_rep2.mif new file mode 100644 index 00000000..f8d26256 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/fir_prbs10_invert_rep2.mif @@ -0,0 +1,2048 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 0 0 0 4 0 +00000001 0 0 0 0 5 0 +00000001 0 0 0 0 6 0 +00000001 0 0 0 0 7 0 +00000001 0 0 0 0 8 0 +00000001 0 0 0 0 9 0 +00000001 0 0 0 0 10 0 +00000001 0 0 0 0 11 0 +00000001 0 0 0 0 12 0 +00000001 0 0 0 0 13 0 +ffffffff 0 0 0 0 14 0 +ffffffff 0 0 0 0 15 0 +00000001 0 1 0 0 16 0 +00000001 0 1 0 0 17 0 +00000001 0 1 0 0 18 0 +00000001 0 1 0 0 19 0 +ffffffff 0 1 0 0 20 0 +ffffffff 0 1 0 0 21 0 +00000001 0 1 0 0 22 0 +00000001 0 1 0 0 23 0 +00000001 0 1 0 0 24 0 +00000001 0 1 0 0 25 0 +00000001 0 1 0 0 26 0 +00000001 0 1 0 0 27 0 +ffffffff 0 1 0 0 28 0 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b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/fir_prbs10_invert_rep2.sh similarity index 83% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/fir_prbs7_invert_rep4.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/fir_prbs10_invert_rep2.sh index bec26712..20566f64 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/fir_prbs7_invert_rep4.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/fir_prbs10_invert_rep2.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : fir_prbs7_invert_rep4.sh +# Filename : fir_prbs10_invert_rep2.sh # Simulator : Cadence Xcelium Parallel Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 11:00:01 CST 2023 +# Generated by Vivado on Fri May 12 16:04:30 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: fir_prbs7_invert_rep4.sh [-help] -# usage: fir_prbs7_invert_rep4.sh [-lib_map_path] -# usage: fir_prbs7_invert_rep4.sh [-noclean_files] -# usage: fir_prbs7_invert_rep4.sh [-reset_run] +# usage: fir_prbs10_invert_rep2.sh [-help] +# usage: fir_prbs10_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs10_invert_rep2.sh [-noclean_files] +# usage: fir_prbs10_invert_rep2.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'fir_prbs7_invert_rep4.sh -help' for more information. +# executing this script. Please type 'fir_prbs10_invert_rep2.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler sim_lib_dir="xcelium_lib" # Script info -echo -e "fir_prbs7_invert_rep4.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "fir_prbs10_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,11 +73,11 @@ execute() -reflib "$ref_lib_dir/secureip:secureip" \ -reflib "$ref_lib_dir/unimacro:unimacro" \ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.fir_prbs7_invert_rep4 \ + -top xil_defaultlib.fir_prbs10_invert_rep2 \ -f run.f \ -top glbl \ glbl.v \ - +incdir+"../../../ip/fir_prbs7_invert_rep4/cmodel" + +incdir+"../../../ip/fir_prbs10_invert_rep2/cmodel" } # STEP: setup @@ -86,7 +86,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 else ref_lib_dir=$2 @@ -145,7 +145,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi @@ -157,10 +157,10 @@ check_args() # Script usage usage() { - msg="Usage: fir_prbs7_invert_rep4.sh [-help]\n\ -Usage: fir_prbs7_invert_rep4.sh [-lib_map_path]\n\ -Usage: fir_prbs7_invert_rep4.sh [-reset_run]\n\ -Usage: fir_prbs7_invert_rep4.sh [-noclean_files]\n\n\ + msg="Usage: fir_prbs10_invert_rep2.sh [-help]\n\ +Usage: fir_prbs10_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs10_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs10_invert_rep2.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/prbs10_invert_rep2.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/prbs10_invert_rep2.coe new file mode 100755 index 00000000..0ab98031 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/prbs10_invert_rep2.coe @@ -0,0 +1,2050 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, 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projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/run.f rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/run.f index f6fb103e..d99165bb 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/run.f +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xcelium/run.f @@ -1,4 +1,5 @@ -makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib xcelium_lib/xpm \ @@ -14,7 +15,7 @@ "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ -endlib -makelib xcelium_lib/xil_defaultlib \ - "../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd" \ + "../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd" \ -endlib -makelib xcelium_lib/xil_defaultlib \ glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/README.txt new file mode 100644 index 00000000..275ac2f2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:04:30 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fir_prbs10_invert_rep2.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fir_prbs10_invert_rep2.sh' script. + +./fir_prbs10_invert_rep2.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fir_prbs10_invert_rep2.sh -noclean_files + +For more information on the script, please type './fir_prbs10_invert_rep2.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/cmd.tcl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/cmd.tcl similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/cmd.tcl rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/cmd.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/file_info.txt new file mode 100644 index 00000000..218339e1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/file_info.txt @@ -0,0 +1,2 @@ +fir_prbs10_invert_rep2.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd,incdir="../../../ip/fir_prbs10_invert_rep2/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/fir_prbs10_invert_rep2.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/fir_prbs10_invert_rep2.mif new file mode 100644 index 00000000..f8d26256 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/fir_prbs10_invert_rep2.mif @@ -0,0 +1,2048 @@ +00000001 0 0 0 0 0 0 +00000001 0 0 0 0 1 0 +00000001 0 0 0 0 2 0 +00000001 0 0 0 0 3 0 +00000001 0 0 0 0 4 0 +00000001 0 0 0 0 5 0 +00000001 0 0 0 0 6 0 +00000001 0 0 0 0 7 0 +00000001 0 0 0 0 8 0 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+00000001 0 127 0 0 2038 0 +00000001 0 127 0 0 2039 0 +00000001 0 127 0 0 2040 0 +00000001 0 127 0 0 2041 0 +00000001 0 127 0 0 2042 0 +00000001 0 127 0 0 2043 0 +00000001 0 127 0 0 2044 0 +00000001 0 127 0 0 2045 0 +ffffffff 0 127 0 0 2046 0 +ffffffff 0 127 0 0 2047 0 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/fir_prbs7_invert_rep4.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/fir_prbs10_invert_rep2.sh similarity index 82% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/fir_prbs7_invert_rep4.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/fir_prbs10_invert_rep2.sh index f3e34be7..b7bd5a0e 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/fir_prbs7_invert_rep4.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/fir_prbs10_invert_rep2.sh @@ -2,32 +2,33 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : fir_prbs7_invert_rep4.sh +# Filename : fir_prbs10_invert_rep2.sh # Simulator : Xilinx Vivado Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 11:00:01 CST 2023 +# Generated by Vivado on Fri May 12 16:04:30 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: fir_prbs7_invert_rep4.sh [-help] -# usage: fir_prbs7_invert_rep4.sh [-lib_map_path] -# usage: fir_prbs7_invert_rep4.sh [-noclean_files] -# usage: fir_prbs7_invert_rep4.sh [-reset_run] +# usage: fir_prbs10_invert_rep2.sh [-help] +# usage: fir_prbs10_invert_rep2.sh [-lib_map_path] +# usage: fir_prbs10_invert_rep2.sh [-noclean_files] +# usage: fir_prbs10_invert_rep2.sh [-reset_run] # #********************************************************************************************************* # Command line options xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" xvhdl_opts="--relax" # Script info -echo -e "fir_prbs7_invert_rep4.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "fir_prbs10_invert_rep2.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -43,6 +44,7 @@ run() compile() { # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log } @@ -50,13 +52,13 @@ compile() # RUN_STEP: elaborate() { - xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L secureip -L xpm --snapshot fir_prbs7_invert_rep4 xil_defaultlib.fir_prbs7_invert_rep4 -log elaborate.log + xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot fir_prbs10_invert_rep2 xil_defaultlib.fir_prbs10_invert_rep2 xil_defaultlib.glbl -log elaborate.log } # RUN_STEP: simulate() { - xsim fir_prbs7_invert_rep4 -key {Behavioral:sim_1:Functional:fir_prbs7_invert_rep4} -tclbatch cmd.tcl -log simulate.log + xsim fir_prbs10_invert_rep2 -key {Behavioral:sim_1:Functional:fir_prbs10_invert_rep2} -tclbatch cmd.tcl -log simulate.log } # STEP: setup @@ -65,7 +67,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi copy_setup_file $2 @@ -168,7 +170,7 @@ map_local_libs() # Delete generated data from the previous run reset_run() { - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb fir_prbs7_invert_rep4.wdb xsim.dir) + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb fir_prbs10_invert_rep2.wdb xsim.dir) for (( i=0; i<${#files_to_remove[*]}; i++ )); do file="${files_to_remove[i]}" if [[ -e $file ]]; then @@ -181,7 +183,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs7_invert_rep4.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./fir_prbs10_invert_rep2.sh -help\" for more information)\n" exit 1 fi @@ -193,10 +195,10 @@ check_args() # Script usage usage() { - msg="Usage: fir_prbs7_invert_rep4.sh [-help]\n\ -Usage: fir_prbs7_invert_rep4.sh [-lib_map_path]\n\ -Usage: fir_prbs7_invert_rep4.sh [-reset_run]\n\ -Usage: fir_prbs7_invert_rep4.sh [-noclean_files]\n\n\ + msg="Usage: fir_prbs10_invert_rep2.sh [-help]\n\ +Usage: fir_prbs10_invert_rep2.sh [-lib_map_path]\n\ +Usage: fir_prbs10_invert_rep2.sh [-reset_run]\n\ +Usage: fir_prbs10_invert_rep2.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/prbs10_invert_rep2.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/prbs10_invert_rep2.coe new file mode 100755 index 00000000..0ab98031 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/prbs10_invert_rep2.coe @@ -0,0 +1,2050 @@ +RADIX = 10; +COEFDATA = +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, 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+-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +-1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +-1, +-1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +-1, +-1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +-1, +-1; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/vhdl.prj b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/vhdl.prj new file mode 100644 index 00000000..e19e4434 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/vhdl.prj @@ -0,0 +1,4 @@ +vhdl xil_defaultlib \ +"../../../ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd" \ + +nosort diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/vlog.prj b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/vlog.prj similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xsim/vlog.prj rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs10_invert_rep2/xsim/vlog.prj diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/README.txt deleted file mode 100644 index 73e66f1f..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun May 07 11:00:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./fir_prbs7_invert_rep4.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './fir_prbs7_invert_rep4.sh' script. - -./fir_prbs7_invert_rep4.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./fir_prbs7_invert_rep4.sh -noclean_files - -For more information on the script, please type './fir_prbs7_invert_rep4.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/file_info.txt deleted file mode 100644 index 605d9ee7..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/file_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -fir_prbs7_invert_rep4.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/fir_prbs7_invert_rep4.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/fir_prbs7_invert_rep4.mif deleted file mode 100644 index f4b188fe..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/fir_prbs7_invert_rep4.mif +++ /dev/null @@ -1,512 +0,0 @@ -00000001 0 0 0 0 0 0 -00000001 0 0 0 0 1 0 -00000001 0 1 0 0 2 0 -00000001 0 1 0 0 3 0 -00000001 0 2 0 0 4 0 -00000001 0 2 0 0 5 0 -00000001 0 3 0 0 6 0 -00000001 0 3 0 0 7 0 -00000001 0 4 0 0 8 0 -00000001 0 4 0 0 9 0 -00000001 0 5 0 0 10 0 -00000001 0 5 0 0 11 0 -00000001 0 6 0 0 12 0 -00000001 0 6 0 0 13 0 -00000001 0 7 0 0 14 0 -00000001 0 7 0 0 15 0 -00000001 0 8 0 0 16 0 -00000001 0 8 0 0 17 0 -00000001 0 9 0 0 18 0 -00000001 0 9 0 0 19 0 -00000001 0 10 0 0 20 0 -00000001 0 10 0 0 21 0 -00000001 0 11 0 0 22 0 -00000001 0 11 0 0 23 0 -ffffffff 0 12 0 0 24 0 -ffffffff 0 12 0 0 25 0 -ffffffff 0 13 0 0 26 0 -ffffffff 0 13 0 0 27 0 -ffffffff 0 14 0 0 28 0 -ffffffff 0 14 0 0 29 0 -ffffffff 0 15 0 0 30 0 -ffffffff 0 15 0 0 31 0 -00000001 0 16 0 0 32 0 -00000001 0 16 0 0 33 0 -00000001 0 17 0 0 34 0 -00000001 0 17 0 0 35 0 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0 -00000001 0 253 0 0 506 0 -00000001 0 253 0 0 507 0 -ffffffff 0 254 0 0 508 0 -ffffffff 0 254 0 0 509 0 -ffffffff 0 255 0 0 510 0 -ffffffff 0 255 0 0 511 0 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/prbs7_invert_rep4.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/prbs7_invert_rep4.coe deleted file mode 100755 index 4ade3f8b..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/prbs7_invert_rep4.coe +++ /dev/null @@ -1,514 +0,0 @@ -RADIX = 10; -COEFDATA = -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, 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a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/simulate.do deleted file mode 100644 index 121ff28a..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/activehdl/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+fir_prbs7_invert_rep4 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fir_prbs7_invert_rep4 xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {fir_prbs7_invert_rep4.udo} - -run -all - -endsim - -quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/file_info.txt deleted file mode 100644 index 605d9ee7..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/file_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -fir_prbs7_invert_rep4.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/fir_prbs7_invert_rep4.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/fir_prbs7_invert_rep4.mif deleted file mode 100644 index f4b188fe..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/fir_prbs7_invert_rep4.mif +++ /dev/null @@ -1,512 +0,0 @@ -00000001 0 0 0 0 0 0 -00000001 0 0 0 0 1 0 -00000001 0 1 0 0 2 0 -00000001 0 1 0 0 3 0 -00000001 0 2 0 0 4 0 -00000001 0 2 0 0 5 0 -00000001 0 3 0 0 6 0 -00000001 0 3 0 0 7 0 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b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/prbs7_invert_rep4.coe deleted file mode 100755 index 4ade3f8b..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/prbs7_invert_rep4.coe +++ /dev/null @@ -1,514 +0,0 @@ -RADIX = 10; -COEFDATA = -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, 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a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun May 07 11:00:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./fir_prbs7_invert_rep4.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './fir_prbs7_invert_rep4.sh' script. - -./fir_prbs7_invert_rep4.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./fir_prbs7_invert_rep4.sh -noclean_files - -For more information on the script, please type './fir_prbs7_invert_rep4.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/file_info.txt deleted file mode 100644 index 4f87c222..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/file_info.txt +++ /dev/null @@ -1 +0,0 @@ -fir_prbs7_invert_rep4.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/fir_prbs7_invert_rep4.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/fir_prbs7_invert_rep4.mif deleted file mode 100644 index f4b188fe..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/fir_prbs7_invert_rep4.mif +++ /dev/null @@ -1,512 +0,0 @@ -00000001 0 0 0 0 0 0 -00000001 0 0 0 0 1 0 -00000001 0 1 0 0 2 0 -00000001 0 1 0 0 3 0 -00000001 0 2 0 0 4 0 -00000001 0 2 0 0 5 0 -00000001 0 3 0 0 6 0 -00000001 0 3 0 0 7 0 -00000001 0 4 0 0 8 0 -00000001 0 4 0 0 9 0 -00000001 0 5 0 0 10 0 -00000001 0 5 0 0 11 0 -00000001 0 6 0 0 12 0 -00000001 0 6 0 0 13 0 -00000001 0 7 0 0 14 0 -00000001 0 7 0 0 15 0 -00000001 0 8 0 0 16 0 -00000001 0 8 0 0 17 0 -00000001 0 9 0 0 18 0 -00000001 0 9 0 0 19 0 -00000001 0 10 0 0 20 0 -00000001 0 10 0 0 21 0 -00000001 0 11 0 0 22 0 -00000001 0 11 0 0 23 0 -ffffffff 0 12 0 0 24 0 -ffffffff 0 12 0 0 25 0 -ffffffff 0 13 0 0 26 0 -ffffffff 0 13 0 0 27 0 -ffffffff 0 14 0 0 28 0 -ffffffff 0 14 0 0 29 0 -ffffffff 0 15 0 0 30 0 -ffffffff 0 15 0 0 31 0 -00000001 0 16 0 0 32 0 -00000001 0 16 0 0 33 0 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0 -00000001 0 252 0 0 504 0 -00000001 0 252 0 0 505 0 -00000001 0 253 0 0 506 0 -00000001 0 253 0 0 507 0 -ffffffff 0 254 0 0 508 0 -ffffffff 0 254 0 0 509 0 -ffffffff 0 255 0 0 510 0 -ffffffff 0 255 0 0 511 0 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/prbs7_invert_rep4.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/prbs7_invert_rep4.coe deleted file mode 100755 index 4ade3f8b..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/prbs7_invert_rep4.coe +++ /dev/null @@ -1,514 +0,0 @@ -RADIX = 10; -COEFDATA = -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 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--1; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/simulate.do deleted file mode 100644 index 02ca8851..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.fir_prbs7_invert_rep4 - -do {wave.do} - -view wave -view structure -view signals - -do {fir_prbs7_invert_rep4.udo} - -run -all - -quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/wave.do deleted file mode 100644 index 05fa26a6..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/modelsim/wave.do +++ /dev/null @@ -1 +0,0 @@ -add wave * diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/README.txt deleted file mode 100644 index 73e66f1f..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun May 07 11:00:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./fir_prbs7_invert_rep4.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './fir_prbs7_invert_rep4.sh' script. - -./fir_prbs7_invert_rep4.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./fir_prbs7_invert_rep4.sh -noclean_files - -For more information on the script, please type './fir_prbs7_invert_rep4.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/file_info.txt deleted file mode 100644 index 605d9ee7..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/file_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -fir_prbs7_invert_rep4.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/fir_prbs7_invert_rep4.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/fir_prbs7_invert_rep4.mif deleted file mode 100644 index f4b188fe..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/fir_prbs7_invert_rep4.mif +++ /dev/null @@ -1,512 +0,0 @@ -00000001 0 0 0 0 0 0 -00000001 0 0 0 0 1 0 -00000001 0 1 0 0 2 0 -00000001 0 1 0 0 3 0 -00000001 0 2 0 0 4 0 -00000001 0 2 0 0 5 0 -00000001 0 3 0 0 6 0 -00000001 0 3 0 0 7 0 -00000001 0 4 0 0 8 0 -00000001 0 4 0 0 9 0 -00000001 0 5 0 0 10 0 -00000001 0 5 0 0 11 0 -00000001 0 6 0 0 12 0 -00000001 0 6 0 0 13 0 -00000001 0 7 0 0 14 0 -00000001 0 7 0 0 15 0 -00000001 0 8 0 0 16 0 -00000001 0 8 0 0 17 0 -00000001 0 9 0 0 18 0 -00000001 0 9 0 0 19 0 -00000001 0 10 0 0 20 0 -00000001 0 10 0 0 21 0 -00000001 0 11 0 0 22 0 -00000001 0 11 0 0 23 0 -ffffffff 0 12 0 0 24 0 -ffffffff 0 12 0 0 25 0 -ffffffff 0 13 0 0 26 0 -ffffffff 0 13 0 0 27 0 -ffffffff 0 14 0 0 28 0 -ffffffff 0 14 0 0 29 0 -ffffffff 0 15 0 0 30 0 -ffffffff 0 15 0 0 31 0 -00000001 0 16 0 0 32 0 -00000001 0 16 0 0 33 0 -00000001 0 17 0 0 34 0 -00000001 0 17 0 0 35 0 -00000001 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0 253 0 0 506 0 -00000001 0 253 0 0 507 0 -ffffffff 0 254 0 0 508 0 -ffffffff 0 254 0 0 509 0 -ffffffff 0 255 0 0 510 0 -ffffffff 0 255 0 0 511 0 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/prbs7_invert_rep4.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/prbs7_invert_rep4.coe deleted file mode 100755 index 4ade3f8b..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/prbs7_invert_rep4.coe +++ /dev/null @@ -1,514 +0,0 @@ -RADIX = 10; -COEFDATA = -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, 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a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/README.txt deleted file mode 100644 index 73e66f1f..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun May 07 11:00:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./fir_prbs7_invert_rep4.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './fir_prbs7_invert_rep4.sh' script. - -./fir_prbs7_invert_rep4.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./fir_prbs7_invert_rep4.sh -noclean_files - -For more information on the script, please type './fir_prbs7_invert_rep4.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/file_info.txt deleted file mode 100644 index 605d9ee7..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/file_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -fir_prbs7_invert_rep4.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/fir_prbs7_invert_rep4.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/fir_prbs7_invert_rep4.mif deleted file mode 100644 index f4b188fe..00000000 --- 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0 253 0 0 506 0 -00000001 0 253 0 0 507 0 -ffffffff 0 254 0 0 508 0 -ffffffff 0 254 0 0 509 0 -ffffffff 0 255 0 0 510 0 -ffffffff 0 255 0 0 511 0 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/prbs7_invert_rep4.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/prbs7_invert_rep4.coe deleted file mode 100755 index 4ade3f8b..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/prbs7_invert_rep4.coe +++ /dev/null @@ -1,514 +0,0 @@ -RADIX = 10; -COEFDATA = -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, 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a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/simulate.do deleted file mode 100644 index 121ff28a..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/riviera/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+fir_prbs7_invert_rep4 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fir_prbs7_invert_rep4 xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {fir_prbs7_invert_rep4.udo} - -run -all - -endsim - -quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/README.txt deleted file mode 100644 index 73e66f1f..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun May 07 11:00:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./fir_prbs7_invert_rep4.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './fir_prbs7_invert_rep4.sh' script. - -./fir_prbs7_invert_rep4.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./fir_prbs7_invert_rep4.sh -noclean_files - -For more information on the script, please type './fir_prbs7_invert_rep4.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/file_info.txt deleted file mode 100644 index 4f87c222..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/file_info.txt +++ /dev/null @@ -1 +0,0 @@ -fir_prbs7_invert_rep4.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/fir_prbs7_invert_rep4.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/fir_prbs7_invert_rep4.mif deleted file mode 100644 index f4b188fe..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/fir_prbs7_invert_rep4.mif +++ /dev/null @@ -1,512 +0,0 @@ -00000001 0 0 0 0 0 0 -00000001 0 0 0 0 1 0 -00000001 0 1 0 0 2 0 -00000001 0 1 0 0 3 0 -00000001 0 2 0 0 4 0 -00000001 0 2 0 0 5 0 -00000001 0 3 0 0 6 0 -00000001 0 3 0 0 7 0 -00000001 0 4 0 0 8 0 -00000001 0 4 0 0 9 0 -00000001 0 5 0 0 10 0 -00000001 0 5 0 0 11 0 -00000001 0 6 0 0 12 0 -00000001 0 6 0 0 13 0 -00000001 0 7 0 0 14 0 -00000001 0 7 0 0 15 0 -00000001 0 8 0 0 16 0 -00000001 0 8 0 0 17 0 -00000001 0 9 0 0 18 0 -00000001 0 9 0 0 19 0 -00000001 0 10 0 0 20 0 -00000001 0 10 0 0 21 0 -00000001 0 11 0 0 22 0 -00000001 0 11 0 0 23 0 -ffffffff 0 12 0 0 24 0 -ffffffff 0 12 0 0 25 0 -ffffffff 0 13 0 0 26 0 -ffffffff 0 13 0 0 27 0 -ffffffff 0 14 0 0 28 0 -ffffffff 0 14 0 0 29 0 -ffffffff 0 15 0 0 30 0 -ffffffff 0 15 0 0 31 0 -00000001 0 16 0 0 32 0 -00000001 0 16 0 0 33 0 -00000001 0 17 0 0 34 0 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0 -00000001 0 252 0 0 505 0 -00000001 0 253 0 0 506 0 -00000001 0 253 0 0 507 0 -ffffffff 0 254 0 0 508 0 -ffffffff 0 254 0 0 509 0 -ffffffff 0 255 0 0 510 0 -ffffffff 0 255 0 0 511 0 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/prbs7_invert_rep4.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/prbs7_invert_rep4.coe deleted file mode 100755 index 4ade3f8b..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/vcs/prbs7_invert_rep4.coe +++ /dev/null @@ -1,514 +0,0 @@ -RADIX = 10; -COEFDATA = -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, 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a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/file_info.txt deleted file mode 100644 index 605d9ee7..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/file_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -fir_prbs7_invert_rep4.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/fir_prbs7_invert_rep4.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/fir_prbs7_invert_rep4.mif deleted file mode 100644 index f4b188fe..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/fir_prbs7_invert_rep4.mif +++ /dev/null @@ -1,512 +0,0 @@ -00000001 0 0 0 0 0 0 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a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/prbs7_invert_rep4.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/prbs7_invert_rep4.coe deleted file mode 100755 index 4ade3f8b..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/prbs7_invert_rep4.coe +++ /dev/null @@ -1,514 +0,0 @@ -RADIX = 10; -COEFDATA = -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, 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b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/README.txt deleted file mode 100644 index 73e66f1f..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun May 07 11:00:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./fir_prbs7_invert_rep4.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './fir_prbs7_invert_rep4.sh' script. - -./fir_prbs7_invert_rep4.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./fir_prbs7_invert_rep4.sh -noclean_files - -For more information on the script, please type './fir_prbs7_invert_rep4.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/file_info.txt deleted file mode 100644 index 4f87c222..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/file_info.txt +++ /dev/null @@ -1 +0,0 @@ -fir_prbs7_invert_rep4.vhd,vhdl,xil_defaultlib,../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd,incdir="../../../ip/fir_prbs7_invert_rep4/cmodel" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/fir_prbs7_invert_rep4.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/fir_prbs7_invert_rep4.mif deleted file mode 100644 index f4b188fe..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/fir_prbs7_invert_rep4.mif +++ /dev/null @@ -1,512 +0,0 @@ -00000001 0 0 0 0 0 0 -00000001 0 0 0 0 1 0 -00000001 0 1 0 0 2 0 -00000001 0 1 0 0 3 0 -00000001 0 2 0 0 4 0 -00000001 0 2 0 0 5 0 -00000001 0 3 0 0 6 0 -00000001 0 3 0 0 7 0 -00000001 0 4 0 0 8 0 -00000001 0 4 0 0 9 0 -00000001 0 5 0 0 10 0 -00000001 0 5 0 0 11 0 -00000001 0 6 0 0 12 0 -00000001 0 6 0 0 13 0 -00000001 0 7 0 0 14 0 -00000001 0 7 0 0 15 0 -00000001 0 8 0 0 16 0 -00000001 0 8 0 0 17 0 -00000001 0 9 0 0 18 0 -00000001 0 9 0 0 19 0 -00000001 0 10 0 0 20 0 -00000001 0 10 0 0 21 0 -00000001 0 11 0 0 22 0 -00000001 0 11 0 0 23 0 -ffffffff 0 12 0 0 24 0 -ffffffff 0 12 0 0 25 0 -ffffffff 0 13 0 0 26 0 -ffffffff 0 13 0 0 27 0 -ffffffff 0 14 0 0 28 0 -ffffffff 0 14 0 0 29 0 -ffffffff 0 15 0 0 30 0 -ffffffff 0 15 0 0 31 0 -00000001 0 16 0 0 32 0 -00000001 0 16 0 0 33 0 -00000001 0 17 0 0 34 0 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0 -00000001 0 252 0 0 505 0 -00000001 0 253 0 0 506 0 -00000001 0 253 0 0 507 0 -ffffffff 0 254 0 0 508 0 -ffffffff 0 254 0 0 509 0 -ffffffff 0 255 0 0 510 0 -ffffffff 0 255 0 0 511 0 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/prbs7_invert_rep4.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/prbs7_invert_rep4.coe deleted file mode 100755 index 4ade3f8b..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/prbs7_invert_rep4.coe +++ /dev/null @@ -1,514 +0,0 @@ -RADIX = 10; -COEFDATA = -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, -1, -1, -1, -1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, --1, --1, --1, --1; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/vhdl.prj b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/vhdl.prj deleted file mode 100644 index eb381046..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xsim/vhdl.prj +++ /dev/null @@ -1,4 +0,0 @@ -vhdl xil_defaultlib \ -"../../../ip/fir_prbs7_invert_rep4/sim/fir_prbs7_invert_rep4.vhd" \ - -nosort diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/README.txt index 5b9b1407..f4274897 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 12:12:09 CST 2023 +# Generated by export_simulation on Fri May 12 16:03:34 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/ila_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/ila_freq_comp.sh index 043515f7..46efd591 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/ila_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/activehdl/ila_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 12:12:09 CST 2023 +# Generated by Vivado on Fri May 12 16:03:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/README.txt index 7c1c4c7f..e5ee49e4 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 12:12:09 CST 2023 +# Generated by export_simulation on Fri May 12 16:03:34 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/ila_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/ila_freq_comp.sh index b17b968a..0cc32a79 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/ila_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/ies/ila_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 12:12:09 CST 2023 +# Generated by Vivado on Fri May 12 16:03:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/README.txt index 5b9b1407..f4274897 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 12:12:09 CST 2023 +# Generated by export_simulation on Fri May 12 16:03:34 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/ila_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/ila_freq_comp.sh index be776c31..633ce223 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/ila_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/modelsim/ila_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 12:12:09 CST 2023 +# Generated by Vivado on Fri May 12 16:03:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/README.txt index 5b9b1407..f4274897 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 12:12:09 CST 2023 +# Generated by export_simulation on Fri May 12 16:03:34 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/ila_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/ila_freq_comp.sh index fc347044..d547ef49 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/ila_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/questa/ila_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 12:12:09 CST 2023 +# Generated by Vivado on Fri May 12 16:03:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/README.txt index 5b9b1407..f4274897 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 12:12:09 CST 2023 +# Generated by export_simulation on Fri May 12 16:03:34 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/ila_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/ila_freq_comp.sh index 73081c7d..5a65427b 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/ila_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/riviera/ila_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 12:12:09 CST 2023 +# Generated by Vivado on Fri May 12 16:03:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/README.txt index 5b9b1407..f4274897 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 12:12:09 CST 2023 +# Generated by export_simulation on Fri May 12 16:03:34 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/ila_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/ila_freq_comp.sh index 6ccb7ab4..3eb41213 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/ila_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/vcs/ila_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 12:12:09 CST 2023 +# Generated by Vivado on Fri May 12 16:03:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/README.txt index 7c1c4c7f..e5ee49e4 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 12:12:09 CST 2023 +# Generated by export_simulation on Fri May 12 16:03:34 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/ila_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/ila_freq_comp.sh index 70f822c5..b31156e8 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/ila_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xcelium/ila_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 12:12:09 CST 2023 +# Generated by Vivado on Fri May 12 16:03:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/README.txt index 5b9b1407..f4274897 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 12:12:09 CST 2023 +# Generated by export_simulation on Fri May 12 16:03:34 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/ila_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/ila_freq_comp.sh index 2a64f10a..5f2a53b3 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/ila_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_freq_comp/xsim/ila_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 12:12:09 CST 2023 +# Generated by Vivado on Fri May 12 16:03:34 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/README.txt new file mode 100644 index 00000000..5278ed31 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:02:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_auto_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_auto_control.sh' script. + +./ila_rf_auto_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_auto_control.sh -noclean_files + +For more information on the script, please type './ila_rf_auto_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/compile.do new file mode 100644 index 00000000..cda35910 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rf_auto_control/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rf_auto_control/hdl/verilog" \ +"../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/file_info.txt new file mode 100644 index 00000000..45c739e9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +ila_rf_auto_control.v,verilog,xil_defaultlib,../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/ila_rf_auto_control.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/ila_rf_auto_control.sh new file mode 100755 index 00000000..e6165219 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/ila_rf_auto_control.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_auto_control.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:02:01 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_auto_control.sh [-help] +# usage: ila_rf_auto_control.sh [-lib_map_path] +# usage: ila_rf_auto_control.sh [-noclean_files] +# usage: ila_rf_auto_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_auto_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rf_auto_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_auto_control.sh [-help]\n\ +Usage: ila_rf_auto_control.sh [-lib_map_path]\n\ +Usage: ila_rf_auto_control.sh [-reset_run]\n\ +Usage: ila_rf_auto_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/ila_rf_auto_control.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/.Vivado_Synthesis.queue.rst rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/ila_rf_auto_control.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/simulate.do new file mode 100644 index 00000000..819e698e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_rf_auto_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rf_auto_control xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_rf_auto_control.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/README.txt similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/README.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/README.txt index 4d50d279..2a411957 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/ies/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun May 07 11:00:01 CST 2023 +# Generated by export_simulation on Fri May 12 16:02:01 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./fir_prbs7_invert_rep4.sh +./ila_rf_auto_control.sh This command will launch the 'execute' function for the single-step flow. This function is called from the main 'run' function in the script file. @@ -25,16 +25,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './fir_prbs7_invert_rep4.sh' script. +'-reset_run' switch to the './ila_rf_auto_control.sh' script. -./fir_prbs7_invert_rep4.sh -reset_run +./ila_rf_auto_control.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./fir_prbs7_invert_rep4.sh -noclean_files +./ila_rf_auto_control.sh -noclean_files -For more information on the script, please type './fir_prbs7_invert_rep4.sh -help'. +For more information on the script, please type './ila_rf_auto_control.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/file_info.txt new file mode 100644 index 00000000..45c739e9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +ila_rf_auto_control.v,verilog,xil_defaultlib,../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/ila_rf_auto_control.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/ila_rf_auto_control.sh new file mode 100755 index 00000000..d1c21abd --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/ila_rf_auto_control.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_auto_control.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:02:01 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_auto_control.sh [-help] +# usage: ila_rf_auto_control.sh [-lib_map_path] +# usage: ila_rf_auto_control.sh [-noclean_files] +# usage: ila_rf_auto_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_auto_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "ila_rf_auto_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ila_rf_auto_control \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ila_rf_auto_control/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_auto_control.sh [-help]\n\ +Usage: ila_rf_auto_control.sh [-lib_map_path]\n\ +Usage: ila_rf_auto_control.sh [-reset_run]\n\ +Usage: ila_rf_auto_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/run.f new file mode 100644 index 00000000..f426aaf3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/README.txt new file mode 100644 index 00000000..5278ed31 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:02:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_auto_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_auto_control.sh' script. + +./ila_rf_auto_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_auto_control.sh -noclean_files + +For more information on the script, please type './ila_rf_auto_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/compile.do new file mode 100644 index 00000000..296a45b3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_rf_auto_control/hdl/verilog" \ +"../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/file_info.txt new file mode 100644 index 00000000..b52083f1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/file_info.txt @@ -0,0 +1,2 @@ +ila_rf_auto_control.v,verilog,xil_defaultlib,../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/ila_rf_auto_control.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/ila_rf_auto_control.sh new file mode 100755 index 00000000..9b0d55bd --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/ila_rf_auto_control.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_auto_control.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:02:01 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_auto_control.sh [-help] +# usage: ila_rf_auto_control.sh [-lib_map_path] +# usage: ila_rf_auto_control.sh [-noclean_files] +# usage: ila_rf_auto_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_auto_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rf_auto_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_auto_control.sh [-help]\n\ +Usage: ila_rf_auto_control.sh [-lib_map_path]\n\ +Usage: ila_rf_auto_control.sh [-reset_run]\n\ +Usage: ila_rf_auto_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/.vivado.end.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/ila_rf_auto_control.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/.vivado.end.rst rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/ila_rf_auto_control.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/simulate.do new file mode 100644 index 00000000..7eaaba06 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.ila_rf_auto_control xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {ila_rf_auto_control.udo} + +run -all + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/README.txt new file mode 100644 index 00000000..5278ed31 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:02:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_auto_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_auto_control.sh' script. + +./ila_rf_auto_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_auto_control.sh -noclean_files + +For more information on the script, please type './ila_rf_auto_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/compile.do new file mode 100644 index 00000000..7b4ea612 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_rf_auto_control/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_rf_auto_control/hdl/verilog" \ +"../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/elaborate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/elaborate.do new file mode 100644 index 00000000..81b3bb36 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_rf_auto_control xil_defaultlib.glbl -o ila_rf_auto_control_opt diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/file_info.txt new file mode 100644 index 00000000..45c739e9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +ila_rf_auto_control.v,verilog,xil_defaultlib,../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/ila_rf_auto_control.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/ila_rf_auto_control.sh new file mode 100755 index 00000000..cb821030 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/ila_rf_auto_control.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_auto_control.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:02:01 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_auto_control.sh [-help] +# usage: ila_rf_auto_control.sh [-lib_map_path] +# usage: ila_rf_auto_control.sh [-noclean_files] +# usage: ila_rf_auto_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_auto_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rf_auto_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_auto_control.sh [-help]\n\ +Usage: ila_rf_auto_control.sh [-lib_map_path]\n\ +Usage: ila_rf_auto_control.sh [-reset_run]\n\ +Usage: ila_rf_auto_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/__synthesis_is_complete__ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/ila_rf_auto_control.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/__synthesis_is_complete__ rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/ila_rf_auto_control.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/simulate.do similarity index 56% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/simulate.do rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/simulate.do index afe501a0..d7cb13c7 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/questa/simulate.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/simulate.do @@ -1,7 +1,7 @@ onbreak {quit -f} onerror {quit -f} -vsim -t 1ps -lib xil_defaultlib fir_prbs7_invert_rep4_opt +vsim -t 1ps -lib xil_defaultlib ila_rf_auto_control_opt do {wave.do} @@ -9,7 +9,7 @@ view wave view structure view signals -do {fir_prbs7_invert_rep4.udo} +do {ila_rf_auto_control.udo} run -all diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/README.txt new file mode 100644 index 00000000..5278ed31 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:02:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_auto_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_auto_control.sh' script. + +./ila_rf_auto_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_auto_control.sh -noclean_files + +For more information on the script, please type './ila_rf_auto_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/compile.do new file mode 100644 index 00000000..43574dc0 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rf_auto_control/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rf_auto_control/hdl/verilog" \ +"../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/file_info.txt new file mode 100644 index 00000000..45c739e9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +ila_rf_auto_control.v,verilog,xil_defaultlib,../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/ila_rf_auto_control.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/ila_rf_auto_control.sh new file mode 100755 index 00000000..ef19e7f3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/ila_rf_auto_control.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_auto_control.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:02:01 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_auto_control.sh [-help] +# usage: ila_rf_auto_control.sh [-lib_map_path] +# usage: ila_rf_auto_control.sh [-noclean_files] +# usage: ila_rf_auto_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_auto_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rf_auto_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_auto_control.sh [-help]\n\ +Usage: ila_rf_auto_control.sh [-lib_map_path]\n\ +Usage: ila_rf_auto_control.sh [-reset_run]\n\ +Usage: ila_rf_auto_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/ila_rf_auto_control.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/ila_rf_auto_control.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/simulate.do new file mode 100644 index 00000000..819e698e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_rf_auto_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rf_auto_control xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_rf_auto_control.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/README.txt new file mode 100644 index 00000000..5278ed31 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:02:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_auto_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_auto_control.sh' script. + +./ila_rf_auto_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_auto_control.sh -noclean_files + +For more information on the script, please type './ila_rf_auto_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/file_info.txt new file mode 100644 index 00000000..b52083f1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/file_info.txt @@ -0,0 +1,2 @@ +ila_rf_auto_control.v,verilog,xil_defaultlib,../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/ila_rf_auto_control.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/ila_rf_auto_control.sh new file mode 100755 index 00000000..a806fdea --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/ila_rf_auto_control.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_auto_control.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:02:01 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_auto_control.sh [-help] +# usage: ila_rf_auto_control.sh [-lib_map_path] +# usage: ila_rf_auto_control.sh [-noclean_files] +# usage: ila_rf_auto_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_auto_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "ila_rf_auto_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_rf_auto_control/hdl/verilog" \ + "$ref_dir/../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.ila_rf_auto_control xil_defaultlib.glbl -o ila_rf_auto_control_simv +} + +# RUN_STEP: +simulate() +{ + ./ila_rf_auto_control_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key ila_rf_auto_control_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ila_rf_auto_control_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_auto_control.sh [-help]\n\ +Usage: ila_rf_auto_control.sh [-lib_map_path]\n\ +Usage: ila_rf_auto_control.sh [-reset_run]\n\ +Usage: ila_rf_auto_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/README.txt similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/README.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/README.txt index 4d50d279..2a411957 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_prbs7_invert_rep4/xcelium/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun May 07 11:00:01 CST 2023 +# Generated by export_simulation on Fri May 12 16:02:01 CST 2023 # ################################################################################ @@ -12,7 +12,7 @@ From the shell prompt in the current directory, issue the following command:- -./fir_prbs7_invert_rep4.sh +./ila_rf_auto_control.sh This command will launch the 'execute' function for the single-step flow. This function is called from the main 'run' function in the script file. @@ -25,16 +25,16 @@ current directory. The 'setup' function is also used for removing the simulator generated data in order to reset the current directory to the original state when export_simulation was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './fir_prbs7_invert_rep4.sh' script. +'-reset_run' switch to the './ila_rf_auto_control.sh' script. -./fir_prbs7_invert_rep4.sh -reset_run +./ila_rf_auto_control.sh -reset_run To keep the generated data from the previous run but regenerate the setup files and library directories, use the '-noclean_files' switch. -./fir_prbs7_invert_rep4.sh -noclean_files +./ila_rf_auto_control.sh -noclean_files -For more information on the script, please type './fir_prbs7_invert_rep4.sh -help'. +For more information on the script, please type './ila_rf_auto_control.sh -help'. 2. Additional design information files:- diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/file_info.txt new file mode 100644 index 00000000..45c739e9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +ila_rf_auto_control.v,verilog,xil_defaultlib,../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/ila_rf_auto_control.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/ila_rf_auto_control.sh new file mode 100755 index 00000000..b3ea7a11 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/ila_rf_auto_control.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_auto_control.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:02:01 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_auto_control.sh [-help] +# usage: ila_rf_auto_control.sh [-lib_map_path] +# usage: ila_rf_auto_control.sh [-noclean_files] +# usage: ila_rf_auto_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_auto_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "ila_rf_auto_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ila_rf_auto_control \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ila_rf_auto_control/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_auto_control.sh [-help]\n\ +Usage: ila_rf_auto_control.sh [-lib_map_path]\n\ +Usage: ila_rf_auto_control.sh [-reset_run]\n\ +Usage: ila_rf_auto_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/run.f new file mode 100644 index 00000000..68623894 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/README.txt new file mode 100644 index 00000000..5278ed31 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:02:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_auto_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_auto_control.sh' script. + +./ila_rf_auto_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_auto_control.sh -noclean_files + +For more information on the script, please type './ila_rf_auto_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/cmd.tcl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/file_info.txt new file mode 100644 index 00000000..b52083f1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/file_info.txt @@ -0,0 +1,2 @@ +ila_rf_auto_control.v,verilog,xil_defaultlib,../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v,incdir="../../../ip/ila_rf_auto_control/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/ila_rf_auto_control.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/ila_rf_auto_control.sh new file mode 100755 index 00000000..30562604 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/ila_rf_auto_control.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_auto_control.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:02:01 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_auto_control.sh [-help] +# usage: ila_rf_auto_control.sh [-lib_map_path] +# usage: ila_rf_auto_control.sh [-noclean_files] +# usage: ila_rf_auto_control.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "ila_rf_auto_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ila_rf_auto_control xil_defaultlib.ila_rf_auto_control xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim ila_rf_auto_control -key {Behavioral:sim_1:Functional:ila_rf_auto_control} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ila_rf_auto_control.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_auto_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_auto_control.sh [-help]\n\ +Usage: ila_rf_auto_control.sh [-lib_map_path]\n\ +Usage: ila_rf_auto_control.sh [-reset_run]\n\ +Usage: ila_rf_auto_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/vlog.prj b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/vlog.prj new file mode 100644 index 00000000..4892179c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rf_auto_control/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/ila_rf_auto_control/hdl/verilog" \ +"../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/README.txt new file mode 100644 index 00000000..34d28703 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:01:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/compile.do new file mode 100644 index 00000000..cec194d4 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/file_info.txt new file mode 100644 index 00000000..bceaf25a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/dds_32b_8b_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.sh similarity index 84% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/dds_32b_8b_comp.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.sh index 750d5d5d..aa28606b 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/activehdl/dds_32b_8b_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : dds_32b_8b_comp.sh +# Filename : ila_rx_data_cnt.sh # Simulator : Aldec Active-HDL Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 00:28:50 CST 2023 +# Generated by Vivado on Fri May 12 16:01:01 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: dds_32b_8b_comp.sh [-help] -# usage: dds_32b_8b_comp.sh [-lib_map_path] -# usage: dds_32b_8b_comp.sh [-noclean_files] -# usage: dds_32b_8b_comp.sh [-reset_run] +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'dds_32b_8b_comp.sh -help' for more information. +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "dds_32b_8b_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -66,7 +66,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi map_setup_file $2 @@ -121,7 +121,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi @@ -133,10 +133,10 @@ check_args() # Script usage usage() { - msg="Usage: dds_32b_8b_comp.sh [-help]\n\ -Usage: dds_32b_8b_comp.sh [-lib_map_path]\n\ -Usage: dds_32b_8b_comp.sh [-reset_run]\n\ -Usage: dds_32b_8b_comp.sh [-noclean_files]\n\n\ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/simulate.do new file mode 100644 index 00000000..068bbc78 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_rx_data_cnt -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_rx_data_cnt.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/README.txt new file mode 100644 index 00000000..d846abdc --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:01:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/file_info.txt new file mode 100644 index 00000000..bceaf25a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/dds_32b_8b_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/ila_rx_data_cnt.sh similarity index 82% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/dds_32b_8b_comp.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/ila_rx_data_cnt.sh index 5b8f0699..cf039434 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/ies/dds_32b_8b_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/ila_rx_data_cnt.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : dds_32b_8b_comp.sh +# Filename : ila_rx_data_cnt.sh # Simulator : Cadence Incisive Enterprise Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 00:28:50 CST 2023 +# Generated by Vivado on Fri May 12 16:01:01 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: dds_32b_8b_comp.sh [-help] -# usage: dds_32b_8b_comp.sh [-lib_map_path] -# usage: dds_32b_8b_comp.sh [-noclean_files] -# usage: dds_32b_8b_comp.sh [-reset_run] +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'dds_32b_8b_comp.sh -help' for more information. +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -48,13 +48,13 @@ ref_lib_dir="." irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" # Design libraries -design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 xbip_dsp48_wrapper_v3_0_4 xbip_dsp48_addsub_v3_0_6 xbip_dsp48_multadd_v3_0_6 dds_compiler_v6_0_18) +design_libs=(xil_defaultlib xpm) # Simulation root library directory sim_lib_dir="ies_lib" # Script info -echo -e "dds_32b_8b_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,10 +73,11 @@ execute() -reflib "$ref_lib_dir/secureip:secureip" \ -reflib "$ref_lib_dir/unimacro:unimacro" \ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.dds_32b_8b_comp \ + -top xil_defaultlib.ila_rx_data_cnt \ -f run.f \ -top glbl \ - glbl.v + glbl.v \ + +incdir+"../../../ip/ila_rx_data_cnt/hdl/verilog" } # STEP: setup @@ -85,7 +86,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 else ref_lib_dir=$2 @@ -144,7 +145,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi @@ -156,10 +157,10 @@ check_args() # Script usage usage() { - msg="Usage: dds_32b_8b_comp.sh [-help]\n\ -Usage: dds_32b_8b_comp.sh [-lib_map_path]\n\ -Usage: dds_32b_8b_comp.sh [-reset_run]\n\ -Usage: dds_32b_8b_comp.sh [-noclean_files]\n\n\ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/run.f new file mode 100644 index 00000000..2fc025f3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/README.txt new file mode 100644 index 00000000..34d28703 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:01:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/compile.do new file mode 100644 index 00000000..9fc0a8d5 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/file_info.txt new file mode 100644 index 00000000..0689f6df --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/file_info.txt @@ -0,0 +1,2 @@ +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/dds_32b_8b_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.sh similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/dds_32b_8b_comp.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.sh index 99994cdf..7532a742 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/modelsim/dds_32b_8b_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : dds_32b_8b_comp.sh +# Filename : ila_rx_data_cnt.sh # Simulator : Mentor Graphics ModelSim Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 00:28:50 CST 2023 +# Generated by Vivado on Fri May 12 16:01:01 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: dds_32b_8b_comp.sh [-help] -# usage: dds_32b_8b_comp.sh [-lib_map_path] -# usage: dds_32b_8b_comp.sh [-noclean_files] -# usage: dds_32b_8b_comp.sh [-reset_run] +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'dds_32b_8b_comp.sh -help' for more information. +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "dds_32b_8b_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -66,7 +66,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi copy_setup_file $2 @@ -136,7 +136,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi @@ -148,10 +148,10 @@ check_args() # Script usage usage() { - msg="Usage: dds_32b_8b_comp.sh [-help]\n\ -Usage: dds_32b_8b_comp.sh [-lib_map_path]\n\ -Usage: dds_32b_8b_comp.sh [-reset_run]\n\ -Usage: dds_32b_8b_comp.sh [-noclean_files]\n\n\ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/simulate.do new file mode 100644 index 00000000..17f1eccd --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {ila_rx_data_cnt.udo} + +run -all + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/README.txt new file mode 100644 index 00000000..34d28703 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:01:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/compile.do new file mode 100644 index 00000000..1cdeccee --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/elaborate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/elaborate.do new file mode 100644 index 00000000..7d20aec2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl -o ila_rx_data_cnt_opt diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/file_info.txt new file mode 100644 index 00000000..bceaf25a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/dds_32b_8b_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.sh similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/dds_32b_8b_comp.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.sh index 7fd43513..4d4df67d 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/questa/dds_32b_8b_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : dds_32b_8b_comp.sh +# Filename : ila_rx_data_cnt.sh # Simulator : Mentor Graphics Questa Advanced Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 00:28:50 CST 2023 +# Generated by Vivado on Fri May 12 16:01:01 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: dds_32b_8b_comp.sh [-help] -# usage: dds_32b_8b_comp.sh [-lib_map_path] -# usage: dds_32b_8b_comp.sh [-noclean_files] -# usage: dds_32b_8b_comp.sh [-reset_run] +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'dds_32b_8b_comp.sh -help' for more information. +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "dds_32b_8b_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,7 +73,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi copy_setup_file $2 @@ -143,7 +143,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi @@ -155,10 +155,10 @@ check_args() # Script usage usage() { - msg="Usage: dds_32b_8b_comp.sh [-help]\n\ -Usage: dds_32b_8b_comp.sh [-lib_map_path]\n\ -Usage: dds_32b_8b_comp.sh [-reset_run]\n\ -Usage: dds_32b_8b_comp.sh [-noclean_files]\n\n\ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/simulate.do new file mode 100644 index 00000000..11bbded3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib ila_rx_data_cnt_opt + +do {wave.do} + +view wave +view structure +view signals + +do {ila_rx_data_cnt.udo} + +run -all + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/README.txt new file mode 100644 index 00000000..34d28703 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:01:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/compile.do new file mode 100644 index 00000000..39317df9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/file_info.txt new file mode 100644 index 00000000..bceaf25a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/dds_32b_8b_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.sh similarity index 84% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/dds_32b_8b_comp.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.sh index a9e9024d..7bc0ab6e 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/riviera/dds_32b_8b_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : dds_32b_8b_comp.sh +# Filename : ila_rx_data_cnt.sh # Simulator : Aldec Riviera-PRO Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 00:28:50 CST 2023 +# Generated by Vivado on Fri May 12 16:01:01 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: dds_32b_8b_comp.sh [-help] -# usage: dds_32b_8b_comp.sh [-lib_map_path] -# usage: dds_32b_8b_comp.sh [-noclean_files] -# usage: dds_32b_8b_comp.sh [-reset_run] +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'dds_32b_8b_comp.sh -help' for more information. +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "dds_32b_8b_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -66,7 +66,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi map_setup_file $2 @@ -122,7 +122,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi @@ -134,10 +134,10 @@ check_args() # Script usage usage() { - msg="Usage: dds_32b_8b_comp.sh [-help]\n\ -Usage: dds_32b_8b_comp.sh [-lib_map_path]\n\ -Usage: dds_32b_8b_comp.sh [-reset_run]\n\ -Usage: dds_32b_8b_comp.sh [-noclean_files]\n\n\ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.udo b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/simulate.do new file mode 100644 index 00000000..068bbc78 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_rx_data_cnt -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_rx_data_cnt.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/wave.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/README.txt new file mode 100644 index 00000000..34d28703 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:01:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/file_info.txt new file mode 100644 index 00000000..0689f6df --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/file_info.txt @@ -0,0 +1,2 @@ +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/dds_32b_8b_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/ila_rx_data_cnt.sh similarity index 81% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/dds_32b_8b_comp.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/ila_rx_data_cnt.sh index bf9c870e..535222b2 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/vcs/dds_32b_8b_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/ila_rx_data_cnt.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : dds_32b_8b_comp.sh +# Filename : ila_rx_data_cnt.sh # Simulator : Synopsys Verilog Compiler Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 00:28:50 CST 2023 +# Generated by Vivado on Fri May 12 16:01:01 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: dds_32b_8b_comp.sh [-help] -# usage: dds_32b_8b_comp.sh [-lib_map_path] -# usage: dds_32b_8b_comp.sh [-noclean_files] -# usage: dds_32b_8b_comp.sh [-reset_run] +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'dds_32b_8b_comp.sh -help' for more information. +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib) sim_lib_dir="vcs_lib" # Script info -echo -e "dds_32b_8b_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -70,9 +70,9 @@ run() compile() { # Compile design files - vhdlan -work xil_defaultlib $vhdlan_opts \ - "$ref_dir/../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \ - 2>&1 | tee -a vhdlan.log + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_rx_data_cnt/hdl/verilog" \ + "$ref_dir/../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + 2>&1 | tee -a vlogan.log vlogan -work xil_defaultlib $vlogan_opts +v2k \ @@ -84,13 +84,13 @@ compile() # RUN_STEP: elaborate() { - vcs $vcs_elab_opts xil_defaultlib.dds_32b_8b_comp xil_defaultlib.glbl -o dds_32b_8b_comp_simv + vcs $vcs_elab_opts xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl -o ila_rx_data_cnt_simv } # RUN_STEP: simulate() { - ./dds_32b_8b_comp_simv $vcs_sim_opts -do simulate.do + ./ila_rx_data_cnt_simv $vcs_sim_opts -do simulate.do } # STEP: setup @@ -99,7 +99,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi create_lib_mappings $2 @@ -175,7 +175,7 @@ create_lib_dir() # Delete generated data from the previous run reset_run() { - files_to_remove=(ucli.key dds_32b_8b_comp_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc dds_32b_8b_comp_simv.daidir) + files_to_remove=(ucli.key ila_rx_data_cnt_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ila_rx_data_cnt_simv.daidir) for (( i=0; i<${#files_to_remove[*]}; i++ )); do file="${files_to_remove[i]}" if [[ -e $file ]]; then @@ -190,7 +190,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi @@ -202,10 +202,10 @@ check_args() # Script usage usage() { - msg="Usage: dds_32b_8b_comp.sh [-help]\n\ -Usage: dds_32b_8b_comp.sh [-lib_map_path]\n\ -Usage: dds_32b_8b_comp.sh [-reset_run]\n\ -Usage: dds_32b_8b_comp.sh [-noclean_files]\n\n\ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/README.txt new file mode 100644 index 00000000..d846abdc --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:01:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/file_info.txt new file mode 100644 index 00000000..bceaf25a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/dds_32b_8b_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/ila_rx_data_cnt.sh similarity index 82% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/dds_32b_8b_comp.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/ila_rx_data_cnt.sh index 2c551bf5..643da31a 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/dds_32b_8b_comp/xcelium/dds_32b_8b_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/ila_rx_data_cnt.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : dds_32b_8b_comp.sh +# Filename : ila_rx_data_cnt.sh # Simulator : Cadence Xcelium Parallel Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 00:28:50 CST 2023 +# Generated by Vivado on Fri May 12 16:01:01 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: dds_32b_8b_comp.sh [-help] -# usage: dds_32b_8b_comp.sh [-lib_map_path] -# usage: dds_32b_8b_comp.sh [-noclean_files] -# usage: dds_32b_8b_comp.sh [-reset_run] +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'dds_32b_8b_comp.sh -help' for more information. +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -48,13 +48,13 @@ ref_lib_dir="." xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" # Design libraries -design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 xbip_dsp48_wrapper_v3_0_4 xbip_dsp48_addsub_v3_0_6 xbip_dsp48_multadd_v3_0_6 dds_compiler_v6_0_18) +design_libs=(xil_defaultlib xpm) # Simulation root library directory sim_lib_dir="xcelium_lib" # Script info -echo -e "dds_32b_8b_comp.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,10 +73,11 @@ execute() -reflib "$ref_lib_dir/secureip:secureip" \ -reflib "$ref_lib_dir/unimacro:unimacro" \ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.dds_32b_8b_comp \ + -top xil_defaultlib.ila_rx_data_cnt \ -f run.f \ -top glbl \ - glbl.v + glbl.v \ + +incdir+"../../../ip/ila_rx_data_cnt/hdl/verilog" } # STEP: setup @@ -85,7 +86,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 else ref_lib_dir=$2 @@ -144,7 +145,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./dds_32b_8b_comp.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" exit 1 fi @@ -156,10 +157,10 @@ check_args() # Script usage usage() { - msg="Usage: dds_32b_8b_comp.sh [-help]\n\ -Usage: dds_32b_8b_comp.sh [-lib_map_path]\n\ -Usage: dds_32b_8b_comp.sh [-reset_run]\n\ -Usage: dds_32b_8b_comp.sh [-noclean_files]\n\n\ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/run.f new file mode 100644 index 00000000..fd1b270c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/README.txt new file mode 100644 index 00000000..34d28703 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Fri May 12 16:01:01 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/cmd.tcl b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/file_info.txt new file mode 100644 index 00000000..0689f6df --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/file_info.txt @@ -0,0 +1,2 @@ +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/glbl.v b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/ila_rx_data_cnt.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/ila_rx_data_cnt.sh new file mode 100755 index 00000000..28182648 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/ila_rx_data_cnt.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rx_data_cnt.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Fri May 12 16:01:01 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ila_rx_data_cnt xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim ila_rx_data_cnt -key {Behavioral:sim_1:Functional:ila_rx_data_cnt} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ila_rx_data_cnt.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/vlog.prj b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/vlog.prj new file mode 100644 index 00000000..23d83e79 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt index cdeba977..78fdd432 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 11:43:18 CST 2023 +# Generated by export_simulation on Fri May 12 16:05:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe index d58c706e..20ed79a7 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1076, -1088, -1100, -1112, -1124, -1136, -1148, -1160, -1172, -1184, -1196, -1208, -1220, -1232, -1244, -1256, -1268, -1280, -1292, -1304, -1316, -1328, -1340, -1352, -1364, -1376, -1388, -1400, -1412, -1424, -1436, -1448, -1460, -1472, -1484, -1496, -1508, -1520, -1532, -1544, -1556, -1568, -1580, -1592, -1604, -1616, -1628, -1640, -1652, -1664, -1676, -1688, -1700, -1712, -1724, -1736, -1748, -1760, -1772, -1784, -1796, -1808, -1820, -1832, -1844, -1856, -1868, -1880, -1892, -1904, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, 1916, -1928, -1940, -1952, -1964, -1976, -1988, -2000, -2012, -2024, -2036, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif index c796b340..4c2a27b1 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif @@ -1,81 +1,81 @@ -0000010000110100 -0000010001000000 -0000010001001100 -0000010001011000 -0000010001100100 -0000010001110000 -0000010001111100 -0000010010001000 -0000010010010100 -0000010010100000 -0000010010101100 -0000010010111000 -0000010011000100 -0000010011010000 -0000010011011100 -0000010011101000 -0000010011110100 -0000010100000000 -0000010100001100 -0000010100011000 -0000010100100100 -0000010100110000 -0000010100111100 -0000010101001000 -0000010101010100 -0000010101100000 -0000010101101100 -0000010101111000 -0000010110000100 -0000010110010000 -0000010110011100 -0000010110101000 -0000010110110100 -0000010111000000 -0000010111001100 -0000010111011000 -0000010111100100 -0000010111110000 -0000010111111100 -0000011000001000 -0000011000010100 -0000011000100000 -0000011000101100 -0000011000111000 -0000011001000100 -0000011001010000 -0000011001011100 -0000011001101000 -0000011001110100 -0000011010000000 -0000011010001100 -0000011010011000 -0000011010100100 -0000011010110000 -0000011010111100 -0000011011001000 -0000011011010100 -0000011011100000 -0000011011101100 -0000011011111000 -0000011100000100 -0000011100010000 -0000011100011100 -0000011100101000 -0000011100110100 -0000011101000000 -0000011101001100 -0000011101011000 -0000011101100100 -0000011101110000 +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 0000011101111100 -0000011110001000 -0000011110010100 -0000011110100000 -0000011110101100 -0000011110111000 -0000011111000100 -0000011111010000 -0000011111011100 -0000011111101000 -0000011111110100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh index 83e944fa..76f0c0f7 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 11:43:18 CST 2023 +# Generated by Vivado on Fri May 12 16:05:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt index 6f809da1..53fd7690 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 11:43:18 CST 2023 +# Generated by export_simulation on Fri May 12 16:05:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe index d58c706e..20ed79a7 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1076, -1088, -1100, -1112, -1124, -1136, -1148, -1160, -1172, -1184, -1196, -1208, -1220, -1232, -1244, -1256, -1268, -1280, -1292, -1304, -1316, -1328, -1340, -1352, -1364, -1376, -1388, -1400, -1412, -1424, -1436, -1448, -1460, -1472, -1484, -1496, -1508, -1520, -1532, -1544, -1556, -1568, -1580, -1592, -1604, -1616, -1628, -1640, -1652, -1664, -1676, -1688, -1700, -1712, -1724, -1736, -1748, -1760, -1772, -1784, -1796, -1808, -1820, -1832, -1844, -1856, -1868, -1880, -1892, -1904, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, 1916, -1928, -1940, -1952, -1964, -1976, -1988, -2000, -2012, -2024, -2036, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif index c796b340..4c2a27b1 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif @@ -1,81 +1,81 @@ -0000010000110100 -0000010001000000 -0000010001001100 -0000010001011000 -0000010001100100 -0000010001110000 -0000010001111100 -0000010010001000 -0000010010010100 -0000010010100000 -0000010010101100 -0000010010111000 -0000010011000100 -0000010011010000 -0000010011011100 -0000010011101000 -0000010011110100 -0000010100000000 -0000010100001100 -0000010100011000 -0000010100100100 -0000010100110000 -0000010100111100 -0000010101001000 -0000010101010100 -0000010101100000 -0000010101101100 -0000010101111000 -0000010110000100 -0000010110010000 -0000010110011100 -0000010110101000 -0000010110110100 -0000010111000000 -0000010111001100 -0000010111011000 -0000010111100100 -0000010111110000 -0000010111111100 -0000011000001000 -0000011000010100 -0000011000100000 -0000011000101100 -0000011000111000 -0000011001000100 -0000011001010000 -0000011001011100 -0000011001101000 -0000011001110100 -0000011010000000 -0000011010001100 -0000011010011000 -0000011010100100 -0000011010110000 -0000011010111100 -0000011011001000 -0000011011010100 -0000011011100000 -0000011011101100 -0000011011111000 -0000011100000100 -0000011100010000 -0000011100011100 -0000011100101000 -0000011100110100 -0000011101000000 -0000011101001100 -0000011101011000 -0000011101100100 -0000011101110000 +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 0000011101111100 -0000011110001000 -0000011110010100 -0000011110100000 -0000011110101100 -0000011110111000 -0000011111000100 -0000011111010000 -0000011111011100 -0000011111101000 -0000011111110100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh index 7b76cd2f..f2554072 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 11:43:18 CST 2023 +# Generated by Vivado on Fri May 12 16:05:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt index cdeba977..78fdd432 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 11:43:18 CST 2023 +# Generated by export_simulation on Fri May 12 16:05:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe index d58c706e..20ed79a7 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1076, -1088, -1100, -1112, -1124, -1136, -1148, -1160, -1172, -1184, -1196, -1208, -1220, -1232, -1244, -1256, -1268, -1280, -1292, -1304, -1316, -1328, -1340, -1352, -1364, -1376, -1388, -1400, -1412, -1424, -1436, -1448, -1460, -1472, -1484, -1496, -1508, -1520, -1532, -1544, -1556, -1568, -1580, -1592, -1604, -1616, -1628, -1640, -1652, -1664, -1676, -1688, -1700, -1712, -1724, -1736, -1748, -1760, -1772, -1784, -1796, -1808, -1820, -1832, -1844, -1856, -1868, -1880, -1892, -1904, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, 1916, -1928, -1940, -1952, -1964, -1976, -1988, -2000, -2012, -2024, -2036, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif index c796b340..4c2a27b1 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif @@ -1,81 +1,81 @@ -0000010000110100 -0000010001000000 -0000010001001100 -0000010001011000 -0000010001100100 -0000010001110000 -0000010001111100 -0000010010001000 -0000010010010100 -0000010010100000 -0000010010101100 -0000010010111000 -0000010011000100 -0000010011010000 -0000010011011100 -0000010011101000 -0000010011110100 -0000010100000000 -0000010100001100 -0000010100011000 -0000010100100100 -0000010100110000 -0000010100111100 -0000010101001000 -0000010101010100 -0000010101100000 -0000010101101100 -0000010101111000 -0000010110000100 -0000010110010000 -0000010110011100 -0000010110101000 -0000010110110100 -0000010111000000 -0000010111001100 -0000010111011000 -0000010111100100 -0000010111110000 -0000010111111100 -0000011000001000 -0000011000010100 -0000011000100000 -0000011000101100 -0000011000111000 -0000011001000100 -0000011001010000 -0000011001011100 -0000011001101000 -0000011001110100 -0000011010000000 -0000011010001100 -0000011010011000 -0000011010100100 -0000011010110000 -0000011010111100 -0000011011001000 -0000011011010100 -0000011011100000 -0000011011101100 -0000011011111000 -0000011100000100 -0000011100010000 -0000011100011100 -0000011100101000 -0000011100110100 -0000011101000000 -0000011101001100 -0000011101011000 -0000011101100100 -0000011101110000 +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 0000011101111100 -0000011110001000 -0000011110010100 -0000011110100000 -0000011110101100 -0000011110111000 -0000011111000100 -0000011111010000 -0000011111011100 -0000011111101000 -0000011111110100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh index 68c75636..eae46c5b 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 11:43:18 CST 2023 +# Generated by Vivado on Fri May 12 16:05:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt index cdeba977..78fdd432 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 11:43:18 CST 2023 +# Generated by export_simulation on Fri May 12 16:05:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe index d58c706e..20ed79a7 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1076, -1088, -1100, -1112, -1124, -1136, -1148, -1160, -1172, -1184, -1196, -1208, -1220, -1232, -1244, -1256, -1268, -1280, -1292, -1304, -1316, -1328, -1340, -1352, -1364, -1376, -1388, -1400, -1412, -1424, -1436, -1448, -1460, -1472, -1484, -1496, -1508, -1520, -1532, -1544, -1556, -1568, -1580, -1592, -1604, -1616, -1628, -1640, -1652, -1664, -1676, -1688, -1700, -1712, -1724, -1736, -1748, -1760, -1772, -1784, -1796, -1808, -1820, -1832, -1844, -1856, -1868, -1880, -1892, -1904, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, 1916, -1928, -1940, -1952, -1964, -1976, -1988, -2000, -2012, -2024, -2036, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif index c796b340..4c2a27b1 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif @@ -1,81 +1,81 @@ -0000010000110100 -0000010001000000 -0000010001001100 -0000010001011000 -0000010001100100 -0000010001110000 -0000010001111100 -0000010010001000 -0000010010010100 -0000010010100000 -0000010010101100 -0000010010111000 -0000010011000100 -0000010011010000 -0000010011011100 -0000010011101000 -0000010011110100 -0000010100000000 -0000010100001100 -0000010100011000 -0000010100100100 -0000010100110000 -0000010100111100 -0000010101001000 -0000010101010100 -0000010101100000 -0000010101101100 -0000010101111000 -0000010110000100 -0000010110010000 -0000010110011100 -0000010110101000 -0000010110110100 -0000010111000000 -0000010111001100 -0000010111011000 -0000010111100100 -0000010111110000 -0000010111111100 -0000011000001000 -0000011000010100 -0000011000100000 -0000011000101100 -0000011000111000 -0000011001000100 -0000011001010000 -0000011001011100 -0000011001101000 -0000011001110100 -0000011010000000 -0000011010001100 -0000011010011000 -0000011010100100 -0000011010110000 -0000011010111100 -0000011011001000 -0000011011010100 -0000011011100000 -0000011011101100 -0000011011111000 -0000011100000100 -0000011100010000 -0000011100011100 -0000011100101000 -0000011100110100 -0000011101000000 -0000011101001100 -0000011101011000 -0000011101100100 -0000011101110000 +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 0000011101111100 -0000011110001000 -0000011110010100 -0000011110100000 -0000011110101100 -0000011110111000 -0000011111000100 -0000011111010000 -0000011111011100 -0000011111101000 -0000011111110100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh index 93475c9d..e4c72607 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 11:43:18 CST 2023 +# Generated by Vivado on Fri May 12 16:05:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt index cdeba977..78fdd432 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 11:43:18 CST 2023 +# Generated by export_simulation on Fri May 12 16:05:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe index d58c706e..20ed79a7 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1076, -1088, -1100, -1112, -1124, -1136, -1148, -1160, -1172, -1184, -1196, -1208, -1220, -1232, -1244, -1256, -1268, -1280, -1292, -1304, -1316, -1328, -1340, -1352, -1364, -1376, -1388, -1400, -1412, -1424, -1436, -1448, -1460, -1472, -1484, -1496, -1508, -1520, -1532, -1544, -1556, -1568, -1580, -1592, -1604, -1616, -1628, -1640, -1652, -1664, -1676, -1688, -1700, -1712, -1724, -1736, -1748, -1760, -1772, -1784, -1796, -1808, -1820, -1832, -1844, -1856, -1868, -1880, -1892, -1904, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, 1916, -1928, -1940, -1952, -1964, -1976, -1988, -2000, -2012, -2024, -2036, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif index c796b340..4c2a27b1 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif @@ -1,81 +1,81 @@ -0000010000110100 -0000010001000000 -0000010001001100 -0000010001011000 -0000010001100100 -0000010001110000 -0000010001111100 -0000010010001000 -0000010010010100 -0000010010100000 -0000010010101100 -0000010010111000 -0000010011000100 -0000010011010000 -0000010011011100 -0000010011101000 -0000010011110100 -0000010100000000 -0000010100001100 -0000010100011000 -0000010100100100 -0000010100110000 -0000010100111100 -0000010101001000 -0000010101010100 -0000010101100000 -0000010101101100 -0000010101111000 -0000010110000100 -0000010110010000 -0000010110011100 -0000010110101000 -0000010110110100 -0000010111000000 -0000010111001100 -0000010111011000 -0000010111100100 -0000010111110000 -0000010111111100 -0000011000001000 -0000011000010100 -0000011000100000 -0000011000101100 -0000011000111000 -0000011001000100 -0000011001010000 -0000011001011100 -0000011001101000 -0000011001110100 -0000011010000000 -0000011010001100 -0000011010011000 -0000011010100100 -0000011010110000 -0000011010111100 -0000011011001000 -0000011011010100 -0000011011100000 -0000011011101100 -0000011011111000 -0000011100000100 -0000011100010000 -0000011100011100 -0000011100101000 -0000011100110100 -0000011101000000 -0000011101001100 -0000011101011000 -0000011101100100 -0000011101110000 +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 0000011101111100 -0000011110001000 -0000011110010100 -0000011110100000 -0000011110101100 -0000011110111000 -0000011111000100 -0000011111010000 -0000011111011100 -0000011111101000 -0000011111110100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh index 12fb3789..f00b81fb 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 11:43:18 CST 2023 +# Generated by Vivado on Fri May 12 16:05:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt index cdeba977..78fdd432 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 11:43:18 CST 2023 +# Generated by export_simulation on Fri May 12 16:05:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe index d58c706e..20ed79a7 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1076, -1088, -1100, -1112, -1124, -1136, -1148, -1160, -1172, -1184, -1196, -1208, -1220, -1232, -1244, -1256, -1268, -1280, -1292, -1304, -1316, -1328, -1340, -1352, -1364, -1376, -1388, -1400, -1412, -1424, -1436, -1448, -1460, -1472, -1484, -1496, -1508, -1520, -1532, -1544, -1556, -1568, -1580, -1592, -1604, -1616, -1628, -1640, -1652, -1664, -1676, -1688, -1700, -1712, -1724, -1736, -1748, -1760, -1772, -1784, -1796, -1808, -1820, -1832, -1844, -1856, -1868, -1880, -1892, -1904, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, 1916, -1928, -1940, -1952, -1964, -1976, -1988, -2000, -2012, -2024, -2036, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif index c796b340..4c2a27b1 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif @@ -1,81 +1,81 @@ -0000010000110100 -0000010001000000 -0000010001001100 -0000010001011000 -0000010001100100 -0000010001110000 -0000010001111100 -0000010010001000 -0000010010010100 -0000010010100000 -0000010010101100 -0000010010111000 -0000010011000100 -0000010011010000 -0000010011011100 -0000010011101000 -0000010011110100 -0000010100000000 -0000010100001100 -0000010100011000 -0000010100100100 -0000010100110000 -0000010100111100 -0000010101001000 -0000010101010100 -0000010101100000 -0000010101101100 -0000010101111000 -0000010110000100 -0000010110010000 -0000010110011100 -0000010110101000 -0000010110110100 -0000010111000000 -0000010111001100 -0000010111011000 -0000010111100100 -0000010111110000 -0000010111111100 -0000011000001000 -0000011000010100 -0000011000100000 -0000011000101100 -0000011000111000 -0000011001000100 -0000011001010000 -0000011001011100 -0000011001101000 -0000011001110100 -0000011010000000 -0000011010001100 -0000011010011000 -0000011010100100 -0000011010110000 -0000011010111100 -0000011011001000 -0000011011010100 -0000011011100000 -0000011011101100 -0000011011111000 -0000011100000100 -0000011100010000 -0000011100011100 -0000011100101000 -0000011100110100 -0000011101000000 -0000011101001100 -0000011101011000 -0000011101100100 -0000011101110000 +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 0000011101111100 -0000011110001000 -0000011110010100 -0000011110100000 -0000011110101100 -0000011110111000 -0000011111000100 -0000011111010000 -0000011111011100 -0000011111101000 -0000011111110100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh index b10a00b4..32536444 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 11:43:18 CST 2023 +# Generated by Vivado on Fri May 12 16:05:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt index 6f809da1..53fd7690 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 11:43:18 CST 2023 +# Generated by export_simulation on Fri May 12 16:05:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe index d58c706e..20ed79a7 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1076, -1088, -1100, -1112, -1124, -1136, -1148, -1160, -1172, -1184, -1196, -1208, -1220, -1232, -1244, -1256, -1268, -1280, -1292, -1304, -1316, -1328, -1340, -1352, -1364, -1376, -1388, -1400, -1412, -1424, -1436, -1448, -1460, -1472, -1484, -1496, -1508, -1520, -1532, -1544, -1556, -1568, -1580, -1592, -1604, -1616, -1628, -1640, -1652, -1664, -1676, -1688, -1700, -1712, -1724, -1736, -1748, -1760, -1772, -1784, -1796, -1808, -1820, -1832, -1844, -1856, -1868, -1880, -1892, -1904, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, 1916, -1928, -1940, -1952, -1964, -1976, -1988, -2000, -2012, -2024, -2036, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif index c796b340..4c2a27b1 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif @@ -1,81 +1,81 @@ -0000010000110100 -0000010001000000 -0000010001001100 -0000010001011000 -0000010001100100 -0000010001110000 -0000010001111100 -0000010010001000 -0000010010010100 -0000010010100000 -0000010010101100 -0000010010111000 -0000010011000100 -0000010011010000 -0000010011011100 -0000010011101000 -0000010011110100 -0000010100000000 -0000010100001100 -0000010100011000 -0000010100100100 -0000010100110000 -0000010100111100 -0000010101001000 -0000010101010100 -0000010101100000 -0000010101101100 -0000010101111000 -0000010110000100 -0000010110010000 -0000010110011100 -0000010110101000 -0000010110110100 -0000010111000000 -0000010111001100 -0000010111011000 -0000010111100100 -0000010111110000 -0000010111111100 -0000011000001000 -0000011000010100 -0000011000100000 -0000011000101100 -0000011000111000 -0000011001000100 -0000011001010000 -0000011001011100 -0000011001101000 -0000011001110100 -0000011010000000 -0000011010001100 -0000011010011000 -0000011010100100 -0000011010110000 -0000011010111100 -0000011011001000 -0000011011010100 -0000011011100000 -0000011011101100 -0000011011111000 -0000011100000100 -0000011100010000 -0000011100011100 -0000011100101000 -0000011100110100 -0000011101000000 -0000011101001100 -0000011101011000 -0000011101100100 -0000011101110000 +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 0000011101111100 -0000011110001000 -0000011110010100 -0000011110100000 -0000011110101100 -0000011110111000 -0000011111000100 -0000011111010000 -0000011111011100 -0000011111101000 -0000011111110100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh index 57249540..2ac8a13a 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 11:43:18 CST 2023 +# Generated by Vivado on Fri May 12 16:05:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt index cdeba977..78fdd432 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 11:43:18 CST 2023 +# Generated by export_simulation on Fri May 12 16:05:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe index d58c706e..20ed79a7 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1076, -1088, -1100, -1112, -1124, -1136, -1148, -1160, -1172, -1184, -1196, -1208, -1220, -1232, -1244, -1256, -1268, -1280, -1292, -1304, -1316, -1328, -1340, -1352, -1364, -1376, -1388, -1400, -1412, -1424, -1436, -1448, -1460, -1472, -1484, -1496, -1508, -1520, -1532, -1544, -1556, -1568, -1580, -1592, -1604, -1616, -1628, -1640, -1652, -1664, -1676, -1688, -1700, -1712, -1724, -1736, -1748, -1760, -1772, -1784, -1796, -1808, -1820, -1832, -1844, -1856, -1868, -1880, -1892, -1904, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, 1916, -1928, -1940, -1952, -1964, -1976, -1988, -2000, -2012, -2024, -2036, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif index c796b340..4c2a27b1 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif @@ -1,81 +1,81 @@ -0000010000110100 -0000010001000000 -0000010001001100 -0000010001011000 -0000010001100100 -0000010001110000 -0000010001111100 -0000010010001000 -0000010010010100 -0000010010100000 -0000010010101100 -0000010010111000 -0000010011000100 -0000010011010000 -0000010011011100 -0000010011101000 -0000010011110100 -0000010100000000 -0000010100001100 -0000010100011000 -0000010100100100 -0000010100110000 -0000010100111100 -0000010101001000 -0000010101010100 -0000010101100000 -0000010101101100 -0000010101111000 -0000010110000100 -0000010110010000 -0000010110011100 -0000010110101000 -0000010110110100 -0000010111000000 -0000010111001100 -0000010111011000 -0000010111100100 -0000010111110000 -0000010111111100 -0000011000001000 -0000011000010100 -0000011000100000 -0000011000101100 -0000011000111000 -0000011001000100 -0000011001010000 -0000011001011100 -0000011001101000 -0000011001110100 -0000011010000000 -0000011010001100 -0000011010011000 -0000011010100100 -0000011010110000 -0000011010111100 -0000011011001000 -0000011011010100 -0000011011100000 -0000011011101100 -0000011011111000 -0000011100000100 -0000011100010000 -0000011100011100 -0000011100101000 -0000011100110100 -0000011101000000 -0000011101001100 -0000011101011000 -0000011101100100 -0000011101110000 +0000100001001100 +0000100000111111 +0000100000110010 +0000100000100101 +0000100000011000 +0000100000001011 +0000011111111110 +0000011111110001 +0000011111100100 +0000011111010111 +0000011111001010 +0000011110111101 +0000011110110000 +0000011110100011 +0000011110010110 +0000011110001001 0000011101111100 -0000011110001000 -0000011110010100 -0000011110100000 -0000011110101100 -0000011110111000 -0000011111000100 -0000011111010000 -0000011111011100 -0000011111101000 -0000011111110100 +0000011101101111 +0000011101100010 +0000011101010101 +0000011101001000 +0000011100111011 +0000011100101110 +0000011100100001 +0000011100010100 +0000011100000111 +0000011011111010 +0000011011101101 +0000011011100000 +0000011011010011 +0000011011000110 +0000011010111001 +0000011010101100 +0000011010011111 +0000011010010010 +0000011010000101 +0000011001111000 +0000011001101011 +0000011001011110 +0000011001010001 +0000011001000100 +0000011000110111 +0000011000101010 +0000011000011101 +0000011000010000 +0000011000000011 +0000010111110110 +0000010111101001 +0000010111011100 +0000010111001111 +0000010111000010 +0000010110110101 +0000010110101000 +0000010110011011 +0000010110001110 +0000010110000001 +0000010101110100 +0000010101100111 +0000010101011010 +0000010101001101 +0000010101000000 +0000010100110011 +0000010100100110 +0000010100011001 +0000010100001100 +0000010011111111 +0000010011110010 +0000010011100101 +0000010011011000 +0000010011001011 +0000010010111110 +0000010010110001 +0000010010100100 +0000010010010111 +0000010010001010 +0000010001111101 +0000010001110000 +0000010001100011 +0000010001010110 +0000010001001001 +0000010000111100 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh index b089e8f1..8dde2fec 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 11:43:18 CST 2023 +# Generated by Vivado on Fri May 12 16:05:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt index c8840182..3f212327 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun May 07 16:51:16 CST 2023 +# Generated by export_simulation on Fri May 12 16:01:41 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/compile.do index bf15a6f3..ec00d4c4 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/compile.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/compile.do @@ -2,13 +2,21 @@ vlib work vlib activehdl vlib activehdl/xil_defaultlib +vlib activehdl/xpm vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ "../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ - vlog -work xil_defaultlib \ "glbl.v" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/file_info.txt index 5dc177b4..3b96929b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/file_info.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/file_info.txt @@ -1,2 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/simulate.do index 48a31298..dcde758a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/simulate.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/simulate.do @@ -1,7 +1,7 @@ onbreak {quit -force} onerror {quit -force} -asim -t 1ps +access +r +m+vio_freq_comp -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_freq_comp xil_defaultlib.glbl +asim -t 1ps +access +r +m+vio_freq_comp -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_freq_comp xil_defaultlib.glbl do {wave.do} diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh index 6e1e1632..db49af82 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 16:51:16 CST 2023 +# Generated by Vivado on Fri May 12 16:01:41 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt index af1b8f25..1be8fd3d 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun May 07 16:51:16 CST 2023 +# Generated by export_simulation on Fri May 12 16:01:41 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/file_info.txt index 5dc177b4..3b96929b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/file_info.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/file_info.txt @@ -1,2 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/run.f index 4bb8821d..8ac393b6 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/run.f +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/run.f @@ -1,3 +1,10 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib -makelib ies_lib/xil_defaultlib \ "../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ -endlib diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh index 62b76150..2650c545 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 16:51:16 CST 2023 +# Generated by Vivado on Fri May 12 16:01:41 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -48,7 +48,7 @@ ref_lib_dir="." irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" # Design libraries -design_libs=(xil_defaultlib) +design_libs=(xil_defaultlib xpm) # Simulation root library directory sim_lib_dir="ies_lib" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt index c8840182..3f212327 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun May 07 16:51:16 CST 2023 +# Generated by export_simulation on Fri May 12 16:01:41 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh index 3de4aa68..8754fe27 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 16:51:16 CST 2023 +# Generated by Vivado on Fri May 12 16:01:41 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt index c8840182..3f212327 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun May 07 16:51:16 CST 2023 +# Generated by export_simulation on Fri May 12 16:01:41 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/compile.do index e1e3b204..4abf33e3 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/compile.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/compile.do @@ -2,13 +2,21 @@ vlib questa_lib/work vlib questa_lib/msim vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ "../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ - vlog -work xil_defaultlib \ "glbl.v" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/elaborate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/elaborate.do index 587637ef..ff83f085 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/elaborate.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/elaborate.do @@ -1 +1 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_freq_comp xil_defaultlib.glbl -o vio_freq_comp_opt +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_freq_comp xil_defaultlib.glbl -o vio_freq_comp_opt diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/file_info.txt index 5dc177b4..3b96929b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/file_info.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/file_info.txt @@ -1,2 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh index 2cdc1d1b..abd2e3f2 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 16:51:16 CST 2023 +# Generated by Vivado on Fri May 12 16:01:41 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt index c8840182..3f212327 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun May 07 16:51:16 CST 2023 +# Generated by export_simulation on Fri May 12 16:01:41 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/compile.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/compile.do index f2965a5f..33a3f439 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/compile.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/compile.do @@ -2,13 +2,21 @@ vlib work vlib riviera vlib riviera/xil_defaultlib +vlib riviera/xpm vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_freq_comp/hdl/verilog" "+incdir+../../../ip/vio_freq_comp/hdl" \ "../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ - vlog -work xil_defaultlib \ "glbl.v" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/file_info.txt index 5dc177b4..3b96929b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/file_info.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/file_info.txt @@ -1,2 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/simulate.do b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/simulate.do index 48a31298..dcde758a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/simulate.do +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/simulate.do @@ -1,7 +1,7 @@ onbreak {quit -force} onerror {quit -force} -asim -t 1ps +access +r +m+vio_freq_comp -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_freq_comp xil_defaultlib.glbl +asim -t 1ps +access +r +m+vio_freq_comp -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_freq_comp xil_defaultlib.glbl do {wave.do} diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh index beee1861..65370b60 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 16:51:16 CST 2023 +# Generated by Vivado on Fri May 12 16:01:41 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt index c8840182..3f212327 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun May 07 16:51:16 CST 2023 +# Generated by export_simulation on Fri May 12 16:01:41 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh index 9b1de7d3..8e08ee7f 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 16:51:16 CST 2023 +# Generated by Vivado on Fri May 12 16:01:41 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt index af1b8f25..1be8fd3d 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun May 07 16:51:16 CST 2023 +# Generated by export_simulation on Fri May 12 16:01:41 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/file_info.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/file_info.txt index 5dc177b4..3b96929b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/file_info.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/file_info.txt @@ -1,2 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" vio_freq_comp.v,verilog,xil_defaultlib,../../../ip/vio_freq_comp/sim/vio_freq_comp.v,incdir="../../../ip/vio_freq_comp/hdl/verilog"incdir="../../../ip/vio_freq_comp/hdl" glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/run.f b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/run.f index 595c673f..33886eca 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/run.f +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/run.f @@ -1,3 +1,10 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib -makelib xcelium_lib/xil_defaultlib \ "../../../ip/vio_freq_comp/sim/vio_freq_comp.v" \ -endlib diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh index 11293522..78d02629 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 16:51:16 CST 2023 +# Generated by Vivado on Fri May 12 16:01:41 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -48,7 +48,7 @@ ref_lib_dir="." xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" # Design libraries -design_libs=(xil_defaultlib) +design_libs=(xil_defaultlib xpm) # Simulation root library directory sim_lib_dir="xcelium_lib" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt index c8840182..3f212327 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun May 07 16:51:16 CST 2023 +# Generated by export_simulation on Fri May 12 16:01:41 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh index 12bf4a7e..cc08de10 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun May 07 16:51:16 CST 2023 +# Generated by Vivado on Fri May 12 16:01:41 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt index 9dc3348a..00e21f02 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 10:18:28 CST 2023 +# Generated by export_simulation on Fri May 12 15:58:50 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh index 4827acf2..45a2079f 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 10:18:28 CST 2023 +# Generated by Vivado on Fri May 12 15:58:50 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt index 2a0bae62..a4a5c50a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 10:18:28 CST 2023 +# Generated by export_simulation on Fri May 12 15:58:50 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh index 8c58fdd2..1c72accc 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 10:18:28 CST 2023 +# Generated by Vivado on Fri May 12 15:58:50 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt index 9dc3348a..00e21f02 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 10:18:28 CST 2023 +# Generated by export_simulation on Fri May 12 15:58:50 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh index 687d7188..5005df66 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 10:18:28 CST 2023 +# Generated by Vivado on Fri May 12 15:58:50 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt index 9dc3348a..00e21f02 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 10:18:28 CST 2023 +# Generated by export_simulation on Fri May 12 15:58:50 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh index 7d505038..45e80b6c 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 10:18:28 CST 2023 +# Generated by Vivado on Fri May 12 15:58:50 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt index 9dc3348a..00e21f02 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 10:18:28 CST 2023 +# Generated by export_simulation on Fri May 12 15:58:50 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh index 7d741699..59d4f9c2 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 10:18:28 CST 2023 +# Generated by Vivado on Fri May 12 15:58:50 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt index 9dc3348a..00e21f02 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 10:18:28 CST 2023 +# Generated by export_simulation on Fri May 12 15:58:50 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh index 698443f1..57758305 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 10:18:28 CST 2023 +# Generated by Vivado on Fri May 12 15:58:50 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt index 2a0bae62..a4a5c50a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 10:18:28 CST 2023 +# Generated by export_simulation on Fri May 12 15:58:50 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh index c954fdf3..35a746fd 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 10:18:28 CST 2023 +# Generated by Vivado on Fri May 12 15:58:50 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt index 9dc3348a..00e21f02 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 10:18:28 CST 2023 +# Generated by export_simulation on Fri May 12 15:58:50 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh index f4d91fca..f0edf0ca 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 10:18:28 CST 2023 +# Generated by Vivado on Fri May 12 15:58:50 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/1db6be14a58c55bc.xci b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/1db6be14a58c55bc.xci new file mode 100644 index 00000000..7f90443f --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/1db6be14a58c55bc.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 1db6be14a58c55bc + 0 + + + vio_rfcontrl + + + 100000000 + 0 + 1 + 2 + 21 + 16 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 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sha256:92ea35e93e4094d3d1b2e0233c1e533e6a4f8b8f0385ae08847b968c34139850 +size 251125 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_sim_netlist.v new file mode 100755 index 00000000..3e215d76 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c1d6ca184be2ed14ffbd63bba3f5d8ce74dca4e54cbcd756c55019bf9e11d26e +size 534816 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_sim_netlist.vhdl new file mode 100755 index 00000000..6110aaa4 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7ce1ef08007a3fcaceb1d6309c74566c84847b01ae788f5e60c91a96aa7ce192 +size 926156 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_stub.v new file mode 100755 index 00000000..d9514e79 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_stub.v @@ -0,0 +1,46 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 15:59:08 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.v +// Design : vio_rfcontrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_out0, + probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, + probe_out9, probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, + probe_out16, probe_out17, probe_out18, probe_out19, probe_out20) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]" */; + input clk; + input [15:0]probe_in0; + input [0:0]probe_in1; + output [0:0]probe_out0; + output [0:0]probe_out1; + output [15:0]probe_out2; + output [7:0]probe_out3; + output [3:0]probe_out4; + output [3:0]probe_out5; + output [3:0]probe_out6; + output [3:0]probe_out7; + output [7:0]probe_out8; + output [7:0]probe_out9; + output [15:0]probe_out10; + output [15:0]probe_out11; + output [15:0]probe_out12; + output [0:0]probe_out13; + output [0:0]probe_out14; + output [0:0]probe_out15; + output [0:0]probe_out16; + output [31:0]probe_out17; + output [31:0]probe_out18; + output [31:0]probe_out19; + output [31:0]probe_out20; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_stub.vhdl new file mode 100755 index 00000000..327c7c96 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1db6be14a58c55bc/vio_rfcontrl_stub.vhdl @@ -0,0 +1,53 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 15:59:09 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.vhdl +-- Design : vio_rfcontrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out17 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out18 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out19 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out20 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/550f19e2bcab89f4.xci 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VERILOG + + -2 + + + TRUE + TRUE + 550f19e2bcab89f4 + 48c58d29 + 142 + IP_Unknown + 9 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp.dcp new file mode 100644 index 00000000..32aea001 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:40bd547ade1c4e2006cc804e696c4bb05530a850d678eb2130a0056ea63462c1 +size 4755382 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_sim_netlist.v new file mode 100755 index 00000000..983b0af4 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8f8c10cec019d97e62e95eddfbaae58fa4b050f3ee5cabb8b2d19d0627be6d20 +size 12214368 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_sim_netlist.vhdl new file mode 100755 index 00000000..5d3cf786 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3326dee37d85e1a274cede49688902ecd22fd33397844e1a24d593d354d83588 +size 15487405 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_stub.v new file mode 100755 index 00000000..d4950c61 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_stub.v @@ -0,0 +1,43 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:05:59 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.v +// Design : ila_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, + probe18, probe19, probe20) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[10:0],probe10[10:0],probe11[10:0],probe12[10:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[31:0],probe20[11:0]" */; + input clk; + input [0:0]probe0; + input [17:0]probe1; + input [17:0]probe2; + input [17:0]probe3; + input [17:0]probe4; + input [17:0]probe5; + input [17:0]probe6; + input [17:0]probe7; + input [17:0]probe8; + input [10:0]probe9; + input [10:0]probe10; + input [10:0]probe11; + input [10:0]probe12; + input [0:0]probe13; + input [2:0]probe14; + input [11:0]probe15; + input [11:0]probe16; + input [17:0]probe17; + input [17:0]probe18; + input [31:0]probe19; + input [11:0]probe20; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_stub.vhdl new file mode 100755 index 00000000..83e9e5d3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/550f19e2bcab89f4/ila_freq_comp_stub.vhdl @@ -0,0 +1,51 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:05:59 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_freq_comp_stub.vhdl +-- Design : ila_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe12 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe13 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe14 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + probe15 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe16 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe17 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe18 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe19 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe20 : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[10:0],probe10[10:0],probe11[10:0],probe12[10:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[31:0],probe20[11:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/56186d833b788b44.xci b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/56186d833b788b44.xci new file mode 100644 index 00000000..b8f8f65b --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/56186d833b788b44.xci @@ -0,0 +1,109 @@ + + + xilinx.com + ipcache + 56186d833b788b44 + 0 + + + rom_freq_word + + + 100000000 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../coe/freq_word.coe + ALL + rom_freq_word + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 16 + 16 + false + true + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 81 + 16 + 16 + No_ECC + false + false + false + Stand_Alone + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 56186d833b788b44 + 0137cb81 + 41 + IP_Unknown + 3 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word.dcp new file mode 100644 index 00000000..7c9bea9a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f8c5e3f4ed9685025de8a417b30b632f353e95bfcc8239d4869bcc698e9fb098 +size 26983 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_sim_netlist.v new file mode 100755 index 00000000..390b6c17 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9e64b8b734e0383fa691908ef469ef6884a57a4996564f10a9a97c4490fcfabf +size 28757 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_sim_netlist.vhdl new file mode 100755 index 00000000..6267c4cf --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2513e0801dd30d6430cb514327eb880624eb0af8007cfef574824efb89026655 +size 44335 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_stub.v new file mode 100755 index 00000000..19918edc --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:06:18 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[15:0]" */; + input clka; + input [6:0]addra; + output [15:0]douta; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_stub.vhdl new file mode 100755 index 00000000..4daee10f --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/56186d833b788b44/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:06:18 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/63d607d13d6695a3.xci b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/63d607d13d6695a3.xci new file mode 100644 index 00000000..41effcd9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/63d607d13d6695a3.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 63d607d13d6695a3 + 0 + + + vio_freq_comp + + + 100000000 + 0 + 1 + 1 + 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b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp.dcp new file mode 100644 index 00000000..8134ef6a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1dba56c21d108b32cb4b21cb0056163c34766b6299b6a9867743a426882f5da3 +size 147480 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_sim_netlist.v new file mode 100755 index 00000000..dcfddc13 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c6c486dcf11f82de77fa4faf4bc87a623e4f0411355cb24303525acd1b65acda +size 359193 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_sim_netlist.vhdl new file mode 100755 index 00000000..5e47e913 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8a0ae95b3f274d7cadc20fc6433903d43140fa920eda17a7c78d29d081e9106b +size 676464 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_stub.v new file mode 100755 index 00000000..58c98775 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_stub.v @@ -0,0 +1,28 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:01:59 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_freq_comp_stub.v +// Design : vio_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0],probe_out5[0:0]" */; + input clk; + input [0:0]probe_in0; + output [0:0]probe_out0; + output [7:0]probe_out1; + output [0:0]probe_out2; + output [31:0]probe_out3; + output [0:0]probe_out4; + output [0:0]probe_out5; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_stub.vhdl new file mode 100755 index 00000000..2a65bacc --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/63d607d13d6695a3/vio_freq_comp_stub.vhdl @@ -0,0 +1,37 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:01:59 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_freq_comp_stub.vhdl +-- Design : vio_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0],probe_out5[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/662b4d6b8ea25fd2.xci b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/662b4d6b8ea25fd2.xci new file mode 100644 index 00000000..e3f8db2c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/662b4d6b8ea25fd2.xci @@ -0,0 +1,3147 @@ + + + xilinx.com + ipcache + 662b4d6b8ea25fd2 + 0 + + + ila_rf_auto_control + + + 100000000 + TRUE + 1 + FALSE + 10 + 10 + 200 + 5 + 1024 + FALSE + 3 + FALSE + FALSE + 0 + 0 + 2000000 + 0 + Native + 1 + 6 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 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a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control.dcp new file mode 100644 index 00000000..c3bad8d9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:148ae839d9d5e3d568ae4a2e19ecc37c902c390bc08e9d3cf645b95d363edfa3 +size 747726 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_sim_netlist.v new file mode 100755 index 00000000..2bd9d317 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dc3b199b3e1b2f422868c3d6d97264a903c900611124d9c206607878b66b4176 +size 1745351 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_sim_netlist.vhdl new file mode 100755 index 00000000..20afb6b3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c54614abedcfcbad66af89814550569412d1a485a94f0c9d0ac92823e7808440 +size 3631332 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_stub.v new file mode 100755 index 00000000..19160206 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:01:06 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_auto_control_stub.v +// Design : ila_rf_auto_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]" */; + input clk; + input [0:0]probe0; + input [31:0]probe1; + input [31:0]probe2; + input [0:0]probe3; + input [0:0]probe4; + input [7:0]probe5; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_stub.vhdl new file mode 100755 index 00000000..7f3744f2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/662b4d6b8ea25fd2/ila_rf_auto_control_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:01:06 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_auto_control_stub.vhdl +-- Design : ila_rf_auto_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe4 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/8cd2f1d8d3f01d35.xci b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/8cd2f1d8d3f01d35.xci new file mode 100644 index 00000000..09536f97 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/8cd2f1d8d3f01d35.xci @@ -0,0 +1,107 @@ + + + xilinx.com + ipcache + 8cd2f1d8d3f01d35 + 0 + + + fir_prbs10_invert_rep2 + + + 100000000 + 100000000 + 100000000 + false + false + Basic + 192 + COE_File + 1,1,1,1,1,1,-1,-1,1,1,1,1,-1,1,-1,1,1,1,-1,-1,-1,-1,1,1,-1,1,1,1,-1,1,-1,-1,1,1,-1,-1,-1,1,-1,1,-1,1,1,-1,-1,-1,-1,-1,1,-1,1,1,1,1,-1,-1,-1,1,1,1,-1,1,1,-1,1,1,-1,-1,1,-1,-1,1,-1,1,-1,-1,1,-1,-1,-1,-1,1,-1,-1,1,1,1,-1,-1,1,-1,1,1,-1,1,-1,-1,-1,1,-1,-1,-1,1,1,-1,-1,1,1,-1,1,-1,1,-1,1,-1,-1,-1,-1,-1,-1,-1,1,1,1,1,1,1,-1 + Automatic + ../coe/prbs10_invert_rep2.coe + 0 + false + 1 + Signed + Inferred + 2 + 128 + fir_prbs10_invert_rep2 + Not_Required + 1 + Automatic + 0 + Signed + 12 + 1 + false + Systolic_Multiply_Accumulate + 1 + Single_Rate + Coregen + false + false + false + 1 + false + true + Automatic + 4 + 1 + false + Not_Required + Automatic + 1 + 1 + 1 + Area + None + None + Automatic + Full_Precision + 23 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + Automatic + Integer_Coefficients + Frequency_Specification + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 1 + 12 + All + 1.0 + 0.5 + 1 + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 8cd2f1d8d3f01d35 + 71c522b0 + 37 + IP_Unknown + 12 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2.dcp new file mode 100644 index 00000000..3e80613f --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f99123f3154e30381f5e5dc485b17fd7ee053df9925cc2921f0b4596caf9bebd +size 2775355 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_sim_netlist.v new file mode 100755 index 00000000..e8c9c866 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:88de4dc04804cc7d2539b9b5b2b6ed89b1230f39f5bc361080999e3368cd8ea6 +size 6510348 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_sim_netlist.vhdl new file mode 100755 index 00000000..fdc3bfed --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c9f6f8a1746afdf9cc7d42a00ac5c1cc0010b6f6023b8cd6c5aab2d36e1ce4e3 +size 9347282 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_stub.v old mode 100644 new mode 100755 similarity index 81% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_stub.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_stub.v index 10f816e4..9c476038 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_stub.v @@ -1,11 +1,11 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Sun May 7 09:32:08 2023 +// Date : Fri May 12 16:05:12 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -// Command : write_verilog -force -mode synth_stub -rename_top fir_prbs7_invert_rep4 -prefix -// fir_prbs7_invert_rep4_ fir_prbs7_invert_rep4_stub.v -// Design : fir_prbs7_invert_rep4 +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs10_invert_rep2_stub.v +// Design : fir_prbs10_invert_rep2 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 // -------------------------------------------------------------------------------- @@ -14,7 +14,7 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) -module fir_prbs7_invert_rep4(aresetn, aclk, s_axis_data_tvalid, +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aresetn, aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) /* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */; input aresetn; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_stub.vhdl old mode 100644 new mode 100755 similarity index 77% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_stub.vhdl rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_stub.vhdl index b7a913c4..cfaa887d --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/8cd2f1d8d3f01d35/fir_prbs10_invert_rep2_stub.vhdl @@ -1,18 +1,18 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Sun May 7 09:32:08 2023 +-- Date : Fri May 12 16:05:12 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub -rename_top fir_prbs7_invert_rep4 -prefix --- fir_prbs7_invert_rep4_ fir_prbs7_invert_rep4_stub.vhdl --- Design : fir_prbs7_invert_rep4 +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs10_invert_rep2_stub.vhdl +-- Design : fir_prbs10_invert_rep2 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -entity fir_prbs7_invert_rep4 is +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( aresetn : in STD_LOGIC; aclk : in STD_LOGIC; @@ -23,9 +23,9 @@ entity fir_prbs7_invert_rep4 is m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ) ); -end fir_prbs7_invert_rep4; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; -architecture stub of fir_prbs7_invert_rep4 is +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ac5110ede4bd2290/ac5110ede4bd2290.xci b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ac5110ede4bd2290/ac5110ede4bd2290.xci new file mode 100644 index 00000000..7cec4e07 --- /dev/null +++ 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a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ac5110ede4bd2290/ila_rx_data_cnt_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ac5110ede4bd2290/ila_rx_data_cnt_stub.v new file mode 100755 index 00000000..13ced9b9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ac5110ede4bd2290/ila_rx_data_cnt_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:03:07 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_stub.v +// Design : ila_rx_data_cnt +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]" */; + input clk; + input [11:0]probe0; + input [11:0]probe1; + input [11:0]probe2; + input [11:0]probe3; + input [11:0]probe4; + input [11:0]probe5; + input [11:0]probe6; + input [11:0]probe7; + input [11:0]probe8; + input [12:0]probe9; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ac5110ede4bd2290/ila_rx_data_cnt_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ac5110ede4bd2290/ila_rx_data_cnt_stub.vhdl new file mode 100755 index 00000000..6e6a1bd9 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ac5110ede4bd2290/ila_rx_data_cnt_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:03:07 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_stub.vhdl +-- Design : ila_rx_data_cnt +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/d259ec5277241eb0.xci b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/d259ec5277241eb0.xci new file mode 100644 index 00000000..20ca9060 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/d259ec5277241eb0.xci @@ -0,0 +1,3147 @@ + + + xilinx.com + ipcache + d259ec5277241eb0 + 0 + + + ila_rf_auto_control + + + 100000000 + TRUE + 2 + true + 10 + 10 + 200 + 5 + 1024 + FALSE + 3 + FALSE + FALSE + 1 + 0 + 2000000 + 0 + Native + 1 + 6 + 2 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 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VERILOG + + -2 + + + TRUE + TRUE + d259ec5277241eb0 + 48c58d29 + 70 + IP_Unknown + 9 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control.dcp new file mode 100644 index 00000000..d664b1cb --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:51fbbc03773f5e9252c953434e7a248a9fb5195daf088d76b4537079efe7b085 +size 1639350 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_sim_netlist.v new file mode 100755 index 00000000..8c5ba96a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:30d07d7444efc584894b60e2a6dd9c8ece109b04b89f209fe3c894bbe28ce9e3 +size 3355722 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_sim_netlist.vhdl new file mode 100755 index 00000000..239501db --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e80694587b9e981890c0dee30019109857c73d922a152c62ebeecc56f8732e29 +size 5643259 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_stub.v new file mode 100755 index 00000000..4554a3e0 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:03:13 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_auto_control_stub.v +// Design : ila_rf_auto_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]" */; + input clk; + input [0:0]probe0; + input [31:0]probe1; + input [31:0]probe2; + input [0:0]probe3; + input [0:0]probe4; + input [7:0]probe5; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_stub.vhdl new file mode 100755 index 00000000..60e388e4 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d259ec5277241eb0/ila_rf_auto_control_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:03:13 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_auto_control_stub.vhdl +-- Design : ila_rf_auto_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe4 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/ff5ef8baace3dbcc.xci b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/ff5ef8baace3dbcc.xci new file mode 100644 index 00000000..bf7b72d7 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/ff5ef8baace3dbcc.xci @@ -0,0 +1,206 @@ + + + xilinx.com + ipcache + ff5ef8baace3dbcc + 0 + + + fifo_rx_data + + + 100000000 + 100000000 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_rx_data + 64 + false + 4 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 13 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 12 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 96 + 16 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 96 + 16 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 4 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 4 + false + FIFO + false + false + false + false + FIFO + FIFO + 3 + 2 + false + FIFO + FIFO + FIFO + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + ff5ef8baace3dbcc + e223bb28 + 23 + IP_Unknown + 4 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data.dcp new file mode 100644 index 00000000..a7c9846a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:67ac07cc4a9cc0a81f2a32e05eb3993783923d44abac892efca5329dcff75501 +size 126685 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_sim_netlist.v new file mode 100755 index 00000000..0bc856dc --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fc427bee2b417a177c2cf6541460a6519d0d2a20af01025a66e50f11d260cf5d +size 141872 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_sim_netlist.vhdl new file mode 100755 index 00000000..61d0982d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:470dfb262d2a0f759d207dcfcc9e35d780699dcd2a369bd66b9a32f761cf14df +size 226616 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_stub.v new file mode 100755 index 00000000..4884e4a8 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_stub.v @@ -0,0 +1,29 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:08:03 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_rx_data_stub.v +// Design : fifo_rx_data +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty) +/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[95:0],wr_en,rd_en,dout[95:0],full,empty" */; + input rst; + input wr_clk; + input rd_clk; + input [95:0]din; + input wr_en; + input rd_en; + output [95:0]dout; + output full; + output empty; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_stub.vhdl new file mode 100755 index 00000000..cd4c050d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/ff5ef8baace3dbcc/fifo_rx_data_stub.vhdl @@ -0,0 +1,38 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:08:03 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_rx_data_stub.vhdl +-- Design : fifo_rx_data +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + rst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 95 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 95 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[95:0],wr_en,rd_en,dout[95:0],full,empty"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index cb488107..7f510c48 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ 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b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:21 +6d6f64655f636f756e7465727c4755494d6f6465:23 eof: diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf index 593917f4..013f5d39 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -1,7 +1,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 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a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index c6336654..ce500cd9 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,61 +17,62 @@ This means code written to parse this file will need to be revisited each subseq - - - - - + + + + + - - + + - - + + - - - - + + + + - + - + - + - - - + + + - - - + + + + - - + + - + - +
diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_41.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_41.xml new file mode 100644 index 00000000..4fb11b9c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_41.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_42.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_42.xml new file mode 100644 index 00000000..da262cde --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_42.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_43.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_43.xml new file mode 100644 index 00000000..9ab02a94 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_43.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_44.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_44.xml new file mode 100644 index 00000000..0655aa28 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_44.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_45.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_45.xml new file mode 100644 index 00000000..da262cde --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_45.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_46.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_46.xml new file mode 100644 index 00000000..767f1af7 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_46.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_47.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_47.xml new file mode 100644 index 00000000..72e7de07 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_47.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_48.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_48.xml new file mode 100644 index 00000000..2b40211d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_48.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_49.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_49.xml new file mode 100644 index 00000000..ac2aee44 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_49.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.dcp deleted file mode 100644 index c7255267..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.dcp +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:7537ec08b3834c9dd03aae362dcd1d2a199a819bbc3a1dd5bd1166cc9661ef78 -size 107007 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.vds b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.vds deleted file mode 100644 index 254bb2fc..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.vds +++ /dev/null @@ -1,423 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Mon May 8 00:28:50 2023 -# Process ID: 1529692 -# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1 -# Command line: vivado -log dds_32b_8b_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b_comp.tcl -# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.vds -# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/vivado.jou -#----------------------------------------------------------- -source dds_32b_8b_comp.tcl -notrace -Command: synth_design -top dds_32b_8b_comp -part xc7k410tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Device 21-403] Loading part xc7k410tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 1529787 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1841.941 ; gain = 153.719 ; free physical = 457 ; free virtual = 46431 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'dds_32b_8b_comp' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/synth/dds_32b_8b_comp.vhd:71] -WARNING: [Synth 8-5640] Port 'debug_axi_pinc_in' is missing in component declaration [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/synth/dds_32b_8b_comp.vhd:74] -WARNING: [Synth 8-5640] Port 'debug_axi_poff_in' is missing in component declaration [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/synth/dds_32b_8b_comp.vhd:74] -WARNING: [Synth 8-5640] Port 'debug_axi_resync_in' is missing in component declaration [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/synth/dds_32b_8b_comp.vhd:74] -WARNING: [Synth 8-5640] Port 'debug_axi_chan_in' is missing in component declaration [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/synth/dds_32b_8b_comp.vhd:74] -WARNING: [Synth 8-5640] Port 'debug_core_nd' is missing in component declaration [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/synth/dds_32b_8b_comp.vhd:74] -WARNING: [Synth 8-5640] Port 'debug_phase' is missing in component declaration [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/synth/dds_32b_8b_comp.vhd:74] -WARNING: [Synth 8-5640] Port 'debug_phase_nd' is missing in component declaration [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/synth/dds_32b_8b_comp.vhd:74] - Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string - Parameter C_MODE_OF_OPERATION bound to: 0 - type: integer - Parameter C_MODULUS bound to: 9 - type: integer - Parameter C_ACCUMULATOR_WIDTH bound to: 32 - type: integer - Parameter C_CHANNELS bound to: 1 - type: integer - Parameter C_HAS_PHASE_OUT bound to: 1 - type: integer - Parameter C_HAS_PHASEGEN bound to: 1 - type: integer - Parameter C_HAS_SINCOS bound to: 1 - type: integer - Parameter C_LATENCY bound to: 4 - type: integer - Parameter C_MEM_TYPE bound to: 1 - type: integer - Parameter C_NEGATIVE_COSINE bound to: 0 - type: integer - Parameter C_NEGATIVE_SINE bound to: 0 - type: integer - Parameter C_NOISE_SHAPING bound to: 0 - type: integer - Parameter C_OUTPUTS_REQUIRED bound to: 2 - type: integer - Parameter C_OUTPUT_FORM bound to: 0 - type: integer - Parameter C_OUTPUT_WIDTH bound to: 8 - type: integer - Parameter C_PHASE_ANGLE_WIDTH bound to: 8 - type: integer - Parameter C_PHASE_INCREMENT bound to: 1 - type: integer - Parameter C_PHASE_INCREMENT_VALUE bound to: 1101000110110111,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - type: string - Parameter C_RESYNC bound to: 0 - type: integer - Parameter C_PHASE_OFFSET bound to: 1 - type: integer - Parameter C_PHASE_OFFSET_VALUE bound to: 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - type: string - Parameter C_OPTIMISE_GOAL bound to: 0 - type: integer - Parameter C_USE_DSP48 bound to: 0 - type: integer - Parameter C_POR_MODE bound to: 0 - type: integer - Parameter C_AMPLITUDE bound to: 0 - type: integer - Parameter C_HAS_ACLKEN bound to: 0 - type: integer - Parameter C_HAS_ARESETN bound to: 0 - type: integer - Parameter C_HAS_TLAST bound to: 0 - type: integer - Parameter C_HAS_TREADY bound to: 0 - type: integer - Parameter C_HAS_S_PHASE bound to: 0 - type: integer - Parameter C_S_PHASE_TDATA_WIDTH bound to: 1 - type: integer - Parameter C_S_PHASE_HAS_TUSER bound to: 0 - type: integer - Parameter C_S_PHASE_TUSER_WIDTH bound to: 1 - type: integer - Parameter C_HAS_S_CONFIG bound to: 1 - type: integer - Parameter C_S_CONFIG_SYNC_MODE bound to: 0 - type: integer - Parameter C_S_CONFIG_TDATA_WIDTH bound to: 64 - type: integer - Parameter C_HAS_M_DATA bound to: 1 - type: integer - Parameter C_M_DATA_TDATA_WIDTH bound to: 16 - type: integer - Parameter C_M_DATA_HAS_TUSER bound to: 0 - type: integer - Parameter C_M_DATA_TUSER_WIDTH bound to: 1 - type: integer - Parameter C_HAS_M_PHASE bound to: 1 - type: integer - Parameter C_M_PHASE_TDATA_WIDTH bound to: 32 - type: integer - Parameter C_M_PHASE_HAS_TUSER bound to: 0 - type: integer - Parameter C_M_PHASE_TUSER_WIDTH bound to: 1 - type: integer - Parameter C_DEBUG_INTERFACE bound to: 0 - type: integer - Parameter C_CHAN_WIDTH bound to: 1 - type: integer -INFO: [Synth 8-3491] module 'dds_compiler_v6_0_18' declared at '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/hdl/dds_compiler_v6_0_vh_rfs.vhd:47308' bound to instance 'U0' of component 'dds_compiler_v6_0_18' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/synth/dds_32b_8b_comp.vhd:179] -INFO: [Synth 8-256] done synthesizing module 'dds_32b_8b_comp' (9#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/synth/dds_32b_8b_comp.vhd:71] -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv has unconnected port SINIT -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized12 has unconnected port CLK -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized12 has unconnected port CE -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized12 has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized12 has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized12 has unconnected port SINIT -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port SINIT -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized20 has unconnected port CLK -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized20 has unconnected port CE -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized20 has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized20 has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized20 has unconnected port SINIT -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized18 has unconnected port CLK -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized18 has unconnected port CE -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized18 has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized18 has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized18 has unconnected port SINIT -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized16 has unconnected port CLK -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized16 has unconnected port CE -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized16 has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized16 has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized16 has unconnected port SINIT -WARNING: [Synth 8-3331] design sin_cos has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port SINIT -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port CLK -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port CE -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port SINIT -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port CLK -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port CE -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port SINIT -WARNING: [Synth 8-3331] design accum has unconnected port chan_addr[0] -WARNING: [Synth 8-3331] design accum has unconnected port chan_addr_del2[0] -WARNING: [Synth 8-3331] design accum has unconnected port chan_addr_del3[0] -WARNING: [Synth 8-3331] design accum has unconnected port addr_i[3] -WARNING: [Synth 8-3331] design accum has unconnected port addr_i[2] -WARNING: [Synth 8-3331] design accum has unconnected port addr_i[1] -WARNING: [Synth 8-3331] design accum has unconnected port addr_i[0] -WARNING: [Synth 8-3331] design accum has unconnected port phase_inc_we -WARNING: [Synth 8-3331] design accum has unconnected port phase_adj_we -WARNING: [Synth 8-3331] design accum has unconnected port data_i[31] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[30] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[29] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[28] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[27] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[26] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[25] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[24] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[23] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[22] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[21] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[20] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[19] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[18] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[17] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[16] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[15] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[14] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[13] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[12] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[11] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[10] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[9] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[8] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[7] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[6] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[5] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[4] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[3] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[2] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[1] -WARNING: [Synth 8-3331] design accum has unconnected port data_i[0] -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized14 has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized14 has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized14 has unconnected port SINIT -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized1 has unconnected port SCLR -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized1 has unconnected port SSET -WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized1 has unconnected port SINIT -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port RFD -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port CHANNEL[0] -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port ADDR[0] -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port REG_SELECT -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port SCLR -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port PHASE_IN[31] -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port PHASE_IN[30] -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port PHASE_IN[29] -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port PHASE_IN[28] -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port PHASE_IN[27] -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port PHASE_IN[26] -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port PHASE_IN[25] -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port PHASE_IN[24] -WARNING: [Synth 8-3331] design dds_compiler_v6_0_18_core has unconnected port PHASE_IN[23] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1935.660 ; gain = 247.438 ; free physical = 543 ; free virtual = 46484 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1935.660 ; gain = 247.438 ; free physical = 541 ; free virtual = 46481 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1935.660 ; gain = 247.438 ; free physical = 541 ; free virtual = 46481 ---------------------------------------------------------------------------------- -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp_ooc.xdc] for cell 'U0' -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp_ooc.xdc] for cell 'U0' -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dont_touch.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2102.410 ; gain = 0.000 ; free physical = 448 ; free virtual = 46405 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2102.410 ; gain = 0.000 ; free physical = 448 ; free virtual = 46405 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 505 ; free virtual = 46475 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k410tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 505 ; free virtual = 46475 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 508 ; free virtual = 46477 ---------------------------------------------------------------------------------- -INFO: [Synth 8-7031] Trying to map ROM "sin_cos_lut" into Block RAM due to explicit "ram_style" or "rom_style" specification -INFO: [Synth 8-7031] Trying to map ROM "sin_cos_lut" into Block RAM due to explicit "ram_style" or "rom_style" specification ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 502 ; free virtual = 46474 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 1540 (col length:140) -BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification -INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 486 ; free virtual = 46459 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6837] The timing for the instance U0/i_synth/i_0/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. -INFO: [Synth 8-6837] The timing for the instance U0/i_synth/i_1/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 401 ; free virtual = 46297 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 400 ; free virtual = 46296 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 446 ; free virtual = 46291 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 436 ; free virtual = 46283 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 436 ; free virtual = 46283 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 436 ; free virtual = 46283 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 436 ; free virtual = 46283 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 436 ; free virtual = 46283 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 436 ; free virtual = 46283 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-----------+------+ -| |Cell |Count | -+------+-----------+------+ -|1 |CARRY4 | 18| -|2 |LUT2 | 67| -|3 |RAMB18E1_2 | 1| -|4 |SRL16E | 1| -|5 |FDRE | 232| -+------+-----------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 436 ; free virtual = 46283 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 13 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2102.410 ; gain = 247.438 ; free physical = 491 ; free virtual = 46338 -Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2102.410 ; gain = 414.188 ; free physical = 491 ; free virtual = 46338 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2102.410 ; gain = 0.000 ; free physical = 433 ; free virtual = 46283 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -21 Infos, 107 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2102.410 ; gain = 692.020 ; free physical = 525 ; free virtual = 46376 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2102.410 ; gain = 0.000 ; free physical = 525 ; free virtual = 46376 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP dds_32b_8b_comp, cache-ID = 0740cd06f1784082 -INFO: [Coretcl 2-1174] Renamed 15 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2126.422 ; gain = 0.000 ; free physical = 511 ; free virtual = 46363 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file dds_32b_8b_comp_utilization_synth.rpt -pb dds_32b_8b_comp_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Mon May 8 00:29:10 2023... diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.v deleted file mode 100644 index da95da03..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:279139d452d1f9af7126efdbacc5f55b925ac298e555c1864b646b8aeb5771c6 -size 186473 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.vhdl deleted file mode 100644 index fb42e9c7..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:a3ca59fd07c5116d76ea3256a9cbf057da7f8cfe96c00f421f5dda2b326e709e -size 252777 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_utilization_synth.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_utilization_synth.pb deleted file mode 100644 index fa98a8e9..00000000 Binary files a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_utilization_synth.pb and /dev/null differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dont_touch.xdc b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dont_touch.xdc deleted file mode 100644 index c2a6f8e3..00000000 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dont_touch.xdc +++ /dev/null @@ -1,16 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp.xci -# IP: The module: 'dds_32b_8b_comp' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'dds_32b_8b_comp'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp.xci -# IP: The module: 'dds_32b_8b_comp' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'dds_32b_8b_comp'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/vivado.pb deleted file mode 100644 index 471a0aa9..00000000 Binary files a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/vivado.pb and /dev/null differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/.vivado.begin.rst similarity index 75% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/.vivado.begin.rst rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/.vivado.begin.rst index 409043f1..80a617ca 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/.vivado.begin.rst +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/.vivado.end.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/ISEWrap.js b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/ISEWrap.js similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/ISEWrap.js rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/ISEWrap.js diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/ISEWrap.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/ISEWrap.sh similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/ISEWrap.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/ISEWrap.sh diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/__synthesis_is_complete__ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/dont_touch.xdc b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/dont_touch.xdc new file mode 100644 index 00000000..15b52375 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xci +# IP: The module: 'fifo_rx_data' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_rx_data'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_clocks.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_rx_data'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_rx_data'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xci +# IP: The module: 'fifo_rx_data' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_rx_data'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_clocks.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_rx_data'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_rx_data'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.dcp new file mode 100644 index 00000000..58923d9e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b5968d5e9affcd27cccaefef5781cc4c451873feb2bbfcec3e956db9ac429d84 +size 127212 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.tcl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.tcl new file mode 100644 index 00000000..b2fc88f0 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.tcl @@ -0,0 +1,158 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7k410tffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_clocks.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1 -new_name fifo_rx_data -ip [get_ips fifo_rx_data]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top fifo_rx_data -part xc7k410tffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix fifo_rx_data_ fifo_rx_data.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_rx_data_stub.v + lappend ipCachedFiles fifo_rx_data_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_rx_data_stub.vhdl + lappend ipCachedFiles fifo_rx_data_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_rx_data_sim_netlist.v + lappend ipCachedFiles fifo_rx_data_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_rx_data_sim_netlist.vhdl + lappend ipCachedFiles fifo_rx_data_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp fifo_rx_data.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips fifo_rx_data] +} + +rename_ref -prefix_all fifo_rx_data_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef fifo_rx_data.dcp +create_report "fifo_rx_data_synth_1_synth_report_utilization_0" "report_utilization -file fifo_rx_data_utilization_synth.rpt -pb fifo_rx_data_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.vds b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.vds new file mode 100644 index 00000000..7cf27d4d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.vds @@ -0,0 +1,728 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Fri May 12 16:07:37 2023 +# Process ID: 1479422 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1 +# Command line: vivado -log fifo_rx_data.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_rx_data.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/vivado.jou +#----------------------------------------------------------- +source fifo_rx_data.tcl -notrace +Command: synth_design -top fifo_rx_data -part xc7k410tffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Device 21-403] Loading part xc7k410tffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 1479548 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1826.496 ; gain = 153.688 ; free physical = 537 ; free virtual = 43677 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'fifo_rx_data' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/synth/fifo_rx_data.vhd:73] + Parameter C_COMMON_CLOCK bound to: 0 - type: integer + Parameter C_SELECT_XPM bound to: 0 - type: integer + Parameter C_COUNT_TYPE bound to: 0 - type: integer + Parameter C_DATA_COUNT_WIDTH bound to: 4 - type: integer + Parameter C_DEFAULT_VALUE bound to: BlankString - type: string + Parameter C_DIN_WIDTH bound to: 96 - type: integer + Parameter C_DOUT_RST_VAL bound to: 0 - type: string + Parameter C_DOUT_WIDTH bound to: 96 - type: integer + Parameter C_ENABLE_RLOCS bound to: 0 - type: integer + Parameter C_FAMILY bound to: kintex7 - type: string + Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer + Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer + Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer + Parameter C_HAS_BACKUP bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer + Parameter C_HAS_INT_CLK bound to: 0 - type: integer + Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer + Parameter C_HAS_OVERFLOW bound to: 0 - type: integer + Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer + Parameter C_HAS_RD_RST bound to: 0 - type: integer + Parameter C_HAS_RST bound to: 1 - type: integer + Parameter C_HAS_SRST bound to: 0 - type: integer + Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer + Parameter C_HAS_VALID bound to: 0 - type: integer + Parameter C_HAS_WR_ACK bound to: 0 - type: integer + Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer + Parameter C_HAS_WR_RST bound to: 0 - type: integer + Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer + Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer + Parameter C_MEMORY_TYPE bound to: 2 - type: integer + Parameter C_MIF_FILE_NAME bound to: BlankString - type: string + Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer + Parameter C_OVERFLOW_LOW bound to: 0 - type: integer + Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer + Parameter C_PRELOAD_REGS bound to: 0 - type: integer + Parameter C_PRIM_FIFO_TYPE bound to: 512x72 - type: string + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 2 - type: integer + Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 3 - type: integer + Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 13 - type: integer + Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 12 - type: integer + Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer + Parameter C_RD_DATA_COUNT_WIDTH bound to: 4 - type: integer + Parameter C_RD_DEPTH bound to: 16 - type: integer + Parameter C_RD_FREQ bound to: 1 - type: integer + Parameter C_RD_PNTR_WIDTH bound to: 4 - type: integer + Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer + Parameter C_USE_DOUT_RST bound to: 1 - type: integer + Parameter C_USE_ECC bound to: 0 - type: integer + Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer + Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer + Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer + Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer + Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer + Parameter C_VALID_LOW bound to: 0 - type: integer + Parameter C_WR_ACK_LOW bound to: 0 - type: integer + Parameter C_WR_DATA_COUNT_WIDTH bound to: 4 - type: integer + Parameter C_WR_DEPTH bound to: 16 - type: integer + Parameter C_WR_FREQ bound to: 1 - type: integer + Parameter C_WR_PNTR_WIDTH bound to: 4 - type: integer + Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer + Parameter C_MSGON_VAL bound to: 1 - type: integer + Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer + Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer + Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer + Parameter C_INTERFACE_TYPE bound to: 0 - type: integer + Parameter C_AXI_TYPE bound to: 1 - type: integer + Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer + Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer + Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer + Parameter C_HAS_MASTER_CE bound to: 0 - type: integer + Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer + Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer + Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer + Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer + Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer + Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer + Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer + Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer + Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer + Parameter C_HAS_AXI_ID bound to: 0 - type: integer + Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer + Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer + Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer + Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer + Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer + Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer + Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer + Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer + Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer + Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer + Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer + Parameter C_HAS_AXIS_TID bound to: 0 - type: integer + Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer + Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer + Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer + Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer + Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer + Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer + Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer + Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer + Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer + Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer + Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer + Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer + Parameter C_WACH_TYPE bound to: 0 - type: integer + Parameter C_WDCH_TYPE bound to: 0 - type: integer + Parameter C_WRCH_TYPE bound to: 0 - type: integer + Parameter C_RACH_TYPE bound to: 0 - type: integer + Parameter C_RDCH_TYPE bound to: 0 - type: integer + Parameter C_AXIS_TYPE bound to: 0 - type: integer + Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer + Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer + Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer + Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer + Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer + Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer + Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer + Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer + Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer + Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer + Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer + Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer + Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string + Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string + Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string + Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string + Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string + Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string + Parameter C_USE_ECC_WACH bound to: 0 - type: integer + Parameter C_USE_ECC_WDCH bound to: 0 - type: integer + Parameter C_USE_ECC_WRCH bound to: 0 - type: integer + Parameter C_USE_ECC_RACH bound to: 0 - type: integer + Parameter C_USE_ECC_RDCH bound to: 0 - type: integer + Parameter C_USE_ECC_AXIS bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer + Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer + Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer + Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer + Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer + Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer + Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer + Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer + Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer + Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer + Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer + Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer + Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer + Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer + Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer + Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer + Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer + Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer + Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer + Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer + Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer + Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer + Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer + Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer + Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer + Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer + Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer + Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer + Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer + Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer + Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer + Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer +INFO: [Synth 8-3491] module 'fifo_generator_v13_2_4' declared at '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38586' bound to instance 'U0' of component 'fifo_generator_v13_2_4' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/synth/fifo_rx_data.vhd:543] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1226] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (1#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] +INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:205] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (2#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] +INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (7#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] +INFO: [Synth 8-256] done synthesizing module 'fifo_rx_data' (21#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/synth/fifo_rx_data.vhd:73] +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_RST +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SRST +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SAFETY_CKT_WR_RST +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[3] +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[2] +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[1] +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[0] +WARNING: [Synth 8-3331] design wr_bin_cntr has unconnected port SRST +WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_EN_INTO_LOGIC +WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_INTO_LOGIC +WARNING: [Synth 8-3331] design wr_logic has unconnected port RD_EN +WARNING: [Synth 8-3331] design wr_logic has unconnected port SRST_FULL_FF +WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_BUSY +WARNING: [Synth 8-3331] design wr_logic has unconnected port EMPTY +WARNING: [Synth 8-3331] design wr_logic has unconnected port RAM_RD_EN +WARNING: [Synth 8-3331] design wr_logic has unconnected port ALMOST_EMPTY +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[3] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[2] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[1] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[0] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[3] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[2] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[1] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[0] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[3] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[2] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[1] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[0] +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SRST +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SAFETY_CKT_RD_RST +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[3] +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[2] +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[1] +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[0] +WARNING: [Synth 8-3331] design rd_bin_cntr has unconnected port SRST +WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_EN_INTO_LOGIC +WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_INTO_LOGIC +WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_BUSY +WARNING: [Synth 8-3331] design rd_logic has unconnected port RAM_WR_EN +WARNING: [Synth 8-3331] design rd_logic has unconnected port RST_FULL_FF +WARNING: [Synth 8-3331] design rd_logic has unconnected port ALMOST_FULL_FB +WARNING: [Synth 8-3331] design rd_logic has unconnected port FULL +WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[3] +WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[2] +WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[1] +WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[0] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[3] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[2] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[1] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[0] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[3] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[2] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[1] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[0] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[3] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[2] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[1] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[0] +WARNING: [Synth 8-3331] design clk_x_pntrs has unconnected port WR_RST +WARNING: [Synth 8-3331] design clk_x_pntrs has unconnected port RD_RST +WARNING: [Synth 8-3331] design dmem has unconnected port SRST +WARNING: [Synth 8-3331] design memory has unconnected port RAM_REGOUT_EN +WARNING: [Synth 8-3331] design memory has unconnected port FAB_REGOUT_EN +WARNING: [Synth 8-3331] design memory has unconnected port SFT_RST +WARNING: [Synth 8-3331] design memory has unconnected port SRST +WARNING: [Synth 8-3331] design memory has unconnected port SAFETY_CKT_RD_RST +WARNING: [Synth 8-3331] design memory has unconnected port SLEEP +WARNING: [Synth 8-3331] design memory has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design memory has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design output_blk has unconnected port ALMOST_FULL_I +WARNING: [Synth 8-3331] design output_blk has unconnected port PROG_FULL_I +WARNING: [Synth 8-3331] design output_blk has unconnected port ALMOST_EMPTY_I +WARNING: [Synth 8-3331] design output_blk has unconnected port PROG_EMPTY_I +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_ACK_I +WARNING: [Synth 8-3331] design output_blk has unconnected port VALID_I +WARNING: [Synth 8-3331] design output_blk has unconnected port OVERFLOW_I +WARNING: [Synth 8-3331] design output_blk has unconnected port UNDERFLOW_I +WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[4] +WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[3] +WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[2] +WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[1] +WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[0] +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[4] +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[3] +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[2] +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[1] +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[0] +WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[4] +WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[3] +WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[2] +WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[1] +WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[0] +WARNING: [Synth 8-3331] design output_blk has unconnected port SBITERR_I +WARNING: [Synth 8-3331] design output_blk has unconnected port DBITERR_I +WARNING: [Synth 8-3331] design input_blk has unconnected port CLK +WARNING: [Synth 8-3331] design input_blk has unconnected port INT_CLK +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[3] +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[2] +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[1] +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[0] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1973.215 ; gain = 300.406 ; free physical = 600 ; free virtual = 43666 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1973.215 ; gain = 300.406 ; free physical = 599 ; free virtual = 43665 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1973.215 ; gain = 300.406 ; free physical = 599 ; free virtual = 43665 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/dont_touch.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_clocks.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_clocks.xdc] for cell 'U0' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fifo_rx_data/fifo_rx_data_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_rx_data_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_rx_data_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' +Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' +Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' +Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_rx_data_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_rx_data_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' +Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' +Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' +Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_rx_data_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_rx_data_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' +Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' +Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' +Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_rx_data_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_rx_data_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2118.965 ; gain = 0.000 ; free physical = 434 ; free virtual = 43507 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2118.965 ; gain = 0.000 ; free physical = 434 ; free virtual = 43507 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 478 ; free virtual = 43552 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k410tffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 478 ; free virtual = 43552 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/dont_touch.xdc, line 9). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 478 ; free virtual = 43552 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 469 ; free virtual = 43544 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 2 ++---XORs : + 2 Input 4 Bit XORs := 2 + 2 Input 1 Bit XORs := 22 ++---Registers : + 96 Bit Registers := 1 + 5 Bit Registers := 2 + 4 Bit Registers := 16 + 2 Bit Registers := 3 + 1 Bit Registers := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module xpm_cdc_async_rst +Detailed RTL Component Info : ++---Registers : + 2 Bit Registers := 1 +Module xpm_cdc_single +Detailed RTL Component Info : ++---Registers : + 5 Bit Registers := 1 +Module reset_blk_ramfifo +Detailed RTL Component Info : ++---Registers : + 4 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 6 +Module dmem +Detailed RTL Component Info : ++---Registers : + 96 Bit Registers := 1 +Module xpm_cdc_gray +Detailed RTL Component Info : ++---XORs : + 2 Input 4 Bit XORs := 1 + 2 Input 1 Bit XORs := 3 ++---Registers : + 4 Bit Registers := 5 +Module rd_bin_cntr +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 4 Bit Registers := 2 +Module compare +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 4 +Module rd_status_flags_as +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 2 +Module wr_bin_cntr +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 4 Bit Registers := 3 +Module wr_status_flags_as +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 2 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 1540 (col length:140) +BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 449 ; free virtual = 43527 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+-------------------------------------------------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+-------------------------------------------------------------------------------+----------------+----------------------+---------------+ +|U0 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 96 | RAM32M x 16 | ++------------+-------------------------------------------------------------------------------+----------------+----------------------+---------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 1069 ; free virtual = 44135 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 1056 ; free virtual = 44122 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+-------------------------------------------------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+-------------------------------------------------------------------------------+----------------+----------------------+---------------+ +|U0 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 96 | RAM32M x 16 | ++------------+-------------------------------------------------------------------------------+----------------+----------------------+---------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 1035 ; free virtual = 44102 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 757 ; free virtual = 43882 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 757 ; free virtual = 43882 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 751 ; free virtual = 43878 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 751 ; free virtual = 43878 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 750 ; free virtual = 43878 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 749 ; free virtual = 43878 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |LUT1 | 2| +|2 |LUT2 | 14| +|3 |LUT3 | 5| +|4 |LUT4 | 9| +|5 |LUT5 | 1| +|6 |LUT6 | 4| +|7 |RAM32M | 16| +|8 |FDCE | 119| +|9 |FDPE | 17| +|10 |FDRE | 50| ++------+-------+------+ + +Report Instance Areas: ++------+-------------------------------------------------------------------------------------+-----------------------------+------+ +| |Instance |Module |Cells | ++------+-------------------------------------------------------------------------------------+-----------------------------+------+ +|1 |top | | 237| +|2 | U0 |fifo_generator_v13_2_4 | 237| +|3 | inst_fifo_gen |fifo_generator_v13_2_4_synth | 237| +|4 | \gconvfifo.rf |fifo_generator_top | 237| +|5 | \grf.rf |fifo_generator_ramfifo | 237| +|6 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs | 53| +|7 | wr_pntr_cdc_inst |xpm_cdc_gray__2 | 26| +|8 | rd_pntr_cdc_inst |xpm_cdc_gray | 26| +|9 | \gntv_or_sync_fifo.gl0.rd |rd_logic | 20| +|10 | \gras.rsts |rd_status_flags_as | 3| +|11 | rpntr |rd_bin_cntr | 17| +|12 | \gntv_or_sync_fifo.gl0.wr |wr_logic | 22| +|13 | \gwas.wsts |wr_status_flags_as | 4| +|14 | wpntr |wr_bin_cntr | 18| +|15 | \gntv_or_sync_fifo.mem |memory | 112| +|16 | \gdm.dm_gen.dm |dmem | 112| +|17 | rstblk |reset_blk_ramfifo | 30| +|18 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst |xpm_cdc_async_rst__2 | 2| +|19 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst |xpm_cdc_async_rst | 2| +|20 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd |xpm_cdc_single__2 | 5| +|21 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr |xpm_cdc_single | 5| ++------+-------------------------------------------------------------------------------------+-----------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 749 ; free virtual = 43877 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 439 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.965 ; gain = 300.406 ; free physical = 748 ; free virtual = 43876 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2118.965 ; gain = 446.156 ; free physical = 747 ; free virtual = 43875 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2118.965 ; gain = 0.000 ; free physical = 489 ; free virtual = 43621 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 16 instances were transformed. + RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 16 instances + +INFO: [Common 17-83] Releasing license: Synthesis +28 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 2118.965 ; gain = 723.020 ; free physical = 571 ; free virtual = 43704 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2118.965 ; gain = 0.000 ; free physical = 571 ; free virtual = 43704 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP fifo_rx_data, cache-ID = ff5ef8baace3dbcc +INFO: [Coretcl 2-1174] Renamed 20 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2142.977 ; gain = 0.000 ; free physical = 516 ; free virtual = 43651 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file fifo_rx_data_utilization_synth.rpt -pb fifo_rx_data_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri May 12 16:08:04 2023... diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.v new file mode 100644 index 00000000..f8ebe84d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c045e1dbd6d623be59942e501ae9331d174a02d6ff7537125f01fcdff7944a7e +size 141399 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.vhdl new file mode 100644 index 00000000..544d26e3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ab1d169eb1f1cc2f544dd343e261187a2808e901bf0371c80006113153a67a8c +size 218893 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.v new file mode 100644 index 00000000..6dc32dc5 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.v @@ -0,0 +1,29 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:08:03 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.v +// Design : fifo_rx_data +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *) +module fifo_rx_data(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty) +/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[95:0],wr_en,rd_en,dout[95:0],full,empty" */; + input rst; + input wr_clk; + input rd_clk; + input [95:0]din; + input wr_en; + input rd_en; + output [95:0]dout; + output full; + output empty; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.vhdl new file mode 100644 index 00000000..79d3bbca --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.vhdl @@ -0,0 +1,38 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:08:04 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.vhdl +-- Design : fifo_rx_data +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity fifo_rx_data is + Port ( + rst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 95 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 95 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC + ); + +end fifo_rx_data; + +architecture stub of fifo_rx_data is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[95:0],wr_en,rd_en,dout[95:0],full,empty"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_utilization_synth.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_utilization_synth.pb new file mode 100644 index 00000000..443333bf Binary files /dev/null and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_utilization_synth.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_utilization_synth.rpt new file mode 100644 index 00000000..9014616b --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_utilization_synth.rpt @@ -0,0 +1,185 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Fri May 12 16:08:03 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file fifo_rx_data_utilization_synth.rpt -pb fifo_rx_data_utilization_synth.pb +| Design : fifo_rx_data +| Device : 7k410tffg900-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 94 | 0 | 254200 | 0.04 | +| LUT as Logic | 30 | 0 | 254200 | 0.01 | +| LUT as Memory | 64 | 0 | 90600 | 0.07 | +| LUT as Distributed RAM | 64 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 186 | 0 | 508400 | 0.04 | +| Register as Flip Flop | 186 | 0 | 508400 | 0.04 | +| Register as Latch | 0 | 0 | 508400 | 0.00 | +| F7 Muxes | 0 | 0 | 127100 | 0.00 | +| F8 Muxes | 0 | 0 | 63550 | 0.00 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 17 | Yes | - | Set | +| 119 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 50 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 795 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | +| RAMB18 | 0 | 0 | 1590 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 1540 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 500 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| PHY_CONTROL | 0 | 0 | 10 | 0.00 | +| PHASER_REF | 0 | 0 | 10 | 0.00 | +| OUT_FIFO | 0 | 0 | 40 | 0.00 | +| IN_FIFO | 0 | 0 | 40 | 0.00 | +| IDELAYCTRL | 0 | 0 | 10 | 0.00 | +| IBUFDS | 0 | 0 | 480 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 500 | 0.00 | +| OLOGIC | 0 | 0 | 500 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 40 | 0.00 | +| MMCME2_ADV | 0 | 0 | 10 | 0.00 | +| PLLE2_ADV | 0 | 0 | 10 | 0.00 | +| BUFMRCE | 0 | 0 | 20 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 40 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 119 | Flop & Latch | +| RAMD32 | 96 | Distributed Memory | +| FDRE | 50 | Flop & Latch | +| RAMS32 | 32 | Distributed Memory | +| FDPE | 17 | Flop & Latch | +| LUT2 | 14 | LUT | +| LUT4 | 9 | LUT | +| LUT3 | 5 | LUT | +| LUT6 | 4 | LUT | +| LUT1 | 2 | LUT | +| LUT5 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/gen_run.xml new file mode 100644 index 00000000..0cefbab4 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/htr.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/htr.txt similarity index 67% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/htr.txt rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/htr.txt index 0021a123..4fb714ce 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/htr.txt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/htr.txt @@ -6,4 +6,4 @@ # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -vivado -log dds_32b_8b_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b_comp.tcl +vivado -log fifo_rx_data.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_rx_data.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/project.wdf new file mode 100644 index 00000000..5e9327e8 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/project.wdf @@ -0,0 +1,44 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 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@@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log fifo_rx_data.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_rx_data.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/runme.bat b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/runme.bat similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/runme.bat rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/runme.bat diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/runme.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/runme.sh new file mode 100755 index 00000000..840c1934 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log fifo_rx_data.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_rx_data.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/vivado.pb new file mode 100644 index 00000000..772223cd Binary files /dev/null and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..3e441e8a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/.vivado.end.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/ISEWrap.js b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/ISEWrap.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/__synthesis_is_complete__ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/dont_touch.xdc b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/dont_touch.xdc new file mode 100644 index 00000000..9241bc0f --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/dont_touch.xdc @@ -0,0 +1,24 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.xci +# IP: The module: 'fir_prbs10_invert_rep2' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/constraints/fir_compiler_v7_2.xdc +# XDC: The top module name and the constraint reference have the same name: 'fir_prbs10_invert_rep2'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'fir_prbs10_invert_rep2'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.xci +# IP: The module: 'fir_prbs10_invert_rep2' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/constraints/fir_compiler_v7_2.xdc +# XDC: The top module name and the constraint reference have the same name: 'fir_prbs10_invert_rep2'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'fir_prbs10_invert_rep2'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.dcp new file mode 100644 index 00000000..980be501 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6308a56cf2b571ed2c8901acf6ba93ac8f671c70c58ccc8afd7af4fbf781dcf4 +size 2784696 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.tcl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.tcl new file mode 100644 index 00000000..57ee8b8a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.tcl @@ -0,0 +1,157 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7k410tffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/constraints/fir_compiler_v7_2.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1 -new_name fir_prbs10_invert_rep2 -ip [get_ips fir_prbs10_invert_rep2]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top fir_prbs10_invert_rep2 -part xc7k410tffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix fir_prbs10_invert_rep2_ fir_prbs10_invert_rep2.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs10_invert_rep2_stub.v + lappend ipCachedFiles fir_prbs10_invert_rep2_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs10_invert_rep2_stub.vhdl + lappend ipCachedFiles fir_prbs10_invert_rep2_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs10_invert_rep2_sim_netlist.v + lappend ipCachedFiles fir_prbs10_invert_rep2_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fir_prbs10_invert_rep2_sim_netlist.vhdl + lappend ipCachedFiles fir_prbs10_invert_rep2_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp fir_prbs10_invert_rep2.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips fir_prbs10_invert_rep2] +} + +rename_ref -prefix_all fir_prbs10_invert_rep2_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef fir_prbs10_invert_rep2.dcp +create_report "fir_prbs10_invert_rep2_synth_1_synth_report_utilization_0" "report_utilization -file fir_prbs10_invert_rep2_utilization_synth.rpt -pb fir_prbs10_invert_rep2_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2 + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fir_prbs10_invert_rep2 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.vds b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.vds new file mode 100644 index 00000000..3eedac1d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.vds @@ -0,0 +1,762 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Fri May 12 16:04:31 2023 +# Process ID: 1474839 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1 +# Command line: vivado -log fir_prbs10_invert_rep2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs10_invert_rep2.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/vivado.jou +#----------------------------------------------------------- +source fir_prbs10_invert_rep2.tcl -notrace +Command: synth_design -top fir_prbs10_invert_rep2 -part xc7k410tffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Device 21-403] Loading part xc7k410tffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 1474946 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1824.496 ; gain = 151.719 ; free physical = 882 ; free virtual = 44292 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'fir_prbs10_invert_rep2' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/synth/fir_prbs10_invert_rep2.vhd:71] + Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string + Parameter C_ELABORATION_DIR bound to: ./ - type: string + Parameter C_COMPONENT_NAME bound to: fir_prbs10_invert_rep2 - type: string + Parameter C_COEF_FILE bound to: fir_prbs10_invert_rep2.mif - type: string + Parameter C_COEF_FILE_LINES bound to: 2048 - type: integer + Parameter C_FILTER_TYPE bound to: 0 - type: integer + Parameter C_INTERP_RATE bound to: 1 - type: integer + Parameter C_DECIM_RATE bound to: 1 - type: integer + Parameter C_ZERO_PACKING_FACTOR bound to: 1 - type: integer + Parameter C_SYMMETRY bound to: 0 - type: integer + Parameter C_NUM_FILTS bound to: 1 - type: integer + Parameter C_NUM_TAPS bound to: 2048 - type: integer + Parameter C_NUM_CHANNELS bound to: 1 - type: integer + Parameter C_CHANNEL_PATTERN bound to: fixed - type: string + Parameter C_ROUND_MODE bound to: 0 - type: integer + Parameter C_COEF_RELOAD bound to: 0 - type: integer + Parameter C_NUM_RELOAD_SLOTS bound to: 1 - type: integer + Parameter C_COL_MODE bound to: 1 - type: integer + Parameter C_COL_PIPE_LEN bound to: 4 - type: integer + Parameter C_COL_CONFIG bound to: 128 - type: string + Parameter C_OPTIMIZATION bound to: 0 - type: integer + Parameter C_DATA_PATH_WIDTHS bound to: 12 - type: string + Parameter C_DATA_IP_PATH_WIDTHS bound to: 12 - type: string + Parameter C_DATA_PX_PATH_WIDTHS bound to: 12 - type: string + Parameter C_DATA_WIDTH bound to: 12 - type: integer + Parameter C_COEF_PATH_WIDTHS bound to: 2 - type: string + Parameter C_COEF_WIDTH bound to: 2 - type: integer + Parameter C_DATA_PATH_SRC bound to: 0 - type: string + Parameter C_COEF_PATH_SRC bound to: 0 - type: string + Parameter C_PX_PATH_SRC bound to: 0 - type: string + Parameter C_DATA_PATH_SIGN bound to: 0 - type: string + Parameter C_COEF_PATH_SIGN bound to: 0 - type: string + Parameter C_ACCUM_PATH_WIDTHS bound to: 23 - type: string + Parameter C_OUTPUT_WIDTH bound to: 23 - type: integer + Parameter C_OUTPUT_PATH_WIDTHS bound to: 23 - type: string + Parameter C_ACCUM_OP_PATH_WIDTHS bound to: 23 - type: string + Parameter C_EXT_MULT_CNFG bound to: none - type: string + Parameter C_DATA_PATH_PSAMP_SRC bound to: 0 - type: string + Parameter C_OP_PATH_PSAMP_SRC bound to: 0 - type: string + Parameter C_NUM_MADDS bound to: 128 - type: integer + Parameter C_OPT_MADDS bound to: none - type: string + Parameter C_OVERSAMPLING_RATE bound to: 16 - type: integer + Parameter C_INPUT_RATE bound to: 16 - type: integer + Parameter C_OUTPUT_RATE bound to: 16 - type: integer + Parameter C_DATA_MEMTYPE bound to: 0 - type: integer + Parameter C_COEF_MEMTYPE bound to: 2 - type: integer + Parameter C_IPBUFF_MEMTYPE bound to: 2 - type: integer + Parameter C_OPBUFF_MEMTYPE bound to: 0 - type: integer + Parameter C_DATAPATH_MEMTYPE bound to: 2 - type: integer + Parameter C_MEM_ARRANGEMENT bound to: 0 - type: integer + Parameter C_DATA_MEM_PACKING bound to: 0 - type: integer + Parameter C_COEF_MEM_PACKING bound to: 0 - type: integer + Parameter C_FILTS_PACKED bound to: 0 - type: integer + Parameter C_LATENCY bound to: 151 - type: integer + Parameter C_HAS_ARESETn bound to: 1 - type: integer + Parameter C_HAS_ACLKEN bound to: 0 - type: integer + Parameter C_DATA_HAS_TLAST bound to: 0 - type: integer + Parameter C_S_DATA_HAS_FIFO bound to: 0 - type: integer + Parameter C_S_DATA_HAS_TUSER bound to: 0 - type: integer + Parameter C_S_DATA_TDATA_WIDTH bound to: 16 - type: integer + Parameter C_S_DATA_TUSER_WIDTH bound to: 1 - type: integer + Parameter C_M_DATA_HAS_TREADY bound to: 0 - type: integer + Parameter C_M_DATA_HAS_TUSER bound to: 0 - type: integer + Parameter C_M_DATA_TDATA_WIDTH bound to: 24 - type: integer + Parameter C_M_DATA_TUSER_WIDTH bound to: 1 - type: integer + Parameter C_HAS_CONFIG_CHANNEL bound to: 0 - type: integer + Parameter C_CONFIG_SYNC_MODE bound to: 0 - type: integer + Parameter C_CONFIG_PACKET_SIZE bound to: 0 - type: integer + Parameter C_CONFIG_TDATA_WIDTH bound to: 1 - type: integer + Parameter C_RELOAD_TDATA_WIDTH bound to: 1 - type: integer +INFO: [Synth 8-3491] module 'fir_compiler_v7_2_12' declared at '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/hdl/fir_compiler_v7_2_vh_rfs.vhd:61264' bound to instance 'U0' of component 'fir_compiler_v7_2_12' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/synth/fir_prbs10_invert_rep2.vhd:201] +WARNING: [Synth 8-5858] RAM p_path_out_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers +INFO: [Synth 8-256] done synthesizing module 'fir_prbs10_invert_rep2' (12#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/synth/fir_prbs10_invert_rep2.vhd:71] +WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port WE +WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port CE +WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port SCLR +WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port SCLR_ALT +WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port CLK +WARNING: [Synth 8-3331] design cntrl_delay__parameterized0 has unconnected port CE +WARNING: [Synth 8-3331] design cntrl_delay__parameterized0 has unconnected port SCLR +WARNING: [Synth 8-3331] design cntrl_delay__parameterized0 has unconnected port CLK +WARNING: [Synth 8-3331] design delay__parameterized7 has unconnected port SCLR_ALT +WARNING: [Synth 8-3331] design buff has unconnected port RE +WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port WE +WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port CE +WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port SCLR +WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port SCLR_ALT +WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port CLK +WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port WE +WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port CE +WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port SCLR +WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port SCLR_ALT +WARNING: [Synth 8-3331] design delay__parameterized13 has unconnected port CLK +WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port PRE_ADDSUB +WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port PRE_ADD_BYPASS +WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port CED +WARNING: [Synth 8-3331] design delay__parameterized12 has unconnected port WE +WARNING: [Synth 8-3331] design delay__parameterized12 has unconnected port CE +WARNING: [Synth 8-3331] design delay__parameterized12 has unconnected port SCLR +WARNING: [Synth 8-3331] design delay__parameterized12 has unconnected port SCLR_ALT +WARNING: [Synth 8-3331] design delay__parameterized12 has unconnected port CLK +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][57] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][56] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][55] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][54] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][53] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][52] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][51] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][50] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][49] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][48] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][62] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][61] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][60] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][59] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][58] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][57] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][56] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][55] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][54] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][53] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][52] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][51] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][50] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][49] +WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][48] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][57] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][56] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][55] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][54] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][53] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][52] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][51] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][50] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][49] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][48] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][47] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][46] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][45] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][44] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][43] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][42] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][41] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][40] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][39] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][38] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][37] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][36] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][35] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][34] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][33] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][32] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][31] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][30] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][29] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][28] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][27] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][26] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][25] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][24] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][23] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][22] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][21] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][20] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][19] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][18] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][17] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][16] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][15] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][14] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][13] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][12] +WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][11] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1999.215 ; gain = 326.438 ; free physical = 688 ; free virtual = 44128 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2017.027 ; gain = 344.250 ; free physical = 717 ; free virtual = 44157 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2017.027 ; gain = 344.250 ; free physical = 717 ; free virtual = 44157 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 129 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/constraints/fir_compiler_v7_2.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs10_invert_rep2/constraints/fir_compiler_v7_2.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2221.684 ; gain = 0.000 ; free physical = 513 ; free virtual = 43960 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2236.527 ; gain = 14.844 ; free physical = 511 ; free virtual = 43958 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 693 ; free virtual = 44140 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k410tffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 693 ; free virtual = 44140 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 693 ; free virtual = 44140 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic +INFO: [Common 17-14] Message 'Synth 8-5542' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 608 ; free virtual = 44058 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 1540 (col length:140) +BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs +INFO: [Common 17-14] Message 'Synth 8-5587' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_cntrl_signals[4].i_delay/gen_dly.gen_regs.delay_bus_reg[0][0]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.i_cntrl_cntrl_mem_we/gen_reg.d_reg_reg[0]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.sclr_cntrl_algn_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_accum_cntrl.accum_opcode_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_semi_parallel_and_smac.chan_max_early_reg ) +INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[22]' (FDRE) to 'U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[23]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tlast_int_reg ) +INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.base_max_cntrl_reg' (FDR) to 'U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.base_max_reg' +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 614 ; free virtual = 44080 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 480 ; free virtual = 43952 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 483 ; free virtual = 43929 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][6] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][5] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][4] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][2] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][11] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9] cannot be supported because of smaller than expected depth of fanout-free flop chain. +WARNING: [Synth 8-5591] srl_style attribute value srl_reg on U0/i_synth/g_single_rate.i_single_rate/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][8] cannot be supported because of smaller than expected depth of fanout-free flop chain. +INFO: [Common 17-14] Message 'Synth 8-5591' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 469 ; free virtual = 43914 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 466 ; free virtual = 43913 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 465 ; free virtual = 43912 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 460 ; free virtual = 43910 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 460 ; free virtual = 43910 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 459 ; free virtual = 43910 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 459 ; free virtual = 43909 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+----------+------+ +| |Cell |Count | ++------+----------+------+ +|1 |DSP48E1 | 128| +|2 |DSP48E1_1 | 1| +|3 |LUT1 | 5| +|4 |LUT2 | 24| +|5 |LUT3 | 133| +|6 |LUT4 | 11| +|7 |LUT5 | 3| +|8 |LUT6 | 6| +|9 |SRL16E | 1542| +|10 |SRLC32E | 15| +|11 |FDRE | 6200| +|12 |FDSE | 7| ++------+----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 459 ; free virtual = 43909 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 3588 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2236.527 ; gain = 344.250 ; free physical = 512 ; free virtual = 43962 +Synthesis Optimization Complete : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2236.527 ; gain = 563.750 ; free physical = 512 ; free virtual = 43962 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 129 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2236.527 ; gain = 0.000 ; free physical = 483 ; free virtual = 43767 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +234 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2236.527 ; gain = 840.551 ; free physical = 600 ; free virtual = 43884 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2236.527 ; gain = 0.000 ; free physical = 600 ; free virtual = 43884 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP fir_prbs10_invert_rep2, cache-ID = 8cd2f1d8d3f01d35 +INFO: [Coretcl 2-1174] Renamed 910 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2260.539 ; gain = 0.000 ; free physical = 549 ; free virtual = 43855 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file fir_prbs10_invert_rep2_utilization_synth.rpt -pb fir_prbs10_invert_rep2_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri May 12 16:05:15 2023... diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.v new file mode 100644 index 00000000..a873d67d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7eebab10140c57d453e3d92224f3b5fec9139fc31309a8f522a672f514788fe4 +size 6464147 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.vhdl new file mode 100644 index 00000000..eca6dd9a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8d2e59eae4787eafe8638f7fbb7dd093f1697da0b3f8c0c300c196e0cc4ebfb2 +size 9196281 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.v similarity index 59% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.v rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.v index 8dea4d6d..91a01ee8 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.v @@ -1,11 +1,11 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 00:29:10 2023 +// Date : Fri May 12 16:05:14 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.v -// Design : dds_32b_8b_comp +// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.v +// Design : fir_prbs10_invert_rep2 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 // -------------------------------------------------------------------------------- @@ -13,16 +13,15 @@ // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "dds_compiler_v6_0_18,Vivado 2019.1.3" *) -module dds_32b_8b_comp(aclk, s_axis_config_tvalid, - s_axis_config_tdata, m_axis_data_tvalid, m_axis_data_tdata, m_axis_phase_tvalid, - m_axis_phase_tdata) -/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tvalid,s_axis_config_tdata[63:0],m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0]" */; +(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) +module fir_prbs10_invert_rep2(aresetn, aclk, s_axis_data_tvalid, + s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) +/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */; + input aresetn; input aclk; - input s_axis_config_tvalid; - input [63:0]s_axis_config_tdata; + input s_axis_data_tvalid; + output s_axis_data_tready; + input [15:0]s_axis_data_tdata; output m_axis_data_tvalid; - output [15:0]m_axis_data_tdata; - output m_axis_phase_tvalid; - output [31:0]m_axis_phase_tdata; + output [23:0]m_axis_data_tdata; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/dds_32b_8b_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.vhdl similarity index 55% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/dds_32b_8b_comp_stub.vhdl rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.vhdl index 4db19e1c..656c5a79 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp/dds_32b_8b_comp_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.vhdl @@ -1,36 +1,36 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 00:29:10 2023 +-- Date : Fri May 12 16:05:14 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.vhdl --- Design : dds_32b_8b_comp +-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.vhdl +-- Design : fir_prbs10_invert_rep2 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -entity dds_32b_8b_comp is +entity fir_prbs10_invert_rep2 is Port ( + aresetn : in STD_LOGIC; aclk : in STD_LOGIC; - s_axis_config_tvalid : in STD_LOGIC; - s_axis_config_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_data_tvalid : in STD_LOGIC; + s_axis_data_tready : out STD_LOGIC; + s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); - m_axis_phase_tvalid : out STD_LOGIC; - m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) + m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ) ); -end dds_32b_8b_comp; +end fir_prbs10_invert_rep2; -architecture stub of dds_32b_8b_comp is +architecture stub of fir_prbs10_invert_rep2 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_config_tvalid,s_axis_config_tdata[63:0],m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0]"; +attribute black_box_pad_pin of stub : architecture is "aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]"; attribute x_core_info : string; -attribute x_core_info of stub : architecture is "dds_compiler_v6_0_18,Vivado 2019.1.3"; +attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; begin end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_utilization_synth.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_utilization_synth.pb new file mode 100644 index 00000000..0159a658 Binary files /dev/null and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_utilization_synth.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_utilization_synth.rpt new file mode 100644 index 00000000..bf1bb9d1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_utilization_synth.rpt @@ -0,0 +1,186 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Fri May 12 16:05:14 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file fir_prbs10_invert_rep2_utilization_synth.rpt -pb fir_prbs10_invert_rep2_utilization_synth.pb +| Design : fir_prbs10_invert_rep2 +| Device : 7k410tffg900-2 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 1720 | 0 | 254200 | 0.68 | +| LUT as Logic | 163 | 0 | 254200 | 0.06 | +| LUT as Memory | 1557 | 0 | 90600 | 1.72 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 1557 | 0 | | | +| Slice Registers | 6207 | 0 | 508400 | 1.22 | +| Register as Flip Flop | 6207 | 0 | 508400 | 1.22 | +| Register as Latch | 0 | 0 | 508400 | 0.00 | +| F7 Muxes | 0 | 0 | 127100 | 0.00 | +| F8 Muxes | 0 | 0 | 63550 | 0.00 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 7 | Yes | Set | - | +| 6200 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 795 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | +| RAMB18 | 0 | 0 | 1590 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| DSPs | 129 | 0 | 1540 | 8.38 | +| DSP48E1 only | 129 | | | | ++----------------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 500 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| PHY_CONTROL | 0 | 0 | 10 | 0.00 | +| PHASER_REF | 0 | 0 | 10 | 0.00 | +| OUT_FIFO | 0 | 0 | 40 | 0.00 | +| IN_FIFO | 0 | 0 | 40 | 0.00 | +| IDELAYCTRL | 0 | 0 | 10 | 0.00 | +| IBUFDS | 0 | 0 | 480 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 500 | 0.00 | +| OLOGIC | 0 | 0 | 500 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 40 | 0.00 | +| MMCME2_ADV | 0 | 0 | 10 | 0.00 | +| PLLE2_ADV | 0 | 0 | 10 | 0.00 | +| BUFMRCE | 0 | 0 | 20 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 40 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 6200 | Flop & Latch | +| SRL16E | 1542 | Distributed Memory | +| LUT3 | 133 | LUT | +| DSP48E1 | 129 | Block Arithmetic | +| LUT2 | 24 | LUT | +| SRLC32E | 15 | Distributed Memory | +| LUT4 | 11 | LUT | +| FDSE | 7 | Flop & Latch | +| LUT6 | 6 | LUT | +| LUT1 | 5 | LUT | +| LUT5 | 3 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/gen_run.xml new file mode 100644 index 00000000..99636dd6 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/htr.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/htr.txt new file mode 100644 index 00000000..226d7ed1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log fir_prbs10_invert_rep2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs10_invert_rep2.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/project.wdf similarity index 75% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/project.wdf rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/project.wdf index ae3f2769..8b76509e 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/project.wdf +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/project.wdf @@ -1,13 +1,13 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3630:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00 -eof:3822528465 +eof:3708762565 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/rundef.js b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/rundef.js new file mode 100644 index 00000000..4e115eae --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log fir_prbs10_invert_rep2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs10_invert_rep2.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/runme.bat b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/runme.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/runme.sh new file mode 100755 index 00000000..baae24a2 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log fir_prbs10_invert_rep2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_prbs10_invert_rep2.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/vivado.pb new file mode 100644 index 00000000..347a2a1b Binary files /dev/null and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.vivado.begin.rst index bda297bf..5af9d6c9 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.vivado.begin.rst +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml index 5456f396..8704987d 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - + + + + - - - - diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp index c1329171..4176ce0e 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:04ff89c6d963db1c918d6f03fc4adcbb009297ab76f2326029a7b0ee2b06e841 -size 6573959 +oid sha256:a5ad50c29e68927d07e763c87dc6a51b2fa8917eb40f1753f47a619c0da99afd +size 4767749 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.vds b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.vds index df681c60..8e699e42 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.vds +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.vds @@ -2,8 +2,8 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Mon May 8 12:12:10 2023 -# Process ID: 1903901 +# Start of session at: Fri May 12 16:03:35 2023 +# Process ID: 1474174 # Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1 # Command line: vivado -log ila_freq_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_freq_comp.tcl # Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.vds @@ -16,9 +16,9 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Device 21-403] Loading part xc7k410tffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 1904107 +INFO: Helper process launched with PID 1474327 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1852.848 ; gain = 161.719 ; free physical = 3468 ; free virtual = 46118 +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1852.879 ; gain = 161.688 ; free physical = 1995 ; free virtual = 45374 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'ila_freq_comp' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_freq_comp/synth/ila_freq_comp.v:84] INFO: [Synth 8-6157] synthesizing module 'CFGLUT5' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] @@ -33,14 +33,13 @@ INFO: [Synth 8-6157] synthesizing module 'SRLC16E' [/tools/Xilinx/Vivado/2019.1/ INFO: [Synth 8-6155] done synthesizing module 'SRLC16E' (27#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] INFO: [Synth 8-6157] synthesizing module 'FDRE' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] INFO: [Synth 8-6155] done synthesizing module 'FDRE' (32#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] -WARNING: [Synth 8-7023] instance 'inst' of module 'ila_v6_2_9_ila' has 1033 connections declared, but only 1027 given [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_freq_comp/synth/ila_freq_comp.v:3251] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity ila_freq_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_freq_comp/synth/ila_freq_comp.v:140] +WARNING: [Synth 8-7023] instance 'inst' of module 'ila_v6_2_9_ila' has 1033 connections declared, but only 1027 given [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_freq_comp/synth/ila_freq_comp.v:3249] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity ila_freq_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_freq_comp/synth/ila_freq_comp.v:138] INFO: [Synth 8-6155] done synthesizing module 'ila_freq_comp' (52#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_freq_comp/synth/ila_freq_comp.v:84] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MUX_RST[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MEM_LAT_RST WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MUX_REGCE[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port WE -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[15] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[14] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[13] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[12] @@ -56,89 +55,90 @@ WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4095] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4094] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4093] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4092] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4091] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4090] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4089] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4088] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4087] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4086] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4085] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4084] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4083] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4082] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4081] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4080] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4079] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4078] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4077] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4076] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4075] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4074] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4073] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4072] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4071] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4070] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4069] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4068] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4067] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4066] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4065] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4064] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4063] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4062] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4061] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4060] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4059] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4058] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4057] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4056] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4055] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4054] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4053] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4052] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4051] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4050] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4049] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4048] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4047] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4046] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4045] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4044] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4043] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4042] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4041] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4040] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4039] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4038] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4037] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4036] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4035] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4034] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4033] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4032] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4031] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4030] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4029] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4028] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4027] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4026] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4025] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4024] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4023] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4022] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4021] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4020] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4019] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4018] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4017] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[4016] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2383] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2382] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2381] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2380] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2379] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2378] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2377] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2376] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2375] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2374] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2373] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2372] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2371] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2370] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2369] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2368] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2367] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2366] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2365] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2364] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2363] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2362] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2361] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2360] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2359] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2358] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2357] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2356] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2355] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2354] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2353] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2352] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2351] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2350] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2349] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2348] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2347] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2346] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2345] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2344] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2343] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2342] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2341] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2340] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2339] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2338] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2337] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2336] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2335] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2334] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2333] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2332] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2331] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2330] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2329] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2328] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2327] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2326] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2325] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2324] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2323] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2322] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2321] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2320] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2319] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2318] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2317] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2316] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2315] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2314] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2313] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2312] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2311] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2310] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2309] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2308] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2307] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2306] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2305] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2304] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2303] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:02:45 ; elapsed = 00:02:55 . Memory (MB): peak = 2543.988 ; gain = 852.859 ; free physical = 3276 ; free virtual = 45938 +Finished RTL Elaboration : Time (s): cpu = 00:01:29 ; elapsed = 00:01:39 . Memory (MB): peak = 2359.809 ; gain = 668.617 ; free physical = 1905 ; free virtual = 45210 --------------------------------------------------------------------------------- Report Check Netlist: @@ -151,12 +151,12 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:02:46 ; elapsed = 00:02:56 . Memory (MB): peak = 2543.988 ; gain = 852.859 ; free physical = 3384 ; free virtual = 46045 +Finished Handling Custom Attributes : Time (s): cpu = 00:01:30 ; elapsed = 00:01:40 . Memory (MB): peak = 2359.809 ; gain = 668.617 ; free physical = 1980 ; free virtual = 45288 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:02:46 ; elapsed = 00:02:56 . Memory (MB): peak = 2543.988 ; gain = 852.859 ; free physical = 3384 ; free virtual = 46045 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:30 ; elapsed = 00:01:40 . Memory (MB): peak = 2359.809 ; gain = 668.617 ; free physical = 1980 ; free virtual = 45288 --------------------------------------------------------------------------------- -INFO: [Netlist 29-17] Analyzing 2232 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 1951 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization @@ -170,33 +170,32 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_onl Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2608.020 ; gain = 0.000 ; free physical = 3151 ; free virtual = 45806 +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2443.652 ; gain = 0.000 ; free physical = 1496 ; free virtual = 44808 INFO: [Project 1-111] Unisim Transformation Summary: - A total of 1312 instances were transformed. - CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 1232 instances - CFGLUT5 => SRLC32E: 80 instances + A total of 1302 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 1224 instances + CFGLUT5 => SRLC32E: 78 instances -Constraint Validation Runtime : Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2608.020 ; gain = 0.000 ; free physical = 3148 ; free virtual = 45803 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2443.652 ; gain = 0.000 ; free physical = 1494 ; free virtual = 44807 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:02:54 ; elapsed = 00:03:05 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 3370 ; free virtual = 46026 +Finished Constraint Validation : Time (s): cpu = 00:01:37 ; elapsed = 00:01:47 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 1694 ; free virtual = 45008 --------------------------------------------------------------------------------- -INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 4 processes. --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k410tffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:02:54 ; elapsed = 00:03:05 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 3370 ; free virtual = 46026 +Finished Loading Part and Timing Information : Time (s): cpu = 00:01:37 ; elapsed = 00:01:47 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 1694 ; free virtual = 45008 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for inst. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:02:54 ; elapsed = 00:03:05 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 3365 ; free virtual = 46020 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:37 ; elapsed = 00:01:47 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 1700 ; free virtual = 45013 --------------------------------------------------------------------------------- -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized79' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized80' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized77' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized78' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' @@ -275,8 +274,6 @@ INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in modul INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized74' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized75' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized76' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized77' -INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized78' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- @@ -286,7 +283,7 @@ INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in modul P2S | 0100 | 0100 S2P | 1000 | 1000 --------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized79' +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized77' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- @@ -296,7 +293,7 @@ INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in m P2S | 0100 | 0100 S2P | 1000 | 1000 --------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized80' +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized78' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- @@ -1077,98 +1074,76 @@ INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in m S2P | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized76' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized77' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- -* - IDLE | 0001 | 0001 - REG | 0010 | 0010 - P2S | 0100 | 0100 - S2P | 1000 | 1000 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized78' --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:02:59 ; elapsed = 00:03:12 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 2183 ; free virtual = 44844 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:40 ; elapsed = 00:01:52 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 1821 ; free virtual = 45157 --------------------------------------------------------------------------------- Report RTL Partitions: -+------+-------------------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+------+-------------------------+------------+----------+ -|1 |ila_v6_2_9_ila_core__GB0 | 1| 29845| -|2 |ila_v6_2_9_ila_core__GB1 | 1| 21157| -|3 |ila_v6_2_9_ila__GC0 | 1| 6| -+------+-------------------------+------------+----------+ ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 - 2 Input 16 Bit Adders := 1 + 2 Input 15 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 7 Bit Adders := 4 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 - 2 Input 4 Bit Adders := 82 + 2 Input 4 Bit Adders := 80 +---XORs : - 2 Input 13 Bit XORs := 96 + 2 Input 13 Bit XORs := 94 2 Input 1 Bit XORs := 4 +---Registers : 1024 Bit Registers := 2 304 Bit Registers := 1 297 Bit Registers := 9 128 Bit Registers := 1 - 44 Bit Registers := 33 + 42 Bit Registers := 33 33 Bit Registers := 2 - 32 Bit Registers := 17 + 32 Bit Registers := 13 24 Bit Registers := 1 - 18 Bit Registers := 36 + 18 Bit Registers := 40 17 Bit Registers := 2 - 16 Bit Registers := 311 - 12 Bit Registers := 8 - 10 Bit Registers := 16 + 16 Bit Registers := 293 + 15 Bit Registers := 9 + 12 Bit Registers := 12 + 11 Bit Registers := 16 9 Bit Registers := 1 8 Bit Registers := 1 7 Bit Registers := 5 6 Bit Registers := 2 5 Bit Registers := 1 - 4 Bit Registers := 93 - 3 Bit Registers := 4 + 4 Bit Registers := 83 + 3 Bit Registers := 8 2 Bit Registers := 6 - 1 Bit Registers := 513 + 1 Bit Registers := 495 +---Muxes : 2 Input 297 Bit Muxes := 1 2 Input 32 Bit Muxes := 12 - 2 Input 16 Bit Muxes := 96 + 2 Input 16 Bit Muxes := 94 4 Input 16 Bit Muxes := 2 3 Input 16 Bit Muxes := 1 - 8 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 82 + 2 Input 15 Bit Muxes := 80 3 Input 15 Bit Muxes := 1 + 8 Input 15 Bit Muxes := 1 3 Input 7 Bit Muxes := 1 8 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 4 2 Input 5 Bit Muxes := 2 8 Input 5 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 82 - 2 Input 4 Bit Muxes := 248 - 2 Input 3 Bit Muxes := 82 + 2 Input 4 Bit Muxes := 242 + 5 Input 4 Bit Muxes := 80 + 2 Input 3 Bit Muxes := 80 2 Input 2 Bit Muxes := 6 - 2 Input 1 Bit Muxes := 534 - 3 Input 1 Bit Muxes := 82 - 9 Input 1 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 473 4 Input 1 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 80 + 9 Input 1 Bit Muxes := 1 8 Input 1 Bit Muxes := 5 --------------------------------------------------------------------------------- Finished RTL Component Statistics @@ -1177,7 +1152,41 @@ Finished RTL Component Statistics Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report -Module xsdbs_v1_0_2_reg_p2s__parameterized79 +Module ila_v6_2_9_generic_counter +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 2 +Module ila_v6_2_9_ila_adv_trigger_sequencer +Detailed RTL Component Info : ++---Adders : + 2 Input 7 Bit Adders := 2 ++---Registers : + 24 Bit Registers := 1 + 16 Bit Registers := 1 + 7 Bit Registers := 2 + 4 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 10 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 9 + 4 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_fsm_memory_read +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 8 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized77 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 @@ -1216,35 +1225,7 @@ Detailed RTL Component Info : 1 Bit Registers := 4 +---Muxes : 2 Input 16 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_stat__97 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__96 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__95 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__94 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__93 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__92 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_ctl__11 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized75 +Module xsdbs_v1_0_2_reg__parameterized72 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 @@ -1252,107 +1233,35 @@ Module xsdbs_v1_0_2_reg_ctl__parameterized0 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized76 +Module xsdbs_v1_0_2_reg__parameterized73 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_stat__91 +Module xsdbs_v1_0_2_reg__parameterized87 Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__90 ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized88 Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__89 ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized89 Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__88 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__87 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__86 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__85 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__84 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__83 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__82 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__81 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__80 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__79 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_ctl__10 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 Module xsdbs_v1_0_2_reg__parameterized90 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__9 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 Module xsdbs_v1_0_2_reg__parameterized91 Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__8 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized92 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__7 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized93 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__6 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized94 -Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 Module xsdbs_v1_0_2_reg_ctl__parameterized1 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized95 +Module xsdbs_v1_0_2_reg__parameterized92 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 @@ -1360,79 +1269,31 @@ Module xsdbs_v1_0_2_reg_ctl__parameterized2 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized93 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized94 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized95 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 Module xsdbs_v1_0_2_reg__parameterized96 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__5 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 Module xsdbs_v1_0_2_reg__parameterized97 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__parameterized2__1 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 Module xsdbs_v1_0_2_reg__parameterized98 Detailed RTL Component Info : +---XORs : 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__4 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized99 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__3 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized100 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_ctl__2 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg__parameterized101 -Detailed RTL Component Info : -+---XORs : - 2 Input 13 Bit XORs := 1 -Module xsdbs_v1_0_2_reg_stat__78 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__77 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__76 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__75 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__74 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__73 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__72 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized80 +Module xsdbs_v1_0_2_reg_p2s__parameterized78 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 @@ -1450,298 +1311,10 @@ Detailed RTL Component Info : 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_ctl__1 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 Module xsdbs_v1_0_2_reg_stream__parameterized1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__71 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__70 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__69 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__68 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__67 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__66 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__65 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__64 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__63 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__62 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__61 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__60 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__59 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__58 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__57 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__56 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__55 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__54 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__53 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__52 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__51 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__50 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__49 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__48 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__47 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__46 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__45 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__44 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__43 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__42 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__41 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__40 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__39 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__38 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__37 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__36 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__35 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__34 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__33 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__32 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__31 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__30 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__29 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__28 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__27 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__26 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__25 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__24 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__23 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__22 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__21 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__20 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__19 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__18 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__17 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__16 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__15 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__14 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__13 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__12 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__11 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__10 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__9 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__8 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__7 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__6 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__5 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__4 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__3 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__2 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module xsdbs_v1_0_2_reg_stat__1 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 Module xsdbs_v1_0_2_reg_p2s Detailed RTL Component Info : +---Adders : @@ -3130,42 +2703,6 @@ Detailed RTL Component Info : 3 Input 1 Bit Muxes := 1 Module xsdbs_v1_0_2_reg_p2s__parameterized76 Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized77 -Detailed RTL Component Info : -+---Adders : - 2 Input 4 Bit Adders := 1 -+---XORs : - 2 Input 13 Bit XORs := 1 -+---Registers : - 16 Bit Registers := 2 - 4 Bit Registers := 1 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 15 Bit Muxes := 1 - 5 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 3 - 2 Input 3 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 5 - 3 Input 1 Bit Muxes := 1 -Module xsdbs_v1_0_2_reg_p2s__parameterized78 -Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---XORs : @@ -3205,465 +2742,48 @@ Detailed RTL Component Info : 2 Input 5 Bit Muxes := 2 2 Input 1 Bit Muxes := 13 9 Input 1 Bit Muxes := 1 -Module ila_v6_2_9_ila_fsm_memory_read -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 2 - 8 Bit Registers := 1 - 1 Bit Registers := 2 -+---Muxes : - 2 Input 16 Bit Muxes := 1 -Module ila_v6_2_9_ila_adv_trigger_sequencer -Detailed RTL Component Info : -+---Adders : - 2 Input 7 Bit Adders := 2 -+---Registers : - 24 Bit Registers := 1 - 16 Bit Registers := 1 - 7 Bit Registers := 2 - 4 Bit Registers := 1 - 2 Bit Registers := 1 - 1 Bit Registers := 10 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 1 - 2 Input 2 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 9 - 4 Input 1 Bit Muxes := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__5 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__1 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__60 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__1 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__61 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__2 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__2 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__62 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__3 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__3 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__63 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__4 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__4 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__64 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__5 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__5 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__65 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__6 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__6 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__66 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__7 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__7 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__67 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__8 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__8 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__68 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__9 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__9 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__69 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__10 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__10 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__70 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__11 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__11 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__71 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__12 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__12 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__72 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__13 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__13 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__73 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__14 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__14 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__74 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__15 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__15 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__75 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__16 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__16 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__76 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized0__17 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized0__17 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 Module ltlib_v1_0_0_all_typeA_slice__parameterized0 Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA +Detailed RTL Component Info : ++---Registers : + 42 Bit Registers := 1 +Module ltlib_v1_0_0_match +Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module ltlib_v1_0_0_allx_typeA__parameterized0 Detailed RTL Component Info : +---Registers : - 18 Bit Registers := 2 + 1 Bit Registers := 2 Module ltlib_v1_0_0_match__parameterized0 Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__59 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized1__1 -Detailed RTL Component Info : -+---Registers : - 3 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized1__1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__4 -Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module ltlib_v1_0_0_allx_typeA__parameterized1 Detailed RTL Component Info : +---Registers : - 3 Bit Registers := 2 + 18 Bit Registers := 2 Module ltlib_v1_0_0_match__parameterized1 Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__52 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized2__1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized2__1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__53 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized2__2 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized2__2 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__54 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized2__3 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized2__3 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__55 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized2__4 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized2__4 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__56 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized2__5 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized2__5 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__57 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized2__6 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized2__6 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__48 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized3__1 -Detailed RTL Component Info : -+---Registers : - 32 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized3__1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__49 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized3__2 -Detailed RTL Component Info : -+---Registers : - 32 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized3__2 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__58 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized2__7 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized2__7 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__51 -Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module ltlib_v1_0_0_allx_typeA__parameterized2 Detailed RTL Component Info : +---Registers : - 1 Bit Registers := 2 + 11 Bit Registers := 2 Module ltlib_v1_0_0_match__parameterized2 Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__50 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized3__3 -Detailed RTL Component Info : -+---Registers : - 32 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized3__3 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__3 -Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module ltlib_v1_0_0_allx_typeA__parameterized3 Detailed RTL Component Info : +---Registers : - 32 Bit Registers := 2 + 3 Bit Registers := 2 Module ltlib_v1_0_0_match__parameterized3 Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__45 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized4__1 -Detailed RTL Component Info : -+---Registers : - 12 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized4__1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__46 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized4__2 -Detailed RTL Component Info : -+---Registers : - 12 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized4__2 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__47 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized4__3 -Detailed RTL Component Info : -+---Registers : - 12 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized4__3 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__2 -Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module ltlib_v1_0_0_allx_typeA__parameterized4 @@ -3672,486 +2792,14 @@ Detailed RTL Component Info : 12 Bit Registers := 2 Module ltlib_v1_0_0_match__parameterized4 Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__38 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized5__1 -Detailed RTL Component Info : -+---Registers : - 10 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized5__1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__39 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized5__2 -Detailed RTL Component Info : -+---Registers : - 10 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized5__2 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__40 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized5__3 -Detailed RTL Component Info : -+---Registers : - 10 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized5__3 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__41 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized5__4 -Detailed RTL Component Info : -+---Registers : - 10 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized5__4 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__42 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized5__5 -Detailed RTL Component Info : -+---Registers : - 10 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized5__5 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__43 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized5__6 -Detailed RTL Component Info : -+---Registers : - 10 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized5__6 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__44 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__parameterized5__7 -Detailed RTL Component Info : -+---Registers : - 10 Bit Registers := 2 -Module ltlib_v1_0_0_match__parameterized5__7 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__37 -Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module ltlib_v1_0_0_allx_typeA__parameterized5 Detailed RTL Component Info : +---Registers : - 10 Bit Registers := 2 + 32 Bit Registers := 2 Module ltlib_v1_0_0_match__parameterized5 Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__6 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__2 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__2 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__7 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__3 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__3 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__8 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__4 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__4 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__9 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__5 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__5 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__10 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__6 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__6 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__11 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__7 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__7 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__12 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__8 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__8 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__13 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__9 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__9 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__14 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__10 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__10 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__15 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__11 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__11 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__16 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__12 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__12 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__17 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__13 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__13 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__18 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__14 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__14 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__19 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__15 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__15 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__20 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__16 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__16 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__21 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__17 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__17 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__22 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__18 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__18 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__23 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__19 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__19 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__24 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__20 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__20 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__25 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__21 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__21 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__26 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__22 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__22 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__27 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__23 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__23 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__28 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__24 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__24 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__29 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__25 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__25 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__30 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__26 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__26 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__31 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__27 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__27 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__32 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__28 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__28 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__33 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__29 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__29 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__34 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__30 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__30 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__35 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__31 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__31 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__36 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA__32 -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match__32 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_all_typeA_slice__parameterized0__1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA -Detailed RTL Component Info : -+---Registers : - 44 Bit Registers := 1 -Module ltlib_v1_0_0_match -Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module ila_v6_2_9_ila_trigger @@ -4159,37 +2807,12 @@ Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 2 -Module ltlib_v1_0_0_async_edge_xfer__1 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 1 -+---Registers : - 1 Bit Registers := 5 -Module ltlib_v1_0_0_async_edge_xfer__2 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 1 -+---Registers : - 1 Bit Registers := 5 -Module ltlib_v1_0_0_async_edge_xfer__3 -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 1 -+---Registers : - 1 Bit Registers := 5 Module ltlib_v1_0_0_async_edge_xfer Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 1 Bit Registers := 5 -Module ltlib_v1_0_0_rising_edge_detection__1 -Detailed RTL Component Info : -+---Registers : - 2 Bit Registers := 1 - 1 Bit Registers := 1 -+---Muxes : - 2 Input 2 Bit Muxes := 2 Module ltlib_v1_0_0_rising_edge_detection Detailed RTL Component Info : +---Registers : @@ -4202,12 +2825,6 @@ Detailed RTL Component Info : +---Registers : 6 Bit Registers := 1 1 Bit Registers := 2 -Module ltlib_v1_0_0_cfglut7__1 -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 3 Module ltlib_v1_0_0_cfglut7 Detailed RTL Component Info : +---Registers : @@ -4216,32 +2833,21 @@ Detailed RTL Component Info : 2 Input 1 Bit Muxes := 3 Module ltlib_v1_0_0_cfglut6 Detailed RTL Component Info : -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module ltlib_v1_0_0_cfglut6__1 -Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module ltlib_v1_0_0_allx_typeA_nodelay Detailed RTL Component Info : +---Registers : - 16 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA_nodelay__1 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 -Module ltlib_v1_0_0_allx_typeA_nodelay__2 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 + 15 Bit Registers := 1 Module ila_v6_2_9_ila_cap_addrgen Detailed RTL Component Info : +---Registers : 33 Bit Registers := 2 - 16 Bit Registers := 4 + 16 Bit Registers := 1 + 15 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : - 2 Input 1 Bit Muxes := 16 + 2 Input 1 Bit Muxes := 15 Module ltlib_v1_0_0_cfglut6__parameterized0 Detailed RTL Component Info : +---Registers : @@ -4255,106 +2861,44 @@ Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 1 -Module blk_mem_gen_v8_4_3_bindec__3 -Detailed RTL Component Info : -+---Muxes : - 2 Input 1 Bit Muxes := 16 Module blk_mem_gen_v8_4_3_bindec Detailed RTL Component Info : +---Muxes : - 2 Input 1 Bit Muxes := 16 -Module blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized1 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 4 Bit Registers := 2 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized2 -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 4 Bit Registers := 2 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module blk_mem_gen_v8_4_3_bindec__1 -Detailed RTL Component Info : -+---Muxes : - 2 Input 1 Bit Muxes := 16 -Module blk_mem_gen_v8_4_3_bindec__2 -Detailed RTL Component Info : -+---Muxes : - 2 Input 1 Bit Muxes := 16 + 2 Input 1 Bit Muxes := 8 Module blk_mem_gen_v8_4_3_blk_mem_gen_mux Detailed RTL Component Info : +---Registers : - 16 Bit Registers := 1 - 4 Bit Registers := 2 + 15 Bit Registers := 1 + 3 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 1 Module blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 Detailed RTL Component Info : +---Registers : - 16 Bit Registers := 1 - 4 Bit Registers := 2 + 15 Bit Registers := 1 + 3 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ltlib_v1_0_0_generic_memrd Detailed RTL Component Info : +---Adders : - 2 Input 16 Bit Adders := 1 + 2 Input 15 Bit Adders := 1 2 Input 5 Bit Adders := 1 +---Registers : 304 Bit Registers := 1 - 16 Bit Registers := 1 + 15 Bit Registers := 1 7 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 2 1 Bit Registers := 3 +---Muxes : - 8 Input 16 Bit Muxes := 1 + 8 Input 15 Bit Muxes := 1 3 Input 7 Bit Muxes := 1 8 Input 7 Bit Muxes := 1 8 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 8 Input 1 Bit Muxes := 5 -Module ila_v6_2_9_generic_counter__1 -Detailed RTL Component Info : -+---Adders : - 2 Input 32 Bit Adders := 1 -+---Registers : - 32 Bit Registers := 2 -+---Muxes : - 2 Input 32 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 2 -Module ila_v6_2_9_generic_counter__2 -Detailed RTL Component Info : -+---Adders : - 2 Input 32 Bit Adders := 1 -+---Registers : - 32 Bit Registers := 2 -+---Muxes : - 2 Input 32 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 2 -Module ila_v6_2_9_generic_counter__3 -Detailed RTL Component Info : -+---Adders : - 2 Input 32 Bit Adders := 1 -+---Registers : - 32 Bit Registers := 2 -+---Muxes : - 2 Input 32 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 2 -Module ila_v6_2_9_generic_counter -Detailed RTL Component Info : -+---Adders : - 2 Input 32 Bit Adders := 1 -+---Registers : - 32 Bit Registers := 2 -+---Muxes : - 2 Input 32 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 2 Module ila_v6_2_9_ila_core Detailed RTL Component Info : +---Registers : @@ -4385,181 +2929,181 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1008] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1008] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1009] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1009] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1010] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1010] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1011] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1011] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1012] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1012] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1013] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1013] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1014] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1014] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1015] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1015] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1016] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1016] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1017] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1017] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1018] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1018] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1019] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1019] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1020] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1020] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1021] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1021] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1022] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1022] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg1_reg[1023] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\shift_reg0_reg[1023] ) -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[0]' (FDRE) to 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[5]' -INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[0] ) -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[38].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[34].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[32].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[30].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[28].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[26].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[36].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[24].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[1]' (FDRE) to 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[4]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[1] ) -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[38].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[34].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[32].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[30].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[28].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[26].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[36].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[24].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[2]' (FDRE) to 'inst/ila_core_insti_1/u_ila_regs/slaveRegDo_ff8_reg[4]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[2] ) -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[38].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[34].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[32].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[30].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[28].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[26].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[36].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[24].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[42].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/ila_core_insti_1/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_insti_1/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1023] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1023] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[0]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[5]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[0] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[38].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[34].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[32].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[30].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[28].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[26].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[24].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[36].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[1]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[1] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[38].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[34].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[32].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[30].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[28].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[26].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[24].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[36].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[2]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[2] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[38].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[34].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[32].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[30].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[28].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[26].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[20].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[24].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[22].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[40].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[36].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[3] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/ila_core_insti_1/u_ila_regs/\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[8] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[9] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[10] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[11] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[12] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[13] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff8_reg[14] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[14] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_ff7_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[8] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[9] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[10] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[11] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[12] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[13] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[14] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/ila_core_insti_1/u_ila_regs/\slaveRegDo_mux_1_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff8_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[15] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[15] ) --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:03:10 ; elapsed = 00:03:31 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 810 ; free virtual = 43402 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:50 ; elapsed = 00:02:03 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 884 ; free virtual = 44281 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: Preliminary Mapping Report (see note below) -+------------+--------------------------------------+----------------+----------------------+---------------+ -|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | -+------------+--------------------------------------+----------------+----------------------+---------------+ -|inst | ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | -+------------+--------------------------------------+----------------+----------------------+---------------+ ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|inst | ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- @@ -4567,53 +3111,47 @@ Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: -+------+-------------------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+------+-------------------------+------------+----------+ -|1 |ila_v6_2_9_ila_core__GB0 | 1| 15913| -|2 |ila_v6_2_9_ila_core__GB1 | 1| 12362| -|3 |ila_v6_2_9_ila__GC0 | 1| 6| -+------+-------------------------+------------+----------+ ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:17 ; elapsed = 00:03:37 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 788 ; free virtual = 43293 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:56 ; elapsed = 00:02:08 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 558 ; free virtual = 43956 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:03:18 ; elapsed = 00:03:39 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 803 ; free virtual = 43295 +Finished Timing Optimization : Time (s): cpu = 00:01:56 ; elapsed = 00:02:09 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 543 ; free virtual = 43944 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report -+------------+--------------------------------------+----------------+----------------------+---------------+ -|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | -+------------+--------------------------------------+----------------+----------------------+---------------+ -|inst | ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | -+------------+--------------------------------------+----------------+----------------------+---------------+ ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|inst | ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: -+------+-------------------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+------+-------------------------+------------+----------+ -|1 |ila_v6_2_9_ila_core__GB0 | 1| 15913| -|2 |ila_v6_2_9_ila_core__GB1 | 1| 12362| -|3 |ila_v6_2_9_ila__GC0 | 1| 6| -+------+-------------------------+------------+----------+ ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:03:21 ; elapsed = 00:03:41 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 823 ; free virtual = 43300 +Finished Technology Mapping : Time (s): cpu = 00:01:58 ; elapsed = 00:02:11 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 559 ; free virtual = 43964 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -4633,9 +3171,9 @@ Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- -INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [9] is driving 532 big block pins (URAM, BRAM and DSP loads). Created 54 replicas of its driver. -INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [10] is driving 532 big block pins (URAM, BRAM and DSP loads). Created 54 replicas of its driver. -INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_en is driving 532 big block pins (URAM, BRAM and DSP loads). Created 54 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [9] is driving 265 big block pins (URAM, BRAM and DSP loads). Created 27 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [10] is driving 265 big block pins (URAM, BRAM and DSP loads). Created 27 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_en is driving 266 big block pins (URAM, BRAM and DSP loads). Created 27 replicas of its driver. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- @@ -4680,7 +3218,7 @@ INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 INFO: [Synth 8-3295] tying undriven pin inst:trig_in to constant 0 INFO: [Synth 8-3295] tying undriven pin inst:trig_out_ack to constant 0 --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:03:22 ; elapsed = 00:03:42 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 901 ; free virtual = 43304 +Finished IO Insertion : Time (s): cpu = 00:01:59 ; elapsed = 00:02:12 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 510 ; free virtual = 43918 --------------------------------------------------------------------------------- Report Check Netlist: @@ -4693,7 +3231,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:03:22 ; elapsed = 00:03:42 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 901 ; free virtual = 43304 +Finished Renaming Generated Instances : Time (s): cpu = 00:01:59 ; elapsed = 00:02:12 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 499 ; free virtual = 43907 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -4705,25 +3243,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:23 ; elapsed = 00:03:44 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 968 ; free virtual = 43284 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:00 ; elapsed = 00:02:13 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 530 ; free virtual = 43939 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:03:23 ; elapsed = 00:03:44 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 968 ; free virtual = 43284 +Finished Renaming Generated Ports : Time (s): cpu = 00:02:00 ; elapsed = 00:02:13 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 526 ; free virtual = 43935 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:03:23 ; elapsed = 00:03:44 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 984 ; free virtual = 43300 +Finished Handling Custom Attributes : Time (s): cpu = 00:02:00 ; elapsed = 00:02:13 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 511 ; free virtual = 43921 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:03:23 ; elapsed = 00:03:44 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 985 ; free virtual = 43301 +Finished Renaming Generated Nets : Time (s): cpu = 00:02:00 ; elapsed = 00:02:13 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 517 ; free virtual = 43927 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting @@ -4735,9 +3273,9 @@ Static Shift Register Report: +---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |ila_v6_2_9_generic_counter | counter_load_i_reg[16] | 16 | 4 | NO | NO | YES | 4 | 0 | |ila_v6_2_9_ila | ila_core_inst/u_ila_regs/adv_rb_drdy4_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | |ila_v6_2_9_ila | ila_core_inst/shifted_data_in_reg[8][296] | 9 | 297 | NO | NO | YES | 297 | 0 | -|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[3] | 3 | 1 | NO | NO | YES | 1 | 0 | -|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[3] | 3 | 1 | NO | NO | YES | 1 | 0 | +---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- @@ -4757,1835 +3295,1306 @@ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ -|1 |CARRY4 | 416| -|2 |CFGLUT5 | 1312| -|3 |LUT1 | 114| -|4 |LUT2 | 201| -|5 |LUT3 | 692| -|6 |LUT4 | 836| -|7 |LUT5 | 189| -|8 |LUT6 | 3387| -|9 |MUXF7 | 777| -|10 |MUXF8 | 338| +|1 |CARRY4 | 412| +|2 |CFGLUT5 | 1302| +|3 |LUT1 | 112| +|4 |LUT2 | 155| +|5 |LUT3 | 481| +|6 |LUT4 | 752| +|7 |LUT5 | 277| +|8 |LUT6 | 2747| +|9 |MUXF7 | 500| +|10 |MUXF8 | 17| |11 |RAM64M | 32| -|12 |RAMB36E1 | 512| -|13 |RAMB36E1_1 | 10| -|14 |RAMB36E1_2 | 10| -|15 |SRL16E | 305| -|16 |SRLC16E | 2| -|17 |SRLC32E | 17| -|18 |FDRE | 6689| -|19 |FDSE | 9| +|12 |RAMB36E1 | 1| +|13 |RAMB36E1_1 | 264| +|14 |SRL16E | 305| +|15 |SRLC16E | 2| +|16 |SRLC32E | 17| +|17 |FDRE | 6352| +|18 |FDSE | 9| +------+-----------+------+ Report Instance Areas: +------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ | |Instance |Module |Cells | +------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ -|1 |top | | 15848| -|2 | inst |ila_v6_2_9_ila | 15848| -|3 | ila_core_inst |ila_v6_2_9_ila_core | 15841| -|4 | \ADV_TRIG.u_adv_trig |ila_v6_2_9_ila_adv_trigger_sequencer | 205| +|1 |top | | 13737| +|2 | inst |ila_v6_2_9_ila | 13737| +|3 | ila_core_inst |ila_v6_2_9_ila_core | 13730| +|4 | \ADV_TRIG.u_adv_trig |ila_v6_2_9_ila_adv_trigger_sequencer | 185| |5 | \ADV_TRIG_MEM_READ.u_fsm_memory_read_inst |ila_v6_2_9_ila_fsm_memory_read | 52| |6 | \COUNTER.u_count |ila_v6_2_9_ila_counter | 232| |7 | \G_COUNTER[0].U_COUNTER |ila_v6_2_9_generic_counter__1 | 58| |8 | \G_COUNTER[1].U_COUNTER |ila_v6_2_9_generic_counter__2 | 58| |9 | \G_COUNTER[2].U_COUNTER |ila_v6_2_9_generic_counter__3 | 58| |10 | \G_COUNTER[3].U_COUNTER |ila_v6_2_9_generic_counter | 58| -|11 | ila_trace_memory_inst |ila_v6_2_9_ila_trace_memory | 2592| -|12 | \SUBCORE_RAM.BLK_MEM_GEN[0].trace_block_memory |blk_mem_gen_v8_4_3 | 2220| -|13 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 2220| -|14 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_v8_4_3_blk_mem_gen_top | 2220| -|15 | \valid.cstr |blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr | 2220| -|16 | \has_mux_b.B |blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 | 1764| -|17 | \ramloop[0].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width | 1| -|18 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper | 1| -|19 | \ramloop[100].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized99 | 1| -|20 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized99 | 1| -|21 | \ramloop[101].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized100 | 1| -|22 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized100 | 1| -|23 | \ramloop[102].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized101 | 1| -|24 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized101 | 1| -|25 | \ramloop[103].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized102 | 1| -|26 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized102 | 1| -|27 | \ramloop[104].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized103 | 1| -|28 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized103 | 1| -|29 | \ramloop[105].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized104 | 1| -|30 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized104 | 1| -|31 | \ramloop[106].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized105 | 1| -|32 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized105 | 1| -|33 | \ramloop[107].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized106 | 1| -|34 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized106 | 1| -|35 | \ramloop[108].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized107 | 1| -|36 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized107 | 1| -|37 | \ramloop[109].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized108 | 1| -|38 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized108 | 1| -|39 | \ramloop[10].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized9 | 1| -|40 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized9 | 1| -|41 | \ramloop[110].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized109 | 1| -|42 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized109 | 1| -|43 | \ramloop[111].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized110 | 1| -|44 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized110 | 1| -|45 | \ramloop[112].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized111 | 1| -|46 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized111 | 1| -|47 | \ramloop[113].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized112 | 1| -|48 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized112 | 1| -|49 | \ramloop[114].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized113 | 1| -|50 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized113 | 1| -|51 | \ramloop[115].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized114 | 1| -|52 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized114 | 1| -|53 | \ramloop[116].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized115 | 1| -|54 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized115 | 1| -|55 | \ramloop[117].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized116 | 1| -|56 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized116 | 1| -|57 | \ramloop[118].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized117 | 1| -|58 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized117 | 1| -|59 | \ramloop[119].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized118 | 1| -|60 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized118 | 1| -|61 | \ramloop[11].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized10 | 1| -|62 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized10 | 1| -|63 | \ramloop[120].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized119 | 1| -|64 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized119 | 1| -|65 | \ramloop[121].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized120 | 1| -|66 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized120 | 1| -|67 | \ramloop[122].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized121 | 1| -|68 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized121 | 1| -|69 | \ramloop[123].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized122 | 1| -|70 | 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized127 | 1| -|81 | \ramloop[129].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized128 | 1| -|82 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized128 | 1| -|83 | \ramloop[12].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized11 | 1| -|84 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized11 | 1| -|85 | \ramloop[130].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized129 | 1| -|86 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized129 | 1| -|87 | \ramloop[131].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized130 | 1| -|88 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized130 | 1| -|89 | \ramloop[132].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized131 | 1| -|90 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized131 | 1| -|91 | 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized137 | 1| -|102 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized137 | 1| -|103 | \ramloop[139].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized138 | 1| -|104 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized138 | 1| -|105 | \ramloop[13].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized12 | 1| -|106 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized12 | 1| -|107 | \ramloop[140].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized139 | 1| -|108 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized139 | 1| -|109 | \ramloop[141].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized140 | 1| -|110 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized140 | 1| -|111 | \ramloop[142].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized141 | 1| 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized146 | 1| -|123 | \ramloop[148].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized147 | 1| -|124 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized147 | 1| -|125 | \ramloop[149].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized148 | 1| -|126 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized148 | 1| -|127 | \ramloop[14].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized13 | 1| -|128 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized13 | 1| -|129 | \ramloop[150].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized149 | 1| -|130 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized149 | 1| -|131 | \ramloop[151].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized150 | 1| -|132 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized150 | 1| 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized156 | 1| -|144 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized156 | 1| -|145 | \ramloop[158].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized157 | 1| -|146 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized157 | 1| -|147 | \ramloop[159].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized158 | 1| -|148 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized158 | 1| -|149 | \ramloop[15].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized14 | 1| -|150 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized14 | 1| -|151 | \ramloop[160].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized159 | 1| -|152 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized159 | 1| -|153 | \ramloop[161].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized160 | 1| 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized165 | 1| -|165 | \ramloop[167].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized166 | 1| -|166 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized166 | 1| -|167 | \ramloop[168].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized167 | 1| -|168 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized167 | 1| -|169 | \ramloop[169].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized168 | 1| -|170 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized168 | 1| -|171 | \ramloop[16].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized15 | 1| -|172 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized15 | 1| -|173 | \ramloop[170].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized169 | 1| -|174 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized169 | 1| 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized175 | 1| -|186 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized175 | 1| -|187 | \ramloop[177].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized176 | 1| -|188 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized176 | 1| -|189 | \ramloop[178].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized177 | 1| -|190 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized177 | 1| -|191 | \ramloop[179].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized178 | 1| -|192 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized178 | 1| -|193 | \ramloop[17].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized16 | 1| -|194 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized16 | 1| -|195 | \ramloop[180].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized179 | 1| -|196 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized179 | 1| -|197 | \ramloop[181].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized180 | 1| -|198 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized180 | 1| -|199 | \ramloop[182].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized181 | 1| -|200 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized181 | 1| -|201 | \ramloop[183].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized182 | 1| -|202 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized182 | 1| -|203 | \ramloop[184].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized183 | 1| -|204 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized183 | 1| -|205 | \ramloop[185].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized184 | 1| -|206 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized184 | 1| -|207 | \ramloop[186].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized185 | 1| -|208 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized185 | 1| -|209 | \ramloop[187].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized186 | 1| -|210 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized186 | 1| -|211 | \ramloop[188].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized187 | 1| -|212 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized187 | 1| -|213 | \ramloop[189].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized188 | 1| -|214 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized188 | 1| -|215 | \ramloop[18].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized17 | 1| -|216 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized17 | 1| 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized392 | 1| -|669 | \ramloop[394].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized393 | 1| -|670 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized393 | 1| -|671 | \ramloop[395].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized394 | 1| -|672 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized394 | 1| -|673 | \ramloop[396].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized395 | 1| -|674 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized395 | 1| -|675 | \ramloop[397].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized396 | 1| -|676 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized396 | 1| -|677 | \ramloop[398].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized397 | 1| -|678 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized397 | 1| -|679 | \ramloop[399].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized398 | 1| -|680 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized398 | 1| -|681 | \ramloop[39].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized38 | 1| -|682 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized38 | 1| -|683 | \ramloop[3].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized2 | 1| -|684 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 | 1| -|685 | \ramloop[400].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized399 | 1| -|686 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized399 | 1| -|687 | \ramloop[401].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized400 | 1| -|688 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized400 | 1| -|689 | \ramloop[402].ram.r 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-|700 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized406 | 1| -|701 | \ramloop[408].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized407 | 1| -|702 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized407 | 1| -|703 | \ramloop[409].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized408 | 1| -|704 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized408 | 1| -|705 | \ramloop[40].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized39 | 1| -|706 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized39 | 1| -|707 | \ramloop[410].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized409 | 1| -|708 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized409 | 1| -|709 | \ramloop[411].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized410 | 1| -|710 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized410 | 1| -|711 | \ramloop[412].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized411 | 1| -|712 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized411 | 1| -|713 | \ramloop[413].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized412 | 1| -|714 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized412 | 1| -|715 | \ramloop[414].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized413 | 1| -|716 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized413 | 1| -|717 | \ramloop[415].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized414 | 1| -|718 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized414 | 1| -|719 | \ramloop[416].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized415 | 1| -|720 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized415 | 1| -|721 | \ramloop[417].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized416 | 1| -|722 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized416 | 1| -|723 | \ramloop[418].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized417 | 1| -|724 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized417 | 1| -|725 | \ramloop[419].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized418 | 1| -|726 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized418 | 1| -|727 | \ramloop[41].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized40 | 1| -|728 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized40 | 1| -|729 | \ramloop[420].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized419 | 1| -|730 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized419 | 1| -|731 | \ramloop[421].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized420 | 1| -|732 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized420 | 1| -|733 | \ramloop[422].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized421 | 1| -|734 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized421 | 1| -|735 | \ramloop[423].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized422 | 1| -|736 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized422 | 1| -|737 | \ramloop[424].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized423 | 1| -|738 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized423 | 1| -|739 | \ramloop[425].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized424 | 1| -|740 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized424 | 1| -|741 | \ramloop[426].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized425 | 1| -|742 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized425 | 1| -|743 | \ramloop[427].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized426 | 1| -|744 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized426 | 1| -|745 | \ramloop[428].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized427 | 1| -|746 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized427 | 1| -|747 | \ramloop[429].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized428 | 1| -|748 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized428 | 1| -|749 | \ramloop[42].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized41 | 1| -|750 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized41 | 1| -|751 | \ramloop[430].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized429 | 1| -|752 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized429 | 1| -|753 | \ramloop[431].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized430 | 1| -|754 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized430 | 1| -|755 | \ramloop[432].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized431 | 1| -|756 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized431 | 1| -|757 | \ramloop[433].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized432 | 1| -|758 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized432 | 1| -|759 | \ramloop[434].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized433 | 1| -|760 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized433 | 1| -|761 | \ramloop[435].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized434 | 1| -|762 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized434 | 1| -|763 | \ramloop[436].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized435 | 1| -|764 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized435 | 1| -|765 | \ramloop[437].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized436 | 1| -|766 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized436 | 1| -|767 | \ramloop[438].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized437 | 1| -|768 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized437 | 1| -|769 | \ramloop[439].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized438 | 1| -|770 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized438 | 1| -|771 | \ramloop[43].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized42 | 1| -|772 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized42 | 1| -|773 | \ramloop[440].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized439 | 1| -|774 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized439 | 1| -|775 | \ramloop[441].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized440 | 1| -|776 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized440 | 1| -|777 | \ramloop[442].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized441 | 1| -|778 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized441 | 1| -|779 | \ramloop[443].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized442 | 1| -|780 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized442 | 1| -|781 | \ramloop[444].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized443 | 1| -|782 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized443 | 1| -|783 | \ramloop[445].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized444 | 1| -|784 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized444 | 1| -|785 | \ramloop[446].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized445 | 1| -|786 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized445 | 1| -|787 | \ramloop[447].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized446 | 1| -|788 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized446 | 1| -|789 | \ramloop[448].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized447 | 2| -|790 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized447 | 2| -|791 | \ramloop[449].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized448 | 2| -|792 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized448 | 2| -|793 | \ramloop[44].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized43 | 1| -|794 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized43 | 1| -|795 | \ramloop[450].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized449 | 2| -|796 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized449 | 2| -|797 | \ramloop[451].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized450 | 2| -|798 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized450 | 2| -|799 | \ramloop[45].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized44 | 1| -|800 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized44 | 1| -|801 | \ramloop[46].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized45 | 1| -|802 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized45 | 1| -|803 | \ramloop[47].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized46 | 1| -|804 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized46 | 1| -|805 | \ramloop[48].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized47 | 1| -|806 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized47 | 1| -|807 | \ramloop[49].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized48 | 1| -|808 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized48 | 1| -|809 | \ramloop[4].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized3 | 1| -|810 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized3 | 1| -|811 | \ramloop[50].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized49 | 1| -|812 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized49 | 1| -|813 | \ramloop[51].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized50 | 1| -|814 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized50 | 1| -|815 | \ramloop[52].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized51 | 1| -|816 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized51 | 1| -|817 | \ramloop[53].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized52 | 1| -|818 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized52 | 1| -|819 | \ramloop[54].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized53 | 1| -|820 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized53 | 1| -|821 | \ramloop[55].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized54 | 1| -|822 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized54 | 1| -|823 | \ramloop[56].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized55 | 1| -|824 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized55 | 1| -|825 | \ramloop[57].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized56 | 1| -|826 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized56 | 1| -|827 | \ramloop[58].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized57 | 1| -|828 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized57 | 1| -|829 | \ramloop[59].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized58 | 1| -|830 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized58 | 1| -|831 | \ramloop[5].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized4 | 1| -|832 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized4 | 1| -|833 | \ramloop[60].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized59 | 1| -|834 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized59 | 1| -|835 | \ramloop[61].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized60 | 1| -|836 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized60 | 1| -|837 | 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1| -|848 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized66 | 1| -|849 | \ramloop[68].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized67 | 1| -|850 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized67 | 1| -|851 | \ramloop[69].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized68 | 1| -|852 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized68 | 1| -|853 | \ramloop[6].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized5 | 1| -|854 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized5 | 1| -|855 | \ramloop[70].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized69 | 1| -|856 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized69 | 1| -|857 | \ramloop[71].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized70 | 1| -|858 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized70 | 1| -|859 | \ramloop[72].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized71 | 1| -|860 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized71 | 1| -|861 | \ramloop[73].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized72 | 1| -|862 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized72 | 1| -|863 | \ramloop[74].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized73 | 1| -|864 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized73 | 1| -|865 | \ramloop[75].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized74 | 1| -|866 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized74 | 1| -|867 | \ramloop[76].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized75 | 1| -|868 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized75 | 1| -|869 | \ramloop[77].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized76 | 1| -|870 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized76 | 1| -|871 | \ramloop[78].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized77 | 1| -|872 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized77 | 1| -|873 | \ramloop[79].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized78 | 1| -|874 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized78 | 1| -|875 | \ramloop[7].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized6 | 1| -|876 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized6 | 1| -|877 | \ramloop[80].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized79 | 1| -|878 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized79 | 1| -|879 | \ramloop[81].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized80 | 1| -|880 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized80 | 1| -|881 | \ramloop[82].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized81 | 1| -|882 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized81 | 1| -|883 | \ramloop[83].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized82 | 1| -|884 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized82 | 1| -|885 | \ramloop[84].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized83 | 1| -|886 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized83 | 1| -|887 | \ramloop[85].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized84 | 1| -|888 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized84 | 1| -|889 | \ramloop[86].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized85 | 1| -|890 | \prim_noinit.ram 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized482 | 1| -|976 | \ramloop[32].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized483 | 1| -|977 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized483 | 1| -|978 | \ramloop[33].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized484 | 1| -|979 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized484 | 1| -|980 | \ramloop[34].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized485 | 1| -|981 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized485 | 1| -|982 | \ramloop[35].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized486 | 1| -|983 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized486 | 1| -|984 | \ramloop[36].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized487 | 1| -|985 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized487 | 1| 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized492 | 1| -|997 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized492 | 1| -|998 | \ramloop[42].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized493 | 1| -|999 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized493 | 1| -|1000 | \ramloop[43].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized494 | 1| -|1001 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized494 | 1| -|1002 | \ramloop[44].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized495 | 1| -|1003 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized495 | 1| -|1004 | \ramloop[45].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized496 | 1| -|1005 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized496 | 1| -|1006 | \ramloop[46].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized497 | 1| -|1007 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized497 | 1| -|1008 | \ramloop[47].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized498 | 1| -|1009 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized498 | 1| -|1010 | \ramloop[48].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized499 | 1| -|1011 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized499 | 1| -|1012 | \ramloop[49].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized500 | 1| -|1013 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized500 | 1| -|1014 | \ramloop[4].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized455 | 1| -|1015 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized455 | 1| -|1016 | \ramloop[50].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized501 | 1| -|1017 | \prim_noinit.ram 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|blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized456 | 1| -|1038 | \ramloop[60].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized511 | 1| -|1039 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized511 | 1| -|1040 | \ramloop[61].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized512 | 1| -|1041 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized512 | 1| -|1042 | \ramloop[62].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized513 | 1| -|1043 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized513 | 1| -|1044 | \ramloop[63].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized514 | 1| -|1045 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized514 | 1| -|1046 | \ramloop[64].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized515 | 2| -|1047 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized515 | 2| -|1048 | \ramloop[65].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized516 | 2| -|1049 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized516 | 2| -|1050 | \ramloop[66].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized517 | 2| -|1051 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized517 | 2| -|1052 | \ramloop[67].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized518 | 2| -|1053 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized518 | 2| -|1054 | \ramloop[68].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized519 | 2| -|1055 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized519 | 2| -|1056 | \ramloop[69].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized520 | 2| -|1057 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized520 | 2| -|1058 | \ramloop[6].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized457 | 1| -|1059 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized457 | 1| -|1060 | \ramloop[7].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized458 | 1| -|1061 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized458 | 1| -|1062 | \ramloop[8].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized459 | 1| -|1063 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized459 | 1| -|1064 | \ramloop[9].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized460 | 1| -|1065 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized460 | 1| -|1066 | u_ila_cap_ctrl |ila_v6_2_9_ila_cap_ctrl_legacy | 333| -|1067 | U_CDONE |ltlib_v1_0_0_cfglut6__parameterized0 | 5| -|1068 | U_NS0 |ltlib_v1_0_0_cfglut7 | 8| -|1069 | U_NS1 |ltlib_v1_0_0_cfglut7_536 | 10| -|1070 | u_cap_addrgen |ila_v6_2_9_ila_cap_addrgen | 305| -|1071 | U_CMPRESET |ltlib_v1_0_0_cfglut6 | 3| -|1072 | u_cap_sample_counter |ila_v6_2_9_ila_cap_sample_counter | 71| -|1073 | U_SCE |ltlib_v1_0_0_cfglut4_543 | 1| -|1074 | U_SCMPCE |ltlib_v1_0_0_cfglut5_544 | 1| -|1075 | U_SCRST |ltlib_v1_0_0_cfglut6_545 | 3| -|1076 | u_scnt_cmp |ltlib_v1_0_0_match_nodelay_546 | 28| -|1077 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_547 | 28| -|1078 | DUT |ltlib_v1_0_0_all_typeA__parameterized4_548 | 12| -|1079 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_549 | 5| -|1080 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_550 | 5| -|1081 | u_cap_window_counter |ila_v6_2_9_ila_cap_window_counter | 66| -|1082 | U_WCE |ltlib_v1_0_0_cfglut4 | 1| -|1083 | U_WHCMPCE |ltlib_v1_0_0_cfglut5 | 1| -|1084 | U_WLCMPCE |ltlib_v1_0_0_cfglut5_537 | 1| -|1085 | u_wcnt_hcmp |ltlib_v1_0_0_match_nodelay | 12| -|1086 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_539 | 12| -|1087 | DUT |ltlib_v1_0_0_all_typeA__parameterized4_540 | 12| -|1088 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_541 | 5| -|1089 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_542 | 5| -|1090 | u_wcnt_lcmp |ltlib_v1_0_0_match_nodelay_538 | 28| -|1091 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay | 28| -|1092 | DUT |ltlib_v1_0_0_all_typeA__parameterized4 | 12| -|1093 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1 | 5| -|1094 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2 | 5| -|1095 | u_ila_regs |ila_v6_2_9_ila_register | 7890| -|1096 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 302| -|1097 | reg_890 |xsdbs_v1_0_2_reg__parameterized108 | 16| -|1098 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_535 | 16| -|1099 | \ADV_TRIG_STREAM.reg_stream_ffc |xsdbs_v1_0_2_reg_stream__parameterized0 | 24| -|1100 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_534 | 20| -|1101 | \ADV_TRIG_STREAM_READBACK.reg_stream_ffb |xsdbs_v1_0_2_reg_stream | 36| -|1102 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_533 | 36| -|1103 | \CNT.CNT_SRL[0].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized75 | 75| -|1104 | \CNT.CNT_SRL[1].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized76 | 75| -|1105 | \CNT.CNT_SRL[2].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized77 | 105| -|1106 | \CNT.CNT_SRL[3].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized78 | 76| -|1107 | \MU_SRL[0].mu_srl_reg |xsdbs_v1_0_2_reg_p2s | 76| -|1108 | \MU_SRL[10].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized9 | 74| -|1109 | \MU_SRL[11].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized10 | 106| -|1110 | \MU_SRL[12].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized11 | 74| -|1111 | \MU_SRL[13].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized12 | 74| -|1112 | \MU_SRL[14].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized13 | 74| -|1113 | \MU_SRL[15].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized14 | 90| -|1114 | \MU_SRL[16].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized15 | 74| -|1115 | \MU_SRL[17].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized16 | 74| -|1116 | \MU_SRL[18].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized17 | 74| -|1117 | \MU_SRL[19].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized18 | 122| -|1118 | \MU_SRL[1].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized0 | 75| -|1119 | \MU_SRL[20].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized19 | 74| -|1120 | \MU_SRL[21].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized20 | 74| -|1121 | \MU_SRL[22].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized21 | 74| -|1122 | \MU_SRL[23].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized22 | 90| -|1123 | \MU_SRL[24].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized23 | 74| -|1124 | \MU_SRL[25].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized24 | 74| -|1125 | \MU_SRL[26].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized25 | 74| -|1126 | \MU_SRL[27].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized26 | 106| -|1127 | \MU_SRL[28].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized27 | 74| -|1128 | \MU_SRL[29].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized28 | 74| -|1129 | \MU_SRL[2].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized1 | 75| -|1130 | \MU_SRL[30].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized29 | 74| -|1131 | \MU_SRL[31].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized30 | 90| -|1132 | \MU_SRL[32].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized31 | 74| -|1133 | \MU_SRL[33].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized32 | 74| -|1134 | \MU_SRL[34].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized33 | 74| -|1135 | \MU_SRL[35].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized34 | 122| -|1136 | \MU_SRL[36].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized35 | 74| -|1137 | \MU_SRL[37].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized36 | 74| -|1138 | \MU_SRL[38].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized37 | 74| -|1139 | \MU_SRL[39].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized38 | 90| -|1140 | \MU_SRL[3].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized2 | 123| -|1141 | \MU_SRL[40].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized39 | 74| -|1142 | \MU_SRL[41].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized40 | 74| -|1143 | \MU_SRL[42].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized41 | 74| -|1144 | \MU_SRL[43].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized42 | 90| -|1145 | \MU_SRL[4].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized3 | 74| -|1146 | \MU_SRL[5].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized4 | 74| -|1147 | \MU_SRL[6].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized5 | 74| -|1148 | \MU_SRL[7].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized6 | 90| -|1149 | \MU_SRL[8].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized7 | 74| -|1150 | \MU_SRL[9].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized8 | 74| -|1151 | \STRG_QUAL.qual_strg_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized79 | 76| -|1152 | \TC_SRL[0].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized43 | 75| -|1153 | \TC_SRL[10].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized53 | 74| -|1154 | \TC_SRL[11].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized54 | 106| -|1155 | \TC_SRL[12].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized55 | 74| -|1156 | \TC_SRL[13].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized56 | 74| -|1157 | \TC_SRL[14].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized57 | 74| -|1158 | \TC_SRL[15].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized58 | 90| -|1159 | \TC_SRL[16].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized59 | 74| -|1160 | \TC_SRL[17].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized60 | 74| -|1161 | \TC_SRL[18].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized61 | 74| -|1162 | \TC_SRL[19].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized62 | 106| -|1163 | \TC_SRL[1].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized44 | 75| -|1164 | \TC_SRL[20].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized63 | 74| -|1165 | \TC_SRL[21].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized64 | 74| -|1166 | \TC_SRL[22].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized65 | 74| -|1167 | \TC_SRL[23].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized66 | 90| -|1168 | \TC_SRL[24].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized67 | 74| -|1169 | \TC_SRL[25].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized68 | 74| -|1170 | \TC_SRL[26].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized69 | 74| -|1171 | \TC_SRL[27].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized70 | 122| -|1172 | \TC_SRL[28].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized71 | 74| -|1173 | \TC_SRL[29].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized72 | 74| -|1174 | \TC_SRL[2].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized45 | 75| -|1175 | \TC_SRL[30].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized73 | 74| -|1176 | \TC_SRL[31].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized74 | 90| -|1177 | \TC_SRL[3].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized46 | 107| -|1178 | \TC_SRL[4].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized47 | 74| -|1179 | \TC_SRL[5].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized48 | 74| -|1180 | \TC_SRL[6].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized49 | 74| -|1181 | \TC_SRL[7].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized50 | 90| -|1182 | \TC_SRL[8].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized51 | 74| -|1183 | \TC_SRL[9].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized52 | 74| -|1184 | reg_15 |xsdbs_v1_0_2_reg__parameterized90 | 35| -|1185 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_532 | 35| -|1186 | reg_16 |xsdbs_v1_0_2_reg__parameterized91 | 17| -|1187 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_531 | 17| -|1188 | reg_17 |xsdbs_v1_0_2_reg__parameterized92 | 27| -|1189 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_530 | 27| -|1190 | reg_18 |xsdbs_v1_0_2_reg__parameterized93 | 38| -|1191 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_529 | 38| -|1192 | reg_19 |xsdbs_v1_0_2_reg__parameterized94 | 17| -|1193 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_528 | 17| -|1194 | reg_1a |xsdbs_v1_0_2_reg__parameterized95 | 28| -|1195 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1 | 28| -|1196 | reg_6 |xsdbs_v1_0_2_reg__parameterized75 | 23| -|1197 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_527 | 23| -|1198 | reg_7 |xsdbs_v1_0_2_reg__parameterized76 | 37| -|1199 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized0 | 37| -|1200 | reg_8 |xsdbs_v1_0_2_reg__parameterized77 | 8| -|1201 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_526 | 8| -|1202 | reg_80 |xsdbs_v1_0_2_reg__parameterized96 | 18| -|1203 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2_525 | 18| -|1204 | reg_81 |xsdbs_v1_0_2_reg__parameterized97 | 17| -|1205 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_524 | 17| -|1206 | reg_82 |xsdbs_v1_0_2_reg__parameterized98 | 17| -|1207 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2 | 17| -|1208 | reg_83 |xsdbs_v1_0_2_reg__parameterized99 | 36| -|1209 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_523 | 36| -|1210 | reg_84 |xsdbs_v1_0_2_reg__parameterized100 | 48| -|1211 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_522 | 48| -|1212 | reg_85 |xsdbs_v1_0_2_reg__parameterized101 | 17| -|1213 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_521 | 17| -|1214 | reg_887 |xsdbs_v1_0_2_reg__parameterized103 | 1| -|1215 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_520 | 1| -|1216 | reg_88d |xsdbs_v1_0_2_reg__parameterized105 | 4| -|1217 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_519 | 4| -|1218 | reg_88f |xsdbs_v1_0_2_reg__parameterized107 | 38| -|1219 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_518 | 38| -|1220 | reg_892 |xsdbs_v1_0_2_reg__parameterized106 | 4| -|1221 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_517 | 4| -|1222 | reg_9 |xsdbs_v1_0_2_reg__parameterized78 | 18| -|1223 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_516 | 18| -|1224 | reg_srl_fff |xsdbs_v1_0_2_reg_p2s__parameterized80 | 93| -|1225 | reg_stream_ffd |xsdbs_v1_0_2_reg_stream__parameterized1 | 17| -|1226 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl | 17| -|1227 | reg_stream_ffe |xsdbs_v1_0_2_reg_stream__parameterized2 | 16| -|1228 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat | 16| -|1229 | u_ila_reset_ctrl |ila_v6_2_9_ila_reset_ctrl | 47| -|1230 | arm_detection_inst |ltlib_v1_0_0_rising_edge_detection | 5| -|1231 | \asyncrounous_transfer.arm_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer | 7| -|1232 | \asyncrounous_transfer.arm_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_512 | 7| -|1233 | \asyncrounous_transfer.halt_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer_513 | 7| -|1234 | \asyncrounous_transfer.halt_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_514 | 6| -|1235 | halt_detection_inst |ltlib_v1_0_0_rising_edge_detection_515 | 6| -|1236 | u_trig |ila_v6_2_9_ila_trigger | 2520| -|1237 | \N_DDR_TC.N_DDR_TC_INST[0].U_TC |ltlib_v1_0_0_match | 34| -|1238 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_504 | 33| -|1239 | DUT |ltlib_v1_0_0_all_typeA_505 | 33| -|1240 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_506 | 5| -|1241 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_507 | 5| -|1242 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_508 | 5| -|1243 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_509 | 5| -|1244 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_510 | 5| -|1245 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_511 | 6| -|1246 | \N_DDR_TC.N_DDR_TC_INST[10].U_TC |ltlib_v1_0_0_match_0 | 34| -|1247 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_496 | 33| -|1248 | DUT |ltlib_v1_0_0_all_typeA_497 | 33| -|1249 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_498 | 5| -|1250 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_499 | 5| -|1251 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_500 | 5| -|1252 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_501 | 5| -|1253 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_502 | 5| -|1254 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_503 | 6| -|1255 | \N_DDR_TC.N_DDR_TC_INST[11].U_TC |ltlib_v1_0_0_match_1 | 34| -|1256 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_488 | 33| -|1257 | DUT |ltlib_v1_0_0_all_typeA_489 | 33| -|1258 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_490 | 5| -|1259 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_491 | 5| -|1260 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_492 | 5| -|1261 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_493 | 5| -|1262 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_494 | 5| -|1263 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_495 | 6| -|1264 | \N_DDR_TC.N_DDR_TC_INST[12].U_TC |ltlib_v1_0_0_match_2 | 34| -|1265 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_480 | 33| -|1266 | DUT |ltlib_v1_0_0_all_typeA_481 | 33| -|1267 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_482 | 5| -|1268 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_483 | 5| -|1269 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_484 | 5| -|1270 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_485 | 5| -|1271 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_486 | 5| -|1272 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_487 | 6| -|1273 | \N_DDR_TC.N_DDR_TC_INST[13].U_TC |ltlib_v1_0_0_match_3 | 34| -|1274 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_472 | 33| -|1275 | DUT |ltlib_v1_0_0_all_typeA_473 | 33| -|1276 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_474 | 5| -|1277 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_475 | 5| -|1278 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_476 | 5| -|1279 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_477 | 5| -|1280 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_478 | 5| -|1281 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_479 | 6| -|1282 | \N_DDR_TC.N_DDR_TC_INST[14].U_TC |ltlib_v1_0_0_match_4 | 34| -|1283 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_464 | 33| -|1284 | DUT |ltlib_v1_0_0_all_typeA_465 | 33| -|1285 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_466 | 5| -|1286 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_467 | 5| -|1287 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_468 | 5| -|1288 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_469 | 5| -|1289 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_470 | 5| -|1290 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_471 | 6| -|1291 | \N_DDR_TC.N_DDR_TC_INST[15].U_TC |ltlib_v1_0_0_match_5 | 34| -|1292 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_456 | 33| -|1293 | DUT |ltlib_v1_0_0_all_typeA_457 | 33| -|1294 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_458 | 5| -|1295 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_459 | 5| -|1296 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_460 | 5| -|1297 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_461 | 5| -|1298 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_462 | 5| -|1299 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_463 | 6| -|1300 | \N_DDR_TC.N_DDR_TC_INST[16].U_TC |ltlib_v1_0_0_match_6 | 34| -|1301 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_448 | 33| -|1302 | DUT |ltlib_v1_0_0_all_typeA_449 | 33| -|1303 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_450 | 5| -|1304 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_451 | 5| -|1305 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_452 | 5| -|1306 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_453 | 5| -|1307 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_454 | 5| -|1308 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_455 | 6| -|1309 | \N_DDR_TC.N_DDR_TC_INST[17].U_TC |ltlib_v1_0_0_match_7 | 34| -|1310 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_440 | 33| -|1311 | DUT |ltlib_v1_0_0_all_typeA_441 | 33| -|1312 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_442 | 5| -|1313 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_443 | 5| -|1314 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_444 | 5| -|1315 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_445 | 5| -|1316 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_446 | 5| -|1317 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_447 | 6| -|1318 | \N_DDR_TC.N_DDR_TC_INST[18].U_TC |ltlib_v1_0_0_match_8 | 34| -|1319 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_432 | 33| -|1320 | DUT |ltlib_v1_0_0_all_typeA_433 | 33| -|1321 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_434 | 5| -|1322 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_435 | 5| -|1323 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_436 | 5| -|1324 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_437 | 5| -|1325 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_438 | 5| -|1326 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_439 | 6| -|1327 | \N_DDR_TC.N_DDR_TC_INST[19].U_TC |ltlib_v1_0_0_match_9 | 34| -|1328 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_424 | 33| -|1329 | DUT |ltlib_v1_0_0_all_typeA_425 | 33| -|1330 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_426 | 5| -|1331 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_427 | 5| -|1332 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_428 | 5| -|1333 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_429 | 5| -|1334 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_430 | 5| -|1335 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_431 | 6| -|1336 | \N_DDR_TC.N_DDR_TC_INST[1].U_TC |ltlib_v1_0_0_match_10 | 34| -|1337 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_416 | 33| -|1338 | DUT |ltlib_v1_0_0_all_typeA_417 | 33| -|1339 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_418 | 5| -|1340 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_419 | 5| -|1341 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_420 | 5| -|1342 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_421 | 5| -|1343 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_422 | 5| -|1344 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_423 | 6| -|1345 | \N_DDR_TC.N_DDR_TC_INST[20].U_TC |ltlib_v1_0_0_match_11 | 34| -|1346 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_408 | 33| -|1347 | DUT |ltlib_v1_0_0_all_typeA_409 | 33| -|1348 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_410 | 5| -|1349 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_411 | 5| -|1350 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_412 | 5| -|1351 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_413 | 5| -|1352 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_414 | 5| -|1353 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_415 | 6| -|1354 | \N_DDR_TC.N_DDR_TC_INST[21].U_TC |ltlib_v1_0_0_match_12 | 34| -|1355 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_400 | 33| -|1356 | DUT |ltlib_v1_0_0_all_typeA_401 | 33| -|1357 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_402 | 5| -|1358 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_403 | 5| -|1359 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_404 | 5| -|1360 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_405 | 5| -|1361 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_406 | 5| -|1362 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_407 | 6| -|1363 | \N_DDR_TC.N_DDR_TC_INST[22].U_TC |ltlib_v1_0_0_match_13 | 34| -|1364 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_392 | 33| -|1365 | DUT |ltlib_v1_0_0_all_typeA_393 | 33| -|1366 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_394 | 5| -|1367 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_395 | 5| -|1368 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_396 | 5| -|1369 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_397 | 5| -|1370 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_398 | 5| -|1371 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_399 | 6| -|1372 | \N_DDR_TC.N_DDR_TC_INST[23].U_TC |ltlib_v1_0_0_match_14 | 34| -|1373 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_384 | 33| -|1374 | DUT |ltlib_v1_0_0_all_typeA_385 | 33| -|1375 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_386 | 5| -|1376 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_387 | 5| -|1377 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_388 | 5| -|1378 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_389 | 5| -|1379 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_390 | 5| -|1380 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_391 | 6| -|1381 | \N_DDR_TC.N_DDR_TC_INST[24].U_TC |ltlib_v1_0_0_match_15 | 34| -|1382 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_376 | 33| -|1383 | DUT |ltlib_v1_0_0_all_typeA_377 | 33| -|1384 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_378 | 5| -|1385 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_379 | 5| -|1386 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_380 | 5| -|1387 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_381 | 5| -|1388 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_382 | 5| -|1389 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_383 | 6| -|1390 | \N_DDR_TC.N_DDR_TC_INST[25].U_TC |ltlib_v1_0_0_match_16 | 34| -|1391 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_368 | 33| -|1392 | DUT |ltlib_v1_0_0_all_typeA_369 | 33| -|1393 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_370 | 5| -|1394 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_371 | 5| -|1395 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_372 | 5| -|1396 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_373 | 5| -|1397 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_374 | 5| -|1398 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_375 | 6| -|1399 | \N_DDR_TC.N_DDR_TC_INST[26].U_TC |ltlib_v1_0_0_match_17 | 34| -|1400 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_360 | 33| -|1401 | DUT |ltlib_v1_0_0_all_typeA_361 | 33| -|1402 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_362 | 5| -|1403 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_363 | 5| -|1404 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_364 | 5| -|1405 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_365 | 5| -|1406 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_366 | 5| -|1407 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_367 | 6| -|1408 | \N_DDR_TC.N_DDR_TC_INST[27].U_TC |ltlib_v1_0_0_match_18 | 34| -|1409 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_352 | 33| -|1410 | DUT |ltlib_v1_0_0_all_typeA_353 | 33| -|1411 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_354 | 5| -|1412 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_355 | 5| -|1413 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_356 | 5| -|1414 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_357 | 5| -|1415 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_358 | 5| -|1416 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_359 | 6| -|1417 | \N_DDR_TC.N_DDR_TC_INST[28].U_TC |ltlib_v1_0_0_match_19 | 34| -|1418 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_344 | 33| -|1419 | DUT |ltlib_v1_0_0_all_typeA_345 | 33| -|1420 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_346 | 5| -|1421 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_347 | 5| -|1422 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_348 | 5| -|1423 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_349 | 5| -|1424 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_350 | 5| -|1425 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_351 | 6| -|1426 | \N_DDR_TC.N_DDR_TC_INST[29].U_TC |ltlib_v1_0_0_match_20 | 34| -|1427 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_336 | 33| -|1428 | DUT |ltlib_v1_0_0_all_typeA_337 | 33| -|1429 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_338 | 5| -|1430 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_339 | 5| -|1431 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_340 | 5| -|1432 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_341 | 5| -|1433 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_342 | 5| -|1434 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_343 | 6| -|1435 | \N_DDR_TC.N_DDR_TC_INST[2].U_TC |ltlib_v1_0_0_match_21 | 34| -|1436 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_328 | 33| -|1437 | DUT |ltlib_v1_0_0_all_typeA_329 | 33| -|1438 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_330 | 5| -|1439 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_331 | 5| -|1440 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_332 | 5| -|1441 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_333 | 5| -|1442 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_334 | 5| -|1443 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_335 | 6| -|1444 | \N_DDR_TC.N_DDR_TC_INST[30].U_TC |ltlib_v1_0_0_match_22 | 34| -|1445 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_320 | 33| -|1446 | DUT |ltlib_v1_0_0_all_typeA_321 | 33| -|1447 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_322 | 5| -|1448 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_323 | 5| -|1449 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_324 | 5| -|1450 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_325 | 5| -|1451 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_326 | 5| -|1452 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_327 | 6| -|1453 | \N_DDR_TC.N_DDR_TC_INST[31].U_TC |ltlib_v1_0_0_match_23 | 34| -|1454 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_312 | 33| -|1455 | DUT |ltlib_v1_0_0_all_typeA_313 | 33| -|1456 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_314 | 5| -|1457 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_315 | 5| -|1458 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_316 | 5| -|1459 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_317 | 5| -|1460 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_318 | 5| -|1461 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_319 | 6| -|1462 | \N_DDR_TC.N_DDR_TC_INST[3].U_TC |ltlib_v1_0_0_match_24 | 34| -|1463 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_304 | 33| -|1464 | DUT |ltlib_v1_0_0_all_typeA_305 | 33| -|1465 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_306 | 5| -|1466 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_307 | 5| -|1467 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_308 | 5| -|1468 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_309 | 5| -|1469 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_310 | 5| -|1470 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_311 | 6| -|1471 | \N_DDR_TC.N_DDR_TC_INST[4].U_TC |ltlib_v1_0_0_match_25 | 34| -|1472 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_296 | 33| -|1473 | DUT |ltlib_v1_0_0_all_typeA_297 | 33| -|1474 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_298 | 5| -|1475 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_299 | 5| -|1476 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_300 | 5| -|1477 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_301 | 5| -|1478 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_302 | 5| -|1479 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_303 | 6| -|1480 | \N_DDR_TC.N_DDR_TC_INST[5].U_TC |ltlib_v1_0_0_match_26 | 34| -|1481 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_288 | 33| -|1482 | DUT |ltlib_v1_0_0_all_typeA_289 | 33| -|1483 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_290 | 5| -|1484 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_291 | 5| -|1485 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_292 | 5| -|1486 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_293 | 5| -|1487 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_294 | 5| -|1488 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_295 | 6| -|1489 | \N_DDR_TC.N_DDR_TC_INST[6].U_TC |ltlib_v1_0_0_match_27 | 34| -|1490 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_280 | 33| -|1491 | DUT |ltlib_v1_0_0_all_typeA_281 | 33| -|1492 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_282 | 5| -|1493 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_283 | 5| -|1494 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_284 | 5| -|1495 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_285 | 5| -|1496 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_286 | 5| -|1497 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_287 | 6| -|1498 | \N_DDR_TC.N_DDR_TC_INST[7].U_TC |ltlib_v1_0_0_match_28 | 34| -|1499 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_272 | 33| -|1500 | DUT |ltlib_v1_0_0_all_typeA_273 | 33| -|1501 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_274 | 5| -|1502 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_275 | 5| -|1503 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_276 | 5| -|1504 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_277 | 5| -|1505 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_278 | 5| -|1506 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_279 | 6| -|1507 | \N_DDR_TC.N_DDR_TC_INST[8].U_TC |ltlib_v1_0_0_match_29 | 34| -|1508 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_264 | 33| -|1509 | DUT |ltlib_v1_0_0_all_typeA_265 | 33| -|1510 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_266 | 5| -|1511 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_267 | 5| -|1512 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_268 | 5| -|1513 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_269 | 5| -|1514 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_270 | 5| -|1515 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_271 | 6| -|1516 | \N_DDR_TC.N_DDR_TC_INST[9].U_TC |ltlib_v1_0_0_match_30 | 34| -|1517 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_256 | 33| -|1518 | DUT |ltlib_v1_0_0_all_typeA_257 | 33| -|1519 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_258 | 5| -|1520 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_259 | 5| -|1521 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_260 | 5| -|1522 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_261 | 5| -|1523 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_262 | 5| -|1524 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_263 | 6| -|1525 | \STRG_QUAL.U_STRG_QUAL |ltlib_v1_0_0_match_31 | 78| -|1526 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA | 77| -|1527 | DUT |ltlib_v1_0_0_all_typeA | 33| -|1528 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_250 | 5| -|1529 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_251 | 5| -|1530 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_252 | 5| -|1531 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_253 | 5| -|1532 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_254 | 5| -|1533 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_255 | 6| -|1534 | U_TM |ila_v6_2_9_ila_trig_match | 1306| -|1535 | \N_DDR_MODE.G_NMU[0].U_M |ltlib_v1_0_0_match__parameterized0 | 71| -|1536 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_245 | 70| -|1537 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_246 | 18| -|1538 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_247 | 5| -|1539 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_248 | 5| -|1540 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_249 | 6| -|1541 | \N_DDR_MODE.G_NMU[10].U_M |ltlib_v1_0_0_match__parameterized0_32 | 55| -|1542 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_240 | 54| -|1543 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_241 | 18| -|1544 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_242 | 5| -|1545 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_243 | 5| -|1546 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_244 | 6| -|1547 | \N_DDR_MODE.G_NMU[11].U_M |ltlib_v1_0_0_match__parameterized0_33 | 19| -|1548 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_235 | 18| -|1549 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_236 | 18| -|1550 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_237 | 5| -|1551 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_238 | 5| -|1552 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_239 | 6| -|1553 | \N_DDR_MODE.G_NMU[12].U_M |ltlib_v1_0_0_match__parameterized0_34 | 55| -|1554 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_230 | 54| -|1555 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_231 | 18| -|1556 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_232 | 5| -|1557 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_233 | 5| -|1558 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_234 | 6| -|1559 | \N_DDR_MODE.G_NMU[13].U_M |ltlib_v1_0_0_match__parameterized0_35 | 19| -|1560 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_225 | 18| -|1561 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_226 | 18| -|1562 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_227 | 5| -|1563 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_228 | 5| -|1564 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_229 | 6| -|1565 | \N_DDR_MODE.G_NMU[14].U_M |ltlib_v1_0_0_match__parameterized0_36 | 55| -|1566 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_220 | 54| -|1567 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_221 | 18| -|1568 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_222 | 5| -|1569 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_223 | 5| -|1570 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_224 | 6| -|1571 | \N_DDR_MODE.G_NMU[15].U_M |ltlib_v1_0_0_match__parameterized0_37 | 19| -|1572 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_215 | 18| -|1573 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_216 | 18| -|1574 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_217 | 5| -|1575 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_218 | 5| -|1576 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_219 | 6| -|1577 | \N_DDR_MODE.G_NMU[16].U_M |ltlib_v1_0_0_match__parameterized0_38 | 55| -|1578 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_210 | 54| -|1579 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_211 | 18| -|1580 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_212 | 5| -|1581 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_213 | 5| -|1582 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_214 | 6| -|1583 | \N_DDR_MODE.G_NMU[17].U_M |ltlib_v1_0_0_match__parameterized0_39 | 19| -|1584 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_205 | 18| -|1585 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_206 | 18| -|1586 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_207 | 5| -|1587 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_208 | 5| -|1588 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_209 | 6| -|1589 | \N_DDR_MODE.G_NMU[18].U_M |ltlib_v1_0_0_match__parameterized1 | 15| -|1590 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_202 | 14| -|1591 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_203 | 8| -|1592 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_204 | 6| -|1593 | \N_DDR_MODE.G_NMU[19].U_M |ltlib_v1_0_0_match__parameterized1_40 | 9| -|1594 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1 | 8| -|1595 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_200 | 8| -|1596 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_201 | 6| -|1597 | \N_DDR_MODE.G_NMU[1].U_M |ltlib_v1_0_0_match__parameterized0_41 | 19| -|1598 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_195 | 18| -|1599 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_196 | 18| -|1600 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_197 | 5| -|1601 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_198 | 5| -|1602 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_199 | 6| -|1603 | \N_DDR_MODE.G_NMU[20].U_M |ltlib_v1_0_0_match__parameterized2 | 11| -|1604 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_192 | 10| -|1605 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_193 | 8| -|1606 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_194 | 6| -|1607 | \N_DDR_MODE.G_NMU[21].U_M |ltlib_v1_0_0_match__parameterized2_42 | 9| -|1608 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_189 | 8| -|1609 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_190 | 8| -|1610 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_191 | 6| -|1611 | \N_DDR_MODE.G_NMU[22].U_M |ltlib_v1_0_0_match__parameterized2_43 | 11| -|1612 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_186 | 10| -|1613 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_187 | 8| -|1614 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_188 | 6| -|1615 | \N_DDR_MODE.G_NMU[23].U_M |ltlib_v1_0_0_match__parameterized2_44 | 9| -|1616 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_183 | 8| -|1617 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_184 | 8| -|1618 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_185 | 6| -|1619 | \N_DDR_MODE.G_NMU[24].U_M |ltlib_v1_0_0_match__parameterized2_45 | 11| -|1620 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_180 | 10| -|1621 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_181 | 8| -|1622 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_182 | 6| -|1623 | \N_DDR_MODE.G_NMU[25].U_M |ltlib_v1_0_0_match__parameterized2_46 | 9| -|1624 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_177 | 8| -|1625 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_178 | 8| -|1626 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_179 | 6| -|1627 | \N_DDR_MODE.G_NMU[26].U_M |ltlib_v1_0_0_match__parameterized3 | 88| -|1628 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized3_171 | 87| -|1629 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_172 | 23| -|1630 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_173 | 5| -|1631 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_174 | 5| -|1632 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_175 | 5| -|1633 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_176 | 6| -|1634 | \N_DDR_MODE.G_NMU[27].U_M |ltlib_v1_0_0_match__parameterized3_47 | 24| -|1635 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized3_165 | 23| -|1636 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_166 | 23| -|1637 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_167 | 5| -|1638 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_168 | 5| -|1639 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_169 | 5| -|1640 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_170 | 6| -|1641 | \N_DDR_MODE.G_NMU[28].U_M |ltlib_v1_0_0_match__parameterized2_48 | 11| -|1642 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_162 | 10| -|1643 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_163 | 8| -|1644 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_164 | 6| -|1645 | \N_DDR_MODE.G_NMU[29].U_M |ltlib_v1_0_0_match__parameterized2_49 | 9| -|1646 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2 | 8| -|1647 | DUT |ltlib_v1_0_0_all_typeA__parameterized1 | 8| -|1648 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_161 | 6| -|1649 | \N_DDR_MODE.G_NMU[2].U_M |ltlib_v1_0_0_match__parameterized0_50 | 55| -|1650 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_156 | 54| -|1651 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_157 | 18| -|1652 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_158 | 5| -|1653 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_159 | 5| -|1654 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_160 | 6| -|1655 | \N_DDR_MODE.G_NMU[30].U_M |ltlib_v1_0_0_match__parameterized3_51 | 88| -|1656 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized3_150 | 87| -|1657 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_151 | 23| -|1658 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_152 | 5| -|1659 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_153 | 5| -|1660 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_154 | 5| -|1661 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_155 | 6| -|1662 | \N_DDR_MODE.G_NMU[31].U_M |ltlib_v1_0_0_match__parameterized3_52 | 24| -|1663 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized3 | 23| -|1664 | DUT |ltlib_v1_0_0_all_typeA__parameterized2 | 23| -|1665 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_146 | 5| -|1666 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_147 | 5| -|1667 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_148 | 5| -|1668 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_149 | 6| -|1669 | \N_DDR_MODE.G_NMU[32].U_M |ltlib_v1_0_0_match__parameterized4 | 38| -|1670 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_142 | 37| -|1671 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_143 | 13| -|1672 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_144 | 5| -|1673 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_145 | 6| -|1674 | \N_DDR_MODE.G_NMU[33].U_M |ltlib_v1_0_0_match__parameterized4_53 | 14| -|1675 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_138 | 13| -|1676 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_139 | 13| -|1677 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_140 | 5| -|1678 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_141 | 6| -|1679 | \N_DDR_MODE.G_NMU[34].U_M |ltlib_v1_0_0_match__parameterized4_54 | 38| -|1680 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_134 | 37| -|1681 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_135 | 13| -|1682 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_136 | 5| -|1683 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_137 | 6| -|1684 | \N_DDR_MODE.G_NMU[35].U_M |ltlib_v1_0_0_match__parameterized4_55 | 14| -|1685 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4 | 13| -|1686 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_131 | 13| -|1687 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_132 | 5| -|1688 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_133 | 6| -|1689 | \N_DDR_MODE.G_NMU[36].U_M |ltlib_v1_0_0_match__parameterized5 | 34| -|1690 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5_127 | 33| -|1691 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_128 | 13| -|1692 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_129 | 5| -|1693 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_130 | 6| -|1694 | \N_DDR_MODE.G_NMU[37].U_M |ltlib_v1_0_0_match__parameterized5_56 | 14| -|1695 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5_123 | 13| -|1696 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_124 | 13| -|1697 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_125 | 5| -|1698 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_126 | 6| -|1699 | \N_DDR_MODE.G_NMU[38].U_M |ltlib_v1_0_0_match__parameterized5_57 | 34| -|1700 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5_119 | 33| -|1701 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_120 | 13| -|1702 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_121 | 5| -|1703 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_122 | 6| -|1704 | \N_DDR_MODE.G_NMU[39].U_M |ltlib_v1_0_0_match__parameterized5_58 | 14| -|1705 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5_115 | 13| -|1706 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_116 | 13| -|1707 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_117 | 5| -|1708 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_118 | 6| -|1709 | \N_DDR_MODE.G_NMU[3].U_M |ltlib_v1_0_0_match__parameterized0_59 | 19| -|1710 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_110 | 18| -|1711 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_111 | 18| -|1712 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_112 | 5| -|1713 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_113 | 5| -|1714 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_114 | 6| -|1715 | \N_DDR_MODE.G_NMU[40].U_M |ltlib_v1_0_0_match__parameterized5_60 | 34| -|1716 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5_106 | 33| -|1717 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_107 | 13| -|1718 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_108 | 5| -|1719 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_109 | 6| -|1720 | \N_DDR_MODE.G_NMU[41].U_M |ltlib_v1_0_0_match__parameterized5_61 | 14| -|1721 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5_102 | 13| -|1722 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_103 | 13| -|1723 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_104 | 5| -|1724 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_105 | 6| -|1725 | \N_DDR_MODE.G_NMU[42].U_M |ltlib_v1_0_0_match__parameterized5_62 | 34| -|1726 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5_98 | 33| -|1727 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_99 | 13| -|1728 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_100 | 5| -|1729 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_101 | 6| -|1730 | \N_DDR_MODE.G_NMU[43].U_M |ltlib_v1_0_0_match__parameterized5_63 | 14| -|1731 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5 | 13| -|1732 | DUT |ltlib_v1_0_0_all_typeA__parameterized3 | 13| -|1733 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_96 | 5| -|1734 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_97 | 6| -|1735 | \N_DDR_MODE.G_NMU[4].U_M |ltlib_v1_0_0_match__parameterized0_64 | 55| -|1736 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_91 | 54| -|1737 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_92 | 18| -|1738 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_93 | 5| -|1739 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_94 | 5| -|1740 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_95 | 6| -|1741 | \N_DDR_MODE.G_NMU[5].U_M |ltlib_v1_0_0_match__parameterized0_65 | 19| -|1742 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_86 | 18| -|1743 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_87 | 18| -|1744 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_88 | 5| -|1745 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_89 | 5| -|1746 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_90 | 6| -|1747 | \N_DDR_MODE.G_NMU[6].U_M |ltlib_v1_0_0_match__parameterized0_66 | 55| -|1748 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_81 | 54| -|1749 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_82 | 18| -|1750 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_83 | 5| -|1751 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_84 | 5| -|1752 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_85 | 6| -|1753 | \N_DDR_MODE.G_NMU[7].U_M |ltlib_v1_0_0_match__parameterized0_67 | 19| -|1754 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_76 | 18| -|1755 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_77 | 18| -|1756 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_78 | 5| -|1757 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_79 | 5| -|1758 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_80 | 6| -|1759 | \N_DDR_MODE.G_NMU[8].U_M |ltlib_v1_0_0_match__parameterized0_68 | 55| -|1760 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_71 | 54| -|1761 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_72 | 18| -|1762 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_73 | 5| -|1763 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_74 | 5| -|1764 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_75 | 6| -|1765 | \N_DDR_MODE.G_NMU[9].U_M |ltlib_v1_0_0_match__parameterized0_69 | 19| -|1766 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0 | 18| -|1767 | DUT |ltlib_v1_0_0_all_typeA__parameterized0 | 18| -|1768 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice | 5| -|1769 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_70 | 5| -|1770 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0 | 6| -|1771 | xsdb_memory_read_inst |ltlib_v1_0_0_generic_memrd | 1333| +|11 | ila_trace_memory_inst |ila_v6_2_9_ila_trace_memory | 1176| +|12 | \SUBCORE_RAM_BLK_MEM_1.trace_block_memory |blk_mem_gen_v8_4_3 | 1176| +|13 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 1176| +|14 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_v8_4_3_blk_mem_gen_top | 1176| +|15 | \valid.cstr |blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr | 1176| +|16 | \bindec_a.bindec_inst_a |blk_mem_gen_v8_4_3_bindec | 6| +|17 | \has_mux_b.B |blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 | 905| +|18 | \ramloop[0].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width | 1| +|19 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper | 1| +|20 | \ramloop[100].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized99 | 1| +|21 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized99 | 1| +|22 | \ramloop[101].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized100 | 1| +|23 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized100 | 1| +|24 | \ramloop[102].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized101 | 1| +|25 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized101 | 1| +|26 | \ramloop[103].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized102 | 1| +|27 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized102 | 1| +|28 | \ramloop[104].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized103 | 1| +|29 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized103 | 1| +|30 | \ramloop[105].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized104 | 1| +|31 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized104 | 1| +|32 | \ramloop[106].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized105 | 1| +|33 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized105 | 1| +|34 | \ramloop[107].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized106 | 1| +|35 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized106 | 1| +|36 | \ramloop[108].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized107 | 1| +|37 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized107 | 1| +|38 | \ramloop[109].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized108 | 1| +|39 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized108 | 1| +|40 | \ramloop[10].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized9 | 1| +|41 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized9 | 1| +|42 | \ramloop[110].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized109 | 1| +|43 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized109 | 1| +|44 | \ramloop[111].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized110 | 1| +|45 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized110 | 1| +|46 | \ramloop[112].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized111 | 1| +|47 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized111 | 1| +|48 | \ramloop[113].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized112 | 1| +|49 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized112 | 1| +|50 | \ramloop[114].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized113 | 1| +|51 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized113 | 1| +|52 | \ramloop[115].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized114 | 1| +|53 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized114 | 1| +|54 | \ramloop[116].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized115 | 1| +|55 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized115 | 1| +|56 | \ramloop[117].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized116 | 1| +|57 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized116 | 1| +|58 | \ramloop[118].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized117 | 1| +|59 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized117 | 1| +|60 | \ramloop[119].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized118 | 1| +|61 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized118 | 1| +|62 | \ramloop[11].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized10 | 1| +|63 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized10 | 1| +|64 | \ramloop[120].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized119 | 1| +|65 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized119 | 1| +|66 | \ramloop[121].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized120 | 1| +|67 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized120 | 1| +|68 | \ramloop[122].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized121 | 1| +|69 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized121 | 1| +|70 | \ramloop[123].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized122 | 1| +|71 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized122 | 1| +|72 | \ramloop[124].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized123 | 1| +|73 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized123 | 1| +|74 | \ramloop[125].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized124 | 1| +|75 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized124 | 1| +|76 | \ramloop[126].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized125 | 1| +|77 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized125 | 1| +|78 | \ramloop[127].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized126 | 1| +|79 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized126 | 1| +|80 | \ramloop[128].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized127 | 1| +|81 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized127 | 1| +|82 | \ramloop[129].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized128 | 1| +|83 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized128 | 1| +|84 | \ramloop[12].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized11 | 1| +|85 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized11 | 1| +|86 | \ramloop[130].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized129 | 1| +|87 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized129 | 1| +|88 | \ramloop[131].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized130 | 1| +|89 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized130 | 1| +|90 | \ramloop[132].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized131 | 1| +|91 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized131 | 1| +|92 | \ramloop[133].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized132 | 1| +|93 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized132 | 1| +|94 | \ramloop[134].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized133 | 1| +|95 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized133 | 1| +|96 | \ramloop[135].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized134 | 1| +|97 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized134 | 1| +|98 | \ramloop[136].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized135 | 1| +|99 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized135 | 1| +|100 | \ramloop[137].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized136 | 1| +|101 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized136 | 1| +|102 | \ramloop[138].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized137 | 1| +|103 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized137 | 1| +|104 | \ramloop[139].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized138 | 1| +|105 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized138 | 1| +|106 | \ramloop[13].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized12 | 1| +|107 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized12 | 1| +|108 | \ramloop[140].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized139 | 1| +|109 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized139 | 1| +|110 | \ramloop[141].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized140 | 1| +|111 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized140 | 1| +|112 | \ramloop[142].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized141 | 1| +|113 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized141 | 1| +|114 | \ramloop[143].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized142 | 1| +|115 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized142 | 1| +|116 | \ramloop[144].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized143 | 1| +|117 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized143 | 1| +|118 | \ramloop[145].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized144 | 1| +|119 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized144 | 1| +|120 | \ramloop[146].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized145 | 1| +|121 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized145 | 1| +|122 | \ramloop[147].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized146 | 1| +|123 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized146 | 1| +|124 | \ramloop[148].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized147 | 1| +|125 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized147 | 1| +|126 | \ramloop[149].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized148 | 1| +|127 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized148 | 1| +|128 | \ramloop[14].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized13 | 1| +|129 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized13 | 1| +|130 | \ramloop[150].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized149 | 1| +|131 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized149 | 1| +|132 | \ramloop[151].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized150 | 1| +|133 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized150 | 1| +|134 | \ramloop[152].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized151 | 1| +|135 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized151 | 1| +|136 | \ramloop[153].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized152 | 1| +|137 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized152 | 1| +|138 | \ramloop[154].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized153 | 1| +|139 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized153 | 1| +|140 | \ramloop[155].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized154 | 1| +|141 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized154 | 1| +|142 | \ramloop[156].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized155 | 1| +|143 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized155 | 1| +|144 | \ramloop[157].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized156 | 1| +|145 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized156 | 1| +|146 | \ramloop[158].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized157 | 1| +|147 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized157 | 1| +|148 | \ramloop[159].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized158 | 1| +|149 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized158 | 1| +|150 | \ramloop[15].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized14 | 1| +|151 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized14 | 1| +|152 | \ramloop[160].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized159 | 1| +|153 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized159 | 1| +|154 | \ramloop[161].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized160 | 1| +|155 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized160 | 1| +|156 | \ramloop[162].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized161 | 1| +|157 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized161 | 1| +|158 | \ramloop[163].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized162 | 1| +|159 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized162 | 1| +|160 | \ramloop[164].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized163 | 1| +|161 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized163 | 1| +|162 | \ramloop[165].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized164 | 1| +|163 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized164 | 1| +|164 | \ramloop[166].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized165 | 1| +|165 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized165 | 1| +|166 | \ramloop[167].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized166 | 1| +|167 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized166 | 1| +|168 | \ramloop[168].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized167 | 1| +|169 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized167 | 1| +|170 | \ramloop[169].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized168 | 1| +|171 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized168 | 1| +|172 | \ramloop[16].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized15 | 1| +|173 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized15 | 1| +|174 | \ramloop[170].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized169 | 1| +|175 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized169 | 1| +|176 | \ramloop[171].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized170 | 1| +|177 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized170 | 1| +|178 | \ramloop[172].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized171 | 1| +|179 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized171 | 1| +|180 | \ramloop[173].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized172 | 1| +|181 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized172 | 1| +|182 | \ramloop[174].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized173 | 1| +|183 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized173 | 1| +|184 | \ramloop[175].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized174 | 1| +|185 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized174 | 1| +|186 | \ramloop[176].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized175 | 1| +|187 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized175 | 1| +|188 | \ramloop[177].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized176 | 1| +|189 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized176 | 1| +|190 | \ramloop[178].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized177 | 1| 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+|508 | \ramloop[82].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized81 | 1| +|509 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized81 | 1| +|510 | \ramloop[83].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized82 | 1| +|511 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized82 | 1| +|512 | \ramloop[84].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized83 | 1| +|513 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized83 | 1| +|514 | \ramloop[85].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized84 | 1| +|515 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized84 | 1| +|516 | \ramloop[86].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized85 | 1| +|517 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized85 | 1| +|518 | \ramloop[87].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized86 | 1| +|519 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized86 | 1| +|520 | \ramloop[88].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized87 | 1| +|521 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized87 | 1| +|522 | \ramloop[89].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized88 | 1| +|523 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized88 | 1| +|524 | \ramloop[8].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized7 | 1| +|525 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized7 | 1| +|526 | \ramloop[90].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized89 | 1| +|527 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized89 | 1| +|528 | \ramloop[91].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized90 | 1| +|529 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized90 | 1| +|530 | \ramloop[92].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized91 | 1| +|531 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized91 | 1| +|532 | \ramloop[93].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized92 | 1| +|533 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized92 | 1| +|534 | \ramloop[94].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized93 | 1| +|535 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized93 | 1| +|536 | \ramloop[95].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized94 | 1| +|537 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized94 | 1| +|538 | \ramloop[96].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized95 | 1| +|539 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized95 | 1| +|540 | \ramloop[97].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized96 | 1| +|541 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized96 | 1| +|542 | \ramloop[98].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized97 | 1| +|543 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized97 | 1| +|544 | \ramloop[99].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized98 | 1| +|545 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized98 | 1| +|546 | \ramloop[9].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized8 | 1| +|547 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized8 | 1| +|548 | u_ila_cap_ctrl |ila_v6_2_9_ila_cap_ctrl_legacy | 311| +|549 | U_CDONE |ltlib_v1_0_0_cfglut6__parameterized0 | 5| +|550 | U_NS0 |ltlib_v1_0_0_cfglut7 | 8| +|551 | U_NS1 |ltlib_v1_0_0_cfglut7_528 | 10| +|552 | u_cap_addrgen |ila_v6_2_9_ila_cap_addrgen | 283| +|553 | U_CMPRESET |ltlib_v1_0_0_cfglut6 | 3| +|554 | u_cap_sample_counter |ila_v6_2_9_ila_cap_sample_counter | 68| +|555 | U_SCE |ltlib_v1_0_0_cfglut4_535 | 1| +|556 | U_SCMPCE |ltlib_v1_0_0_cfglut5_536 | 1| +|557 | U_SCRST |ltlib_v1_0_0_cfglut6_537 | 3| +|558 | u_scnt_cmp |ltlib_v1_0_0_match_nodelay_538 | 27| +|559 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_539 | 27| +|560 | DUT |ltlib_v1_0_0_all_typeA__parameterized4_540 | 12| +|561 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_541 | 5| +|562 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_542 | 5| +|563 | u_cap_window_counter |ila_v6_2_9_ila_cap_window_counter | 64| +|564 | U_WCE |ltlib_v1_0_0_cfglut4 | 1| +|565 | U_WHCMPCE |ltlib_v1_0_0_cfglut5 | 1| +|566 | U_WLCMPCE |ltlib_v1_0_0_cfglut5_529 | 1| +|567 | u_wcnt_hcmp |ltlib_v1_0_0_match_nodelay | 12| +|568 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_531 | 12| +|569 | DUT |ltlib_v1_0_0_all_typeA__parameterized4_532 | 12| +|570 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_533 | 5| +|571 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_534 | 5| +|572 | u_wcnt_lcmp |ltlib_v1_0_0_match_nodelay_530 | 27| +|573 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay | 27| +|574 | DUT |ltlib_v1_0_0_all_typeA__parameterized4 | 12| +|575 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1 | 5| +|576 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2 | 5| +|577 | u_ila_regs |ila_v6_2_9_ila_register | 7689| +|578 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 302| +|579 | reg_890 |xsdbs_v1_0_2_reg__parameterized105 | 16| +|580 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_527 | 16| +|581 | \ADV_TRIG_STREAM.reg_stream_ffc |xsdbs_v1_0_2_reg_stream__parameterized0 | 25| +|582 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_526 | 21| +|583 | \ADV_TRIG_STREAM_READBACK.reg_stream_ffb |xsdbs_v1_0_2_reg_stream | 40| +|584 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_525 | 40| +|585 | \CNT.CNT_SRL[0].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized73 | 74| +|586 | \CNT.CNT_SRL[1].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized74 | 74| +|587 | \CNT.CNT_SRL[2].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized75 | 107| +|588 | \CNT.CNT_SRL[3].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized76 | 75| +|589 | \MU_SRL[0].mu_srl_reg |xsdbs_v1_0_2_reg_p2s | 74| +|590 | \MU_SRL[10].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized9 | 74| +|591 | \MU_SRL[11].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized10 | 106| +|592 | \MU_SRL[12].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized11 | 74| +|593 | \MU_SRL[13].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized12 | 74| +|594 | \MU_SRL[14].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized13 | 74| +|595 | \MU_SRL[15].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized14 | 90| +|596 | \MU_SRL[16].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized15 | 74| +|597 | \MU_SRL[17].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized16 | 74| +|598 | \MU_SRL[18].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized17 | 74| +|599 | \MU_SRL[19].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized18 | 106| +|600 | \MU_SRL[1].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized0 | 74| +|601 | \MU_SRL[20].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized19 | 74| +|602 | \MU_SRL[21].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized20 | 74| +|603 | \MU_SRL[22].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized21 | 74| +|604 | \MU_SRL[23].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized22 | 90| +|605 | \MU_SRL[24].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized23 | 74| +|606 | \MU_SRL[25].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized24 | 74| +|607 | \MU_SRL[26].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized25 | 74| +|608 | \MU_SRL[27].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized26 | 138| +|609 | \MU_SRL[28].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized27 | 74| +|610 | \MU_SRL[29].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized28 | 74| +|611 | \MU_SRL[2].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized1 | 74| +|612 | \MU_SRL[30].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized29 | 74| +|613 | \MU_SRL[31].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized30 | 90| +|614 | \MU_SRL[32].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized31 | 74| +|615 | \MU_SRL[33].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized32 | 74| +|616 | \MU_SRL[34].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized33 | 74| +|617 | \MU_SRL[35].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized34 | 90| +|618 | \MU_SRL[36].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized35 | 74| +|619 | \MU_SRL[37].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized36 | 74| +|620 | \MU_SRL[38].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized37 | 74| +|621 | \MU_SRL[39].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized38 | 90| +|622 | \MU_SRL[3].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized2 | 106| +|623 | \MU_SRL[40].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized39 | 74| +|624 | \MU_SRL[41].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized40 | 90| +|625 | \MU_SRL[4].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized3 | 74| +|626 | \MU_SRL[5].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized4 | 74| +|627 | \MU_SRL[6].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized5 | 74| +|628 | \MU_SRL[7].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized6 | 90| +|629 | \MU_SRL[8].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized7 | 74| +|630 | \MU_SRL[9].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized8 | 74| +|631 | \STRG_QUAL.qual_strg_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized77 | 74| +|632 | \TC_SRL[0].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized41 | 74| +|633 | \TC_SRL[10].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized51 | 74| +|634 | \TC_SRL[11].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized52 | 106| +|635 | \TC_SRL[12].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized53 | 74| +|636 | \TC_SRL[13].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized54 | 74| +|637 | \TC_SRL[14].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized55 | 74| +|638 | \TC_SRL[15].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized56 | 90| +|639 | \TC_SRL[16].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized57 | 74| +|640 | \TC_SRL[17].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized58 | 74| +|641 | \TC_SRL[18].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized59 | 74| +|642 | \TC_SRL[19].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized60 | 106| +|643 | \TC_SRL[1].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized42 | 74| +|644 | \TC_SRL[20].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized61 | 74| +|645 | \TC_SRL[21].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized62 | 74| +|646 | \TC_SRL[22].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized63 | 74| +|647 | \TC_SRL[23].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized64 | 90| +|648 | \TC_SRL[24].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized65 | 74| +|649 | \TC_SRL[25].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized66 | 74| +|650 | \TC_SRL[26].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized67 | 74| +|651 | \TC_SRL[27].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized68 | 122| +|652 | \TC_SRL[28].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized69 | 74| +|653 | \TC_SRL[29].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized70 | 74| +|654 | \TC_SRL[2].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized43 | 74| +|655 | \TC_SRL[30].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized71 | 74| +|656 | \TC_SRL[31].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized72 | 90| +|657 | \TC_SRL[3].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized44 | 106| +|658 | \TC_SRL[4].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized45 | 74| +|659 | \TC_SRL[5].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized46 | 74| +|660 | \TC_SRL[6].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized47 | 74| +|661 | \TC_SRL[7].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized48 | 90| +|662 | \TC_SRL[8].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized49 | 74| +|663 | \TC_SRL[9].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized50 | 74| +|664 | reg_15 |xsdbs_v1_0_2_reg__parameterized87 | 44| +|665 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_524 | 44| +|666 | reg_16 |xsdbs_v1_0_2_reg__parameterized88 | 18| +|667 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_523 | 18| +|668 | reg_17 |xsdbs_v1_0_2_reg__parameterized89 | 22| +|669 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_522 | 22| +|670 | reg_18 |xsdbs_v1_0_2_reg__parameterized90 | 32| +|671 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_521 | 32| +|672 | reg_19 |xsdbs_v1_0_2_reg__parameterized91 | 17| +|673 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_520 | 17| +|674 | reg_1a |xsdbs_v1_0_2_reg__parameterized92 | 27| +|675 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1 | 27| +|676 | reg_6 |xsdbs_v1_0_2_reg__parameterized72 | 32| +|677 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_519 | 32| +|678 | reg_7 |xsdbs_v1_0_2_reg__parameterized73 | 28| +|679 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized0 | 28| +|680 | reg_8 |xsdbs_v1_0_2_reg__parameterized74 | 6| +|681 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_518 | 6| +|682 | reg_80 |xsdbs_v1_0_2_reg__parameterized93 | 17| +|683 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2_517 | 17| +|684 | reg_81 |xsdbs_v1_0_2_reg__parameterized94 | 17| +|685 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_516 | 17| +|686 | reg_82 |xsdbs_v1_0_2_reg__parameterized95 | 17| +|687 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2 | 17| +|688 | reg_83 |xsdbs_v1_0_2_reg__parameterized96 | 58| +|689 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_515 | 58| +|690 | reg_84 |xsdbs_v1_0_2_reg__parameterized97 | 22| +|691 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_514 | 22| +|692 | reg_85 |xsdbs_v1_0_2_reg__parameterized98 | 19| +|693 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_513 | 19| +|694 | reg_887 |xsdbs_v1_0_2_reg__parameterized100 | 2| +|695 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_512 | 2| +|696 | reg_88d |xsdbs_v1_0_2_reg__parameterized102 | 2| +|697 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_511 | 2| +|698 | reg_88f |xsdbs_v1_0_2_reg__parameterized104 | 39| +|699 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_510 | 39| +|700 | reg_892 |xsdbs_v1_0_2_reg__parameterized103 | 7| +|701 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_509 | 7| +|702 | reg_9 |xsdbs_v1_0_2_reg__parameterized75 | 20| +|703 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_508 | 20| +|704 | reg_srl_fff |xsdbs_v1_0_2_reg_p2s__parameterized78 | 97| +|705 | reg_stream_ffd |xsdbs_v1_0_2_reg_stream__parameterized1 | 17| +|706 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl | 17| +|707 | reg_stream_ffe |xsdbs_v1_0_2_reg_stream__parameterized2 | 16| +|708 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat | 16| +|709 | u_ila_reset_ctrl |ila_v6_2_9_ila_reset_ctrl | 47| +|710 | arm_detection_inst |ltlib_v1_0_0_rising_edge_detection | 5| +|711 | \asyncrounous_transfer.arm_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer | 7| +|712 | \asyncrounous_transfer.arm_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_504 | 7| +|713 | \asyncrounous_transfer.halt_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer_505 | 7| +|714 | \asyncrounous_transfer.halt_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_506 | 6| +|715 | halt_detection_inst |ltlib_v1_0_0_rising_edge_detection_507 | 6| +|716 | u_trig |ila_v6_2_9_ila_trigger | 2484| +|717 | \N_DDR_TC.N_DDR_TC_INST[0].U_TC |ltlib_v1_0_0_match | 34| +|718 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_496 | 33| +|719 | DUT |ltlib_v1_0_0_all_typeA_497 | 33| +|720 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_498 | 5| +|721 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_499 | 5| +|722 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_500 | 5| +|723 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_501 | 5| +|724 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_502 | 5| +|725 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_503 | 6| +|726 | \N_DDR_TC.N_DDR_TC_INST[10].U_TC |ltlib_v1_0_0_match_0 | 34| +|727 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_488 | 33| +|728 | DUT |ltlib_v1_0_0_all_typeA_489 | 33| +|729 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_490 | 5| +|730 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_491 | 5| +|731 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_492 | 5| +|732 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_493 | 5| +|733 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_494 | 5| +|734 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_495 | 6| +|735 | \N_DDR_TC.N_DDR_TC_INST[11].U_TC |ltlib_v1_0_0_match_1 | 34| +|736 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_480 | 33| +|737 | DUT |ltlib_v1_0_0_all_typeA_481 | 33| +|738 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_482 | 5| +|739 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_483 | 5| +|740 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_484 | 5| +|741 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_485 | 5| +|742 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_486 | 5| +|743 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_487 | 6| +|744 | \N_DDR_TC.N_DDR_TC_INST[12].U_TC |ltlib_v1_0_0_match_2 | 34| +|745 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_472 | 33| +|746 | DUT |ltlib_v1_0_0_all_typeA_473 | 33| +|747 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_474 | 5| +|748 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_475 | 5| +|749 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_476 | 5| +|750 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_477 | 5| +|751 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_478 | 5| +|752 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_479 | 6| +|753 | \N_DDR_TC.N_DDR_TC_INST[13].U_TC |ltlib_v1_0_0_match_3 | 34| +|754 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_464 | 33| +|755 | DUT |ltlib_v1_0_0_all_typeA_465 | 33| +|756 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_466 | 5| +|757 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_467 | 5| +|758 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_468 | 5| +|759 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_469 | 5| +|760 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_470 | 5| +|761 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_471 | 6| +|762 | \N_DDR_TC.N_DDR_TC_INST[14].U_TC |ltlib_v1_0_0_match_4 | 34| +|763 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_456 | 33| +|764 | DUT |ltlib_v1_0_0_all_typeA_457 | 33| +|765 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_458 | 5| +|766 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_459 | 5| +|767 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_460 | 5| +|768 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_461 | 5| +|769 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_462 | 5| +|770 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_463 | 6| +|771 | \N_DDR_TC.N_DDR_TC_INST[15].U_TC |ltlib_v1_0_0_match_5 | 34| +|772 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_448 | 33| +|773 | DUT |ltlib_v1_0_0_all_typeA_449 | 33| +|774 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_450 | 5| +|775 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_451 | 5| +|776 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_452 | 5| +|777 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_453 | 5| +|778 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_454 | 5| +|779 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_455 | 6| +|780 | \N_DDR_TC.N_DDR_TC_INST[16].U_TC |ltlib_v1_0_0_match_6 | 34| +|781 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_440 | 33| +|782 | DUT |ltlib_v1_0_0_all_typeA_441 | 33| +|783 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_442 | 5| +|784 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_443 | 5| +|785 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_444 | 5| +|786 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_445 | 5| +|787 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_446 | 5| +|788 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_447 | 6| +|789 | \N_DDR_TC.N_DDR_TC_INST[17].U_TC |ltlib_v1_0_0_match_7 | 34| +|790 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_432 | 33| +|791 | DUT |ltlib_v1_0_0_all_typeA_433 | 33| +|792 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_434 | 5| +|793 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_435 | 5| +|794 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_436 | 5| +|795 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_437 | 5| +|796 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_438 | 5| +|797 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_439 | 6| +|798 | \N_DDR_TC.N_DDR_TC_INST[18].U_TC |ltlib_v1_0_0_match_8 | 34| +|799 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_424 | 33| +|800 | DUT |ltlib_v1_0_0_all_typeA_425 | 33| +|801 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_426 | 5| +|802 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_427 | 5| +|803 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_428 | 5| +|804 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_429 | 5| +|805 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_430 | 5| +|806 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_431 | 6| +|807 | \N_DDR_TC.N_DDR_TC_INST[19].U_TC |ltlib_v1_0_0_match_9 | 34| +|808 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_416 | 33| +|809 | DUT |ltlib_v1_0_0_all_typeA_417 | 33| +|810 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_418 | 5| +|811 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_419 | 5| +|812 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_420 | 5| +|813 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_421 | 5| +|814 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_422 | 5| +|815 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_423 | 6| +|816 | \N_DDR_TC.N_DDR_TC_INST[1].U_TC |ltlib_v1_0_0_match_10 | 34| +|817 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_408 | 33| +|818 | DUT |ltlib_v1_0_0_all_typeA_409 | 33| +|819 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_410 | 5| +|820 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_411 | 5| +|821 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_412 | 5| +|822 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_413 | 5| +|823 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_414 | 5| +|824 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_415 | 6| +|825 | \N_DDR_TC.N_DDR_TC_INST[20].U_TC |ltlib_v1_0_0_match_11 | 34| +|826 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_400 | 33| +|827 | DUT |ltlib_v1_0_0_all_typeA_401 | 33| +|828 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_402 | 5| +|829 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_403 | 5| +|830 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_404 | 5| +|831 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_405 | 5| +|832 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_406 | 5| +|833 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_407 | 6| +|834 | \N_DDR_TC.N_DDR_TC_INST[21].U_TC |ltlib_v1_0_0_match_12 | 34| +|835 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_392 | 33| +|836 | DUT |ltlib_v1_0_0_all_typeA_393 | 33| +|837 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_394 | 5| +|838 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_395 | 5| +|839 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_396 | 5| +|840 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_397 | 5| +|841 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_398 | 5| +|842 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_399 | 6| +|843 | \N_DDR_TC.N_DDR_TC_INST[22].U_TC |ltlib_v1_0_0_match_13 | 34| +|844 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_384 | 33| +|845 | DUT |ltlib_v1_0_0_all_typeA_385 | 33| +|846 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_386 | 5| +|847 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_387 | 5| +|848 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_388 | 5| +|849 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_389 | 5| +|850 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_390 | 5| +|851 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_391 | 6| +|852 | \N_DDR_TC.N_DDR_TC_INST[23].U_TC |ltlib_v1_0_0_match_14 | 34| +|853 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_376 | 33| +|854 | DUT |ltlib_v1_0_0_all_typeA_377 | 33| +|855 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_378 | 5| +|856 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_379 | 5| +|857 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_380 | 5| +|858 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_381 | 5| +|859 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_382 | 5| +|860 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_383 | 6| +|861 | \N_DDR_TC.N_DDR_TC_INST[24].U_TC |ltlib_v1_0_0_match_15 | 34| +|862 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_368 | 33| +|863 | DUT |ltlib_v1_0_0_all_typeA_369 | 33| +|864 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_370 | 5| +|865 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_371 | 5| +|866 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_372 | 5| +|867 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_373 | 5| +|868 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_374 | 5| +|869 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_375 | 6| +|870 | \N_DDR_TC.N_DDR_TC_INST[25].U_TC |ltlib_v1_0_0_match_16 | 34| +|871 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_360 | 33| +|872 | DUT |ltlib_v1_0_0_all_typeA_361 | 33| +|873 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_362 | 5| +|874 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_363 | 5| +|875 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_364 | 5| +|876 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_365 | 5| +|877 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_366 | 5| +|878 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_367 | 6| +|879 | \N_DDR_TC.N_DDR_TC_INST[26].U_TC |ltlib_v1_0_0_match_17 | 34| +|880 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_352 | 33| +|881 | DUT |ltlib_v1_0_0_all_typeA_353 | 33| +|882 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_354 | 5| +|883 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_355 | 5| +|884 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_356 | 5| +|885 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_357 | 5| +|886 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_358 | 5| +|887 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_359 | 6| +|888 | \N_DDR_TC.N_DDR_TC_INST[27].U_TC |ltlib_v1_0_0_match_18 | 34| +|889 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_344 | 33| +|890 | DUT |ltlib_v1_0_0_all_typeA_345 | 33| +|891 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_346 | 5| +|892 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_347 | 5| +|893 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_348 | 5| +|894 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_349 | 5| +|895 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_350 | 5| +|896 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_351 | 6| +|897 | \N_DDR_TC.N_DDR_TC_INST[28].U_TC |ltlib_v1_0_0_match_19 | 34| +|898 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_336 | 33| +|899 | DUT |ltlib_v1_0_0_all_typeA_337 | 33| +|900 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_338 | 5| +|901 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_339 | 5| +|902 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_340 | 5| +|903 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_341 | 5| +|904 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_342 | 5| +|905 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_343 | 6| +|906 | \N_DDR_TC.N_DDR_TC_INST[29].U_TC |ltlib_v1_0_0_match_20 | 34| +|907 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_328 | 33| +|908 | DUT |ltlib_v1_0_0_all_typeA_329 | 33| +|909 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_330 | 5| +|910 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_331 | 5| +|911 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_332 | 5| +|912 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_333 | 5| +|913 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_334 | 5| +|914 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_335 | 6| +|915 | \N_DDR_TC.N_DDR_TC_INST[2].U_TC |ltlib_v1_0_0_match_21 | 34| +|916 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_320 | 33| +|917 | DUT |ltlib_v1_0_0_all_typeA_321 | 33| +|918 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_322 | 5| +|919 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_323 | 5| +|920 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_324 | 5| +|921 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_325 | 5| +|922 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_326 | 5| +|923 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_327 | 6| +|924 | \N_DDR_TC.N_DDR_TC_INST[30].U_TC |ltlib_v1_0_0_match_22 | 34| +|925 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_312 | 33| +|926 | DUT |ltlib_v1_0_0_all_typeA_313 | 33| +|927 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_314 | 5| +|928 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_315 | 5| +|929 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_316 | 5| +|930 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_317 | 5| +|931 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_318 | 5| +|932 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_319 | 6| +|933 | \N_DDR_TC.N_DDR_TC_INST[31].U_TC |ltlib_v1_0_0_match_23 | 34| +|934 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_304 | 33| +|935 | DUT |ltlib_v1_0_0_all_typeA_305 | 33| +|936 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_306 | 5| +|937 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_307 | 5| +|938 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_308 | 5| +|939 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_309 | 5| +|940 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_310 | 5| +|941 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_311 | 6| +|942 | \N_DDR_TC.N_DDR_TC_INST[3].U_TC |ltlib_v1_0_0_match_24 | 34| +|943 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_296 | 33| +|944 | DUT |ltlib_v1_0_0_all_typeA_297 | 33| +|945 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_298 | 5| +|946 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_299 | 5| +|947 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_300 | 5| +|948 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_301 | 5| +|949 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_302 | 5| +|950 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_303 | 6| +|951 | \N_DDR_TC.N_DDR_TC_INST[4].U_TC |ltlib_v1_0_0_match_25 | 34| +|952 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_288 | 33| +|953 | DUT |ltlib_v1_0_0_all_typeA_289 | 33| +|954 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_290 | 5| +|955 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_291 | 5| +|956 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_292 | 5| +|957 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_293 | 5| +|958 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_294 | 5| +|959 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_295 | 6| +|960 | \N_DDR_TC.N_DDR_TC_INST[5].U_TC |ltlib_v1_0_0_match_26 | 34| +|961 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_280 | 33| +|962 | DUT |ltlib_v1_0_0_all_typeA_281 | 33| +|963 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_282 | 5| +|964 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_283 | 5| +|965 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_284 | 5| +|966 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_285 | 5| +|967 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_286 | 5| +|968 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_287 | 6| +|969 | \N_DDR_TC.N_DDR_TC_INST[6].U_TC |ltlib_v1_0_0_match_27 | 34| +|970 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_272 | 33| +|971 | DUT |ltlib_v1_0_0_all_typeA_273 | 33| +|972 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_274 | 5| +|973 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_275 | 5| +|974 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_276 | 5| +|975 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_277 | 5| +|976 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_278 | 5| +|977 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_279 | 6| +|978 | \N_DDR_TC.N_DDR_TC_INST[7].U_TC |ltlib_v1_0_0_match_28 | 34| +|979 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_264 | 33| +|980 | DUT |ltlib_v1_0_0_all_typeA_265 | 33| +|981 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_266 | 5| +|982 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_267 | 5| +|983 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_268 | 5| +|984 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_269 | 5| +|985 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_270 | 5| +|986 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_271 | 6| +|987 | \N_DDR_TC.N_DDR_TC_INST[8].U_TC |ltlib_v1_0_0_match_29 | 34| +|988 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_256 | 33| +|989 | DUT |ltlib_v1_0_0_all_typeA_257 | 33| +|990 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_258 | 5| +|991 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_259 | 5| +|992 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_260 | 5| +|993 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_261 | 5| +|994 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_262 | 5| +|995 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_263 | 6| +|996 | \N_DDR_TC.N_DDR_TC_INST[9].U_TC |ltlib_v1_0_0_match_30 | 34| +|997 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_248 | 33| +|998 | DUT |ltlib_v1_0_0_all_typeA_249 | 33| +|999 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_250 | 5| +|1000 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_251 | 5| +|1001 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_252 | 5| +|1002 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_253 | 5| +|1003 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_254 | 5| +|1004 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_255 | 6| +|1005 | \STRG_QUAL.U_STRG_QUAL |ltlib_v1_0_0_match_31 | 76| +|1006 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA | 75| +|1007 | DUT |ltlib_v1_0_0_all_typeA | 33| +|1008 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_242 | 5| +|1009 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_243 | 5| +|1010 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_244 | 5| +|1011 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_245 | 5| +|1012 | \I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_246 | 5| +|1013 | \I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_247 | 6| +|1014 | U_TM |ila_v6_2_9_ila_trig_match | 1272| +|1015 | \N_DDR_MODE.G_NMU[0].U_M |ltlib_v1_0_0_match__parameterized0 | 11| +|1016 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_239 | 10| +|1017 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_240 | 8| +|1018 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_241 | 6| +|1019 | \N_DDR_MODE.G_NMU[10].U_M |ltlib_v1_0_0_match__parameterized1 | 55| +|1020 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_234 | 54| +|1021 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_235 | 18| +|1022 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_236 | 5| +|1023 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_237 | 5| +|1024 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_238 | 6| +|1025 | \N_DDR_MODE.G_NMU[11].U_M |ltlib_v1_0_0_match__parameterized1_32 | 19| +|1026 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_229 | 18| +|1027 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_230 | 18| +|1028 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_231 | 5| +|1029 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_232 | 5| +|1030 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_233 | 6| +|1031 | \N_DDR_MODE.G_NMU[12].U_M |ltlib_v1_0_0_match__parameterized1_33 | 55| +|1032 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_224 | 54| +|1033 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_225 | 18| +|1034 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_226 | 5| +|1035 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_227 | 5| +|1036 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_228 | 6| +|1037 | \N_DDR_MODE.G_NMU[13].U_M |ltlib_v1_0_0_match__parameterized1_34 | 19| +|1038 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_219 | 18| +|1039 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_220 | 18| +|1040 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_221 | 5| +|1041 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_222 | 5| +|1042 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_223 | 6| +|1043 | \N_DDR_MODE.G_NMU[14].U_M |ltlib_v1_0_0_match__parameterized1_35 | 55| +|1044 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_214 | 54| +|1045 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_215 | 18| +|1046 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_216 | 5| +|1047 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_217 | 5| +|1048 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_218 | 6| +|1049 | \N_DDR_MODE.G_NMU[15].U_M |ltlib_v1_0_0_match__parameterized1_36 | 19| +|1050 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_209 | 18| +|1051 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_210 | 18| +|1052 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_211 | 5| +|1053 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_212 | 5| +|1054 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_213 | 6| +|1055 | \N_DDR_MODE.G_NMU[16].U_M |ltlib_v1_0_0_match__parameterized1_37 | 55| +|1056 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_204 | 54| +|1057 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_205 | 18| +|1058 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_206 | 5| +|1059 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_207 | 5| +|1060 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_208 | 6| +|1061 | \N_DDR_MODE.G_NMU[17].U_M |ltlib_v1_0_0_match__parameterized1_38 | 19| +|1062 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_199 | 18| +|1063 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_200 | 18| +|1064 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_201 | 5| +|1065 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_202 | 5| +|1066 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_203 | 6| +|1067 | \N_DDR_MODE.G_NMU[18].U_M |ltlib_v1_0_0_match__parameterized2 | 36| +|1068 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_195 | 35| +|1069 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_196 | 13| +|1070 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_197 | 5| +|1071 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_198 | 6| +|1072 | \N_DDR_MODE.G_NMU[19].U_M |ltlib_v1_0_0_match__parameterized2_39 | 14| +|1073 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_191 | 13| +|1074 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_192 | 13| +|1075 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_193 | 5| +|1076 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_194 | 6| +|1077 | \N_DDR_MODE.G_NMU[1].U_M |ltlib_v1_0_0_match__parameterized0_40 | 9| +|1078 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_188 | 8| +|1079 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_189 | 8| +|1080 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_190 | 6| +|1081 | \N_DDR_MODE.G_NMU[20].U_M |ltlib_v1_0_0_match__parameterized2_41 | 36| +|1082 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_184 | 35| +|1083 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_185 | 13| +|1084 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_186 | 5| +|1085 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_187 | 6| +|1086 | \N_DDR_MODE.G_NMU[21].U_M |ltlib_v1_0_0_match__parameterized2_42 | 14| +|1087 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_180 | 13| +|1088 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_181 | 13| +|1089 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_182 | 5| +|1090 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_183 | 6| +|1091 | \N_DDR_MODE.G_NMU[22].U_M |ltlib_v1_0_0_match__parameterized2_43 | 36| +|1092 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_176 | 35| +|1093 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_177 | 13| +|1094 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_178 | 5| +|1095 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_179 | 6| +|1096 | \N_DDR_MODE.G_NMU[23].U_M |ltlib_v1_0_0_match__parameterized2_44 | 14| +|1097 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_172 | 13| +|1098 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_173 | 13| +|1099 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_174 | 5| +|1100 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_175 | 6| +|1101 | \N_DDR_MODE.G_NMU[24].U_M |ltlib_v1_0_0_match__parameterized2_45 | 36| +|1102 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_168 | 35| +|1103 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_169 | 13| +|1104 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_170 | 5| +|1105 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_171 | 6| +|1106 | \N_DDR_MODE.G_NMU[25].U_M |ltlib_v1_0_0_match__parameterized2_46 | 14| +|1107 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2 | 13| +|1108 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_165 | 13| +|1109 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_166 | 5| +|1110 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_167 | 6| +|1111 | \N_DDR_MODE.G_NMU[26].U_M |ltlib_v1_0_0_match__parameterized0_47 | 11| +|1112 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_162 | 10| +|1113 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_163 | 8| +|1114 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_164 | 6| +|1115 | \N_DDR_MODE.G_NMU[27].U_M |ltlib_v1_0_0_match__parameterized0_48 | 9| +|1116 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0 | 8| +|1117 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_160 | 8| +|1118 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_161 | 6| +|1119 | \N_DDR_MODE.G_NMU[28].U_M |ltlib_v1_0_0_match__parameterized3 | 15| +|1120 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized3_157 | 14| +|1121 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_158 | 8| +|1122 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_159 | 6| +|1123 | \N_DDR_MODE.G_NMU[29].U_M |ltlib_v1_0_0_match__parameterized3_49 | 9| +|1124 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized3 | 8| +|1125 | DUT |ltlib_v1_0_0_all_typeA__parameterized0 | 8| +|1126 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_156 | 6| +|1127 | \N_DDR_MODE.G_NMU[2].U_M |ltlib_v1_0_0_match__parameterized1_50 | 55| +|1128 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_151 | 54| +|1129 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_152 | 18| +|1130 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_153 | 5| +|1131 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_154 | 5| +|1132 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_155 | 6| +|1133 | \N_DDR_MODE.G_NMU[30].U_M |ltlib_v1_0_0_match__parameterized4 | 38| +|1134 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_147 | 37| +|1135 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_148 | 13| +|1136 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_149 | 5| +|1137 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_150 | 6| +|1138 | \N_DDR_MODE.G_NMU[31].U_M |ltlib_v1_0_0_match__parameterized4_51 | 14| +|1139 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_143 | 13| +|1140 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_144 | 13| +|1141 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_145 | 5| +|1142 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_146 | 6| +|1143 | \N_DDR_MODE.G_NMU[32].U_M |ltlib_v1_0_0_match__parameterized4_52 | 38| +|1144 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_139 | 37| +|1145 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_140 | 13| +|1146 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_141 | 5| +|1147 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_142 | 6| +|1148 | \N_DDR_MODE.G_NMU[33].U_M |ltlib_v1_0_0_match__parameterized4_53 | 14| +|1149 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_135 | 13| +|1150 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_136 | 13| +|1151 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_137 | 5| +|1152 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_138 | 6| +|1153 | \N_DDR_MODE.G_NMU[34].U_M |ltlib_v1_0_0_match__parameterized1_54 | 55| +|1154 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_130 | 54| +|1155 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_131 | 18| +|1156 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_132 | 5| +|1157 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_133 | 5| +|1158 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_134 | 6| +|1159 | \N_DDR_MODE.G_NMU[35].U_M |ltlib_v1_0_0_match__parameterized1_55 | 19| +|1160 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_125 | 18| +|1161 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_126 | 18| +|1162 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_127 | 5| +|1163 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_128 | 5| +|1164 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_129 | 6| +|1165 | \N_DDR_MODE.G_NMU[36].U_M |ltlib_v1_0_0_match__parameterized1_56 | 55| +|1166 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_120 | 54| +|1167 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_121 | 18| +|1168 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_122 | 5| +|1169 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_123 | 5| +|1170 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_124 | 6| +|1171 | \N_DDR_MODE.G_NMU[37].U_M |ltlib_v1_0_0_match__parameterized1_57 | 19| +|1172 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_115 | 18| +|1173 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_116 | 18| +|1174 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_117 | 5| +|1175 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_118 | 5| +|1176 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_119 | 6| +|1177 | \N_DDR_MODE.G_NMU[38].U_M |ltlib_v1_0_0_match__parameterized5 | 88| +|1178 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5_109 | 87| +|1179 | DUT |ltlib_v1_0_0_all_typeA__parameterized3_110 | 23| +|1180 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_111 | 5| +|1181 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_112 | 5| +|1182 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_113 | 5| +|1183 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_114 | 6| +|1184 | \N_DDR_MODE.G_NMU[39].U_M |ltlib_v1_0_0_match__parameterized5_58 | 24| +|1185 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized5 | 23| +|1186 | DUT |ltlib_v1_0_0_all_typeA__parameterized3 | 23| +|1187 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_105 | 5| +|1188 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_106 | 5| +|1189 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_107 | 5| +|1190 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_108 | 6| +|1191 | \N_DDR_MODE.G_NMU[3].U_M |ltlib_v1_0_0_match__parameterized1_59 | 19| +|1192 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_100 | 18| +|1193 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_101 | 18| +|1194 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_102 | 5| +|1195 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_103 | 5| +|1196 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_104 | 6| +|1197 | \N_DDR_MODE.G_NMU[40].U_M |ltlib_v1_0_0_match__parameterized4_60 | 38| +|1198 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4_96 | 37| +|1199 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_97 | 13| +|1200 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_98 | 5| +|1201 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_99 | 6| +|1202 | \N_DDR_MODE.G_NMU[41].U_M |ltlib_v1_0_0_match__parameterized4_61 | 14| +|1203 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized4 | 13| +|1204 | DUT |ltlib_v1_0_0_all_typeA__parameterized2 | 13| +|1205 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_94 | 5| +|1206 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_95 | 6| +|1207 | \N_DDR_MODE.G_NMU[4].U_M |ltlib_v1_0_0_match__parameterized1_62 | 55| +|1208 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_89 | 54| +|1209 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_90 | 18| +|1210 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_91 | 5| +|1211 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_92 | 5| +|1212 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_93 | 6| +|1213 | \N_DDR_MODE.G_NMU[5].U_M |ltlib_v1_0_0_match__parameterized1_63 | 19| +|1214 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_84 | 18| +|1215 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_85 | 18| +|1216 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_86 | 5| +|1217 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_87 | 5| +|1218 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_88 | 6| +|1219 | \N_DDR_MODE.G_NMU[6].U_M |ltlib_v1_0_0_match__parameterized1_64 | 55| +|1220 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_79 | 54| +|1221 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_80 | 18| +|1222 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_81 | 5| +|1223 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_82 | 5| +|1224 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_83 | 6| +|1225 | \N_DDR_MODE.G_NMU[7].U_M |ltlib_v1_0_0_match__parameterized1_65 | 19| +|1226 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_74 | 18| +|1227 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_75 | 18| +|1228 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_76 | 5| +|1229 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_77 | 5| +|1230 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_78 | 6| +|1231 | \N_DDR_MODE.G_NMU[8].U_M |ltlib_v1_0_0_match__parameterized1_66 | 55| +|1232 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_69 | 54| +|1233 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_70 | 18| +|1234 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_71 | 5| +|1235 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_72 | 5| +|1236 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_73 | 6| +|1237 | \N_DDR_MODE.G_NMU[9].U_M |ltlib_v1_0_0_match__parameterized1_67 | 19| +|1238 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1 | 18| +|1239 | DUT |ltlib_v1_0_0_all_typeA__parameterized1 | 18| +|1240 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice | 5| +|1241 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_68 | 5| +|1242 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0 | 6| +|1243 | xsdb_memory_read_inst |ltlib_v1_0_0_generic_memrd | 870| +------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:03:23 ; elapsed = 00:03:44 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 984 ; free virtual = 43301 +Finished Writing Synthesis Report : Time (s): cpu = 00:02:00 ; elapsed = 00:02:13 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 536 ; free virtual = 43946 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1003 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:03:17 ; elapsed = 00:03:38 . Memory (MB): peak = 2608.020 ; gain = 852.859 ; free physical = 3690 ; free virtual = 46006 -Synthesis Optimization Complete : Time (s): cpu = 00:03:24 ; elapsed = 00:03:45 . Memory (MB): peak = 2608.020 ; gain = 916.891 ; free physical = 3690 ; free virtual = 46006 +Synthesis finished with 0 errors, 0 critical warnings and 10707 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:55 ; elapsed = 00:02:08 . Memory (MB): peak = 2443.652 ; gain = 668.617 ; free physical = 582 ; free virtual = 43993 +Synthesis Optimization Complete : Time (s): cpu = 00:02:00 ; elapsed = 00:02:13 . Memory (MB): peak = 2443.652 ; gain = 752.461 ; free physical = 596 ; free virtual = 44006 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 3407 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 2528 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2616.023 ; gain = 0.000 ; free physical = 3582 ; free virtual = 45899 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2443.652 ; gain = 0.000 ; free physical = 668 ; free virtual = 44084 INFO: [Project 1-111] Unisim Transformation Summary: - A total of 1344 instances were transformed. - CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 1232 instances - CFGLUT5 => SRLC32E: 80 instances + A total of 1334 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 1224 instances + CFGLUT5 => SRLC32E: 78 instances RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 32 instances INFO: [Common 17-83] Releasing license: Synthesis -398 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. +393 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:03:29 ; elapsed = 00:03:50 . Memory (MB): peak = 2616.023 ; gain = 1204.570 ; free physical = 3726 ; free virtual = 46043 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2616.023 ; gain = 0.000 ; free physical = 3726 ; free virtual = 46043 +synth_design: Time (s): cpu = 00:02:05 ; elapsed = 00:02:18 . Memory (MB): peak = 2443.652 ; gain = 1032.199 ; free physical = 736 ; free virtual = 44153 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2443.652 ; gain = 0.000 ; free physical = 731 ; free virtual = 44147 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ila_freq_comp, cache-ID = 5e0193d275cb4eca -INFO: [Coretcl 2-1174] Renamed 1770 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2640.035 ; gain = 0.000 ; free physical = 3672 ; free virtual = 46040 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ila_freq_comp, cache-ID = 550f19e2bcab89f4 +INFO: [Coretcl 2-1174] Renamed 1242 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2467.664 ; gain = 0.000 ; free physical = 704 ; free virtual = 44170 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file ila_freq_comp_utilization_synth.rpt -pb ila_freq_comp_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Mon May 8 12:16:14 2023... +INFO: [Common 17-206] Exiting Vivado at Fri May 12 16:06:04 2023... diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.v index 4f923514..2c7ee1a9 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e8e7200f4395edba4481919e098863a6a7fd3778af090109fcee96297f7db274 -size 18011561 +oid sha256:89c5e821de1bbd17ea62f021a9991db343820db0f85a52c7312ce1c5d1a70a25 +size 12146898 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.vhdl index 578dac67..7440011d 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f141430a5a41fde5e9944483f8cda8a2648c839774ff52828aed356e6de3dcfd -size 21597145 +oid sha256:a17d9c1e5462a5933eb41329e115f3eae9713ad2775740a719930a516b4e7daf +size 15059408 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v index df69028e..057f4af7 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 12:16:12 2023 +// Date : Fri May 12 16:06:03 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v @@ -16,10 +16,10 @@ (* X_CORE_INFO = "ila,Vivado 2019.1.3" *) module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5, probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, - probe18, probe19, probe20, probe21) -/* synthesis syn_black_box black_box_pad_pin="clk,probe0[17:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[2:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[31:0],probe14[0:0],probe15[31:0],probe16[11:0],probe17[11:0],probe18[9:0],probe19[9:0],probe20[9:0],probe21[9:0]" */; + probe18, probe19, probe20) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[10:0],probe10[10:0],probe11[10:0],probe12[10:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[31:0],probe20[11:0]" */; input clk; - input [17:0]probe0; + input [0:0]probe0; input [17:0]probe1; input [17:0]probe2; input [17:0]probe3; @@ -28,17 +28,16 @@ module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5, input [17:0]probe6; input [17:0]probe7; input [17:0]probe8; - input [2:0]probe9; - input [0:0]probe10; - input [0:0]probe11; - input [0:0]probe12; - input [31:0]probe13; - input [0:0]probe14; - input [31:0]probe15; + input [10:0]probe9; + input [10:0]probe10; + input [10:0]probe11; + input [10:0]probe12; + input [0:0]probe13; + input [2:0]probe14; + input [11:0]probe15; input [11:0]probe16; - input [11:0]probe17; - input [9:0]probe18; - input [9:0]probe19; - input [9:0]probe20; - input [9:0]probe21; + input [17:0]probe17; + input [17:0]probe18; + input [31:0]probe19; + input [11:0]probe20; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl index 2531f1e9..51c469a0 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 12:16:12 2023 +-- Date : Fri May 12 16:06:03 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl @@ -15,7 +15,7 @@ use IEEE.STD_LOGIC_1164.ALL; entity ila_freq_comp is Port ( clk : in STD_LOGIC; - probe0 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 ); probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 ); probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 ); @@ -24,19 +24,18 @@ entity ila_freq_comp is probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 ); probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 ); probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 ); - probe9 : in STD_LOGIC_VECTOR ( 2 downto 0 ); - probe10 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe11 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe12 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe13 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - probe14 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe15 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe10 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe11 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe12 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe13 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe14 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + probe15 : in STD_LOGIC_VECTOR ( 11 downto 0 ); probe16 : in STD_LOGIC_VECTOR ( 11 downto 0 ); - probe17 : in STD_LOGIC_VECTOR ( 11 downto 0 ); - probe18 : in STD_LOGIC_VECTOR ( 9 downto 0 ); - probe19 : in STD_LOGIC_VECTOR ( 9 downto 0 ); - probe20 : in STD_LOGIC_VECTOR ( 9 downto 0 ); - probe21 : in STD_LOGIC_VECTOR ( 9 downto 0 ) + probe17 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe18 : in STD_LOGIC_VECTOR ( 17 downto 0 ); + probe19 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe20 : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end ila_freq_comp; @@ -45,7 +44,7 @@ architecture stub of ila_freq_comp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe0[17:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[2:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[31:0],probe14[0:0],probe15[31:0],probe16[11:0],probe17[11:0],probe18[9:0],probe19[9:0],probe20[9:0],probe21[9:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[10:0],probe10[10:0],probe11[10:0],probe12[10:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[31:0],probe20[11:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.pb index 4aa2ac19..eba608d6 100644 Binary files a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.pb and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.rpt index 15e56b9e..d2ff3376 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.rpt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Mon May 8 12:16:12 2023 +| Date : Fri May 12 16:06:03 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file ila_freq_comp_utilization_synth.rpt -pb ila_freq_comp_utilization_synth.pb | Design : ila_freq_comp @@ -30,16 +30,16 @@ Table of Contents +----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 6829 | 0 | 254200 | 2.69 | -| LUT as Logic | 5065 | 0 | 254200 | 1.99 | -| LUT as Memory | 1764 | 0 | 90600 | 1.95 | +| Slice LUTs* | 5942 | 0 | 254200 | 2.34 | +| LUT as Logic | 4188 | 0 | 254200 | 1.65 | +| LUT as Memory | 1754 | 0 | 90600 | 1.94 | | LUT as Distributed RAM | 128 | 0 | | | -| LUT as Shift Register | 1636 | 0 | | | -| Slice Registers | 6698 | 0 | 508400 | 1.32 | -| Register as Flip Flop | 6698 | 0 | 508400 | 1.32 | +| LUT as Shift Register | 1626 | 0 | | | +| Slice Registers | 6361 | 0 | 508400 | 1.25 | +| Register as Flip Flop | 6361 | 0 | 508400 | 1.25 | | Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 777 | 0 | 127100 | 0.61 | -| F8 Muxes | 338 | 0 | 63550 | 0.53 | +| F7 Muxes | 500 | 0 | 127100 | 0.39 | +| F8 Muxes | 17 | 0 | 63550 | 0.03 | +----------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -59,7 +59,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 9 | Yes | Set | - | -| 6689 | Yes | Reset | - | +| 6352 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -69,9 +69,9 @@ Table of Contents +-------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 532 | 0 | 795 | 66.92 | -| RAMB36/FIFO* | 532 | 0 | 795 | 66.92 | -| RAMB36E1 only | 532 | | | | +| Block RAM Tile | 265 | 0 | 795 | 33.33 | +| RAMB36/FIFO* | 265 | 0 | 795 | 33.33 | +| RAMB36E1 only | 265 | | | | | RAMB18 | 0 | 0 | 1590 | 0.00 | +-------------------+------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 @@ -154,20 +154,20 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 6689 | Flop & Latch | -| LUT6 | 3387 | LUT | -| SRL16E | 1537 | Distributed Memory | -| SRLC32E | 1329 | Distributed Memory | -| LUT4 | 836 | LUT | -| MUXF7 | 777 | MuxFx | -| LUT3 | 692 | LUT | -| RAMB36E1 | 532 | Block Memory | -| CARRY4 | 416 | CarryLogic | -| MUXF8 | 338 | MuxFx | -| LUT2 | 201 | LUT | -| LUT5 | 189 | LUT | +| FDRE | 6352 | Flop & Latch | +| LUT6 | 2747 | LUT | +| SRL16E | 1529 | Distributed Memory | +| SRLC32E | 1319 | Distributed Memory | +| LUT4 | 752 | LUT | +| MUXF7 | 500 | MuxFx | +| LUT3 | 481 | LUT | +| CARRY4 | 412 | CarryLogic | +| LUT5 | 277 | LUT | +| RAMB36E1 | 265 | Block Memory | +| LUT2 | 155 | LUT | | RAMD64E | 128 | Distributed Memory | -| LUT1 | 114 | LUT | +| LUT1 | 112 | LUT | +| MUXF8 | 17 | MuxFx | | FDSE | 9 | Flop & Latch | | SRLC16E | 2 | Distributed Memory | +----------+------+---------------------+ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/project.wdf index b8091625..0511c808 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/project.wdf +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/project.wdf @@ -6,8 +6,8 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:39:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:39:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3131:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3131:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 @@ -15,8 +15,11 @@ version:1 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differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..461e6e33 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/.vivado.end.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ISEWrap.js b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ISEWrap.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/__synthesis_is_complete__ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/dont_touch.xdc b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/dont_touch.xdc new file mode 100644 index 00000000..63e89e93 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control.xci +# IP: The module: 'ila_rf_auto_control' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_v6_2/constraints/ila_impl.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_auto_control'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_v6_2/constraints/ila.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_auto_control'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_auto_control'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control.xci +# IP: The module: 'ila_rf_auto_control' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_v6_2/constraints/ila_impl.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_auto_control'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_v6_2/constraints/ila.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_auto_control'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_auto_control'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/gen_run.xml new file mode 100644 index 00000000..f9abb6d4 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/htr.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/htr.txt new file mode 100644 index 00000000..2ea32481 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log ila_rf_auto_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_auto_control.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.dcp new file mode 100644 index 00000000..55e62bd0 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:baf9b1700cd1442732bc6e6b7efeed794629ff6f90f1682c35e5d6e766cb02d3 +size 1643891 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.tcl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.tcl new file mode 100644 index 00000000..d0d9557c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.tcl @@ -0,0 +1,159 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7k410tffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control.xci +set_property used_in_synthesis false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_v6_2/constraints/ila_impl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_v6_2/constraints/ila_impl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_v6_2/constraints/ila.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1 -new_name ila_rf_auto_control -ip [get_ips ila_rf_auto_control]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top ila_rf_auto_control -part xc7k410tffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix ila_rf_auto_control_ ila_rf_auto_control.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_auto_control_stub.v + lappend ipCachedFiles ila_rf_auto_control_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_auto_control_stub.vhdl + lappend ipCachedFiles ila_rf_auto_control_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_auto_control_sim_netlist.v + lappend ipCachedFiles ila_rf_auto_control_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_auto_control_sim_netlist.vhdl + lappend ipCachedFiles ila_rf_auto_control_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp ila_rf_auto_control.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips ila_rf_auto_control] +} + +rename_ref -prefix_all ila_rf_auto_control_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef ila_rf_auto_control.dcp +create_report "ila_rf_auto_control_synth_1_synth_report_utilization_0" "report_utilization -file ila_rf_auto_control_utilization_synth.rpt -pb ila_rf_auto_control_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rf_auto_control + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.vds b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.vds new file mode 100644 index 00000000..2a419f80 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.vds @@ -0,0 +1,2838 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Fri May 12 16:02:01 2023 +# Process ID: 1473087 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1 +# Command line: vivado -log ila_rf_auto_control.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_auto_control.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/vivado.jou +#----------------------------------------------------------- +source ila_rf_auto_control.tcl -notrace +Command: synth_design -top ila_rf_auto_control -part xc7k410tffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Device 21-403] Loading part xc7k410tffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 1473172 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1852.973 ; gain = 162.719 ; free physical = 824 ; free virtual = 44266 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'ila_rf_auto_control' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/synth/ila_rf_auto_control.v:84] +INFO: [Synth 8-6157] synthesizing module 'CFGLUT5' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] +INFO: [Synth 8-6155] done synthesizing module 'CFGLUT5' (12#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] +INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] +INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (13#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (23#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] +INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] +INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (25#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] +INFO: [Synth 8-6157] synthesizing module 'SRLC16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] +INFO: [Synth 8-6155] done synthesizing module 'SRLC16E' (27#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] +INFO: [Synth 8-6157] synthesizing module 'FDRE' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +INFO: [Synth 8-6155] done synthesizing module 'FDRE' (32#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +WARNING: [Synth 8-7023] instance 'inst' of module 'ila_v6_2_9_ila' has 1033 connections declared, but only 1027 given [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/synth/ila_rf_auto_control.v:3219] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity ila_rf_auto_control does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/synth/ila_rf_auto_control.v:108] +INFO: [Synth 8-6155] done synthesizing module 'ila_rf_auto_control' (50#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/synth/ila_rf_auto_control.v:84] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port REGCEA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[35] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[34] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[33] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[32] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[31] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[30] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[29] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[28] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[27] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[26] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[25] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[24] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[23] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[22] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[21] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[20] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[19] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[18] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[17] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[16] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[15] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[14] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[13] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[12] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[11] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[10] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[9] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port SLEEP +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port ECCPIPECE +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port REGCEA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[35] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[34] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[33] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[32] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[31] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[30] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[29] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[28] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[27] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[26] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[25] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[24] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[23] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[22] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[21] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[20] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[19] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[18] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[17] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[16] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[15] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[14] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[13] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[12] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[11] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[10] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[9] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port SLEEP +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port ECCPIPECE +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port REGCEA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[17] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[16] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[15] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[14] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[13] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[12] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[11] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[10] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 2223.004 ; gain = 532.750 ; free physical = 1152 ; free virtual = 44456 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 2223.004 ; gain = 532.750 ; free physical = 1205 ; free virtual = 44487 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 2223.004 ; gain = 532.750 ; free physical = 1204 ; free virtual = 44487 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 579 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_rf_auto_control_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_v6_2/constraints/ila.xdc] for cell 'inst' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rf_auto_control/ila_v6_2/constraints/ila.xdc] for cell 'inst' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2308.848 ; gain = 0.000 ; free physical = 1066 ; free virtual = 44349 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 432 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 384 instances + CFGLUT5 => SRLC32E: 48 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2308.848 ; gain = 0.000 ; free physical = 1065 ; free virtual = 44347 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1115 ; free virtual = 44398 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k410tffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1115 ; free virtual = 44398 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1115 ; free virtual = 44398 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized47' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized48' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized11' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized12' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized13' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized14' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized15' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized16' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized17' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized18' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized19' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized20' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized21' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized22' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized23' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized24' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized25' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized26' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized27' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized28' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized29' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized30' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized31' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized32' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized33' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized34' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized35' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized36' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized37' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized38' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized39' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized40' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized41' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized42' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized43' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized44' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized45' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized46' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized47' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized48' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized11' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized12' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized13' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized14' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized15' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized16' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized17' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized18' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized19' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized20' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized21' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized22' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized23' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized24' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized25' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized26' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized27' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized28' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized29' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized30' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized31' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized32' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized33' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized34' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized35' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized36' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized37' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized38' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized39' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized40' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized41' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized42' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized43' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized44' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized45' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized46' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1039 ; free virtual = 44324 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 4 + 2 Input 10 Bit Adders := 3 + 2 Input 9 Bit Adders := 1 + 2 Input 7 Bit Adders := 4 + 2 Input 6 Bit Adders := 1 + 2 Input 4 Bit Adders := 50 + 2 Input 3 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 64 + 2 Input 1 Bit XORs := 4 ++---Registers : + 1024 Bit Registers := 2 + 128 Bit Registers := 1 + 80 Bit Registers := 1 + 75 Bit Registers := 9 + 33 Bit Registers := 2 + 32 Bit Registers := 17 + 24 Bit Registers := 1 + 17 Bit Registers := 2 + 16 Bit Registers := 188 + 12 Bit Registers := 33 + 10 Bit Registers := 9 + 9 Bit Registers := 1 + 8 Bit Registers := 5 + 7 Bit Registers := 5 + 6 Bit Registers := 2 + 4 Bit Registers := 53 + 3 Bit Registers := 1 + 2 Bit Registers := 6 + 1 Bit Registers := 349 ++---Muxes : + 2 Input 75 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 12 + 2 Input 16 Bit Muxes := 64 + 4 Input 16 Bit Muxes := 2 + 3 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 50 + 3 Input 15 Bit Muxes := 1 + 8 Input 10 Bit Muxes := 1 + 3 Input 7 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 4 + 2 Input 5 Bit Muxes := 2 + 2 Input 4 Bit Muxes := 152 + 5 Input 4 Bit Muxes := 50 + 2 Input 3 Bit Muxes := 50 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 6 + 2 Input 1 Bit Muxes := 300 + 4 Input 1 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 50 + 9 Input 1 Bit Muxes := 1 + 8 Input 1 Bit Muxes := 5 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module ila_v6_2_9_generic_counter +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 2 +Module ila_v6_2_9_ila_adv_trigger_sequencer +Detailed RTL Component Info : ++---Adders : + 2 Input 7 Bit Adders := 2 ++---Registers : + 24 Bit Registers := 1 + 16 Bit Registers := 1 + 7 Bit Registers := 2 + 4 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 10 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 9 + 4 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_fsm_memory_read +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 8 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized47 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_stat +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_ctl +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stream__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 17 Bit Registers := 1 + 16 Bit Registers := 4 + 1 Bit Registers := 4 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg__parameterized27 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized28 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized42 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized43 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized44 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized45 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized46 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized47 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized48 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized49 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized50 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized51 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized52 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized53 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized48 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_stream__parameterized1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_p2s +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized0 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized1 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized2 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized3 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized4 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized5 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized6 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized7 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized8 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized9 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized10 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized11 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized12 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized13 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized14 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized15 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized16 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized17 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized18 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized19 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized20 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized21 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized22 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized23 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized24 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized25 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized26 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized27 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized28 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized29 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized30 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized31 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized32 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized33 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized34 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized35 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized36 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized37 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized38 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized39 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized40 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized41 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized42 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized43 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized44 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized45 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized46 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_register +Detailed RTL Component Info : ++---Adders : + 2 Input 9 Bit Adders := 1 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 ++---Registers : + 1024 Bit Registers := 2 + 17 Bit Registers := 1 + 16 Bit Registers := 12 + 9 Bit Registers := 1 + 7 Bit Registers := 2 + 6 Bit Registers := 1 + 1 Bit Registers := 31 ++---Muxes : + 2 Input 16 Bit Muxes := 10 + 4 Input 16 Bit Muxes := 2 + 3 Input 16 Bit Muxes := 1 + 3 Input 15 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 4 + 2 Input 5 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 13 + 9 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 1 +Module ltlib_v1_0_0_match +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1 +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized2 +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized2 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ila_v6_2_9_ila_trigger +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 2 +Module ltlib_v1_0_0_async_edge_xfer +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 1 Bit Registers := 5 +Module ltlib_v1_0_0_rising_edge_detection +Detailed RTL Component Info : ++---Registers : + 2 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 2 Bit Muxes := 2 +Module ila_v6_2_9_ila_reset_ctrl +Detailed RTL Component Info : ++---Registers : + 6 Bit Registers := 1 + 1 Bit Registers := 2 +Module ltlib_v1_0_0_cfglut7 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 3 +Module ltlib_v1_0_0_cfglut6 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_allx_typeA_nodelay +Detailed RTL Component Info : ++---Registers : + 10 Bit Registers := 1 +Module ila_v6_2_9_ila_cap_sample_counter +Detailed RTL Component Info : ++---Adders : + 2 Input 10 Bit Adders := 1 ++---Registers : + 10 Bit Registers := 1 +Module ila_v6_2_9_ila_cap_window_counter +Detailed RTL Component Info : ++---Adders : + 2 Input 10 Bit Adders := 1 ++---Registers : + 10 Bit Registers := 1 +Module ila_v6_2_9_ila_cap_addrgen +Detailed RTL Component Info : ++---Registers : + 33 Bit Registers := 2 + 16 Bit Registers := 1 + 10 Bit Registers := 3 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 10 +Module ltlib_v1_0_0_cfglut6__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_cap_ctrl_legacy +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 3 ++---Muxes : + 2 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_generic_memrd +Detailed RTL Component Info : ++---Adders : + 2 Input 10 Bit Adders := 1 + 2 Input 3 Bit Adders := 1 ++---Registers : + 80 Bit Registers := 1 + 10 Bit Registers := 1 + 7 Bit Registers := 1 + 4 Bit Registers := 2 + 3 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 8 Input 10 Bit Muxes := 1 + 3 Input 7 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1 + 8 Input 1 Bit Muxes := 5 +Module ila_v6_2_9_ila_core +Detailed RTL Component Info : ++---Registers : + 75 Bit Registers := 9 + 16 Bit Registers := 2 + 2 Bit Registers := 3 + 1 Bit Registers := 5 ++---Muxes : + 2 Input 75 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 1 +Module ila_v6_2_9_ila +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 6 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 1540 (col length:140) +BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1023] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1023] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[0]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[5]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[0] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[5].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[1]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[1] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[5].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[2]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[2] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[5].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[3]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[3] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[5].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[10] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff8_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[15] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1057 ; free virtual = 44367 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|inst | ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:50 ; elapsed = 00:01:01 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 942 ; free virtual = 44280 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:50 ; elapsed = 00:01:02 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 938 ; free virtual = 44276 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|inst | ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:51 ; elapsed = 00:01:03 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 968 ; free virtual = 44293 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-3295] tying undriven pin dummy_inferred:in0 to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:trig_in to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:trig_out_ack to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:52 ; elapsed = 00:01:03 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1875 ; free virtual = 45196 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:52 ; elapsed = 00:01:03 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1875 ; free virtual = 45196 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:52 ; elapsed = 00:01:03 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1871 ; free virtual = 45192 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:52 ; elapsed = 00:01:03 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1843 ; free virtual = 45192 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:52 ; elapsed = 00:01:03 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1870 ; free virtual = 45190 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:52 ; elapsed = 00:01:03 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1870 ; free virtual = 45190 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|ila_v6_2_9_generic_counter | counter_load_i_reg[16] | 16 | 4 | NO | NO | YES | 4 | 0 | +|ila_v6_2_9_ila | ila_core_inst/u_ila_regs/adv_rb_drdy4_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/shifted_data_in_reg[8][74] | 9 | 75 | NO | NO | YES | 75 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |CARRY4 | 160| +|2 |CFGLUT5 | 432| +|3 |LUT1 | 81| +|4 |LUT2 | 105| +|5 |LUT3 | 251| +|6 |LUT4 | 526| +|7 |LUT5 | 257| +|8 |LUT6 | 1376| +|9 |MUXF7 | 91| +|10 |MUXF8 | 2| +|11 |RAM64M | 32| +|12 |RAMB18E1 | 1| +|13 |RAMB36E1 | 2| +|14 |SRL16E | 83| +|15 |SRLC16E | 2| +|16 |SRLC32E | 17| +|17 |FDRE | 3849| +|18 |FDSE | 9| ++------+---------+------+ + +Report Instance Areas: ++------+------------------------------------------------------------------------+------------------------------------------------------------+------+ +| |Instance |Module |Cells | ++------+------------------------------------------------------------------------+------------------------------------------------------------+------+ +|1 |top | | 7276| +|2 | inst |ila_v6_2_9_ila | 7276| +|3 | ila_core_inst |ila_v6_2_9_ila_core | 7269| +|4 | \ADV_TRIG.u_adv_trig |ila_v6_2_9_ila_adv_trigger_sequencer | 185| +|5 | \ADV_TRIG_MEM_READ.u_fsm_memory_read_inst |ila_v6_2_9_ila_fsm_memory_read | 52| +|6 | \COUNTER.u_count |ila_v6_2_9_ila_counter | 232| +|7 | \G_COUNTER[0].U_COUNTER |ila_v6_2_9_generic_counter__1 | 58| +|8 | \G_COUNTER[1].U_COUNTER |ila_v6_2_9_generic_counter__2 | 58| +|9 | \G_COUNTER[2].U_COUNTER |ila_v6_2_9_generic_counter__3 | 58| +|10 | \G_COUNTER[3].U_COUNTER |ila_v6_2_9_generic_counter | 58| +|11 | ila_trace_memory_inst |ila_v6_2_9_ila_trace_memory | 3| +|12 | \SUBCORE_RAM_BLK_MEM_1.trace_block_memory |blk_mem_gen_v8_4_3 | 3| +|13 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 3| +|14 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_v8_4_3_blk_mem_gen_top | 3| +|15 | \valid.cstr |blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr | 3| +|16 | \ramloop[0].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width | 1| +|17 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper | 1| +|18 | \ramloop[1].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized0 | 1| +|19 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 | 1| +|20 | \ramloop[2].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized1 | 1| +|21 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 | 1| +|22 | u_ila_cap_ctrl |ila_v6_2_9_ila_cap_ctrl_legacy | 281| +|23 | U_CDONE |ltlib_v1_0_0_cfglut6__parameterized0 | 5| +|24 | U_NS0 |ltlib_v1_0_0_cfglut7 | 8| +|25 | U_NS1 |ltlib_v1_0_0_cfglut7_236 | 10| +|26 | u_cap_addrgen |ila_v6_2_9_ila_cap_addrgen | 253| +|27 | U_CMPRESET |ltlib_v1_0_0_cfglut6 | 3| +|28 | u_cap_sample_counter |ila_v6_2_9_ila_cap_sample_counter | 59| +|29 | U_SCE |ltlib_v1_0_0_cfglut4_243 | 1| +|30 | U_SCMPCE |ltlib_v1_0_0_cfglut5_244 | 1| +|31 | U_SCRST |ltlib_v1_0_0_cfglut6_245 | 3| +|32 | u_scnt_cmp |ltlib_v1_0_0_match_nodelay_246 | 22| +|33 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_247 | 22| +|34 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_248 | 12| +|35 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_249 | 5| +|36 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_250 | 5| +|37 | u_cap_window_counter |ila_v6_2_9_ila_cap_window_counter | 60| +|38 | U_WCE |ltlib_v1_0_0_cfglut4 | 1| +|39 | U_WHCMPCE |ltlib_v1_0_0_cfglut5 | 1| +|40 | U_WLCMPCE |ltlib_v1_0_0_cfglut5_237 | 1| +|41 | u_wcnt_hcmp |ltlib_v1_0_0_match_nodelay | 12| +|42 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_239 | 12| +|43 | DUT |ltlib_v1_0_0_all_typeA__parameterized2_240 | 12| +|44 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_241 | 5| +|45 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_242 | 5| +|46 | u_wcnt_lcmp |ltlib_v1_0_0_match_nodelay_238 | 22| +|47 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay | 22| +|48 | DUT |ltlib_v1_0_0_all_typeA__parameterized2 | 12| +|49 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1 | 5| +|50 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2 | 5| +|51 | u_ila_regs |ila_v6_2_9_ila_register | 5223| +|52 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 302| +|53 | reg_890 |xsdbs_v1_0_2_reg__parameterized60 | 16| +|54 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_235 | 16| +|55 | \ADV_TRIG_STREAM.reg_stream_ffc |xsdbs_v1_0_2_reg_stream__parameterized0 | 24| +|56 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_234 | 20| +|57 | \ADV_TRIG_STREAM_READBACK.reg_stream_ffb |xsdbs_v1_0_2_reg_stream | 29| +|58 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_233 | 29| +|59 | \CNT.CNT_SRL[0].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized43 | 74| +|60 | \CNT.CNT_SRL[1].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized44 | 74| +|61 | \CNT.CNT_SRL[2].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized45 | 106| +|62 | \CNT.CNT_SRL[3].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized46 | 75| +|63 | \MU_SRL[0].mu_srl_reg |xsdbs_v1_0_2_reg_p2s | 74| +|64 | \MU_SRL[10].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized9 | 74| +|65 | \MU_SRL[11].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized10 | 106| +|66 | \MU_SRL[1].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized0 | 74| +|67 | \MU_SRL[2].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized1 | 74| +|68 | \MU_SRL[3].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized2 | 90| +|69 | \MU_SRL[4].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized3 | 74| +|70 | \MU_SRL[5].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized4 | 74| +|71 | \MU_SRL[6].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized5 | 74| +|72 | \MU_SRL[7].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized6 | 90| +|73 | \MU_SRL[8].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized7 | 74| +|74 | \MU_SRL[9].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized8 | 74| +|75 | \STRG_QUAL.qual_strg_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized47 | 74| +|76 | \TC_SRL[0].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized11 | 74| +|77 | \TC_SRL[10].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized21 | 74| +|78 | \TC_SRL[11].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized22 | 106| +|79 | \TC_SRL[12].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized23 | 74| +|80 | \TC_SRL[13].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized24 | 74| +|81 | \TC_SRL[14].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized25 | 74| +|82 | \TC_SRL[15].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized26 | 90| +|83 | \TC_SRL[16].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized27 | 74| +|84 | \TC_SRL[17].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized28 | 74| +|85 | \TC_SRL[18].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized29 | 74| +|86 | \TC_SRL[19].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized30 | 106| +|87 | \TC_SRL[1].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized12 | 74| +|88 | \TC_SRL[20].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized31 | 74| +|89 | \TC_SRL[21].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized32 | 74| +|90 | \TC_SRL[22].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized33 | 74| +|91 | \TC_SRL[23].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized34 | 90| +|92 | \TC_SRL[24].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized35 | 74| +|93 | \TC_SRL[25].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized36 | 74| +|94 | \TC_SRL[26].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized37 | 74| +|95 | \TC_SRL[27].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized38 | 122| +|96 | \TC_SRL[28].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized39 | 74| +|97 | \TC_SRL[29].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized40 | 74| +|98 | \TC_SRL[2].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized13 | 74| +|99 | \TC_SRL[30].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized41 | 74| +|100 | \TC_SRL[31].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized42 | 90| +|101 | \TC_SRL[3].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized14 | 106| +|102 | \TC_SRL[4].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized15 | 74| +|103 | \TC_SRL[5].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized16 | 74| +|104 | \TC_SRL[6].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized17 | 74| +|105 | \TC_SRL[7].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized18 | 90| +|106 | \TC_SRL[8].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized19 | 74| +|107 | \TC_SRL[9].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized20 | 74| +|108 | reg_15 |xsdbs_v1_0_2_reg__parameterized42 | 23| +|109 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_232 | 23| +|110 | reg_16 |xsdbs_v1_0_2_reg__parameterized43 | 18| +|111 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_231 | 18| +|112 | reg_17 |xsdbs_v1_0_2_reg__parameterized44 | 45| +|113 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_230 | 45| +|114 | reg_18 |xsdbs_v1_0_2_reg__parameterized45 | 25| +|115 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_229 | 25| +|116 | reg_19 |xsdbs_v1_0_2_reg__parameterized46 | 17| +|117 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_228 | 17| +|118 | reg_1a |xsdbs_v1_0_2_reg__parameterized47 | 33| +|119 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1 | 33| +|120 | reg_6 |xsdbs_v1_0_2_reg__parameterized27 | 34| +|121 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_227 | 34| +|122 | reg_7 |xsdbs_v1_0_2_reg__parameterized28 | 31| +|123 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized0 | 31| +|124 | reg_8 |xsdbs_v1_0_2_reg__parameterized29 | 5| +|125 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_226 | 5| +|126 | reg_80 |xsdbs_v1_0_2_reg__parameterized48 | 17| +|127 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2_225 | 17| +|128 | reg_81 |xsdbs_v1_0_2_reg__parameterized49 | 17| +|129 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_224 | 17| +|130 | reg_82 |xsdbs_v1_0_2_reg__parameterized50 | 17| +|131 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2 | 17| +|132 | reg_83 |xsdbs_v1_0_2_reg__parameterized51 | 60| +|133 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_223 | 60| +|134 | reg_84 |xsdbs_v1_0_2_reg__parameterized52 | 22| +|135 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_222 | 22| +|136 | reg_85 |xsdbs_v1_0_2_reg__parameterized53 | 18| +|137 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_221 | 18| +|138 | reg_887 |xsdbs_v1_0_2_reg__parameterized55 | 4| +|139 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_220 | 4| +|140 | reg_88d |xsdbs_v1_0_2_reg__parameterized57 | 4| +|141 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_219 | 4| +|142 | reg_88f |xsdbs_v1_0_2_reg__parameterized59 | 34| +|143 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_218 | 34| +|144 | reg_892 |xsdbs_v1_0_2_reg__parameterized58 | 4| +|145 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_217 | 4| +|146 | reg_9 |xsdbs_v1_0_2_reg__parameterized30 | 15| +|147 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_216 | 15| +|148 | reg_srl_fff |xsdbs_v1_0_2_reg_p2s__parameterized48 | 95| +|149 | reg_stream_ffd |xsdbs_v1_0_2_reg_stream__parameterized1 | 17| +|150 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl | 17| +|151 | reg_stream_ffe |xsdbs_v1_0_2_reg_stream__parameterized2 | 16| +|152 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat | 16| +|153 | u_ila_reset_ctrl |ila_v6_2_9_ila_reset_ctrl | 47| +|154 | arm_detection_inst |ltlib_v1_0_0_rising_edge_detection | 5| +|155 | \asyncrounous_transfer.arm_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer | 7| +|156 | \asyncrounous_transfer.arm_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_212 | 7| +|157 | \asyncrounous_transfer.halt_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer_213 | 7| +|158 | \asyncrounous_transfer.halt_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_214 | 6| +|159 | halt_detection_inst |ltlib_v1_0_0_rising_edge_detection_215 | 6| +|160 | u_trig |ila_v6_2_9_ila_trigger | 840| +|161 | \N_DDR_TC.N_DDR_TC_INST[0].U_TC |ltlib_v1_0_0_match | 14| +|162 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_208 | 13| +|163 | DUT |ltlib_v1_0_0_all_typeA_209 | 13| +|164 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_210 | 5| +|165 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_211 | 6| +|166 | \N_DDR_TC.N_DDR_TC_INST[10].U_TC |ltlib_v1_0_0_match_0 | 14| +|167 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_204 | 13| +|168 | DUT |ltlib_v1_0_0_all_typeA_205 | 13| +|169 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_206 | 5| +|170 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_207 | 6| +|171 | \N_DDR_TC.N_DDR_TC_INST[11].U_TC |ltlib_v1_0_0_match_1 | 14| +|172 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_200 | 13| +|173 | DUT |ltlib_v1_0_0_all_typeA_201 | 13| +|174 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_202 | 5| +|175 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_203 | 6| +|176 | \N_DDR_TC.N_DDR_TC_INST[12].U_TC |ltlib_v1_0_0_match_2 | 14| +|177 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_196 | 13| +|178 | DUT |ltlib_v1_0_0_all_typeA_197 | 13| +|179 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_198 | 5| +|180 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_199 | 6| +|181 | \N_DDR_TC.N_DDR_TC_INST[13].U_TC |ltlib_v1_0_0_match_3 | 14| +|182 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_192 | 13| +|183 | DUT |ltlib_v1_0_0_all_typeA_193 | 13| +|184 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_194 | 5| +|185 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_195 | 6| +|186 | \N_DDR_TC.N_DDR_TC_INST[14].U_TC |ltlib_v1_0_0_match_4 | 14| +|187 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_188 | 13| +|188 | DUT |ltlib_v1_0_0_all_typeA_189 | 13| +|189 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_190 | 5| +|190 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_191 | 6| +|191 | \N_DDR_TC.N_DDR_TC_INST[15].U_TC |ltlib_v1_0_0_match_5 | 14| +|192 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_184 | 13| +|193 | DUT |ltlib_v1_0_0_all_typeA_185 | 13| +|194 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_186 | 5| +|195 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_187 | 6| +|196 | \N_DDR_TC.N_DDR_TC_INST[16].U_TC |ltlib_v1_0_0_match_6 | 14| +|197 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_180 | 13| +|198 | DUT |ltlib_v1_0_0_all_typeA_181 | 13| +|199 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_182 | 5| +|200 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_183 | 6| +|201 | \N_DDR_TC.N_DDR_TC_INST[17].U_TC |ltlib_v1_0_0_match_7 | 14| +|202 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_176 | 13| +|203 | DUT |ltlib_v1_0_0_all_typeA_177 | 13| +|204 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_178 | 5| +|205 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_179 | 6| +|206 | \N_DDR_TC.N_DDR_TC_INST[18].U_TC |ltlib_v1_0_0_match_8 | 14| +|207 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_172 | 13| +|208 | DUT |ltlib_v1_0_0_all_typeA_173 | 13| +|209 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_174 | 5| +|210 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_175 | 6| +|211 | \N_DDR_TC.N_DDR_TC_INST[19].U_TC |ltlib_v1_0_0_match_9 | 14| +|212 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_168 | 13| +|213 | DUT |ltlib_v1_0_0_all_typeA_169 | 13| +|214 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_170 | 5| +|215 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_171 | 6| +|216 | \N_DDR_TC.N_DDR_TC_INST[1].U_TC |ltlib_v1_0_0_match_10 | 14| +|217 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_164 | 13| +|218 | DUT |ltlib_v1_0_0_all_typeA_165 | 13| +|219 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_166 | 5| +|220 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_167 | 6| +|221 | \N_DDR_TC.N_DDR_TC_INST[20].U_TC |ltlib_v1_0_0_match_11 | 14| +|222 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_160 | 13| +|223 | DUT |ltlib_v1_0_0_all_typeA_161 | 13| +|224 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_162 | 5| +|225 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_163 | 6| +|226 | \N_DDR_TC.N_DDR_TC_INST[21].U_TC |ltlib_v1_0_0_match_12 | 14| +|227 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_156 | 13| +|228 | DUT |ltlib_v1_0_0_all_typeA_157 | 13| +|229 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_158 | 5| +|230 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_159 | 6| +|231 | \N_DDR_TC.N_DDR_TC_INST[22].U_TC |ltlib_v1_0_0_match_13 | 14| +|232 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_152 | 13| +|233 | DUT |ltlib_v1_0_0_all_typeA_153 | 13| +|234 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_154 | 5| +|235 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_155 | 6| +|236 | \N_DDR_TC.N_DDR_TC_INST[23].U_TC |ltlib_v1_0_0_match_14 | 14| +|237 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_148 | 13| +|238 | DUT |ltlib_v1_0_0_all_typeA_149 | 13| +|239 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_150 | 5| +|240 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_151 | 6| +|241 | \N_DDR_TC.N_DDR_TC_INST[24].U_TC |ltlib_v1_0_0_match_15 | 14| +|242 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_144 | 13| +|243 | DUT |ltlib_v1_0_0_all_typeA_145 | 13| +|244 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_146 | 5| +|245 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_147 | 6| +|246 | \N_DDR_TC.N_DDR_TC_INST[25].U_TC |ltlib_v1_0_0_match_16 | 14| +|247 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_140 | 13| +|248 | DUT |ltlib_v1_0_0_all_typeA_141 | 13| +|249 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_142 | 5| +|250 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_143 | 6| +|251 | \N_DDR_TC.N_DDR_TC_INST[26].U_TC |ltlib_v1_0_0_match_17 | 14| +|252 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_136 | 13| +|253 | DUT |ltlib_v1_0_0_all_typeA_137 | 13| +|254 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_138 | 5| +|255 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_139 | 6| +|256 | \N_DDR_TC.N_DDR_TC_INST[27].U_TC |ltlib_v1_0_0_match_18 | 14| +|257 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_132 | 13| +|258 | DUT |ltlib_v1_0_0_all_typeA_133 | 13| +|259 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_134 | 5| +|260 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_135 | 6| +|261 | \N_DDR_TC.N_DDR_TC_INST[28].U_TC |ltlib_v1_0_0_match_19 | 14| +|262 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_128 | 13| +|263 | DUT |ltlib_v1_0_0_all_typeA_129 | 13| +|264 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_130 | 5| +|265 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_131 | 6| +|266 | \N_DDR_TC.N_DDR_TC_INST[29].U_TC |ltlib_v1_0_0_match_20 | 14| +|267 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_124 | 13| +|268 | DUT |ltlib_v1_0_0_all_typeA_125 | 13| +|269 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_126 | 5| +|270 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_127 | 6| +|271 | \N_DDR_TC.N_DDR_TC_INST[2].U_TC |ltlib_v1_0_0_match_21 | 14| +|272 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_120 | 13| +|273 | DUT |ltlib_v1_0_0_all_typeA_121 | 13| +|274 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_122 | 5| +|275 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_123 | 6| +|276 | \N_DDR_TC.N_DDR_TC_INST[30].U_TC |ltlib_v1_0_0_match_22 | 14| +|277 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_116 | 13| +|278 | DUT |ltlib_v1_0_0_all_typeA_117 | 13| +|279 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_118 | 5| +|280 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_119 | 6| +|281 | \N_DDR_TC.N_DDR_TC_INST[31].U_TC |ltlib_v1_0_0_match_23 | 14| +|282 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_112 | 13| +|283 | DUT |ltlib_v1_0_0_all_typeA_113 | 13| +|284 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_114 | 5| +|285 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_115 | 6| +|286 | \N_DDR_TC.N_DDR_TC_INST[3].U_TC |ltlib_v1_0_0_match_24 | 14| +|287 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_108 | 13| +|288 | DUT |ltlib_v1_0_0_all_typeA_109 | 13| +|289 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_110 | 5| +|290 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_111 | 6| +|291 | \N_DDR_TC.N_DDR_TC_INST[4].U_TC |ltlib_v1_0_0_match_25 | 14| +|292 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_104 | 13| +|293 | DUT |ltlib_v1_0_0_all_typeA_105 | 13| +|294 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_106 | 5| +|295 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_107 | 6| +|296 | \N_DDR_TC.N_DDR_TC_INST[5].U_TC |ltlib_v1_0_0_match_26 | 14| +|297 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_100 | 13| +|298 | DUT |ltlib_v1_0_0_all_typeA_101 | 13| +|299 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_102 | 5| +|300 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_103 | 6| +|301 | \N_DDR_TC.N_DDR_TC_INST[6].U_TC |ltlib_v1_0_0_match_27 | 14| +|302 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_96 | 13| +|303 | DUT |ltlib_v1_0_0_all_typeA_97 | 13| +|304 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_98 | 5| +|305 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_99 | 6| +|306 | \N_DDR_TC.N_DDR_TC_INST[7].U_TC |ltlib_v1_0_0_match_28 | 14| +|307 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_92 | 13| +|308 | DUT |ltlib_v1_0_0_all_typeA_93 | 13| +|309 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_94 | 5| +|310 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_95 | 6| +|311 | \N_DDR_TC.N_DDR_TC_INST[8].U_TC |ltlib_v1_0_0_match_29 | 14| +|312 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_88 | 13| +|313 | DUT |ltlib_v1_0_0_all_typeA_89 | 13| +|314 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_90 | 5| +|315 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_91 | 6| +|316 | \N_DDR_TC.N_DDR_TC_INST[9].U_TC |ltlib_v1_0_0_match_30 | 14| +|317 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_84 | 13| +|318 | DUT |ltlib_v1_0_0_all_typeA_85 | 13| +|319 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_86 | 5| +|320 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_87 | 6| +|321 | \STRG_QUAL.U_STRG_QUAL |ltlib_v1_0_0_match_31 | 26| +|322 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA | 25| +|323 | DUT |ltlib_v1_0_0_all_typeA | 13| +|324 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_82 | 5| +|325 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_83 | 6| +|326 | U_TM |ila_v6_2_9_ila_trig_match | 318| +|327 | \N_DDR_MODE.G_NMU[0].U_M |ltlib_v1_0_0_match__parameterized0 | 11| +|328 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_79 | 10| +|329 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_80 | 8| +|330 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_81 | 6| +|331 | \N_DDR_MODE.G_NMU[10].U_M |ltlib_v1_0_0_match__parameterized2 | 25| +|332 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2_76 | 24| +|333 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_77 | 8| +|334 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_78 | 6| +|335 | \N_DDR_MODE.G_NMU[11].U_M |ltlib_v1_0_0_match__parameterized2_32 | 9| +|336 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized2 | 8| +|337 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_74 | 8| +|338 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_75 | 6| +|339 | \N_DDR_MODE.G_NMU[1].U_M |ltlib_v1_0_0_match__parameterized0_33 | 9| +|340 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_71 | 8| +|341 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_72 | 8| +|342 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_73 | 6| +|343 | \N_DDR_MODE.G_NMU[2].U_M |ltlib_v1_0_0_match__parameterized1 | 88| +|344 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_65 | 87| +|345 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_66 | 23| +|346 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_67 | 5| +|347 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_68 | 5| +|348 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_69 | 5| +|349 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_70 | 6| +|350 | \N_DDR_MODE.G_NMU[3].U_M |ltlib_v1_0_0_match__parameterized1_34 | 24| +|351 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_59 | 23| +|352 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_60 | 23| +|353 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_61 | 5| +|354 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_62 | 5| +|355 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_63 | 5| +|356 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_64 | 6| +|357 | \N_DDR_MODE.G_NMU[4].U_M |ltlib_v1_0_0_match__parameterized1_35 | 88| +|358 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_53 | 87| +|359 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_54 | 23| +|360 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_55 | 5| +|361 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_56 | 5| +|362 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_57 | 5| +|363 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_58 | 6| +|364 | \N_DDR_MODE.G_NMU[5].U_M |ltlib_v1_0_0_match__parameterized1_36 | 24| +|365 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1 | 23| +|366 | DUT |ltlib_v1_0_0_all_typeA__parameterized1 | 23| +|367 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice | 5| +|368 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_50 | 5| +|369 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_51 | 5| +|370 | \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_52 | 6| +|371 | \N_DDR_MODE.G_NMU[6].U_M |ltlib_v1_0_0_match__parameterized0_37 | 11| +|372 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_47 | 10| +|373 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_48 | 8| +|374 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_49 | 6| +|375 | \N_DDR_MODE.G_NMU[7].U_M |ltlib_v1_0_0_match__parameterized0_38 | 9| +|376 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_44 | 8| +|377 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_45 | 8| +|378 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_46 | 6| +|379 | \N_DDR_MODE.G_NMU[8].U_M |ltlib_v1_0_0_match__parameterized0_39 | 11| +|380 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_41 | 10| +|381 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_42 | 8| +|382 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_43 | 6| +|383 | \N_DDR_MODE.G_NMU[9].U_M |ltlib_v1_0_0_match__parameterized0_40 | 9| +|384 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0 | 8| +|385 | DUT |ltlib_v1_0_0_all_typeA__parameterized0 | 8| +|386 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0 | 6| +|387 | xsdb_memory_read_inst |ltlib_v1_0_0_generic_memrd | 163| ++------+------------------------------------------------------------------------+------------------------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:52 ; elapsed = 00:01:03 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1870 ; free virtual = 45190 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1146 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2308.848 ; gain = 532.750 ; free physical = 1918 ; free virtual = 45239 +Synthesis Optimization Complete : Time (s): cpu = 00:00:52 ; elapsed = 00:01:03 . Memory (MB): peak = 2308.848 ; gain = 618.594 ; free physical = 1932 ; free virtual = 45252 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 720 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2324.855 ; gain = 0.000 ; free physical = 1857 ; free virtual = 45178 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 464 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 384 instances + CFGLUT5 => SRLC32E: 48 instances + RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 32 instances + +INFO: [Common 17-83] Releasing license: Synthesis +331 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:01:07 . Memory (MB): peak = 2324.855 ; gain = 913.402 ; free physical = 1956 ; free virtual = 45277 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2324.855 ; gain = 0.000 ; free physical = 1956 ; free virtual = 45277 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ila_rf_auto_control, cache-ID = d259ec5277241eb0 +INFO: [Coretcl 2-1174] Renamed 386 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2348.867 ; gain = 0.000 ; free physical = 1948 ; free virtual = 45281 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file ila_rf_auto_control_utilization_synth.rpt -pb ila_rf_auto_control_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri May 12 16:03:15 2023... diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.v new file mode 100644 index 00000000..6f425552 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fd00fae9279829fda4b4e1885ebe5256e00b408d06eb2cd8357fbb8c7b2e3412 +size 3340781 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.vhdl new file mode 100644 index 00000000..83d015ce --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2773b07ea9fba2823d7714c5628c03c1b356e5468d20ea057d97aa443968d0e0 +size 5402482 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.v new file mode 100644 index 00000000..2e98375f --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:03:15 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.v +// Design : ila_rf_auto_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_rf_auto_control(clk, probe0, probe1, probe2, probe3, probe4, probe5) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]" */; + input clk; + input [0:0]probe0; + input [31:0]probe1; + input [31:0]probe2; + input [0:0]probe3; + input [0:0]probe4; + input [7:0]probe5; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.vhdl new file mode 100644 index 00000000..9748e094 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:03:15 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.vhdl +-- Design : ila_rf_auto_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_rf_auto_control is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe4 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + +end ila_rf_auto_control; + +architecture stub of ila_rf_auto_control is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_utilization_synth.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_utilization_synth.pb new file mode 100644 index 00000000..44ee3f65 Binary files /dev/null and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_utilization_synth.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_utilization_synth.rpt new file mode 100644 index 00000000..ab740dd3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_utilization_synth.rpt @@ -0,0 +1,193 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Fri May 12 16:03:15 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file ila_rf_auto_control_utilization_synth.rpt -pb ila_rf_auto_control_utilization_synth.pb +| Design : ila_rf_auto_control +| Device : 7k410tffg900-2 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 2996 | 0 | 254200 | 1.18 | +| LUT as Logic | 2334 | 0 | 254200 | 0.92 | +| LUT as Memory | 662 | 0 | 90600 | 0.73 | +| LUT as Distributed RAM | 128 | 0 | | | +| LUT as Shift Register | 534 | 0 | | | +| Slice Registers | 3858 | 0 | 508400 | 0.76 | +| Register as Flip Flop | 3858 | 0 | 508400 | 0.76 | +| Register as Latch | 0 | 0 | 508400 | 0.00 | +| F7 Muxes | 91 | 0 | 127100 | 0.07 | +| F8 Muxes | 2 | 0 | 63550 | <0.01 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 9 | Yes | Set | - | +| 3849 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------+------+-------+-----------+-------+ +| Block RAM Tile | 2.5 | 0 | 795 | 0.31 | +| RAMB36/FIFO* | 2 | 0 | 795 | 0.25 | +| RAMB36E1 only | 2 | | | | +| RAMB18 | 1 | 0 | 1590 | 0.06 | +| RAMB18E1 only | 1 | | | | ++-------------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 1540 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 500 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| PHY_CONTROL | 0 | 0 | 10 | 0.00 | +| PHASER_REF | 0 | 0 | 10 | 0.00 | +| OUT_FIFO | 0 | 0 | 40 | 0.00 | +| IN_FIFO | 0 | 0 | 40 | 0.00 | +| IDELAYCTRL | 0 | 0 | 10 | 0.00 | +| IBUFDS | 0 | 0 | 480 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 500 | 0.00 | +| OLOGIC | 0 | 0 | 500 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 40 | 0.00 | +| MMCME2_ADV | 0 | 0 | 10 | 0.00 | +| PLLE2_ADV | 0 | 0 | 10 | 0.00 | +| BUFMRCE | 0 | 0 | 20 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 40 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 3849 | Flop & Latch | +| LUT6 | 1376 | LUT | +| LUT4 | 526 | LUT | +| SRL16E | 467 | Distributed Memory | +| SRLC32E | 449 | Distributed Memory | +| LUT5 | 257 | LUT | +| LUT3 | 251 | LUT | +| CARRY4 | 160 | CarryLogic | +| RAMD64E | 128 | Distributed Memory | +| LUT2 | 105 | LUT | +| MUXF7 | 91 | MuxFx | +| LUT1 | 81 | LUT | +| FDSE | 9 | Flop & Latch | +| SRLC16E | 2 | Distributed Memory | +| RAMB36E1 | 2 | Block Memory | +| MUXF8 | 2 | MuxFx | +| RAMB18E1 | 1 | Block Memory | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/project.wdf new file mode 100644 index 00000000..8833b826 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/project.wdf @@ -0,0 +1,43 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3538:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3538:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00 +eof:2867283627 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/rundef.js b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/rundef.js new file mode 100644 index 00000000..d5022d3e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log ila_rf_auto_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_auto_control.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/runme.bat b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/runme.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/runme.sh new file mode 100755 index 00000000..c1343661 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log ila_rf_auto_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_auto_control.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/vivado.pb new file mode 100644 index 00000000..dac97c50 Binary files /dev/null and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..800dae40 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.end.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.js b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/__synthesis_is_complete__ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc new file mode 100644 index 00000000..d0b10d65 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci +# IP: The module: 'ila_rx_data_cnt' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila_impl.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci +# IP: The module: 'ila_rx_data_cnt' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila_impl.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/gen_run.xml similarity index 53% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/gen_run.xml rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/gen_run.xml index 69447ed1..0dee6dd6 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/gen_run.xml +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/gen_run.xml @@ -1,23 +1,20 @@ - - - - - - - - - - - - + + + + + + + + + - + @@ -25,19 +22,19 @@ - - - + + - + @@ -45,7 +42,7 @@ - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/htr.txt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/htr.txt new file mode 100644 index 00000000..fe0a3fdd --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log ila_rx_data_cnt.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rx_data_cnt.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp new file mode 100644 index 00000000..6a059b17 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4a972d979e8301f9523193101c41e2f92624fc1a930931a09b9a84219688f562 +size 3456254 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.tcl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.tcl similarity index 67% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.tcl rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.tcl index 95f6f37b..3875b9ac 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.tcl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.tcl @@ -34,8 +34,11 @@ set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp.xci -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp_ooc.xdc] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci +set_property used_in_synthesis false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila_impl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila_impl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt_ooc.xdc] # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -49,12 +52,12 @@ read_xdc dont_touch.xdc set_property used_in_implementation false [get_files dont_touch.xdc] set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1 -new_name dds_32b_8b_comp -ip [get_ips dds_32b_8b_comp]] +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1 -new_name ila_rx_data_cnt -ip [get_ips ila_rx_data_cnt]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] -synth_design -top dds_32b_8b_comp -part xc7k410tffg900-2 -mode out_of_context +synth_design -top ila_rx_data_cnt -part xc7k410tffg900-2 -mode out_of_context #--------------------------------------------------------- # Generate Checkpoint/Stub/Simulation Files For IP Cache @@ -63,52 +66,52 @@ synth_design -top dds_32b_8b_comp -part xc7k410tffg900-2 -mode out_of_context set_param constraints.enableBinaryConstraints false catch { - write_checkpoint -force -noxdef -rename_prefix dds_32b_8b_comp_ dds_32b_8b_comp.dcp + write_checkpoint -force -noxdef -rename_prefix ila_rx_data_cnt_ ila_rx_data_cnt.dcp set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_comp_stub.v - lappend ipCachedFiles dds_32b_8b_comp_stub.v + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_stub.v + lappend ipCachedFiles ila_rx_data_cnt_stub.v - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_comp_stub.vhdl - lappend ipCachedFiles dds_32b_8b_comp_stub.vhdl + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_stub.vhdl + lappend ipCachedFiles ila_rx_data_cnt_stub.vhdl - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_comp_sim_netlist.v - lappend ipCachedFiles dds_32b_8b_comp_sim_netlist.v + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_sim_netlist.v + lappend ipCachedFiles ila_rx_data_cnt_sim_netlist.v - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_comp_sim_netlist.vhdl - lappend ipCachedFiles dds_32b_8b_comp_sim_netlist.vhdl + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_sim_netlist.vhdl + lappend ipCachedFiles ila_rx_data_cnt_sim_netlist.vhdl set TIME_taken [expr [clock seconds] - $TIME_start] - config_ip_cache -add -dcp dds_32b_8b_comp.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips dds_32b_8b_comp] + config_ip_cache -add -dcp ila_rx_data_cnt.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips ila_rx_data_cnt] } -rename_ref -prefix_all dds_32b_8b_comp_ +rename_ref -prefix_all ila_rx_data_cnt_ # disable binary constraint mode for synth run checkpoints set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef dds_32b_8b_comp.dcp -create_report "dds_32b_8b_comp_synth_1_synth_report_utilization_0" "report_utilization -file dds_32b_8b_comp_utilization_synth.rpt -pb dds_32b_8b_comp_utilization_synth.pb" +write_checkpoint -force -noxdef ila_rx_data_cnt.dcp +create_report "ila_rx_data_cnt_synth_1_synth_report_utilization_0" "report_utilization -file ila_rx_data_cnt_utilization_synth.rpt -pb ila_rx_data_cnt_utilization_synth.pb" if { [catch { - write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.v + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.vhdl + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.v + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.vhdl + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -119,37 +122,37 @@ if { [catch { }; # end if cached_ip -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp.xci] +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci] -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp.xci] +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci] -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp.xci] +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci] -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp.xci] +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci] -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/dds_32b_8b_comp/dds_32b_8b_comp.xci] +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci] -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/dds_32b_8b_comp + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/ila_rx_data_cnt } } file delete __synthesis_is_running__ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds new file mode 100644 index 00000000..e578cbda --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds @@ -0,0 +1,3575 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Fri May 12 16:01:02 2023 +# Process ID: 1471670 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1 +# Command line: vivado -log ila_rx_data_cnt.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rx_data_cnt.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.jou +#----------------------------------------------------------- +source ila_rx_data_cnt.tcl -notrace +Command: synth_design -top ila_rx_data_cnt -part xc7k410tffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Device 21-403] Loading part xc7k410tffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 1471837 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1852.941 ; gain = 162.719 ; free physical = 1008 ; free virtual = 45079 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'ila_rx_data_cnt' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:84] +INFO: [Synth 8-6157] synthesizing module 'CFGLUT5' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] +INFO: [Synth 8-6155] done synthesizing module 'CFGLUT5' (12#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] +INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] +INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (13#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (23#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] +INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] +INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (25#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] +INFO: [Synth 8-6157] synthesizing module 'SRLC16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] +INFO: [Synth 8-6155] done synthesizing module 'SRLC16E' (27#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] +INFO: [Synth 8-6157] synthesizing module 'FDRE' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +INFO: [Synth 8-6155] done synthesizing module 'FDRE' (32#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +WARNING: [Synth 8-7023] instance 'inst' of module 'ila_v6_2_9_ila' has 1033 connections declared, but only 1027 given [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:3227] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity ila_rx_data_cnt does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:116] +INFO: [Synth 8-6155] done synthesizing module 'ila_rx_data_cnt' (52#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:84] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MUX_RST[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MEM_LAT_RST +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MUX_REGCE[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port WE +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[15] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[14] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[13] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[12] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[11] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[10] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[9] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[8] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[7] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[6] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[5] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[4] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1951] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1950] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1949] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1948] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1947] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1946] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1945] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1944] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1943] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1942] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1941] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1940] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1939] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1938] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1937] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1936] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1935] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1934] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1933] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1932] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1931] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1930] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1929] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1928] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1927] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1926] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1925] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1924] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1923] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1922] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1921] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1920] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1919] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1918] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1917] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1916] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1915] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1914] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1913] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1912] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1911] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1910] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1909] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1908] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1907] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1906] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1905] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1904] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1903] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1902] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1901] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1900] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1899] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1898] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1897] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1896] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1895] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1894] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1893] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1892] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1891] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1890] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1889] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1888] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1887] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1886] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1885] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1884] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1883] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1882] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1881] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1880] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1879] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1878] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1877] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1876] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1875] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1874] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1873] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1872] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:01:19 ; elapsed = 00:01:29 . Memory (MB): peak = 2317.113 ; gain = 626.891 ; free physical = 845 ; free virtual = 44201 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:20 ; elapsed = 00:01:30 . Memory (MB): peak = 2317.113 ; gain = 626.891 ; free physical = 869 ; free virtual = 44225 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:20 ; elapsed = 00:01:30 . Memory (MB): peak = 2317.113 ; gain = 626.891 ; free physical = 869 ; free virtual = 44225 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 1055 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila.xdc] for cell 'inst' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila.xdc] for cell 'inst' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2410.957 ; gain = 0.000 ; free physical = 723 ; free virtual = 44058 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 636 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 580 instances + CFGLUT5 => SRLC32E: 56 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2410.957 ; gain = 0.000 ; free physical = 721 ; free virtual = 44056 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:01:25 ; elapsed = 00:01:36 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 898 ; free virtual = 44212 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k410tffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:01:25 ; elapsed = 00:01:36 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 898 ; free virtual = 44212 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:25 ; elapsed = 00:01:36 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 897 ; free virtual = 44211 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized55' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized56' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized11' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized12' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized13' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized14' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized15' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized16' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized17' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized18' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized19' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized20' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized21' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized22' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized23' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized24' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized25' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized26' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized27' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized28' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized29' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized30' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized31' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized32' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized33' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized34' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized35' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized36' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized37' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized38' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized39' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized40' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized41' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized42' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized43' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized44' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized45' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized46' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized47' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized48' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized49' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized50' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized51' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized52' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized53' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized54' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized55' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized56' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized11' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized12' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized13' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized14' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized15' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized16' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized17' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized18' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized19' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized20' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized21' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized22' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized23' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized24' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized25' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized26' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized27' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized28' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized29' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized30' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized31' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized32' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized33' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized34' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized35' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized36' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized37' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized38' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized39' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized40' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized41' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized42' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized43' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized44' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized45' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized46' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized47' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized48' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized49' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized50' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized51' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized52' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized53' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized54' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:28 ; elapsed = 00:01:39 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 919 ; free virtual = 44216 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 4 + 2 Input 16 Bit Adders := 1 + 2 Input 9 Bit Adders := 1 + 2 Input 7 Bit Adders := 4 + 2 Input 6 Bit Adders := 1 + 2 Input 4 Bit Adders := 58 + 2 Input 3 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 72 + 2 Input 1 Bit XORs := 4 ++---Registers : + 1024 Bit Registers := 2 + 128 Bit Registers := 2 + 121 Bit Registers := 9 + 33 Bit Registers := 2 + 32 Bit Registers := 9 + 24 Bit Registers := 1 + 20 Bit Registers := 33 + 17 Bit Registers := 2 + 16 Bit Registers := 225 + 13 Bit Registers := 4 + 12 Bit Registers := 36 + 9 Bit Registers := 1 + 8 Bit Registers := 1 + 7 Bit Registers := 5 + 6 Bit Registers := 2 + 4 Bit Registers := 65 + 3 Bit Registers := 1 + 2 Bit Registers := 6 + 1 Bit Registers := 377 ++---Muxes : + 2 Input 121 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 12 + 2 Input 16 Bit Muxes := 72 + 4 Input 16 Bit Muxes := 2 + 3 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 58 + 3 Input 15 Bit Muxes := 1 + 3 Input 7 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 4 + 2 Input 5 Bit Muxes := 2 + 2 Input 4 Bit Muxes := 176 + 5 Input 4 Bit Muxes := 58 + 2 Input 3 Bit Muxes := 58 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 6 + 2 Input 1 Bit Muxes := 380 + 4 Input 1 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 58 + 9 Input 1 Bit Muxes := 1 + 8 Input 1 Bit Muxes := 5 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module ila_v6_2_9_generic_counter +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 2 +Module ila_v6_2_9_ila_adv_trigger_sequencer +Detailed RTL Component Info : ++---Adders : + 2 Input 7 Bit Adders := 2 ++---Registers : + 24 Bit Registers := 1 + 16 Bit Registers := 1 + 7 Bit Registers := 2 + 4 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 10 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 9 + 4 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_fsm_memory_read +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 8 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized55 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_stat +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_ctl +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stream__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 17 Bit Registers := 1 + 16 Bit Registers := 4 + 1 Bit Registers := 4 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg__parameterized39 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized40 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized54 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized55 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized56 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized57 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized58 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized59 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized60 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized61 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized62 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized63 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized64 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized65 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized56 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_stream__parameterized1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_p2s +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized0 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized1 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized2 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized3 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized4 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized5 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized6 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized7 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized8 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized9 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized10 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized11 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized12 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized13 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized14 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized15 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized16 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized17 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized18 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized19 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized20 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized21 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized22 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized23 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized24 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized25 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized26 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized27 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized28 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized29 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized30 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized31 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized32 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized33 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized34 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized35 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized36 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized37 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized38 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized39 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized40 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized41 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized42 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized43 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized44 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized45 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized46 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized47 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized48 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized49 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized50 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized51 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized52 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized53 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized54 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_register +Detailed RTL Component Info : ++---Adders : + 2 Input 9 Bit Adders := 1 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 ++---Registers : + 1024 Bit Registers := 2 + 17 Bit Registers := 1 + 16 Bit Registers := 12 + 9 Bit Registers := 1 + 7 Bit Registers := 2 + 6 Bit Registers := 1 + 1 Bit Registers := 31 ++---Muxes : + 2 Input 16 Bit Muxes := 10 + 4 Input 16 Bit Muxes := 2 + 3 Input 16 Bit Muxes := 1 + 3 Input 15 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 4 + 2 Input 5 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 13 + 9 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA +Detailed RTL Component Info : ++---Registers : + 20 Bit Registers := 1 +Module ltlib_v1_0_0_match +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized0 +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1 +Detailed RTL Component Info : ++---Registers : + 13 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ila_v6_2_9_ila_trigger +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 2 +Module ltlib_v1_0_0_async_edge_xfer +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 1 Bit Registers := 5 +Module ltlib_v1_0_0_rising_edge_detection +Detailed RTL Component Info : ++---Registers : + 2 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 2 Bit Muxes := 2 +Module ila_v6_2_9_ila_reset_ctrl +Detailed RTL Component Info : ++---Registers : + 6 Bit Registers := 1 + 1 Bit Registers := 2 +Module ltlib_v1_0_0_cfglut7 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 3 +Module ltlib_v1_0_0_cfglut6 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_allx_typeA_nodelay +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module ila_v6_2_9_ila_cap_addrgen +Detailed RTL Component Info : ++---Registers : + 33 Bit Registers := 2 + 16 Bit Registers := 4 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 16 +Module ltlib_v1_0_0_cfglut6__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_cap_ctrl_legacy +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 3 ++---Muxes : + 2 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 1 +Module blk_mem_gen_v8_4_3_bindec +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 16 +Module blk_mem_gen_v8_4_3_blk_mem_gen_mux +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_generic_memrd +Detailed RTL Component Info : ++---Adders : + 2 Input 16 Bit Adders := 1 + 2 Input 3 Bit Adders := 1 ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 1 + 7 Bit Registers := 1 + 4 Bit Registers := 2 + 3 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 8 Input 16 Bit Muxes := 1 + 3 Input 7 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1 + 8 Input 1 Bit Muxes := 5 +Module ila_v6_2_9_ila_core +Detailed RTL Component Info : ++---Registers : + 121 Bit Registers := 9 + 16 Bit Registers := 2 + 2 Bit Registers := 3 + 1 Bit Registers := 5 ++---Muxes : + 2 Input 121 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 1 +Module ila_v6_2_9_ila +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 6 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 1540 (col length:140) +BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1023] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1023] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[0]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[5]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[0] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[1]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[1] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[2]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[2] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[3]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[3] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[6] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff8_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[15] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:35 ; elapsed = 00:01:47 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 1067 ; free virtual = 44349 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|inst | ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:39 ; elapsed = 00:01:51 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 1027 ; free virtual = 44328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:39 ; elapsed = 00:01:52 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 1011 ; free virtual = 44313 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|inst | ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:41 ; elapsed = 00:01:53 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 995 ; free virtual = 44296 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [9] is driving 218 big block pins (URAM, BRAM and DSP loads). Created 22 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_addr [10] is driving 218 big block pins (URAM, BRAM and DSP loads). Created 22 replicas of its driver. +INFO: [Synth 8-6064] Net \ila_core_inst/trace_read_en is driving 228 big block pins (URAM, BRAM and DSP loads). Created 23 replicas of its driver. +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-3295] tying undriven pin dummy_inferred:in0 to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:trig_in to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:trig_out_ack to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:42 ; elapsed = 00:01:54 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 966 ; free virtual = 44267 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:42 ; elapsed = 00:01:54 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 966 ; free virtual = 44267 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:42 ; elapsed = 00:01:54 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 975 ; free virtual = 44276 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:42 ; elapsed = 00:01:54 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 990 ; free virtual = 44291 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:42 ; elapsed = 00:01:55 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 978 ; free virtual = 44280 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:42 ; elapsed = 00:01:55 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 979 ; free virtual = 44280 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|ila_v6_2_9_generic_counter | counter_load_i_reg[16] | 16 | 4 | NO | NO | YES | 4 | 0 | +|ila_v6_2_9_ila | ila_core_inst/u_ila_regs/adv_rb_drdy4_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/shifted_data_in_reg[8][120] | 9 | 121 | NO | NO | YES | 121 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |CARRY4 | 229| +|2 |CFGLUT5 | 636| +|3 |LUT1 | 90| +|4 |LUT2 | 130| +|5 |LUT3 | 420| +|6 |LUT4 | 569| +|7 |LUT5 | 267| +|8 |LUT6 | 2079| +|9 |MUXF7 | 369| +|10 |MUXF8 | 119| +|11 |RAM64M | 32| +|12 |RAMB36E1 | 208| +|13 |RAMB36E1_1 | 5| +|14 |RAMB36E1_2 | 5| +|15 |SRL16E | 129| +|16 |SRLC16E | 2| +|17 |SRLC32E | 17| +|18 |FDRE | 4627| +|19 |FDSE | 9| ++------+-----------+------+ + +Report Instance Areas: ++------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ +| |Instance |Module |Cells | ++------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ +|1 |top | | 9942| +|2 | inst |ila_v6_2_9_ila | 9942| +|3 | ila_core_inst |ila_v6_2_9_ila_core | 9935| +|4 | \ADV_TRIG.u_adv_trig |ila_v6_2_9_ila_adv_trigger_sequencer | 185| +|5 | \ADV_TRIG_MEM_READ.u_fsm_memory_read_inst |ila_v6_2_9_ila_fsm_memory_read | 52| +|6 | \COUNTER.u_count |ila_v6_2_9_ila_counter | 232| +|7 | \G_COUNTER[0].U_COUNTER |ila_v6_2_9_generic_counter__1 | 58| +|8 | \G_COUNTER[1].U_COUNTER |ila_v6_2_9_generic_counter__2 | 58| +|9 | \G_COUNTER[2].U_COUNTER |ila_v6_2_9_generic_counter__3 | 58| +|10 | \G_COUNTER[3].U_COUNTER |ila_v6_2_9_generic_counter | 58| +|11 | ila_trace_memory_inst |ila_v6_2_9_ila_trace_memory | 1067| +|12 | \SUBCORE_RAM_BLK_MEM_1.trace_block_memory |blk_mem_gen_v8_4_3 | 1067| +|13 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 1067| +|14 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_v8_4_3_blk_mem_gen_top | 1067| +|15 | \valid.cstr |blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr | 1067| +|16 | \bindec_a.bindec_inst_a |blk_mem_gen_v8_4_3_bindec | 15| +|17 | \has_mux_b.B |blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 | 834| +|18 | \ramloop[0].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width | 1| +|19 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper | 1| +|20 | \ramloop[100].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized99 | 1| +|21 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized99 | 1| +|22 | \ramloop[101].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized100 | 1| +|23 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized100 | 1| +|24 | \ramloop[102].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized101 | 1| +|25 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized101 | 1| +|26 | \ramloop[103].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized102 | 1| +|27 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized102 | 1| +|28 | \ramloop[104].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized103 | 1| +|29 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized103 | 1| +|30 | \ramloop[105].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized104 | 1| +|31 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized104 | 1| +|32 | \ramloop[106].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized105 | 1| +|33 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized105 | 1| +|34 | \ramloop[107].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized106 | 1| +|35 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized106 | 1| +|36 | \ramloop[108].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized107 | 1| +|37 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized107 | 1| +|38 | \ramloop[109].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized108 | 1| +|39 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized108 | 1| +|40 | \ramloop[10].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized9 | 1| +|41 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized9 | 1| +|42 | \ramloop[110].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized109 | 1| +|43 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized109 | 1| +|44 | \ramloop[111].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized110 | 1| +|45 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized110 | 1| +|46 | \ramloop[112].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized111 | 1| +|47 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized111 | 1| +|48 | \ramloop[113].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized112 | 1| +|49 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized112 | 1| +|50 | \ramloop[114].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized113 | 1| +|51 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized113 | 1| +|52 | \ramloop[115].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized114 | 1| +|53 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized114 | 1| +|54 | \ramloop[116].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized115 | 1| +|55 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized115 | 1| +|56 | \ramloop[117].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized116 | 1| +|57 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized116 | 1| +|58 | \ramloop[118].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized117 | 1| +|59 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized117 | 1| +|60 | \ramloop[119].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized118 | 1| +|61 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized118 | 1| +|62 | \ramloop[11].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized10 | 1| +|63 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized10 | 1| +|64 | \ramloop[120].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized119 | 1| +|65 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized119 | 1| +|66 | \ramloop[121].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized120 | 1| +|67 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized120 | 1| +|68 | \ramloop[122].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized121 | 1| +|69 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized121 | 1| +|70 | \ramloop[123].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized122 | 1| +|71 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized122 | 1| +|72 | \ramloop[124].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized123 | 1| +|73 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized123 | 1| +|74 | \ramloop[125].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized124 | 1| +|75 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized124 | 1| +|76 | \ramloop[126].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized125 | 1| +|77 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized125 | 1| +|78 | \ramloop[127].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized126 | 1| +|79 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized126 | 1| +|80 | \ramloop[128].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized127 | 1| +|81 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized127 | 1| +|82 | \ramloop[129].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized128 | 1| +|83 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized128 | 1| +|84 | \ramloop[12].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized11 | 1| +|85 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized11 | 1| +|86 | \ramloop[130].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized129 | 1| +|87 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized129 | 1| +|88 | \ramloop[131].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized130 | 1| +|89 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized130 | 1| +|90 | \ramloop[132].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized131 | 1| +|91 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized131 | 1| +|92 | \ramloop[133].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized132 | 1| +|93 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized132 | 1| +|94 | \ramloop[134].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized133 | 1| +|95 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized133 | 1| +|96 | \ramloop[135].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized134 | 1| +|97 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized134 | 1| +|98 | \ramloop[136].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized135 | 1| +|99 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized135 | 1| +|100 | \ramloop[137].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized136 | 1| +|101 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized136 | 1| +|102 | \ramloop[138].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized137 | 1| +|103 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized137 | 1| +|104 | \ramloop[139].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized138 | 1| +|105 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized138 | 1| +|106 | \ramloop[13].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized12 | 1| +|107 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized12 | 1| +|108 | \ramloop[140].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized139 | 1| +|109 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized139 | 1| +|110 | \ramloop[141].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized140 | 1| +|111 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized140 | 1| +|112 | \ramloop[142].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized141 | 1| +|113 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized141 | 1| +|114 | \ramloop[143].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized142 | 1| +|115 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized142 | 1| +|116 | \ramloop[144].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized143 | 1| +|117 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized143 | 1| +|118 | \ramloop[145].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized144 | 1| +|119 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized144 | 1| +|120 | \ramloop[146].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized145 | 1| +|121 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized145 | 1| +|122 | \ramloop[147].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized146 | 1| +|123 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized146 | 1| +|124 | \ramloop[148].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized147 | 1| +|125 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized147 | 1| +|126 | \ramloop[149].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized148 | 1| +|127 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized148 | 1| +|128 | \ramloop[14].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized13 | 1| +|129 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized13 | 1| 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1| +|256 | \ramloop[207].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized206 | 1| +|257 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized206 | 1| +|258 | \ramloop[208].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized207 | 2| +|259 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized207 | 2| +|260 | \ramloop[209].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized208 | 2| +|261 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized208 | 2| +|262 | \ramloop[20].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized19 | 1| +|263 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized19 | 1| +|264 | \ramloop[210].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized209 | 2| +|265 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized209 | 2| +|266 | \ramloop[211].ram.r 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\prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized23 | 1| +|278 | \ramloop[25].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized24 | 1| +|279 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized24 | 1| +|280 | \ramloop[26].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized25 | 1| +|281 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized25 | 1| +|282 | \ramloop[27].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized26 | 1| +|283 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized26 | 1| +|284 | \ramloop[28].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized27 | 1| +|285 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized27 | 1| +|286 | \ramloop[29].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized28 | 1| +|287 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized28 | 1| +|288 | \ramloop[2].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized1 | 1| +|289 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 | 1| +|290 | \ramloop[30].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized29 | 1| +|291 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized29 | 1| +|292 | \ramloop[31].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized30 | 1| +|293 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized30 | 1| +|294 | \ramloop[32].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized31 | 1| +|295 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized31 | 1| +|296 | \ramloop[33].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized32 | 1| +|297 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized32 | 1| +|298 | \ramloop[34].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized33 | 1| +|299 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized33 | 1| +|300 | \ramloop[35].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized34 | 1| +|301 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized34 | 1| +|302 | \ramloop[36].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized35 | 1| +|303 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized35 | 1| +|304 | \ramloop[37].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized36 | 1| +|305 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized36 | 1| +|306 | \ramloop[38].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized37 | 1| +|307 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized37 | 1| +|308 | \ramloop[39].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized38 | 1| +|309 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized38 | 1| +|310 | \ramloop[3].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized2 | 1| +|311 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 | 1| +|312 | \ramloop[40].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized39 | 1| +|313 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized39 | 1| +|314 | \ramloop[41].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized40 | 1| +|315 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized40 | 1| +|316 | \ramloop[42].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized41 | 1| +|317 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized41 | 1| +|318 | \ramloop[43].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized42 | 1| +|319 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized42 | 1| +|320 | \ramloop[44].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized43 | 1| +|321 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized43 | 1| +|322 | \ramloop[45].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized44 | 1| +|323 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized44 | 1| +|324 | \ramloop[46].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized45 | 1| +|325 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized45 | 1| +|326 | \ramloop[47].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized46 | 1| +|327 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized46 | 1| +|328 | \ramloop[48].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized47 | 1| +|329 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized47 | 1| +|330 | \ramloop[49].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized48 | 1| +|331 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized48 | 1| +|332 | \ramloop[4].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized3 | 1| +|333 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized3 | 1| +|334 | \ramloop[50].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized49 | 1| +|335 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized49 | 1| +|336 | \ramloop[51].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized50 | 1| +|337 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized50 | 1| +|338 | \ramloop[52].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized51 | 1| +|339 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized51 | 1| +|340 | \ramloop[53].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized52 | 1| +|341 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized52 | 1| +|342 | \ramloop[54].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized53 | 1| +|343 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized53 | 1| +|344 | \ramloop[55].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized54 | 1| +|345 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized54 | 1| +|346 | \ramloop[56].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized55 | 1| +|347 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized55 | 1| +|348 | \ramloop[57].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized56 | 1| +|349 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized56 | 1| +|350 | \ramloop[58].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized57 | 1| +|351 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized57 | 1| +|352 | \ramloop[59].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized58 | 1| +|353 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized58 | 1| +|354 | \ramloop[5].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized4 | 1| +|355 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized4 | 1| +|356 | \ramloop[60].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized59 | 1| +|357 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized59 | 1| +|358 | \ramloop[61].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized60 | 1| +|359 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized60 | 1| +|360 | \ramloop[62].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized61 | 1| +|361 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized61 | 1| +|362 | \ramloop[63].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized62 | 1| +|363 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized62 | 1| +|364 | \ramloop[64].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized63 | 1| +|365 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized63 | 1| +|366 | \ramloop[65].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized64 | 1| +|367 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized64 | 1| +|368 | \ramloop[66].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized65 | 1| +|369 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized65 | 1| +|370 | \ramloop[67].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized66 | 1| +|371 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized66 | 1| +|372 | \ramloop[68].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized67 | 1| +|373 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized67 | 1| +|374 | \ramloop[69].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized68 | 1| +|375 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized68 | 1| +|376 | \ramloop[6].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized5 | 1| +|377 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized5 | 1| +|378 | \ramloop[70].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized69 | 1| +|379 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized69 | 1| +|380 | \ramloop[71].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized70 | 1| +|381 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized70 | 1| +|382 | \ramloop[72].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized71 | 1| +|383 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized71 | 1| +|384 | \ramloop[73].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized72 | 1| +|385 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized72 | 1| +|386 | \ramloop[74].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized73 | 1| +|387 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized73 | 1| +|388 | \ramloop[75].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized74 | 1| +|389 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized74 | 1| +|390 | \ramloop[76].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized75 | 1| +|391 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized75 | 1| +|392 | \ramloop[77].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized76 | 1| +|393 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized76 | 1| +|394 | \ramloop[78].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized77 | 1| +|395 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized77 | 1| +|396 | \ramloop[79].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized78 | 1| +|397 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized78 | 1| +|398 | \ramloop[7].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized6 | 1| +|399 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized6 | 1| +|400 | \ramloop[80].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized79 | 1| +|401 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized79 | 1| +|402 | \ramloop[81].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized80 | 1| +|403 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized80 | 1| +|404 | \ramloop[82].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized81 | 1| +|405 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized81 | 1| +|406 | \ramloop[83].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized82 | 1| +|407 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized82 | 1| +|408 | \ramloop[84].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized83 | 1| +|409 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized83 | 1| +|410 | \ramloop[85].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized84 | 1| +|411 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized84 | 1| +|412 | \ramloop[86].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized85 | 1| +|413 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized85 | 1| +|414 | \ramloop[87].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized86 | 1| +|415 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized86 | 1| +|416 | \ramloop[88].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized87 | 1| +|417 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized87 | 1| +|418 | \ramloop[89].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized88 | 1| +|419 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized88 | 1| +|420 | \ramloop[8].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized7 | 1| +|421 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized7 | 1| +|422 | \ramloop[90].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized89 | 1| +|423 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized89 | 1| +|424 | \ramloop[91].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized90 | 1| +|425 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized90 | 1| +|426 | \ramloop[92].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized91 | 1| +|427 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized91 | 1| +|428 | \ramloop[93].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized92 | 1| +|429 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized92 | 1| +|430 | \ramloop[94].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized93 | 1| +|431 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized93 | 1| +|432 | \ramloop[95].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized94 | 1| +|433 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized94 | 1| +|434 | \ramloop[96].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized95 | 1| +|435 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized95 | 1| +|436 | \ramloop[97].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized96 | 1| +|437 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized96 | 1| +|438 | \ramloop[98].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized97 | 1| +|439 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized97 | 1| +|440 | \ramloop[99].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized98 | 1| +|441 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized98 | 1| +|442 | \ramloop[9].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized8 | 1| +|443 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized8 | 1| +|444 | u_ila_cap_ctrl |ila_v6_2_9_ila_cap_ctrl_legacy | 318| +|445 | U_CDONE |ltlib_v1_0_0_cfglut6__parameterized0 | 5| +|446 | U_NS0 |ltlib_v1_0_0_cfglut7 | 8| +|447 | U_NS1 |ltlib_v1_0_0_cfglut7_312 | 10| +|448 | u_cap_addrgen |ila_v6_2_9_ila_cap_addrgen | 290| +|449 | U_CMPRESET |ltlib_v1_0_0_cfglut6 | 3| +|450 | u_cap_sample_counter |ila_v6_2_9_ila_cap_sample_counter | 71| +|451 | U_SCE |ltlib_v1_0_0_cfglut4_319 | 1| +|452 | U_SCMPCE |ltlib_v1_0_0_cfglut5_320 | 1| +|453 | U_SCRST |ltlib_v1_0_0_cfglut6_321 | 3| +|454 | u_scnt_cmp |ltlib_v1_0_0_match_nodelay_322 | 28| +|455 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_323 | 28| +|456 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_324 | 12| +|457 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_325 | 5| +|458 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_326 | 5| +|459 | u_cap_window_counter |ila_v6_2_9_ila_cap_window_counter | 66| +|460 | U_WCE |ltlib_v1_0_0_cfglut4 | 1| +|461 | U_WHCMPCE |ltlib_v1_0_0_cfglut5 | 1| +|462 | U_WLCMPCE |ltlib_v1_0_0_cfglut5_313 | 1| +|463 | u_wcnt_hcmp |ltlib_v1_0_0_match_nodelay | 12| +|464 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_315 | 12| +|465 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_316 | 12| +|466 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_317 | 5| +|467 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_318 | 5| +|468 | u_wcnt_lcmp |ltlib_v1_0_0_match_nodelay_314 | 28| +|469 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay | 28| +|470 | DUT |ltlib_v1_0_0_all_typeA__parameterized1 | 12| +|471 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1 | 5| +|472 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2 | 5| +|473 | u_ila_regs |ila_v6_2_9_ila_register | 5891| +|474 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 302| +|475 | reg_890 |xsdbs_v1_0_2_reg__parameterized72 | 16| +|476 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_311 | 16| +|477 | \ADV_TRIG_STREAM.reg_stream_ffc |xsdbs_v1_0_2_reg_stream__parameterized0 | 25| +|478 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_310 | 22| +|479 | \ADV_TRIG_STREAM_READBACK.reg_stream_ffb |xsdbs_v1_0_2_reg_stream | 27| +|480 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_309 | 27| +|481 | \CNT.CNT_SRL[0].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized51 | 75| +|482 | \CNT.CNT_SRL[1].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized52 | 74| +|483 | \CNT.CNT_SRL[2].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized53 | 88| +|484 | \CNT.CNT_SRL[3].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized54 | 86| +|485 | \MU_SRL[0].mu_srl_reg |xsdbs_v1_0_2_reg_p2s | 74| +|486 | \MU_SRL[10].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized9 | 74| +|487 | \MU_SRL[11].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized10 | 106| +|488 | \MU_SRL[12].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized11 | 74| +|489 | \MU_SRL[13].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized12 | 74| +|490 | \MU_SRL[14].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized13 | 74| +|491 | \MU_SRL[15].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized14 | 90| +|492 | \MU_SRL[16].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized15 | 74| +|493 | \MU_SRL[17].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized16 | 74| +|494 | \MU_SRL[18].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized17 | 74| +|495 | \MU_SRL[19].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized18 | 106| +|496 | \MU_SRL[1].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized0 | 74| +|497 | \MU_SRL[2].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized1 | 74| +|498 | \MU_SRL[3].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized2 | 106| +|499 | \MU_SRL[4].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized3 | 74| +|500 | \MU_SRL[5].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized4 | 74| +|501 | \MU_SRL[6].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized5 | 74| +|502 | \MU_SRL[7].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized6 | 90| +|503 | \MU_SRL[8].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized7 | 74| +|504 | \MU_SRL[9].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized8 | 74| +|505 | \STRG_QUAL.qual_strg_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized55 | 81| +|506 | \TC_SRL[0].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized19 | 74| +|507 | \TC_SRL[10].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized29 | 74| +|508 | \TC_SRL[11].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized30 | 106| +|509 | \TC_SRL[12].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized31 | 74| +|510 | \TC_SRL[13].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized32 | 74| +|511 | \TC_SRL[14].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized33 | 74| +|512 | \TC_SRL[15].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized34 | 90| +|513 | \TC_SRL[16].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized35 | 74| +|514 | \TC_SRL[17].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized36 | 74| +|515 | \TC_SRL[18].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized37 | 74| +|516 | \TC_SRL[19].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized38 | 106| +|517 | \TC_SRL[1].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized20 | 74| +|518 | \TC_SRL[20].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized39 | 74| +|519 | \TC_SRL[21].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized40 | 74| +|520 | \TC_SRL[22].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized41 | 74| +|521 | \TC_SRL[23].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized42 | 90| +|522 | \TC_SRL[24].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized43 | 74| +|523 | \TC_SRL[25].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized44 | 74| +|524 | \TC_SRL[26].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized45 | 74| +|525 | \TC_SRL[27].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized46 | 122| +|526 | \TC_SRL[28].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized47 | 74| +|527 | \TC_SRL[29].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized48 | 74| +|528 | \TC_SRL[2].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized21 | 74| +|529 | \TC_SRL[30].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized49 | 74| +|530 | \TC_SRL[31].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized50 | 90| +|531 | \TC_SRL[3].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized22 | 106| +|532 | \TC_SRL[4].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized23 | 74| +|533 | \TC_SRL[5].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized24 | 74| +|534 | \TC_SRL[6].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized25 | 74| +|535 | \TC_SRL[7].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized26 | 90| +|536 | \TC_SRL[8].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized27 | 74| +|537 | \TC_SRL[9].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized28 | 74| +|538 | reg_15 |xsdbs_v1_0_2_reg__parameterized54 | 29| +|539 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_308 | 29| +|540 | reg_16 |xsdbs_v1_0_2_reg__parameterized55 | 17| +|541 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_307 | 17| +|542 | reg_17 |xsdbs_v1_0_2_reg__parameterized56 | 26| +|543 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_306 | 26| +|544 | reg_18 |xsdbs_v1_0_2_reg__parameterized57 | 31| +|545 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_305 | 31| +|546 | reg_19 |xsdbs_v1_0_2_reg__parameterized58 | 20| +|547 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_304 | 20| +|548 | reg_1a |xsdbs_v1_0_2_reg__parameterized59 | 33| +|549 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1 | 33| +|550 | reg_6 |xsdbs_v1_0_2_reg__parameterized39 | 20| +|551 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_303 | 20| +|552 | reg_7 |xsdbs_v1_0_2_reg__parameterized40 | 36| +|553 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized0 | 36| +|554 | reg_8 |xsdbs_v1_0_2_reg__parameterized41 | 6| +|555 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_302 | 6| +|556 | reg_80 |xsdbs_v1_0_2_reg__parameterized60 | 17| +|557 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2_301 | 17| +|558 | reg_81 |xsdbs_v1_0_2_reg__parameterized61 | 17| +|559 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_300 | 17| +|560 | reg_82 |xsdbs_v1_0_2_reg__parameterized62 | 17| +|561 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2 | 17| +|562 | reg_83 |xsdbs_v1_0_2_reg__parameterized63 | 63| +|563 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_299 | 63| +|564 | reg_84 |xsdbs_v1_0_2_reg__parameterized64 | 23| +|565 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_298 | 23| +|566 | reg_85 |xsdbs_v1_0_2_reg__parameterized65 | 17| +|567 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_297 | 17| +|568 | reg_887 |xsdbs_v1_0_2_reg__parameterized67 | 3| +|569 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_296 | 3| +|570 | reg_88d |xsdbs_v1_0_2_reg__parameterized69 | 2| +|571 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_295 | 2| +|572 | reg_88f |xsdbs_v1_0_2_reg__parameterized71 | 38| +|573 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_294 | 38| +|574 | reg_892 |xsdbs_v1_0_2_reg__parameterized70 | 4| +|575 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_293 | 4| +|576 | reg_9 |xsdbs_v1_0_2_reg__parameterized42 | 23| +|577 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_292 | 23| +|578 | reg_srl_fff |xsdbs_v1_0_2_reg_p2s__parameterized56 | 102| +|579 | reg_stream_ffd |xsdbs_v1_0_2_reg_stream__parameterized1 | 18| +|580 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl | 18| +|581 | reg_stream_ffe |xsdbs_v1_0_2_reg_stream__parameterized2 | 16| +|582 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat | 16| +|583 | u_ila_reset_ctrl |ila_v6_2_9_ila_reset_ctrl | 47| +|584 | arm_detection_inst |ltlib_v1_0_0_rising_edge_detection | 5| +|585 | \asyncrounous_transfer.arm_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer | 7| +|586 | \asyncrounous_transfer.arm_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_288 | 7| +|587 | \asyncrounous_transfer.halt_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer_289 | 7| +|588 | \asyncrounous_transfer.halt_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_290 | 6| +|589 | halt_detection_inst |ltlib_v1_0_0_rising_edge_detection_291 | 6| +|590 | u_trig |ila_v6_2_9_ila_trigger | 1217| +|591 | \N_DDR_TC.N_DDR_TC_INST[0].U_TC |ltlib_v1_0_0_match | 19| +|592 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_283 | 18| +|593 | DUT |ltlib_v1_0_0_all_typeA_284 | 18| +|594 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_285 | 5| +|595 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_286 | 5| +|596 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_287 | 6| +|597 | \N_DDR_TC.N_DDR_TC_INST[10].U_TC |ltlib_v1_0_0_match_0 | 19| +|598 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_278 | 18| +|599 | DUT |ltlib_v1_0_0_all_typeA_279 | 18| +|600 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_280 | 5| +|601 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_281 | 5| +|602 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_282 | 6| +|603 | \N_DDR_TC.N_DDR_TC_INST[11].U_TC |ltlib_v1_0_0_match_1 | 19| +|604 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_273 | 18| +|605 | DUT |ltlib_v1_0_0_all_typeA_274 | 18| +|606 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_275 | 5| +|607 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_276 | 5| +|608 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_277 | 6| +|609 | \N_DDR_TC.N_DDR_TC_INST[12].U_TC |ltlib_v1_0_0_match_2 | 19| +|610 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_268 | 18| +|611 | DUT |ltlib_v1_0_0_all_typeA_269 | 18| +|612 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_270 | 5| +|613 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_271 | 5| +|614 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_272 | 6| +|615 | \N_DDR_TC.N_DDR_TC_INST[13].U_TC |ltlib_v1_0_0_match_3 | 19| +|616 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_263 | 18| +|617 | DUT |ltlib_v1_0_0_all_typeA_264 | 18| +|618 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_265 | 5| +|619 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_266 | 5| +|620 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_267 | 6| +|621 | \N_DDR_TC.N_DDR_TC_INST[14].U_TC |ltlib_v1_0_0_match_4 | 19| +|622 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_258 | 18| +|623 | DUT |ltlib_v1_0_0_all_typeA_259 | 18| +|624 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_260 | 5| +|625 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_261 | 5| +|626 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_262 | 6| +|627 | \N_DDR_TC.N_DDR_TC_INST[15].U_TC |ltlib_v1_0_0_match_5 | 19| +|628 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_253 | 18| +|629 | DUT |ltlib_v1_0_0_all_typeA_254 | 18| +|630 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_255 | 5| +|631 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_256 | 5| +|632 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_257 | 6| +|633 | \N_DDR_TC.N_DDR_TC_INST[16].U_TC |ltlib_v1_0_0_match_6 | 19| +|634 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_248 | 18| +|635 | DUT |ltlib_v1_0_0_all_typeA_249 | 18| +|636 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_250 | 5| +|637 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_251 | 5| +|638 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_252 | 6| +|639 | \N_DDR_TC.N_DDR_TC_INST[17].U_TC |ltlib_v1_0_0_match_7 | 19| +|640 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_243 | 18| +|641 | DUT |ltlib_v1_0_0_all_typeA_244 | 18| +|642 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_245 | 5| +|643 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_246 | 5| +|644 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_247 | 6| +|645 | \N_DDR_TC.N_DDR_TC_INST[18].U_TC |ltlib_v1_0_0_match_8 | 19| +|646 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_238 | 18| +|647 | DUT |ltlib_v1_0_0_all_typeA_239 | 18| +|648 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_240 | 5| +|649 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_241 | 5| +|650 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_242 | 6| +|651 | \N_DDR_TC.N_DDR_TC_INST[19].U_TC |ltlib_v1_0_0_match_9 | 19| +|652 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_233 | 18| +|653 | DUT |ltlib_v1_0_0_all_typeA_234 | 18| +|654 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_235 | 5| +|655 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_236 | 5| +|656 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_237 | 6| +|657 | \N_DDR_TC.N_DDR_TC_INST[1].U_TC |ltlib_v1_0_0_match_10 | 19| +|658 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_228 | 18| +|659 | DUT |ltlib_v1_0_0_all_typeA_229 | 18| +|660 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_230 | 5| +|661 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_231 | 5| +|662 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_232 | 6| +|663 | \N_DDR_TC.N_DDR_TC_INST[20].U_TC |ltlib_v1_0_0_match_11 | 19| +|664 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_223 | 18| +|665 | DUT |ltlib_v1_0_0_all_typeA_224 | 18| +|666 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_225 | 5| +|667 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_226 | 5| +|668 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_227 | 6| +|669 | \N_DDR_TC.N_DDR_TC_INST[21].U_TC |ltlib_v1_0_0_match_12 | 19| +|670 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_218 | 18| +|671 | DUT |ltlib_v1_0_0_all_typeA_219 | 18| +|672 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_220 | 5| +|673 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_221 | 5| +|674 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_222 | 6| +|675 | \N_DDR_TC.N_DDR_TC_INST[22].U_TC |ltlib_v1_0_0_match_13 | 19| +|676 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_213 | 18| +|677 | DUT |ltlib_v1_0_0_all_typeA_214 | 18| +|678 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_215 | 5| +|679 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_216 | 5| +|680 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_217 | 6| +|681 | \N_DDR_TC.N_DDR_TC_INST[23].U_TC |ltlib_v1_0_0_match_14 | 19| +|682 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_208 | 18| +|683 | DUT |ltlib_v1_0_0_all_typeA_209 | 18| +|684 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_210 | 5| +|685 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_211 | 5| +|686 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_212 | 6| +|687 | \N_DDR_TC.N_DDR_TC_INST[24].U_TC |ltlib_v1_0_0_match_15 | 19| +|688 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_203 | 18| +|689 | DUT |ltlib_v1_0_0_all_typeA_204 | 18| +|690 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_205 | 5| +|691 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_206 | 5| +|692 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_207 | 6| +|693 | \N_DDR_TC.N_DDR_TC_INST[25].U_TC |ltlib_v1_0_0_match_16 | 19| +|694 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_198 | 18| +|695 | DUT |ltlib_v1_0_0_all_typeA_199 | 18| +|696 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_200 | 5| +|697 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_201 | 5| +|698 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_202 | 6| +|699 | \N_DDR_TC.N_DDR_TC_INST[26].U_TC |ltlib_v1_0_0_match_17 | 19| +|700 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_193 | 18| +|701 | DUT |ltlib_v1_0_0_all_typeA_194 | 18| +|702 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_195 | 5| +|703 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_196 | 5| +|704 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_197 | 6| +|705 | \N_DDR_TC.N_DDR_TC_INST[27].U_TC |ltlib_v1_0_0_match_18 | 19| +|706 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_188 | 18| +|707 | DUT |ltlib_v1_0_0_all_typeA_189 | 18| +|708 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_190 | 5| +|709 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_191 | 5| +|710 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_192 | 6| +|711 | \N_DDR_TC.N_DDR_TC_INST[28].U_TC |ltlib_v1_0_0_match_19 | 19| +|712 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_183 | 18| +|713 | DUT |ltlib_v1_0_0_all_typeA_184 | 18| +|714 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_185 | 5| +|715 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_186 | 5| +|716 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_187 | 6| +|717 | \N_DDR_TC.N_DDR_TC_INST[29].U_TC |ltlib_v1_0_0_match_20 | 19| +|718 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_178 | 18| +|719 | DUT |ltlib_v1_0_0_all_typeA_179 | 18| +|720 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_180 | 5| +|721 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_181 | 5| +|722 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_182 | 6| +|723 | \N_DDR_TC.N_DDR_TC_INST[2].U_TC |ltlib_v1_0_0_match_21 | 19| +|724 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_173 | 18| +|725 | DUT |ltlib_v1_0_0_all_typeA_174 | 18| +|726 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_175 | 5| +|727 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_176 | 5| +|728 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_177 | 6| +|729 | \N_DDR_TC.N_DDR_TC_INST[30].U_TC |ltlib_v1_0_0_match_22 | 19| +|730 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_168 | 18| +|731 | DUT |ltlib_v1_0_0_all_typeA_169 | 18| +|732 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_170 | 5| +|733 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_171 | 5| +|734 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_172 | 6| +|735 | \N_DDR_TC.N_DDR_TC_INST[31].U_TC |ltlib_v1_0_0_match_23 | 19| +|736 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_163 | 18| +|737 | DUT |ltlib_v1_0_0_all_typeA_164 | 18| +|738 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_165 | 5| +|739 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_166 | 5| +|740 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_167 | 6| +|741 | \N_DDR_TC.N_DDR_TC_INST[3].U_TC |ltlib_v1_0_0_match_24 | 19| +|742 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_158 | 18| +|743 | DUT |ltlib_v1_0_0_all_typeA_159 | 18| +|744 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_160 | 5| +|745 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_161 | 5| +|746 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_162 | 6| +|747 | \N_DDR_TC.N_DDR_TC_INST[4].U_TC |ltlib_v1_0_0_match_25 | 19| +|748 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_153 | 18| +|749 | DUT |ltlib_v1_0_0_all_typeA_154 | 18| +|750 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_155 | 5| +|751 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_156 | 5| +|752 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_157 | 6| +|753 | \N_DDR_TC.N_DDR_TC_INST[5].U_TC |ltlib_v1_0_0_match_26 | 19| +|754 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_148 | 18| +|755 | DUT |ltlib_v1_0_0_all_typeA_149 | 18| +|756 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_150 | 5| +|757 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_151 | 5| +|758 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_152 | 6| +|759 | \N_DDR_TC.N_DDR_TC_INST[6].U_TC |ltlib_v1_0_0_match_27 | 19| +|760 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_143 | 18| +|761 | DUT |ltlib_v1_0_0_all_typeA_144 | 18| +|762 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_145 | 5| +|763 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_146 | 5| +|764 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_147 | 6| +|765 | \N_DDR_TC.N_DDR_TC_INST[7].U_TC |ltlib_v1_0_0_match_28 | 19| +|766 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_138 | 18| +|767 | DUT |ltlib_v1_0_0_all_typeA_139 | 18| +|768 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_140 | 5| +|769 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_141 | 5| +|770 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_142 | 6| +|771 | \N_DDR_TC.N_DDR_TC_INST[8].U_TC |ltlib_v1_0_0_match_29 | 19| +|772 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_133 | 18| +|773 | DUT |ltlib_v1_0_0_all_typeA_134 | 18| +|774 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_135 | 5| +|775 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_136 | 5| +|776 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_137 | 6| +|777 | \N_DDR_TC.N_DDR_TC_INST[9].U_TC |ltlib_v1_0_0_match_30 | 19| +|778 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_128 | 18| +|779 | DUT |ltlib_v1_0_0_all_typeA_129 | 18| +|780 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_130 | 5| +|781 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_131 | 5| +|782 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_132 | 6| +|783 | \STRG_QUAL.U_STRG_QUAL |ltlib_v1_0_0_match_31 | 39| +|784 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA | 38| +|785 | DUT |ltlib_v1_0_0_all_typeA | 18| +|786 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_125 | 5| +|787 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_126 | 5| +|788 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_127 | 6| +|789 | U_TM |ila_v6_2_9_ila_trig_match | 522| +|790 | \N_DDR_MODE.G_NMU[0].U_M |ltlib_v1_0_0_match__parameterized0 | 38| +|791 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_121 | 37| +|792 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_122 | 13| +|793 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_123 | 5| +|794 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_124 | 6| +|795 | \N_DDR_MODE.G_NMU[10].U_M |ltlib_v1_0_0_match__parameterized0_32 | 38| +|796 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_117 | 37| +|797 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_118 | 13| +|798 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_119 | 5| +|799 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_120 | 6| +|800 | \N_DDR_MODE.G_NMU[11].U_M |ltlib_v1_0_0_match__parameterized0_33 | 14| +|801 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_113 | 13| +|802 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_114 | 13| +|803 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_115 | 5| +|804 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_116 | 6| +|805 | \N_DDR_MODE.G_NMU[12].U_M |ltlib_v1_0_0_match__parameterized0_34 | 38| +|806 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_109 | 37| +|807 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_110 | 13| +|808 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_111 | 5| +|809 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_112 | 6| +|810 | \N_DDR_MODE.G_NMU[13].U_M |ltlib_v1_0_0_match__parameterized0_35 | 14| +|811 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_105 | 13| +|812 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_106 | 13| +|813 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_107 | 5| +|814 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_108 | 6| +|815 | \N_DDR_MODE.G_NMU[14].U_M |ltlib_v1_0_0_match__parameterized0_36 | 38| +|816 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_101 | 37| +|817 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_102 | 13| +|818 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_103 | 5| +|819 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_104 | 6| +|820 | \N_DDR_MODE.G_NMU[15].U_M |ltlib_v1_0_0_match__parameterized0_37 | 14| +|821 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_97 | 13| +|822 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_98 | 13| +|823 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_99 | 5| +|824 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_100 | 6| +|825 | \N_DDR_MODE.G_NMU[16].U_M |ltlib_v1_0_0_match__parameterized0_38 | 38| +|826 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_93 | 37| +|827 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_94 | 13| +|828 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_95 | 5| +|829 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_96 | 6| +|830 | \N_DDR_MODE.G_NMU[17].U_M |ltlib_v1_0_0_match__parameterized0_39 | 14| +|831 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_89 | 13| +|832 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_90 | 13| +|833 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_91 | 5| +|834 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_92 | 6| +|835 | \N_DDR_MODE.G_NMU[18].U_M |ltlib_v1_0_0_match__parameterized1 | 40| +|836 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_85 | 39| +|837 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_86 | 13| +|838 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_87 | 5| +|839 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_88 | 6| +|840 | \N_DDR_MODE.G_NMU[19].U_M |ltlib_v1_0_0_match__parameterized1_40 | 14| +|841 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1 | 13| +|842 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_82 | 13| +|843 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_83 | 5| +|844 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_84 | 6| +|845 | \N_DDR_MODE.G_NMU[1].U_M |ltlib_v1_0_0_match__parameterized0_41 | 14| +|846 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_78 | 13| +|847 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_79 | 13| +|848 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_80 | 5| +|849 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_81 | 6| +|850 | \N_DDR_MODE.G_NMU[2].U_M |ltlib_v1_0_0_match__parameterized0_42 | 38| +|851 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_74 | 37| +|852 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_75 | 13| +|853 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_76 | 5| +|854 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_77 | 6| +|855 | \N_DDR_MODE.G_NMU[3].U_M |ltlib_v1_0_0_match__parameterized0_43 | 14| +|856 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_70 | 13| +|857 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_71 | 13| +|858 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_72 | 5| +|859 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_73 | 6| +|860 | \N_DDR_MODE.G_NMU[4].U_M |ltlib_v1_0_0_match__parameterized0_44 | 38| +|861 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_66 | 37| +|862 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_67 | 13| +|863 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_68 | 5| +|864 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_69 | 6| +|865 | \N_DDR_MODE.G_NMU[5].U_M |ltlib_v1_0_0_match__parameterized0_45 | 14| +|866 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_62 | 13| +|867 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_63 | 13| +|868 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_64 | 5| +|869 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_65 | 6| +|870 | \N_DDR_MODE.G_NMU[6].U_M |ltlib_v1_0_0_match__parameterized0_46 | 38| +|871 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_58 | 37| +|872 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_59 | 13| +|873 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_60 | 5| +|874 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_61 | 6| +|875 | \N_DDR_MODE.G_NMU[7].U_M |ltlib_v1_0_0_match__parameterized0_47 | 14| +|876 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_54 | 13| +|877 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_55 | 13| +|878 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_56 | 5| +|879 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_57 | 6| +|880 | \N_DDR_MODE.G_NMU[8].U_M |ltlib_v1_0_0_match__parameterized0_48 | 38| +|881 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_50 | 37| +|882 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_51 | 13| +|883 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_52 | 5| +|884 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_53 | 6| +|885 | \N_DDR_MODE.G_NMU[9].U_M |ltlib_v1_0_0_match__parameterized0_49 | 14| +|886 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0 | 13| +|887 | DUT |ltlib_v1_0_0_all_typeA__parameterized0 | 13| +|888 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice | 5| +|889 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0 | 6| +|890 | xsdb_memory_read_inst |ltlib_v1_0_0_generic_memrd | 592| ++------+------------------------------------------------------------------------+--------------------------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:42 ; elapsed = 00:01:55 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 985 ; free virtual = 44287 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 9118 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:38 ; elapsed = 00:01:51 . Memory (MB): peak = 2410.957 ; gain = 626.891 ; free physical = 1031 ; free virtual = 44332 +Synthesis Optimization Complete : Time (s): cpu = 00:01:42 ; elapsed = 00:01:55 . Memory (MB): peak = 2410.957 ; gain = 720.734 ; free physical = 1044 ; free virtual = 44346 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 1603 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2410.957 ; gain = 0.000 ; free physical = 953 ; free virtual = 44254 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 668 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 580 instances + CFGLUT5 => SRLC32E: 56 instances + RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 32 instances + +INFO: [Common 17-83] Releasing license: Synthesis +351 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:46 ; elapsed = 00:01:59 . Memory (MB): peak = 2410.957 ; gain = 999.504 ; free physical = 1077 ; free virtual = 44379 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2410.957 ; gain = 0.000 ; free physical = 1071 ; free virtual = 44373 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ila_rx_data_cnt, cache-ID = ac5110ede4bd2290 +INFO: [Coretcl 2-1174] Renamed 889 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2434.969 ; gain = 0.000 ; free physical = 1021 ; free virtual = 44329 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file ila_rx_data_cnt_utilization_synth.rpt -pb ila_rx_data_cnt_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri May 12 16:03:11 2023... diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v new file mode 100644 index 00000000..21ec7c01 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:02dda248f9b1a8197f772221bda8b56d04bea26b3792357949d51d05a91afa5e +size 9313152 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl new file mode 100644 index 00000000..cbfa4c7b --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:61d9c165e3418160c7fe9dc268aff1d33f63f0208399fdad58ae469efb9aaa9c +size 11856008 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v new file mode 100644 index 00000000..912209ee --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Fri May 12 16:03:10 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v +// Design : ila_rx_data_cnt +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]" */; + input clk; + input [11:0]probe0; + input [11:0]probe1; + input [11:0]probe2; + input [11:0]probe3; + input [11:0]probe4; + input [11:0]probe5; + input [11:0]probe6; + input [11:0]probe7; + input [11:0]probe8; + input [12:0]probe9; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl new file mode 100644 index 00000000..5939820e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Fri May 12 16:03:10 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl +-- Design : ila_rx_data_cnt +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_rx_data_cnt is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 ) + ); + +end ila_rx_data_cnt; + +architecture stub of ila_rx_data_cnt is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.pb new file mode 100644 index 00000000..ce0180a7 Binary files /dev/null and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.rpt similarity index 77% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_utilization_synth.rpt rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.rpt index 1c6a0197..180581d3 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_utilization_synth.rpt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.rpt @@ -1,10 +1,10 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Mon May 8 00:29:10 2023 +| Date : Fri May 12 16:03:10 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_utilization -file dds_32b_8b_comp_utilization_synth.rpt -pb dds_32b_8b_comp_utilization_synth.pb -| Design : dds_32b_8b_comp +| Command : report_utilization -file ila_rx_data_cnt_utilization_synth.rpt -pb ila_rx_data_cnt_utilization_synth.pb +| Design : ila_rx_data_cnt | Device : 7k410tffg900-2 | Design State : Synthesized ------------------------------------------------------------------------------------------------------------------------- @@ -30,16 +30,16 @@ Table of Contents +----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 67 | 0 | 254200 | 0.03 | -| LUT as Logic | 66 | 0 | 254200 | 0.03 | -| LUT as Memory | 1 | 0 | 90600 | <0.01 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 1 | 0 | | | -| Slice Registers | 232 | 0 | 508400 | 0.05 | -| Register as Flip Flop | 232 | 0 | 508400 | 0.05 | +| Slice LUTs* | 4197 | 0 | 254200 | 1.65 | +| LUT as Logic | 3285 | 0 | 254200 | 1.29 | +| LUT as Memory | 912 | 0 | 90600 | 1.01 | +| LUT as Distributed RAM | 128 | 0 | | | +| LUT as Shift Register | 784 | 0 | | | +| Slice Registers | 4636 | 0 | 508400 | 0.91 | +| Register as Flip Flop | 4636 | 0 | 508400 | 0.91 | | Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | -| F8 Muxes | 0 | 0 | 63550 | 0.00 | +| F7 Muxes | 369 | 0 | 127100 | 0.29 | +| F8 Muxes | 119 | 0 | 63550 | 0.19 | +----------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -58,8 +58,8 @@ Table of Contents | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 232 | Yes | Reset | - | +| 9 | Yes | Set | - | +| 4627 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -69,10 +69,10 @@ Table of Contents +-------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 0.5 | 0 | 795 | 0.06 | -| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | -| RAMB18 | 1 | 0 | 1590 | 0.06 | -| RAMB18E1 only | 1 | | | | +| Block RAM Tile | 218 | 0 | 795 | 27.42 | +| RAMB36/FIFO* | 218 | 0 | 795 | 27.42 | +| RAMB36E1 only | 218 | | | | +| RAMB18 | 0 | 0 | 1590 | 0.00 | +-------------------+------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 @@ -154,11 +154,22 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 232 | Flop & Latch | -| LUT2 | 67 | LUT | -| CARRY4 | 18 | CarryLogic | -| SRL16E | 1 | Distributed Memory | -| RAMB18E1 | 1 | Block Memory | +| FDRE | 4627 | Flop & Latch | +| LUT6 | 2079 | LUT | +| SRL16E | 709 | Distributed Memory | +| SRLC32E | 653 | Distributed Memory | +| LUT4 | 569 | LUT | +| LUT3 | 420 | LUT | +| MUXF7 | 369 | MuxFx | +| LUT5 | 267 | LUT | +| CARRY4 | 229 | CarryLogic | +| RAMB36E1 | 218 | Block Memory | +| LUT2 | 130 | LUT | +| RAMD64E | 128 | Distributed Memory | +| MUXF8 | 119 | MuxFx | +| LUT1 | 90 | LUT | +| FDSE | 9 | Flop & Latch | +| SRLC16E | 2 | Distributed Memory | +----------+------+---------------------+ diff --git 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3536:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3536:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00 +eof:3271634566 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/rundef.js b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/rundef.js similarity index 90% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/rundef.js rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/rundef.js index 03825001..282eccd2 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/rundef.js +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/rundef.js @@ -27,7 +27,7 @@ eval( EAInclude(ISEJScriptLib) ); ISEStep( "vivado", - "-log dds_32b_8b_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b_comp.tcl" ); + "-log ila_rx_data_cnt.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rx_data_cnt.tcl" ); diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.bat b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/runme.sh b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.sh similarity index 78% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/runme.sh rename to projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.sh index d21edcf5..2b4818af 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/runme.sh +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.sh @@ -20,7 +20,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1' +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1' cd "$HD_PWD" HD_LOG=runme.log @@ -36,4 +36,4 @@ EAStep() fi } -EAStep vivado -log dds_32b_8b_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b_comp.tcl +EAStep vivado -log ila_rx_data_cnt.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rx_data_cnt.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.pb new file mode 100644 index 00000000..03e9d74f Binary files /dev/null and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml index 356cc1aa..e22ee31e 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml @@ -1,9 +1,9 @@ + - diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst index 0dd4e24d..28ef12b8 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml index 214e88a8..aaa42623 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml @@ -1,23 +1,20 @@ - - - - - + + - - + + - + - + @@ -30,14 +27,14 @@ - + - + @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf index 992bd86d..dba90573 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf @@ -1,13 +1,13 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:39:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:39:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3132:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3132:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 @@ -15,8 +15,11 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31327838:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6464735f636f6d70696c65725f76365f305f31385c6464735f3332625f38625f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f7072627331305f696e766572745f72657032:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f70726273375f696e766572745f72657034:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f667265715f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72665f6175746f5f636f6e74726f6c:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f646174615f636e74:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6d756c745f67656e5f7631325f305f31355c6d756c745f3138783138:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c726f6d5f667265715f776f7264:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f667265715f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00 @@ -29,12 +32,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3530:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3530:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3530:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3530:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3530:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3530:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3530:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3631:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3631:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3631:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3631:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3631:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3631:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3631:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00 -eof:3566321396 +eof:2136661241 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp index 25bb406d..fcbce19a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:18172bb58703e3439c687dd44b788e6bb9614e5a2c98ebdeaddab1872c105790 -size 27056 +oid sha256:09006e002c355a00f06308aaa7c60fb88e6deea8dc9f516cd0b7706bee8c0541 +size 27157 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds index b9b6781d..c05ca12b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds @@ -2,8 +2,8 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Mon May 8 11:43:19 2023 -# Process ID: 1749502 +# Start of session at: Fri May 12 16:05:33 2023 +# Process ID: 1476113 # Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1 # Command line: vivado -log rom_freq_word.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl # Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds @@ -16,9 +16,9 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Device 21-403] Loading part xc7k410tffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 1749681 +INFO: Helper process launched with PID 1476273 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1824.469 ; gain = 151.719 ; free physical = 982 ; free virtual = 45562 +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1824.465 ; gain = 150.719 ; free physical = 851 ; free virtual = 44252 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'rom_freq_word' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/synth/rom_freq_word.vhd:67] Parameter C_FAMILY bound to: kintex7 - type: string @@ -200,7 +200,7 @@ WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[10] WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[9] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2038.180 ; gain = 365.430 ; free physical = 1045 ; free virtual = 45625 +Finished RTL Elaboration : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2038.176 ; gain = 364.430 ; free physical = 1600 ; free virtual = 45063 --------------------------------------------------------------------------------- Report Check Netlist: @@ -213,10 +213,10 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2050.055 ; gain = 377.305 ; free physical = 1048 ; free virtual = 45628 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2050.051 ; gain = 376.305 ; free physical = 1621 ; free virtual = 45083 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2050.055 ; gain = 377.305 ; free physical = 1048 ; free virtual = 45628 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2050.051 ; gain = 376.305 ; free physical = 1621 ; free virtual = 45083 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds @@ -230,30 +230,30 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_onl Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2120.023 ; gain = 0.000 ; free physical = 965 ; free virtual = 45545 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1591 ; free virtual = 45056 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2120.023 ; gain = 0.000 ; free physical = 965 ; free virtual = 45545 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1590 ; free virtual = 45055 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 1027 ; free virtual = 45607 +Finished Constraint Validation : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1596 ; free virtual = 45061 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k410tffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 1027 ; free virtual = 45607 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1595 ; free virtual = 45060 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 1027 ; free virtual = 45607 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1594 ; free virtual = 45059 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 1025 ; free virtual = 45606 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1585 ; free virtual = 45050 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -289,7 +289,7 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 1028 ; free virtual = 45615 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1607 ; free virtual = 45073 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -301,13 +301,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 931 ; free virtual = 45518 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1508 ; free virtual = 44984 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 930 ; free virtual = 45517 +Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1508 ; free virtual = 44984 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -319,7 +319,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 925 ; free virtual = 45512 +Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1507 ; free virtual = 44984 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -343,7 +343,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 925 ; free virtual = 45512 +Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 --------------------------------------------------------------------------------- Report Check Netlist: @@ -356,7 +356,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 925 ; free virtual = 45512 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -368,25 +368,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 925 ; free virtual = 45512 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 925 ; free virtual = 45512 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 925 ; free virtual = 45512 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 925 ; free virtual = 45512 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -418,34 +418,34 @@ Report Instance Areas: |7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| +------+---------------------------------------------+------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 925 ; free virtual = 45512 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 179 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2120.023 ; gain = 377.305 ; free physical = 979 ; free virtual = 45566 -Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2120.023 ; gain = 447.273 ; free physical = 979 ; free virtual = 45566 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2122.988 ; gain = 376.305 ; free physical = 1573 ; free virtual = 45050 +Synthesis Optimization Complete : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1573 ; free virtual = 45050 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2120.023 ; gain = 0.000 ; free physical = 919 ; free virtual = 45506 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1516 ; free virtual = 44993 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2120.023 ; gain = 725.043 ; free physical = 1006 ; free virtual = 45593 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2120.023 ; gain = 0.000 ; free physical = 1008 ; free virtual = 45595 +synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2122.988 ; gain = 728.012 ; free physical = 1605 ; free virtual = 45082 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1605 ; free virtual = 45082 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rom_freq_word, cache-ID = 66dd9a4abe00aebf +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rom_freq_word, cache-ID = 56186d833b788b44 INFO: [Coretcl 2-1174] Renamed 6 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2120.023 ; gain = 0.000 ; free physical = 1002 ; free virtual = 45589 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1595 ; free virtual = 45072 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Mon May 8 11:44:04 2023... +INFO: [Common 17-206] Exiting Vivado at Fri May 12 16:06:19 2023... diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v index a69fa1e3..500264d2 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4b4a24873a254183cff7fd29b02c4d9ab739b50e91503717fc79804b2c61dab1 +oid sha256:d505363140e83ab4ba85f39ee9c59f527bbf5844fd7a46084f7effc591c65fd3 size 28713 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl index 17de3cab..18f20291 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b005766068cddc9213805a499ec6154d69816f71aeeb6e1e36e9158c5c2ed978 +oid sha256:381310f0847e8c98a4f35bc631b3508f4fd6df934e1e070b0d680869a20b8f5e size 42212 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v index bbe2ee09..a485cca8 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 11:44:03 2023 +// Date : Fri May 12 16:06:19 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl index c01133d3..20e02f43 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 11:44:03 2023 +-- Date : Fri May 12 16:06:19 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt index f831c4b3..57f696ae 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Mon May 8 11:44:03 2023 +| Date : Fri May 12 16:06:18 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb | Design : rom_freq_word diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb index b6e9b56b..4b58cce0 100644 Binary files a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst index 0fb216f9..2510948d 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml index ad6c9ba3..1153c03a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -7,14 +7,14 @@ - + - + @@ -27,14 +27,14 @@ - + - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf index 54c60c67..373fe13c 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf @@ -1,23 +1,30 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 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a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp index 81ee08e3..577c0f20 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c212db34ba88f41ad897ac846173584e268382b7f968e886fb1124bfad79fed6 -size 142946 +oid sha256:1474f612cd561b9916dae5c8d066672991464797badb478268337468461515e9 +size 147742 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl index 60028777..216f1363 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl @@ -29,6 +29,7 @@ set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds index b48d9bfb..11b3f62f 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds @@ -2,8 +2,8 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Sun May 7 16:51:17 2023 -# Process ID: 1095172 +# Start of session at: Fri May 12 16:01:42 2023 +# Process ID: 1472630 # Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1 # Command line: vivado -log vio_freq_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_freq_comp.tcl # Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds @@ -16,14 +16,13 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Device 21-403] Loading part xc7k410tffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 1095319 +INFO: Helper process launched with PID 1472861 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1829.949 ; gain = 149.719 ; free physical = 3057 ; free virtual = 50482 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1830.434 ; gain = 153.719 ; free physical = 526 ; free virtual = 44214 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'vio_freq_comp' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_freq_comp/synth/vio_freq_comp.v:59] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_freq_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_freq_comp/synth/vio_freq_comp.v:78] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_freq_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_freq_comp/synth/vio_freq_comp.v:82] INFO: [Synth 8-6155] done synthesizing module 'vio_freq_comp' (8#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_freq_comp/synth/vio_freq_comp.v:59] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] @@ -42,6 +41,7 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bu WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] @@ -125,7 +125,7 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in68[0 WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in69[0] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1889.668 ; gain = 209.438 ; free physical = 3072 ; free virtual = 50503 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1892.121 ; gain = 215.406 ; free physical = 712 ; free virtual = 44329 --------------------------------------------------------------------------------- Report Check Netlist: @@ -138,10 +138,10 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1892.637 ; gain = 212.406 ; free physical = 3074 ; free virtual = 50504 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.090 ; gain = 218.375 ; free physical = 712 ; free virtual = 44328 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1892.637 ; gain = 212.406 ; free physical = 3074 ; free virtual = 50504 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.090 ; gain = 218.375 ; free physical = 712 ; free virtual = 44328 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization @@ -153,29 +153,29 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_onl Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_freq_comp/vio_freq_comp.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2066.324 ; gain = 0.000 ; free physical = 2966 ; free virtual = 50395 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2071.746 ; gain = 0.000 ; free physical = 620 ; free virtual = 44234 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2073.262 ; gain = 6.938 ; free physical = 2966 ; free virtual = 50395 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2079.684 ; gain = 7.938 ; free physical = 618 ; free virtual = 44232 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 3065 ; free virtual = 50491 +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 738 ; free virtual = 44323 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k410tffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 3065 ; free virtual = 50491 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 738 ; free virtual = 44323 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 3065 ; free virtual = 50491 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 738 ; free virtual = 44323 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 3062 ; free virtual = 50490 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 727 ; free virtual = 44313 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -188,22 +188,22 @@ Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : - 2 Input 2 Bit Adders := 1 - 2 Input 1 Bit Adders := 1 + 2 Input 2 Bit Adders := 2 +---Registers : 128 Bit Registers := 1 32 Bit Registers := 1 - 16 Bit Registers := 13 + 16 Bit Registers := 14 + 13 Bit Registers := 1 8 Bit Registers := 1 7 Bit Registers := 1 5 Bit Registers := 1 - 3 Bit Registers := 2 + 3 Bit Registers := 3 2 Bit Registers := 2 - 1 Bit Registers := 25 + 1 Bit Registers := 28 +---Muxes : 2 Input 16 Bit Muxes := 3 - 4 Input 16 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 10 + 3 Input 13 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 12 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -245,18 +245,19 @@ Module vio_v3_0_20_probe_out_all Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 - 2 Bit Registers := 1 - 1 Bit Registers := 6 + 3 Bit Registers := 1 + 1 Bit Registers := 8 +---Muxes : - 4 Input 16 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module vio_v3_0_20_probe_width Detailed RTL Component Info : +---Adders : - 2 Input 1 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 +---Registers : - 16 Bit Registers := 1 - 1 Bit Registers := 1 + 13 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 3 Input 13 Bit Muxes := 1 Module xsdbs_v1_0_2_xsdbs Detailed RTL Component Info : +---Registers : @@ -297,63 +298,87 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[1]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FDS) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FDS) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' -INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[10] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]' (FDS) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[13]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[14]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[12]' --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 3040 ; free virtual = 50471 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 706 ; free virtual = 44295 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -365,13 +390,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 3019 ; free virtual = 50450 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 608 ; free virtual = 44158 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 3016 ; free virtual = 50447 +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 613 ; free virtual = 44169 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -383,7 +408,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 3012 ; free virtual = 50443 +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 602 ; free virtual = 44150 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -444,7 +469,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 2909 ; free virtual = 50340 +Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 617 ; free virtual = 44152 --------------------------------------------------------------------------------- Report Check Netlist: @@ -457,7 +482,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 2909 ; free virtual = 50340 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 616 ; free virtual = 44152 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -469,25 +494,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 2909 ; free virtual = 50340 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 616 ; free virtual = 44152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 2909 ; free virtual = 50340 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 616 ; free virtual = 44152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 2909 ; free virtual = 50340 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 616 ; free virtual = 44152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 2909 ; free virtual = 50340 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 616 ; free virtual = 44152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -503,13 +528,13 @@ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ -|1 |LUT1 | 1| +|1 |LUT1 | 2| |2 |LUT2 | 8| -|3 |LUT3 | 51| +|3 |LUT3 | 61| |4 |LUT4 | 11| -|5 |LUT5 | 13| -|6 |LUT6 | 84| -|7 |FDRE | 355| +|5 |LUT5 | 20| +|6 |LUT6 | 83| +|7 |FDRE | 363| |8 |FDSE | 4| +------+-----+------+ @@ -517,45 +542,47 @@ Report Instance Areas: +------+---------------------------------------+------------------------------------------+------+ | |Instance |Module |Cells | +------+---------------------------------------+------------------------------------------+------+ -|1 |top | | 527| -|2 | inst |vio_v3_0_20_vio | 527| +|1 |top | | 552| +|2 | inst |vio_v3_0_20_vio | 552| |3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| -|4 | DECODER_INST |vio_v3_0_20_decoder | 80| +|4 | DECODER_INST |vio_v3_0_20_decoder | 78| |5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 18| -|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 163| +|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 184| |7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| |8 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 16| |9 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| |10 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 105| -|11 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 2| +|11 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3| +|12 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3| +|13 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 8| +------+---------------------------------------+------------------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 2909 ; free virtual = 50340 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 616 ; free virtual = 44152 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 292 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2073.262 ; gain = 212.406 ; free physical = 2964 ; free virtual = 50395 -Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2073.262 ; gain = 393.031 ; free physical = 2977 ; free virtual = 50409 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2079.684 ; gain = 218.375 ; free physical = 679 ; free virtual = 44217 +Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 684 ; free virtual = 44222 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2073.262 ; gain = 0.000 ; free physical = 2925 ; free virtual = 50357 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2079.684 ; gain = 0.000 ; free physical = 732 ; free virtual = 44286 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -67 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +91 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2073.262 ; gain = 674.832 ; free physical = 3015 ; free virtual = 50446 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2073.262 ; gain = 0.000 ; free physical = 3015 ; free virtual = 50446 +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2079.684 ; gain = 680.770 ; free physical = 823 ; free virtual = 44378 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2079.684 ; gain = 0.000 ; free physical = 823 ; free virtual = 44378 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_freq_comp, cache-ID = 7ca35578ce0e4dda -INFO: [Coretcl 2-1174] Renamed 10 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2097.273 ; gain = 0.000 ; free physical = 3015 ; free virtual = 50448 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_freq_comp, cache-ID = 63d607d13d6695a3 +INFO: [Coretcl 2-1174] Renamed 12 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2103.695 ; gain = 0.000 ; free physical = 788 ; free virtual = 44360 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file vio_freq_comp_utilization_synth.rpt -pb vio_freq_comp_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun May 7 16:51:33 2023... +INFO: [Common 17-206] Exiting Vivado at Fri May 12 16:01:59 2023... diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v index d54750ef..fd3b68ef 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2bb0eafe7db4192794511ba4732de759cc0b98077a25b784358aa0ce15434f25 -size 347806 +oid sha256:dd9cd9018e27390f56912a6e268e1cc1df6ac463e944eefbb1088577a51cb6b2 +size 358856 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl index 8f375e59..a69cf7d3 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3e1aa647a426193095c2bb4086b35050e3cc56a9af17458cac22aa0bdf6f4196 -size 626004 +oid sha256:16cbd9d7067933092574fe5c65db17db5a9175430cab7321e7c26769844e4179 +size 638631 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v index b605a111..b5aab159 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Sun May 7 16:51:33 2023 +// Date : Fri May 12 16:01:59 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v @@ -15,12 +15,14 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1, - probe_out2, probe_out3) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]" */; + probe_out2, probe_out3, probe_out4, probe_out5) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0],probe_out5[0:0]" */; input clk; input [0:0]probe_in0; output [0:0]probe_out0; output [7:0]probe_out1; output [0:0]probe_out2; output [31:0]probe_out3; + output [0:0]probe_out4; + output [0:0]probe_out5; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl index 538f6928..767f4405 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Sun May 7 16:51:33 2023 +-- Date : Fri May 12 16:01:59 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl @@ -19,7 +19,9 @@ entity vio_freq_comp is probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end vio_freq_comp; @@ -28,7 +30,7 @@ architecture stub of vio_freq_comp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0],probe_out5[0:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb index cae2429d..fb339427 100644 Binary files a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt index 0e7b2fcb..335af981 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Sun May 7 16:51:33 2023 +| Date : Fri May 12 16:01:59 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file vio_freq_comp_utilization_synth.rpt -pb vio_freq_comp_utilization_synth.pb | Design : vio_freq_comp @@ -30,11 +30,11 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 141 | 0 | 254200 | 0.06 | -| LUT as Logic | 141 | 0 | 254200 | 0.06 | +| Slice LUTs* | 148 | 0 | 254200 | 0.06 | +| LUT as Logic | 148 | 0 | 254200 | 0.06 | | LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 359 | 0 | 508400 | 0.07 | -| Register as Flip Flop | 359 | 0 | 508400 | 0.07 | +| Slice Registers | 367 | 0 | 508400 | 0.07 | +| Register as Flip Flop | 367 | 0 | 508400 | 0.07 | | Register as Latch | 0 | 0 | 508400 | 0.00 | | F7 Muxes | 0 | 0 | 127100 | 0.00 | | F8 Muxes | 0 | 0 | 63550 | 0.00 | @@ -57,7 +57,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 4 | Yes | Set | - | -| 355 | Yes | Reset | - | +| 363 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -151,14 +151,14 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 355 | Flop & Latch | -| LUT6 | 84 | LUT | -| LUT3 | 51 | LUT | -| LUT5 | 13 | LUT | +| FDRE | 363 | Flop & Latch | +| LUT6 | 83 | LUT | +| LUT3 | 61 | LUT | +| LUT5 | 20 | LUT | | LUT4 | 11 | LUT | | LUT2 | 8 | LUT | | FDSE | 4 | Flop & Latch | -| LUT1 | 1 | LUT | +| LUT1 | 2 | LUT | +----------+------+---------------------+ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb index a198af90..152411c0 100644 Binary files a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst index 6921c145..ffdf65bb 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml index de0894af..923e5921 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml @@ -1,23 +1,20 @@ - - - - - + + - - + + - + - + @@ -30,14 +27,14 @@ - + - + @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf index b7ec6648..cb817851 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf @@ -1,13 +1,13 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 @@ -15,9 +15,11 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31327838:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6464735f636f6d70696c65725f76365f305f31385c6464735f3332625f38625f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f7072627331305f696e766572745f72657032:636f72655f636f6e7461696e6572:74727565:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3534:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3534:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3534:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3534:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00 -eof:1828274434 +eof:3228103618 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp index 4141e79f..eca3c13a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:81f372c3f95a4802a6d9c656c935f1de251564f0f75a56f044120ef14bda8d04 -size 190472 +oid sha256:f76ed4c22e08371a92d17e5a4dbde3e0f2407ff1f0a925390eaa8ddf06311988 +size 251720 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds index 18345894..b7f4f606 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds @@ -2,8 +2,8 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Mon May 8 10:18:29 2023 -# Process ID: 1709123 +# Start of session at: Fri May 12 15:58:51 2023 +# Process ID: 1470103 # Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1 # Command line: vivado -log vio_rfcontrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rfcontrl.tcl # Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds @@ -16,16 +16,14 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Device 21-403] Loading part xc7k410tffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 1709234 +INFO: Helper process launched with PID 1470440 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1829.469 ; gain = 152.688 ; free physical = 649 ; free virtual = 45803 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1830.438 ; gain = 153.719 ; free physical = 472 ; free virtual = 45419 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'vio_rfcontrl' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rfcontrl does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_rfcontrl/synth/vio_rfcontrl.v:106] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rfcontrl does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_rfcontrl/synth/vio_rfcontrl.v:113] INFO: [Synth 8-6155] done synthesizing module 'vio_rfcontrl' (8#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized6 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] @@ -47,6 +45,9 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port In WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Internal_cnt_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] @@ -87,8 +88,6 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unc WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_in_one has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] @@ -123,9 +122,10 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0 WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in36[0] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1892.188 ; gain = 215.406 ; free physical = 755 ; free virtual = 45831 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1892.125 ; gain = 215.406 ; free physical = 548 ; free virtual = 45437 --------------------------------------------------------------------------------- Report Check Netlist: @@ -138,10 +138,10 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.156 ; gain = 218.375 ; free physical = 756 ; free virtual = 45832 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.094 ; gain = 218.375 ; free physical = 628 ; free virtual = 45520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.156 ; gain = 218.375 ; free physical = 756 ; free virtual = 45832 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.094 ; gain = 218.375 ; free physical = 628 ; free virtual = 45520 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization @@ -153,29 +153,29 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_onl Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2075.812 ; gain = 0.000 ; free physical = 663 ; free virtual = 45724 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2077.719 ; gain = 0.000 ; free physical = 508 ; free virtual = 45419 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2081.750 ; gain = 5.938 ; free physical = 663 ; free virtual = 45724 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2083.656 ; gain = 5.938 ; free physical = 508 ; free virtual = 45419 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 734 ; free virtual = 45799 +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 615 ; free virtual = 45531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k410tffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 734 ; free virtual = 45799 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 615 ; free virtual = 45531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 734 ; free virtual = 45799 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 615 ; free virtual = 45532 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 738 ; free virtual = 45781 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 682 ; free virtual = 45597 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -189,20 +189,24 @@ Start RTL Component Statistics Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 + 2 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 4 +---Registers : 128 Bit Registers := 1 - 16 Bit Registers := 33 - 12 Bit Registers := 1 + 32 Bit Registers := 4 + 17 Bit Registers := 3 + 16 Bit Registers := 40 + 13 Bit Registers := 1 8 Bit Registers := 3 7 Bit Registers := 1 5 Bit Registers := 2 4 Bit Registers := 5 - 3 Bit Registers := 2 - 1 Bit Registers := 38 + 3 Bit Registers := 3 + 2 Bit Registers := 4 + 1 Bit Registers := 40 +---Muxes : - 2 Input 16 Bit Muxes := 2 - 9 Input 12 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 20 + 2 Input 16 Bit Muxes := 7 + 2 Input 1 Bit Muxes := 19 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -212,11 +216,15 @@ Start RTL Hierarchical Component Statistics Hierarchical RTL Component report Module vio_v3_0_20_probe_in_one Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 +---Registers : - 16 Bit Registers := 4 - 1 Bit Registers := 2 + 17 Bit Registers := 3 + 16 Bit Registers := 1 + 3 Bit Registers := 1 + 1 Bit Registers := 1 +---Muxes : - 2 Input 1 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 1 Module vio_v3_0_20_probe_out_one Detailed RTL Component Info : +---Registers : @@ -257,12 +265,22 @@ Module vio_v3_0_20_probe_out_one__parameterized5 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 2 +Module vio_v3_0_20_probe_out_one__parameterized6 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 Module vio_v3_0_20_probe_out_all Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 5 Bit Registers := 1 - 1 Bit Registers := 20 + 1 Bit Registers := 23 +---Muxes : 2 Input 1 Bit Muxes := 2 Module vio_v3_0_20_probe_width @@ -270,10 +288,8 @@ Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : - 12 Bit Registers := 1 + 13 Bit Registers := 1 4 Bit Registers := 1 -+---Muxes : - 9 Input 12 Bit Muxes := 1 Module xsdbs_v1_0_2_xsdbs Detailed RTL Component Info : +---Registers : @@ -430,7 +446,7 @@ INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PRO INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 745 ; free virtual = 45797 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 664 ; free virtual = 45582 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -442,13 +458,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 676 ; free virtual = 45664 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 446 ; free virtual = 45346 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 675 ; free virtual = 45663 +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 445 ; free virtual = 45345 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -460,7 +476,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 684 ; free virtual = 45657 +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 473 ; free virtual = 45350 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -521,7 +537,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 681 ; free virtual = 45655 +Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 465 ; free virtual = 45343 --------------------------------------------------------------------------------- Report Check Netlist: @@ -534,7 +550,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 681 ; free virtual = 45655 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 465 ; free virtual = 45342 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -546,25 +562,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 675 ; free virtual = 45649 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 465 ; free virtual = 45343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 676 ; free virtual = 45651 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 465 ; free virtual = 45343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 677 ; free virtual = 45651 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 465 ; free virtual = 45342 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 677 ; free virtual = 45651 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 465 ; free virtual = 45342 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -577,29 +593,31 @@ Report BlackBoxes: +-+--------------+----------+ Report Cell Usage: -+------+-----+------+ -| |Cell |Count | -+------+-----+------+ -|1 |LUT1 | 2| -|2 |LUT2 | 16| -|3 |LUT3 | 35| -|4 |LUT4 | 11| -|5 |LUT5 | 42| -|6 |LUT6 | 122| -|7 |FDRE | 569| -|8 |FDSE | 24| -+------+-----+------+ ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |LUT1 | 2| +|2 |LUT2 | 11| +|3 |LUT3 | 101| +|4 |LUT4 | 25| +|5 |LUT5 | 71| +|6 |LUT6 | 125| +|7 |MUXF7 | 5| +|8 |MUXF8 | 1| +|9 |FDRE | 875| +|10 |FDSE | 24| ++------+------+------+ Report Instance Areas: +------+----------------------------------------+---------------------------------------------+------+ | |Instance |Module |Cells | +------+----------------------------------------+---------------------------------------------+------+ -|1 |top | | 821| -|2 | inst |vio_v3_0_20_vio | 821| +|1 |top | | 1240| +|2 | inst |vio_v3_0_20_vio | 1240| |3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| -|4 | DECODER_INST |vio_v3_0_20_decoder | 91| +|4 | DECODER_INST |vio_v3_0_20_decoder | 97| |5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 77| -|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 367| +|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 776| |7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| |8 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 32| |9 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_0 | 32| @@ -608,45 +626,50 @@ Report Instance Areas: |12 | \G_PROBE_OUT[14].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3| |13 | \G_PROBE_OUT[15].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_3 | 3| |14 | \G_PROBE_OUT[16].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_4 | 3| -|15 | \G_PROBE_OUT[17].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_5 | 32| -|16 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_6 | 3| -|17 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 32| -|18 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 16| -|19 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 8| -|20 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_7 | 8| -|21 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_8 | 8| -|22 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_9 | 8| -|23 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_10 | 16| -|24 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 16| -|25 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 22| +|15 | \G_PROBE_OUT[17].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized6 | 101| +|16 | \G_PROBE_OUT[18].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized6_5 | 101| +|17 | \G_PROBE_OUT[19].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized6_6 | 106| +|18 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_7 | 3| +|19 | \G_PROBE_OUT[20].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized6_8 | 104| +|20 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 32| +|21 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 16| +|22 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 8| +|23 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_9 | 8| +|24 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_10 | 8| +|25 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_11 | 8| +|26 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_12 | 16| +|27 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 16| +|28 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 26| +------+----------------------------------------+---------------------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 677 ; free virtual = 45651 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 465 ; free virtual = 45342 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 292 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2081.750 ; gain = 218.375 ; free physical = 724 ; free virtual = 45699 -Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2081.750 ; gain = 404.969 ; free physical = 738 ; free virtual = 45712 +Synthesis finished with 0 errors, 0 critical warnings and 291 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2083.656 ; gain = 218.375 ; free physical = 520 ; free virtual = 45398 +Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.656 ; gain = 406.938 ; free physical = 534 ; free virtual = 45411 INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2081.750 ; gain = 0.000 ; free physical = 673 ; free virtual = 45625 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2083.656 ; gain = 0.000 ; free physical = 463 ; free virtual = 45340 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -127 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +129 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2081.750 ; gain = 682.801 ; free physical = 766 ; free virtual = 45718 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2081.750 ; gain = 0.000 ; free physical = 766 ; free virtual = 45718 +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2083.656 ; gain = 684.738 ; free physical = 557 ; free virtual = 45434 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2083.656 ; gain = 0.000 ; free physical = 557 ; free virtual = 45434 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rfcontrl, cache-ID = b3356ef7f8baa9c9 -INFO: [Coretcl 2-1174] Renamed 24 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.762 ; gain = 0.000 ; free physical = 762 ; free virtual = 45717 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rfcontrl, cache-ID = 1db6be14a58c55bc +INFO: [Coretcl 2-1174] Renamed 27 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2107.668 ; gain = 0.000 ; free physical = 550 ; free virtual = 45430 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Mon May 8 10:18:46 2023... +INFO: [Common 17-206] Exiting Vivado at Fri May 12 15:59:09 2023... diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v index 3c1dab1a..3833ab7f 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:48b2ebe7c1dfe52efb1244db5038274527b29b3e7d11c399a766d95112881ad2 -size 429602 +oid sha256:e1d99c0d0e86597ef6f9fe9afc245f663ef8c0b0f727de31af1e971a9e2daa33 +size 533583 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl index 9c6cd38c..89d07167 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:15118e44db5067dd4c76ab789bc6bf18a0975b87050cfe9e886e2e5154da11ab -size 743535 +oid sha256:a74bd47953750e25a410aa206713f24fceb04072583e91b5e9c663b8c3319a39 +size 884753 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v index bbec2e33..bf8c2df3 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 10:18:46 2023 +// Date : Fri May 12 15:59:09 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v @@ -14,13 +14,14 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, - probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, - probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, probe_out16, - probe_out17) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]" */; +module vio_rfcontrl(clk, probe_in0, probe_in1, probe_out0, + probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, + probe_out9, probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, + probe_out16, probe_out17, probe_out18, probe_out19, probe_out20) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]" */; input clk; input [15:0]probe_in0; + input [0:0]probe_in1; output [0:0]probe_out0; output [0:0]probe_out1; output [15:0]probe_out2; @@ -38,5 +39,8 @@ module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, output [0:0]probe_out14; output [0:0]probe_out15; output [0:0]probe_out16; - output [15:0]probe_out17; + output [31:0]probe_out17; + output [31:0]probe_out18; + output [31:0]probe_out19; + output [31:0]probe_out20; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl index f76a93c0..1262f137 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 10:18:46 2023 +-- Date : Fri May 12 15:59:09 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl @@ -16,6 +16,7 @@ entity vio_rfcontrl is Port ( clk : in STD_LOGIC; probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); @@ -33,7 +34,10 @@ entity vio_rfcontrl is probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + probe_out17 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out18 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out19 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out20 : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); end vio_rfcontrl; @@ -42,7 +46,7 @@ architecture stub of vio_rfcontrl is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb index bcee11d7..c9a6b32f 100644 Binary files a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt index 2ccf3ce0..9229547c 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Mon May 8 10:18:46 2023 +| Date : Fri May 12 15:59:09 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb | Design : vio_rfcontrl @@ -30,14 +30,14 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 203 | 0 | 254200 | 0.08 | -| LUT as Logic | 203 | 0 | 254200 | 0.08 | +| Slice LUTs* | 275 | 0 | 254200 | 0.11 | +| LUT as Logic | 275 | 0 | 254200 | 0.11 | | LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 593 | 0 | 508400 | 0.12 | -| Register as Flip Flop | 593 | 0 | 508400 | 0.12 | +| Slice Registers | 899 | 0 | 508400 | 0.18 | +| Register as Flip Flop | 899 | 0 | 508400 | 0.18 | | Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | -| F8 Muxes | 0 | 0 | 63550 | 0.00 | +| F7 Muxes | 5 | 0 | 127100 | <0.01 | +| F8 Muxes | 1 | 0 | 63550 | <0.01 | +-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -57,7 +57,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 24 | Yes | Set | - | -| 569 | Yes | Reset | - | +| 875 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -151,14 +151,16 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 569 | Flop & Latch | -| LUT6 | 122 | LUT | -| LUT5 | 42 | LUT | -| LUT3 | 35 | LUT | +| FDRE | 875 | Flop & Latch | +| LUT6 | 125 | LUT | +| LUT3 | 101 | LUT | +| LUT5 | 71 | LUT | +| LUT4 | 25 | LUT | | FDSE | 24 | Flop & Latch | -| LUT2 | 16 | LUT | -| LUT4 | 11 | LUT | +| LUT2 | 11 | LUT | +| MUXF7 | 5 | MuxFx | | LUT1 | 2 | LUT | +| MUXF8 | 1 | MuxFx | +----------+------+---------------------+ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb index ebc3faa6..a582a3ea 100644 Binary files a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb and b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.xpr b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.xpr index 47facd77..4d471b44 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@